git.oblomov.eu Git - linux-2.6/blob - arch/x86/kvm/svm.c

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * AMD SVM support
   5  *
   6  * Copyright (C) 2006 Qumranet, Inc.
   7  *
   8  * Authors:
   9  *   Yaniv Kamay  <yaniv@qumranet.com>
  10  *   Avi Kivity   <avi@qumranet.com>
  11  *
  12  * This work is licensed under the terms of the GNU GPL, version 2.  See
  13  * the COPYING file in the top-level directory.
  14  *
  15  */
  16 #include <linux/kvm_host.h>
  17
  18 #include "kvm_svm.h"
  19 #include "irq.h"
  20 #include "mmu.h"
  21 #include "kvm_cache_regs.h"
  22
  23 #include <linux/module.h>
  24 #include <linux/kernel.h>
  25 #include <linux/vmalloc.h>
  26 #include <linux/highmem.h>
  27 #include <linux/sched.h>
  28
  29 #include <asm/desc.h>
  30
  31 #include <asm/virtext.h>
  32
  33 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  34
  35 MODULE_AUTHOR("Qumranet");
  36 MODULE_LICENSE("GPL");
  37
  38 #define IOPM_ALLOC_ORDER 2
  39 #define MSRPM_ALLOC_ORDER 1
  40
  41 #define SEG_TYPE_LDT 2
  42 #define SEG_TYPE_BUSY_TSS16 3
  43
  44 #define SVM_FEATURE_NPT  (1 << 0)
  45 #define SVM_FEATURE_LBRV (1 << 1)
  46 #define SVM_FEATURE_SVML (1 << 2)
  47
  48 #define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
  49
  50 /* Turn on to get debugging output*/
  51 /* #define NESTED_DEBUG */
  52
  53 #ifdef NESTED_DEBUG
  54 #define nsvm_printk(fmt, args...) printk(KERN_INFO fmt, ## args)
  55 #else
  56 #define nsvm_printk(fmt, args...) do {} while(0)
  57 #endif
  58
  59 /* enable NPT for AMD64 and X86 with PAE */
  60 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
  61 static bool npt_enabled = true;
  62 #else
  63 static bool npt_enabled = false;
  64 #endif
  65 static int npt = 1;
  66
  67 module_param(npt, int, S_IRUGO);
  68
  69 static int nested = 0;
  70 module_param(nested, int, S_IRUGO);
  71
  72 static void kvm_reput_irq(struct vcpu_svm *svm);
  73 static void svm_flush_tlb(struct kvm_vcpu *vcpu);
  74
  75 static int nested_svm_exit_handled(struct vcpu_svm *svm, bool kvm_override);
  76 static int nested_svm_vmexit(struct vcpu_svm *svm);
  77 static int nested_svm_vmsave(struct vcpu_svm *svm, void *nested_vmcb,
  78                              void *arg2, void *opaque);
  79 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
  80                                       bool has_error_code, u32 error_code);
  81
  82 static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
  83 {
  84         return container_of(vcpu, struct vcpu_svm, vcpu);
  85 }
  86
  87 static inline bool is_nested(struct vcpu_svm *svm)
  88 {
  89         return svm->nested_vmcb;
  90 }
  91
  92 static unsigned long iopm_base;
  93
  94 struct kvm_ldttss_desc {
  95         u16 limit0;
  96         u16 base0;
  97         unsigned base1 : 8, type : 5, dpl : 2, p : 1;
  98         unsigned limit1 : 4, zero0 : 3, g : 1, base2 : 8;
  99         u32 base3;
 100         u32 zero1;
 101 } __attribute__((packed));
 102
 103 struct svm_cpu_data {
 104         int cpu;
 105
 106         u64 asid_generation;
 107         u32 max_asid;
 108         u32 next_asid;
 109         struct kvm_ldttss_desc *tss_desc;
 110
 111         struct page *save_area;
 112 };
 113
 114 static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
 115 static uint32_t svm_features;
 116
 117 struct svm_init_data {
 118         int cpu;
 119         int r;
 120 };
 121
 122 static u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
 123
 124 #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
 125 #define MSRS_RANGE_SIZE 2048
 126 #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
 127
 128 #define MAX_INST_SIZE 15
 129
 130 static inline u32 svm_has(u32 feat)
 131 {
 132         return svm_features & feat;
 133 }
 134
 135 static inline u8 pop_irq(struct kvm_vcpu *vcpu)
 136 {
 137         int word_index = __ffs(vcpu->arch.irq_summary);
 138         int bit_index = __ffs(vcpu->arch.irq_pending[word_index]);
 139         int irq = word_index * BITS_PER_LONG + bit_index;
 140
 141         clear_bit(bit_index, &vcpu->arch.irq_pending[word_index]);
 142         if (!vcpu->arch.irq_pending[word_index])
 143                 clear_bit(word_index, &vcpu->arch.irq_summary);
 144         return irq;
 145 }
 146
 147 static inline void push_irq(struct kvm_vcpu *vcpu, u8 irq)
 148 {
 149         set_bit(irq, vcpu->arch.irq_pending);
 150         set_bit(irq / BITS_PER_LONG, &vcpu->arch.irq_summary);
 151 }
 152
 153 static inline void clgi(void)
 154 {
 155         asm volatile (__ex(SVM_CLGI));
 156 }
 157
 158 static inline void stgi(void)
 159 {
 160         asm volatile (__ex(SVM_STGI));
 161 }
 162
 163 static inline void invlpga(unsigned long addr, u32 asid)
 164 {
 165         asm volatile (__ex(SVM_INVLPGA) :: "a"(addr), "c"(asid));
 166 }
 167
 168 static inline unsigned long kvm_read_cr2(void)
 169 {
 170         unsigned long cr2;
 171
 172         asm volatile ("mov %%cr2, %0" : "=r" (cr2));
 173         return cr2;
 174 }
 175
 176 static inline void kvm_write_cr2(unsigned long val)
 177 {
 178         asm volatile ("mov %0, %%cr2" :: "r" (val));
 179 }
 180
 181 static inline void force_new_asid(struct kvm_vcpu *vcpu)
 182 {
 183         to_svm(vcpu)->asid_generation--;
 184 }
 185
 186 static inline void flush_guest_tlb(struct kvm_vcpu *vcpu)
 187 {
 188         force_new_asid(vcpu);
 189 }
 190
 191 static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
 192 {
 193         if (!npt_enabled && !(efer & EFER_LMA))
 194                 efer &= ~EFER_LME;
 195
 196         to_svm(vcpu)->vmcb->save.efer = efer | EFER_SVME;
 197         vcpu->arch.shadow_efer = efer;
 198 }
 199
 200 static void svm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
 201                                 bool has_error_code, u32 error_code)
 202 {
 203         struct vcpu_svm *svm = to_svm(vcpu);
 204
 205         /* If we are within a nested VM we'd better #VMEXIT and let the
 206            guest handle the exception */
 207         if (nested_svm_check_exception(svm, nr, has_error_code, error_code))
 208                 return;
 209
 210         svm->vmcb->control.event_inj = nr
 211                 | SVM_EVTINJ_VALID
 212                 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
 213                 | SVM_EVTINJ_TYPE_EXEPT;
 214         svm->vmcb->control.event_inj_err = error_code;
 215 }
 216
 217 static bool svm_exception_injected(struct kvm_vcpu *vcpu)
 218 {
 219         struct vcpu_svm *svm = to_svm(vcpu);
 220
 221         return !(svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID);
 222 }
 223
 224 static int is_external_interrupt(u32 info)
 225 {
 226         info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
 227         return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
 228 }
 229
 230 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
 231 {
 232         struct vcpu_svm *svm = to_svm(vcpu);
 233
 234         if (!svm->next_rip) {
 235                 printk(KERN_DEBUG "%s: NOP\n", __func__);
 236                 return;
 237         }
 238         if (svm->next_rip - kvm_rip_read(vcpu) > MAX_INST_SIZE)
 239                 printk(KERN_ERR "%s: ip 0x%lx next 0x%llx\n",
 240                        __func__, kvm_rip_read(vcpu), svm->next_rip);
 241
 242         kvm_rip_write(vcpu, svm->next_rip);
 243         svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
 244
 245         vcpu->arch.interrupt_window_open = (svm->vcpu.arch.hflags & HF_GIF_MASK);
 246 }
 247
 248 static int has_svm(void)
 249 {
 250         const char *msg;
 251
 252         if (!cpu_has_svm(&msg)) {
 253                 printk(KERN_INFO "has_svm: %s\n", msg);
 254                 return 0;
 255         }
 256
 257         return 1;
 258 }
 259
 260 static void svm_hardware_disable(void *garbage)
 261 {
 262         cpu_svm_disable();
 263 }
 264
 265 static void svm_hardware_enable(void *garbage)
 266 {
 267
 268         struct svm_cpu_data *svm_data;
 269         uint64_t efer;
 270         struct desc_ptr gdt_descr;
 271         struct desc_struct *gdt;
 272         int me = raw_smp_processor_id();
 273
 274         if (!has_svm()) {
 275                 printk(KERN_ERR "svm_cpu_init: err EOPNOTSUPP on %d\n", me);
 276                 return;
 277         }
 278         svm_data = per_cpu(svm_data, me);
 279
 280         if (!svm_data) {
 281                 printk(KERN_ERR "svm_cpu_init: svm_data is NULL on %d\n",
 282                        me);
 283                 return;
 284         }
 285
 286         svm_data->asid_generation = 1;
 287         svm_data->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
 288         svm_data->next_asid = svm_data->max_asid + 1;
 289
 290         asm volatile ("sgdt %0" : "=m"(gdt_descr));
 291         gdt = (struct desc_struct *)gdt_descr.address;
 292         svm_data->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
 293
 294         rdmsrl(MSR_EFER, efer);
 295         wrmsrl(MSR_EFER, efer | EFER_SVME);
 296
 297         wrmsrl(MSR_VM_HSAVE_PA,
 298                page_to_pfn(svm_data->save_area) << PAGE_SHIFT);
 299 }
 300
 301 static void svm_cpu_uninit(int cpu)
 302 {
 303         struct svm_cpu_data *svm_data
 304                 = per_cpu(svm_data, raw_smp_processor_id());
 305
 306         if (!svm_data)
 307                 return;
 308
 309         per_cpu(svm_data, raw_smp_processor_id()) = NULL;
 310         __free_page(svm_data->save_area);
 311         kfree(svm_data);
 312 }
 313
 314 static int svm_cpu_init(int cpu)
 315 {
 316         struct svm_cpu_data *svm_data;
 317         int r;
 318
 319         svm_data = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
 320         if (!svm_data)
 321                 return -ENOMEM;
 322         svm_data->cpu = cpu;
 323         svm_data->save_area = alloc_page(GFP_KERNEL);
 324         r = -ENOMEM;
 325         if (!svm_data->save_area)
 326                 goto err_1;
 327
 328         per_cpu(svm_data, cpu) = svm_data;
 329
 330         return 0;
 331
 332 err_1:
 333         kfree(svm_data);
 334         return r;
 335
 336 }
 337
 338 static void set_msr_interception(u32 *msrpm, unsigned msr,
 339                                  int read, int write)
 340 {
 341         int i;
 342
 343         for (i = 0; i < NUM_MSR_MAPS; i++) {
 344                 if (msr >= msrpm_ranges[i] &&
 345                     msr < msrpm_ranges[i] + MSRS_IN_RANGE) {
 346                         u32 msr_offset = (i * MSRS_IN_RANGE + msr -
 347                                           msrpm_ranges[i]) * 2;
 348
 349                         u32 *base = msrpm + (msr_offset / 32);
 350                         u32 msr_shift = msr_offset % 32;
 351                         u32 mask = ((write) ? 0 : 2) | ((read) ? 0 : 1);
 352                         *base = (*base & ~(0x3 << msr_shift)) |
 353                                 (mask << msr_shift);
 354                         return;
 355                 }
 356         }
 357         BUG();
 358 }
 359
 360 static void svm_vcpu_init_msrpm(u32 *msrpm)
 361 {
 362         memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
 363
 364 #ifdef CONFIG_X86_64
 365         set_msr_interception(msrpm, MSR_GS_BASE, 1, 1);
 366         set_msr_interception(msrpm, MSR_FS_BASE, 1, 1);
 367         set_msr_interception(msrpm, MSR_KERNEL_GS_BASE, 1, 1);
 368         set_msr_interception(msrpm, MSR_LSTAR, 1, 1);
 369         set_msr_interception(msrpm, MSR_CSTAR, 1, 1);
 370         set_msr_interception(msrpm, MSR_SYSCALL_MASK, 1, 1);
 371 #endif
 372         set_msr_interception(msrpm, MSR_K6_STAR, 1, 1);
 373         set_msr_interception(msrpm, MSR_IA32_SYSENTER_CS, 1, 1);
 374         set_msr_interception(msrpm, MSR_IA32_SYSENTER_ESP, 1, 1);
 375         set_msr_interception(msrpm, MSR_IA32_SYSENTER_EIP, 1, 1);
 376 }
 377
 378 static void svm_enable_lbrv(struct vcpu_svm *svm)
 379 {
 380         u32 *msrpm = svm->msrpm;
 381
 382         svm->vmcb->control.lbr_ctl = 1;
 383         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
 384         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
 385         set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
 386         set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
 387 }
 388
 389 static void svm_disable_lbrv(struct vcpu_svm *svm)
 390 {
 391         u32 *msrpm = svm->msrpm;
 392
 393         svm->vmcb->control.lbr_ctl = 0;
 394         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
 395         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
 396         set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
 397         set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
 398 }
 399
 400 static __init int svm_hardware_setup(void)
 401 {
 402         int cpu;
 403         struct page *iopm_pages;
 404         void *iopm_va;
 405         int r;
 406
 407         iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
 408
 409         if (!iopm_pages)
 410                 return -ENOMEM;
 411
 412         iopm_va = page_address(iopm_pages);
 413         memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
 414         clear_bit(0x80, iopm_va); /* allow direct access to PC debug port */
 415         iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
 416
 417         if (boot_cpu_has(X86_FEATURE_NX))
 418                 kvm_enable_efer_bits(EFER_NX);
 419
 420         if (boot_cpu_has(X86_FEATURE_FXSR_OPT))
 421                 kvm_enable_efer_bits(EFER_FFXSR);
 422
 423         if (nested) {
 424                 printk(KERN_INFO "kvm: Nested Virtualization enabled\n");
 425                 kvm_enable_efer_bits(EFER_SVME);
 426         }
 427
 428         for_each_online_cpu(cpu) {
 429                 r = svm_cpu_init(cpu);
 430                 if (r)
 431                         goto err;
 432         }
 433
 434         svm_features = cpuid_edx(SVM_CPUID_FUNC);
 435
 436         if (!svm_has(SVM_FEATURE_NPT))
 437                 npt_enabled = false;
 438
 439         if (npt_enabled && !npt) {
 440                 printk(KERN_INFO "kvm: Nested Paging disabled\n");
 441                 npt_enabled = false;
 442         }
 443
 444         if (npt_enabled) {
 445                 printk(KERN_INFO "kvm: Nested Paging enabled\n");
 446                 kvm_enable_tdp();
 447         } else
 448                 kvm_disable_tdp();
 449
 450         return 0;
 451
 452 err:
 453         __free_pages(iopm_pages, IOPM_ALLOC_ORDER);
 454         iopm_base = 0;
 455         return r;
 456 }
 457
 458 static __exit void svm_hardware_unsetup(void)
 459 {
 460         int cpu;
 461
 462         for_each_online_cpu(cpu)
 463                 svm_cpu_uninit(cpu);
 464
 465         __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
 466         iopm_base = 0;
 467 }
 468
 469 static void init_seg(struct vmcb_seg *seg)
 470 {
 471         seg->selector = 0;
 472         seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
 473                 SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
 474         seg->limit = 0xffff;
 475         seg->base = 0;
 476 }
 477
 478 static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
 479 {
 480         seg->selector = 0;
 481         seg->attrib = SVM_SELECTOR_P_MASK | type;
 482         seg->limit = 0xffff;
 483         seg->base = 0;
 484 }
 485
 486 static void init_vmcb(struct vcpu_svm *svm)
 487 {
 488         struct vmcb_control_area *control = &svm->vmcb->control;
 489         struct vmcb_save_area *save = &svm->vmcb->save;
 490
 491         control->intercept_cr_read =    INTERCEPT_CR0_MASK |
 492                                         INTERCEPT_CR3_MASK |
 493                                         INTERCEPT_CR4_MASK;
 494
 495         control->intercept_cr_write =   INTERCEPT_CR0_MASK |
 496                                         INTERCEPT_CR3_MASK |
 497                                         INTERCEPT_CR4_MASK |
 498                                         INTERCEPT_CR8_MASK;
 499
 500         control->intercept_dr_read =    INTERCEPT_DR0_MASK |
 501                                         INTERCEPT_DR1_MASK |
 502                                         INTERCEPT_DR2_MASK |
 503                                         INTERCEPT_DR3_MASK;
 504
 505         control->intercept_dr_write =   INTERCEPT_DR0_MASK |
 506                                         INTERCEPT_DR1_MASK |
 507                                         INTERCEPT_DR2_MASK |
 508                                         INTERCEPT_DR3_MASK |
 509                                         INTERCEPT_DR5_MASK |
 510                                         INTERCEPT_DR7_MASK;
 511
 512         control->intercept_exceptions = (1 << PF_VECTOR) |
 513                                         (1 << UD_VECTOR) |
 514                                         (1 << MC_VECTOR);
 515
 516
 517         control->intercept =    (1ULL << INTERCEPT_INTR) |
 518                                 (1ULL << INTERCEPT_NMI) |
 519                                 (1ULL << INTERCEPT_SMI) |
 520                                 (1ULL << INTERCEPT_CPUID) |
 521                                 (1ULL << INTERCEPT_INVD) |
 522                                 (1ULL << INTERCEPT_HLT) |
 523                                 (1ULL << INTERCEPT_INVLPG) |
 524                                 (1ULL << INTERCEPT_INVLPGA) |
 525                                 (1ULL << INTERCEPT_IOIO_PROT) |
 526                                 (1ULL << INTERCEPT_MSR_PROT) |
 527                                 (1ULL << INTERCEPT_TASK_SWITCH) |
 528                                 (1ULL << INTERCEPT_SHUTDOWN) |
 529                                 (1ULL << INTERCEPT_VMRUN) |
 530                                 (1ULL << INTERCEPT_VMMCALL) |
 531                                 (1ULL << INTERCEPT_VMLOAD) |
 532                                 (1ULL << INTERCEPT_VMSAVE) |
 533                                 (1ULL << INTERCEPT_STGI) |
 534                                 (1ULL << INTERCEPT_CLGI) |
 535                                 (1ULL << INTERCEPT_SKINIT) |
 536                                 (1ULL << INTERCEPT_WBINVD) |
 537                                 (1ULL << INTERCEPT_MONITOR) |
 538                                 (1ULL << INTERCEPT_MWAIT);
 539
 540         control->iopm_base_pa = iopm_base;
 541         control->msrpm_base_pa = __pa(svm->msrpm);
 542         control->tsc_offset = 0;
 543         control->int_ctl = V_INTR_MASKING_MASK;
 544
 545         init_seg(&save->es);
 546         init_seg(&save->ss);
 547         init_seg(&save->ds);
 548         init_seg(&save->fs);
 549         init_seg(&save->gs);
 550
 551         save->cs.selector = 0xf000;
 552         /* Executable/Readable Code Segment */
 553         save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
 554                 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
 555         save->cs.limit = 0xffff;
 556         /*
 557          * cs.base should really be 0xffff0000, but vmx can't handle that, so
 558          * be consistent with it.
 559          *
 560          * Replace when we have real mode working for vmx.
 561          */
 562         save->cs.base = 0xf0000;
 563
 564         save->gdtr.limit = 0xffff;
 565         save->idtr.limit = 0xffff;
 566
 567         init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
 568         init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
 569
 570         save->efer = EFER_SVME;
 571         save->dr6 = 0xffff0ff0;
 572         save->dr7 = 0x400;
 573         save->rflags = 2;
 574         save->rip = 0x0000fff0;
 575         svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip;
 576
 577         /*
 578          * cr0 val on cpu init should be 0x60000010, we enable cpu
 579          * cache by default. the orderly way is to enable cache in bios.
 580          */
 581         save->cr0 = 0x00000010 | X86_CR0_PG | X86_CR0_WP;
 582         save->cr4 = X86_CR4_PAE;
 583         /* rdx = ?? */
 584
 585         if (npt_enabled) {
 586                 /* Setup VMCB for Nested Paging */
 587                 control->nested_ctl = 1;
 588                 control->intercept &= ~((1ULL << INTERCEPT_TASK_SWITCH) |
 589                                         (1ULL << INTERCEPT_INVLPG));
 590                 control->intercept_exceptions &= ~(1 << PF_VECTOR);
 591                 control->intercept_cr_read &= ~(INTERCEPT_CR0_MASK|
 592                                                 INTERCEPT_CR3_MASK);
 593                 control->intercept_cr_write &= ~(INTERCEPT_CR0_MASK|
 594                                                  INTERCEPT_CR3_MASK);
 595                 save->g_pat = 0x0007040600070406ULL;
 596                 /* enable caching because the QEMU Bios doesn't enable it */
 597                 save->cr0 = X86_CR0_ET;
 598                 save->cr3 = 0;
 599                 save->cr4 = 0;
 600         }
 601         force_new_asid(&svm->vcpu);
 602
 603         svm->nested_vmcb = 0;
 604         svm->vcpu.arch.hflags = HF_GIF_MASK;
 605 }
 606
 607 static int svm_vcpu_reset(struct kvm_vcpu *vcpu)
 608 {
 609         struct vcpu_svm *svm = to_svm(vcpu);
 610
 611         init_vmcb(svm);
 612
 613         if (vcpu->vcpu_id != 0) {
 614                 kvm_rip_write(vcpu, 0);
 615                 svm->vmcb->save.cs.base = svm->vcpu.arch.sipi_vector << 12;
 616                 svm->vmcb->save.cs.selector = svm->vcpu.arch.sipi_vector << 8;
 617         }
 618         vcpu->arch.regs_avail = ~0;
 619         vcpu->arch.regs_dirty = ~0;
 620
 621         return 0;
 622 }
 623
 624 static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
 625 {
 626         struct vcpu_svm *svm;
 627         struct page *page;
 628         struct page *msrpm_pages;
 629         struct page *hsave_page;
 630         struct page *nested_msrpm_pages;
 631         int err;
 632
 633         svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
 634         if (!svm) {
 635                 err = -ENOMEM;
 636                 goto out;
 637         }
 638
 639         err = kvm_vcpu_init(&svm->vcpu, kvm, id);
 640         if (err)
 641                 goto free_svm;
 642
 643         page = alloc_page(GFP_KERNEL);
 644         if (!page) {
 645                 err = -ENOMEM;
 646                 goto uninit;
 647         }
 648
 649         err = -ENOMEM;
 650         msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
 651         if (!msrpm_pages)
 652                 goto uninit;
 653
 654         nested_msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
 655         if (!nested_msrpm_pages)
 656                 goto uninit;
 657
 658         svm->msrpm = page_address(msrpm_pages);
 659         svm_vcpu_init_msrpm(svm->msrpm);
 660
 661         hsave_page = alloc_page(GFP_KERNEL);
 662         if (!hsave_page)
 663                 goto uninit;
 664         svm->hsave = page_address(hsave_page);
 665
 666         svm->nested_msrpm = page_address(nested_msrpm_pages);
 667
 668         svm->vmcb = page_address(page);
 669         clear_page(svm->vmcb);
 670         svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT;
 671         svm->asid_generation = 0;
 672         init_vmcb(svm);
 673
 674         fx_init(&svm->vcpu);
 675         svm->vcpu.fpu_active = 1;
 676         svm->vcpu.arch.apic_base = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
 677         if (svm->vcpu.vcpu_id == 0)
 678                 svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
 679
 680         return &svm->vcpu;
 681
 682 uninit:
 683         kvm_vcpu_uninit(&svm->vcpu);
 684 free_svm:
 685         kmem_cache_free(kvm_vcpu_cache, svm);
 686 out:
 687         return ERR_PTR(err);
 688 }
 689
 690 static void svm_free_vcpu(struct kvm_vcpu *vcpu)
 691 {
 692         struct vcpu_svm *svm = to_svm(vcpu);
 693
 694         __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT));
 695         __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
 696         __free_page(virt_to_page(svm->hsave));
 697         __free_pages(virt_to_page(svm->nested_msrpm), MSRPM_ALLOC_ORDER);
 698         kvm_vcpu_uninit(vcpu);
 699         kmem_cache_free(kvm_vcpu_cache, svm);
 700 }
 701
 702 static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
 703 {
 704         struct vcpu_svm *svm = to_svm(vcpu);
 705         int i;
 706
 707         if (unlikely(cpu != vcpu->cpu)) {
 708                 u64 tsc_this, delta;
 709
 710                 /*
 711                  * Make sure that the guest sees a monotonically
 712                  * increasing TSC.
 713                  */
 714                 rdtscll(tsc_this);
 715                 delta = vcpu->arch.host_tsc - tsc_this;
 716                 svm->vmcb->control.tsc_offset += delta;
 717                 vcpu->cpu = cpu;
 718                 kvm_migrate_timers(vcpu);
 719         }
 720
 721         for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
 722                 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
 723 }
 724
 725 static void svm_vcpu_put(struct kvm_vcpu *vcpu)
 726 {
 727         struct vcpu_svm *svm = to_svm(vcpu);
 728         int i;
 729
 730         ++vcpu->stat.host_state_reload;
 731         for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
 732                 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
 733
 734         rdtscll(vcpu->arch.host_tsc);
 735 }
 736
 737 static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
 738 {
 739         return to_svm(vcpu)->vmcb->save.rflags;
 740 }
 741
 742 static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
 743 {
 744         to_svm(vcpu)->vmcb->save.rflags = rflags;
 745 }
 746
 747 static void svm_set_vintr(struct vcpu_svm *svm)
 748 {
 749         svm->vmcb->control.intercept |= 1ULL << INTERCEPT_VINTR;
 750 }
 751
 752 static void svm_clear_vintr(struct vcpu_svm *svm)
 753 {
 754         svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_VINTR);
 755 }
 756
 757 static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
 758 {
 759         struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
 760
 761         switch (seg) {
 762         case VCPU_SREG_CS: return &save->cs;
 763         case VCPU_SREG_DS: return &save->ds;
 764         case VCPU_SREG_ES: return &save->es;
 765         case VCPU_SREG_FS: return &save->fs;
 766         case VCPU_SREG_GS: return &save->gs;
 767         case VCPU_SREG_SS: return &save->ss;
 768         case VCPU_SREG_TR: return &save->tr;
 769         case VCPU_SREG_LDTR: return &save->ldtr;
 770         }
 771         BUG();
 772         return NULL;
 773 }
 774
 775 static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
 776 {
 777         struct vmcb_seg *s = svm_seg(vcpu, seg);
 778
 779         return s->base;
 780 }
 781
 782 static void svm_get_segment(struct kvm_vcpu *vcpu,
 783                             struct kvm_segment *var, int seg)
 784 {
 785         struct vmcb_seg *s = svm_seg(vcpu, seg);
 786
 787         var->base = s->base;
 788         var->limit = s->limit;
 789         var->selector = s->selector;
 790         var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
 791         var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
 792         var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
 793         var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
 794         var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
 795         var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
 796         var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
 797         var->g = (s->attrib >> SVM_SELECTOR_G_SHIFT) & 1;
 798
 799         switch (seg) {
 800         case VCPU_SREG_CS:
 801                 /*
 802                  * SVM always stores 0 for the 'G' bit in the CS selector in
 803                  * the VMCB on a VMEXIT. This hurts cross-vendor migration:
 804                  * Intel's VMENTRY has a check on the 'G' bit.
 805                  */
 806                 var->g = s->limit > 0xfffff;
 807                 break;
 808         case VCPU_SREG_TR:
 809                 /*
 810                  * Work around a bug where the busy flag in the tr selector
 811                  * isn't exposed
 812                  */
 813                 var->type |= 0x2;
 814                 break;
 815         case VCPU_SREG_DS:
 816         case VCPU_SREG_ES:
 817         case VCPU_SREG_FS:
 818         case VCPU_SREG_GS:
 819                 /*
 820                  * The accessed bit must always be set in the segment
 821                  * descriptor cache, although it can be cleared in the
 822                  * descriptor, the cached bit always remains at 1. Since
 823                  * Intel has a check on this, set it here to support
 824                  * cross-vendor migration.
 825                  */
 826                 if (!var->unusable)
 827                         var->type |= 0x1;
 828                 break;
 829         }
 830
 831         var->unusable = !var->present;
 832 }
 833
 834 static int svm_get_cpl(struct kvm_vcpu *vcpu)
 835 {
 836         struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
 837
 838         return save->cpl;
 839 }
 840
 841 static void svm_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
 842 {
 843         struct vcpu_svm *svm = to_svm(vcpu);
 844
 845         dt->limit = svm->vmcb->save.idtr.limit;
 846         dt->base = svm->vmcb->save.idtr.base;
 847 }
 848
 849 static void svm_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
 850 {
 851         struct vcpu_svm *svm = to_svm(vcpu);
 852
 853         svm->vmcb->save.idtr.limit = dt->limit;
 854         svm->vmcb->save.idtr.base = dt->base ;
 855 }
 856
 857 static void svm_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
 858 {
 859         struct vcpu_svm *svm = to_svm(vcpu);
 860
 861         dt->limit = svm->vmcb->save.gdtr.limit;
 862         dt->base = svm->vmcb->save.gdtr.base;
 863 }
 864
 865 static void svm_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
 866 {
 867         struct vcpu_svm *svm = to_svm(vcpu);
 868
 869         svm->vmcb->save.gdtr.limit = dt->limit;
 870         svm->vmcb->save.gdtr.base = dt->base ;
 871 }
 872
 873 static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
 874 {
 875 }
 876
 877 static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
 878 {
 879         struct vcpu_svm *svm = to_svm(vcpu);
 880
 881 #ifdef CONFIG_X86_64
 882         if (vcpu->arch.shadow_efer & EFER_LME) {
 883                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
 884                         vcpu->arch.shadow_efer |= EFER_LMA;
 885                         svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
 886                 }
 887
 888                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
 889                         vcpu->arch.shadow_efer &= ~EFER_LMA;
 890                         svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
 891                 }
 892         }
 893 #endif
 894         if (npt_enabled)
 895                 goto set;
 896
 897         if ((vcpu->arch.cr0 & X86_CR0_TS) && !(cr0 & X86_CR0_TS)) {
 898                 svm->vmcb->control.intercept_exceptions &= ~(1 << NM_VECTOR);
 899                 vcpu->fpu_active = 1;
 900         }
 901
 902         vcpu->arch.cr0 = cr0;
 903         cr0 |= X86_CR0_PG | X86_CR0_WP;
 904         if (!vcpu->fpu_active) {
 905                 svm->vmcb->control.intercept_exceptions |= (1 << NM_VECTOR);
 906                 cr0 |= X86_CR0_TS;
 907         }
 908 set:
 909         /*
 910          * re-enable caching here because the QEMU bios
 911          * does not do it - this results in some delay at
 912          * reboot
 913          */
 914         cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
 915         svm->vmcb->save.cr0 = cr0;
 916 }
 917
 918 static void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
 919 {
 920         unsigned long host_cr4_mce = read_cr4() & X86_CR4_MCE;
 921         unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4;
 922
 923         if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
 924                 force_new_asid(vcpu);
 925
 926         vcpu->arch.cr4 = cr4;
 927         if (!npt_enabled)
 928                 cr4 |= X86_CR4_PAE;
 929         cr4 |= host_cr4_mce;
 930         to_svm(vcpu)->vmcb->save.cr4 = cr4;
 931 }
 932
 933 static void svm_set_segment(struct kvm_vcpu *vcpu,
 934                             struct kvm_segment *var, int seg)
 935 {
 936         struct vcpu_svm *svm = to_svm(vcpu);
 937         struct vmcb_seg *s = svm_seg(vcpu, seg);
 938
 939         s->base = var->base;
 940         s->limit = var->limit;
 941         s->selector = var->selector;
 942         if (var->unusable)
 943                 s->attrib = 0;
 944         else {
 945                 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
 946                 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
 947                 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
 948                 s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT;
 949                 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
 950                 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
 951                 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
 952                 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
 953         }
 954         if (seg == VCPU_SREG_CS)
 955                 svm->vmcb->save.cpl
 956                         = (svm->vmcb->save.cs.attrib
 957                            >> SVM_SELECTOR_DPL_SHIFT) & 3;
 958
 959 }
 960
 961 static int svm_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
 962 {
 963         int old_debug = vcpu->guest_debug;
 964         struct vcpu_svm *svm = to_svm(vcpu);
 965
 966         vcpu->guest_debug = dbg->control;
 967
 968         svm->vmcb->control.intercept_exceptions &=
 969                 ~((1 << DB_VECTOR) | (1 << BP_VECTOR));
 970         if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
 971                 if (vcpu->guest_debug &
 972                     (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
 973                         svm->vmcb->control.intercept_exceptions |=
 974                                 1 << DB_VECTOR;
 975                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
 976                         svm->vmcb->control.intercept_exceptions |=
 977                                 1 << BP_VECTOR;
 978         } else
 979                 vcpu->guest_debug = 0;
 980
 981         if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
 982                 svm->vmcb->save.dr7 = dbg->arch.debugreg[7];
 983         else
 984                 svm->vmcb->save.dr7 = vcpu->arch.dr7;
 985
 986         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
 987                 svm->vmcb->save.rflags |= X86_EFLAGS_TF | X86_EFLAGS_RF;
 988         else if (old_debug & KVM_GUESTDBG_SINGLESTEP)
 989                 svm->vmcb->save.rflags &= ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
 990
 991         return 0;
 992 }
 993
 994 static int svm_get_irq(struct kvm_vcpu *vcpu)
 995 {
 996         struct vcpu_svm *svm = to_svm(vcpu);
 997         u32 exit_int_info = svm->vmcb->control.exit_int_info;
 998
 999         if (is_external_interrupt(exit_int_info))
1000                 return exit_int_info & SVM_EVTINJ_VEC_MASK;
1001         return -1;
1002 }
1003
1004 static void load_host_msrs(struct kvm_vcpu *vcpu)
1005 {
1006 #ifdef CONFIG_X86_64
1007         wrmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
1008 #endif
1009 }
1010
1011 static void save_host_msrs(struct kvm_vcpu *vcpu)
1012 {
1013 #ifdef CONFIG_X86_64
1014         rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
1015 #endif
1016 }
1017
1018 static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *svm_data)
1019 {
1020         if (svm_data->next_asid > svm_data->max_asid) {
1021                 ++svm_data->asid_generation;
1022                 svm_data->next_asid = 1;
1023                 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
1024         }
1025
1026         svm->vcpu.cpu = svm_data->cpu;
1027         svm->asid_generation = svm_data->asid_generation;
1028         svm->vmcb->control.asid = svm_data->next_asid++;
1029 }
1030
1031 static unsigned long svm_get_dr(struct kvm_vcpu *vcpu, int dr)
1032 {
1033         struct vcpu_svm *svm = to_svm(vcpu);
1034         unsigned long val;
1035
1036         switch (dr) {
1037         case 0 ... 3:
1038                 val = vcpu->arch.db[dr];
1039                 break;
1040         case 6:
1041                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1042                         val = vcpu->arch.dr6;
1043                 else
1044                         val = svm->vmcb->save.dr6;
1045                 break;
1046         case 7:
1047                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1048                         val = vcpu->arch.dr7;
1049                 else
1050                         val = svm->vmcb->save.dr7;
1051                 break;
1052         default:
1053                 val = 0;
1054         }
1055
1056         KVMTRACE_2D(DR_READ, vcpu, (u32)dr, (u32)val, handler);
1057         return val;
1058 }
1059
1060 static void svm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long value,
1061                        int *exception)
1062 {
1063         struct vcpu_svm *svm = to_svm(vcpu);
1064
1065         KVMTRACE_2D(DR_WRITE, vcpu, (u32)dr, (u32)value, handler);
1066
1067         *exception = 0;
1068
1069         switch (dr) {
1070         case 0 ... 3:
1071                 vcpu->arch.db[dr] = value;
1072                 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
1073                         vcpu->arch.eff_db[dr] = value;
1074                 return;
1075         case 4 ... 5:
1076                 if (vcpu->arch.cr4 & X86_CR4_DE)
1077                         *exception = UD_VECTOR;
1078                 return;
1079         case 6:
1080                 if (value & 0xffffffff00000000ULL) {
1081                         *exception = GP_VECTOR;
1082                         return;
1083                 }
1084                 vcpu->arch.dr6 = (value & DR6_VOLATILE) | DR6_FIXED_1;
1085                 return;
1086         case 7:
1087                 if (value & 0xffffffff00000000ULL) {
1088                         *exception = GP_VECTOR;
1089                         return;
1090                 }
1091                 vcpu->arch.dr7 = (value & DR7_VOLATILE) | DR7_FIXED_1;
1092                 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
1093                         svm->vmcb->save.dr7 = vcpu->arch.dr7;
1094                         vcpu->arch.switch_db_regs = (value & DR7_BP_EN_MASK);
1095                 }
1096                 return;
1097         default:
1098                 /* FIXME: Possible case? */
1099                 printk(KERN_DEBUG "%s: unexpected dr %u\n",
1100                        __func__, dr);
1101                 *exception = UD_VECTOR;
1102                 return;
1103         }
1104 }
1105
1106 static int pf_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1107 {
1108         u32 exit_int_info = svm->vmcb->control.exit_int_info;
1109         struct kvm *kvm = svm->vcpu.kvm;
1110         u64 fault_address;
1111         u32 error_code;
1112         bool event_injection = false;
1113
1114         if (!irqchip_in_kernel(kvm) &&
1115             is_external_interrupt(exit_int_info)) {
1116                 event_injection = true;
1117                 push_irq(&svm->vcpu, exit_int_info & SVM_EVTINJ_VEC_MASK);
1118         }
1119
1120         fault_address  = svm->vmcb->control.exit_info_2;
1121         error_code = svm->vmcb->control.exit_info_1;
1122
1123         if (!npt_enabled)
1124                 KVMTRACE_3D(PAGE_FAULT, &svm->vcpu, error_code,
1125                             (u32)fault_address, (u32)(fault_address >> 32),
1126                             handler);
1127         else
1128                 KVMTRACE_3D(TDP_FAULT, &svm->vcpu, error_code,
1129                             (u32)fault_address, (u32)(fault_address >> 32),
1130                             handler);
1131         /*
1132          * FIXME: Tis shouldn't be necessary here, but there is a flush
1133          * missing in the MMU code. Until we find this bug, flush the
1134          * complete TLB here on an NPF
1135          */
1136         if (npt_enabled)
1137                 svm_flush_tlb(&svm->vcpu);
1138
1139         if (!npt_enabled && event_injection)
1140                 kvm_mmu_unprotect_page_virt(&svm->vcpu, fault_address);
1141         return kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code);
1142 }
1143
1144 static int db_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1145 {
1146         if (!(svm->vcpu.guest_debug &
1147               (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
1148                 kvm_queue_exception(&svm->vcpu, DB_VECTOR);
1149                 return 1;
1150         }
1151         kvm_run->exit_reason = KVM_EXIT_DEBUG;
1152         kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1153         kvm_run->debug.arch.exception = DB_VECTOR;
1154         return 0;
1155 }
1156
1157 static int bp_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1158 {
1159         kvm_run->exit_reason = KVM_EXIT_DEBUG;
1160         kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1161         kvm_run->debug.arch.exception = BP_VECTOR;
1162         return 0;
1163 }
1164
1165 static int ud_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1166 {
1167         int er;
1168
1169         er = emulate_instruction(&svm->vcpu, kvm_run, 0, 0, EMULTYPE_TRAP_UD);
1170         if (er != EMULATE_DONE)
1171                 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1172         return 1;
1173 }
1174
1175 static int nm_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1176 {
1177         svm->vmcb->control.intercept_exceptions &= ~(1 << NM_VECTOR);
1178         if (!(svm->vcpu.arch.cr0 & X86_CR0_TS))
1179                 svm->vmcb->save.cr0 &= ~X86_CR0_TS;
1180         svm->vcpu.fpu_active = 1;
1181
1182         return 1;
1183 }
1184
1185 static int mc_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1186 {
1187         /*
1188          * On an #MC intercept the MCE handler is not called automatically in
1189          * the host. So do it by hand here.
1190          */
1191         asm volatile (
1192                 "int $0x12\n");
1193         /* not sure if we ever come back to this point */
1194
1195         return 1;
1196 }
1197
1198 static int shutdown_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1199 {
1200         /*
1201          * VMCB is undefined after a SHUTDOWN intercept
1202          * so reinitialize it.
1203          */
1204         clear_page(svm->vmcb);
1205         init_vmcb(svm);
1206
1207         kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
1208         return 0;
1209 }
1210
1211 static int io_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1212 {
1213         u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
1214         int size, in, string;
1215         unsigned port;
1216
1217         ++svm->vcpu.stat.io_exits;
1218
1219         svm->next_rip = svm->vmcb->control.exit_info_2;
1220
1221         string = (io_info & SVM_IOIO_STR_MASK) != 0;
1222
1223         if (string) {
1224                 if (emulate_instruction(&svm->vcpu,
1225                                         kvm_run, 0, 0, 0) == EMULATE_DO_MMIO)
1226                         return 0;
1227                 return 1;
1228         }
1229
1230         in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
1231         port = io_info >> 16;
1232         size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
1233
1234         skip_emulated_instruction(&svm->vcpu);
1235         return kvm_emulate_pio(&svm->vcpu, kvm_run, in, size, port);
1236 }
1237
1238 static int nmi_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1239 {
1240         KVMTRACE_0D(NMI, &svm->vcpu, handler);
1241         return 1;
1242 }
1243
1244 static int intr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1245 {
1246         ++svm->vcpu.stat.irq_exits;
1247         KVMTRACE_0D(INTR, &svm->vcpu, handler);
1248         return 1;
1249 }
1250
1251 static int nop_on_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1252 {
1253         return 1;
1254 }
1255
1256 static int halt_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1257 {
1258         svm->next_rip = kvm_rip_read(&svm->vcpu) + 1;
1259         skip_emulated_instruction(&svm->vcpu);
1260         return kvm_emulate_halt(&svm->vcpu);
1261 }
1262
1263 static int vmmcall_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1264 {
1265         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1266         skip_emulated_instruction(&svm->vcpu);
1267         kvm_emulate_hypercall(&svm->vcpu);
1268         return 1;
1269 }
1270
1271 static int nested_svm_check_permissions(struct vcpu_svm *svm)
1272 {
1273         if (!(svm->vcpu.arch.shadow_efer & EFER_SVME)
1274             || !is_paging(&svm->vcpu)) {
1275                 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1276                 return 1;
1277         }
1278
1279         if (svm->vmcb->save.cpl) {
1280                 kvm_inject_gp(&svm->vcpu, 0);
1281                 return 1;
1282         }
1283
1284        return 0;
1285 }
1286
1287 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
1288                                       bool has_error_code, u32 error_code)
1289 {
1290         if (is_nested(svm)) {
1291                 svm->vmcb->control.exit_code = SVM_EXIT_EXCP_BASE + nr;
1292                 svm->vmcb->control.exit_code_hi = 0;
1293                 svm->vmcb->control.exit_info_1 = error_code;
1294                 svm->vmcb->control.exit_info_2 = svm->vcpu.arch.cr2;
1295                 if (nested_svm_exit_handled(svm, false)) {
1296                         nsvm_printk("VMexit -> EXCP 0x%x\n", nr);
1297
1298                         nested_svm_vmexit(svm);
1299                         return 1;
1300                 }
1301         }
1302
1303         return 0;
1304 }
1305
1306 static inline int nested_svm_intr(struct vcpu_svm *svm)
1307 {
1308         if (is_nested(svm)) {
1309                 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
1310                         return 0;
1311
1312                 if (!(svm->vcpu.arch.hflags & HF_HIF_MASK))
1313                         return 0;
1314
1315                 svm->vmcb->control.exit_code = SVM_EXIT_INTR;
1316
1317                 if (nested_svm_exit_handled(svm, false)) {
1318                         nsvm_printk("VMexit -> INTR\n");
1319                         nested_svm_vmexit(svm);
1320                         return 1;
1321                 }
1322         }
1323
1324         return 0;
1325 }
1326
1327 static struct page *nested_svm_get_page(struct vcpu_svm *svm, u64 gpa)
1328 {
1329         struct page *page;
1330
1331         down_read(&current->mm->mmap_sem);
1332         page = gfn_to_page(svm->vcpu.kvm, gpa >> PAGE_SHIFT);
1333         up_read(&current->mm->mmap_sem);
1334
1335         if (is_error_page(page)) {
1336                 printk(KERN_INFO "%s: could not find page at 0x%llx\n",
1337                        __func__, gpa);
1338                 kvm_release_page_clean(page);
1339                 kvm_inject_gp(&svm->vcpu, 0);
1340                 return NULL;
1341         }
1342         return page;
1343 }
1344
1345 static int nested_svm_do(struct vcpu_svm *svm,
1346                          u64 arg1_gpa, u64 arg2_gpa, void *opaque,
1347                          int (*handler)(struct vcpu_svm *svm,
1348                                         void *arg1,
1349                                         void *arg2,
1350                                         void *opaque))
1351 {
1352         struct page *arg1_page;
1353         struct page *arg2_page = NULL;
1354         void *arg1;
1355         void *arg2 = NULL;
1356         int retval;
1357
1358         arg1_page = nested_svm_get_page(svm, arg1_gpa);
1359         if(arg1_page == NULL)
1360                 return 1;
1361
1362         if (arg2_gpa) {
1363                 arg2_page = nested_svm_get_page(svm, arg2_gpa);
1364                 if(arg2_page == NULL) {
1365                         kvm_release_page_clean(arg1_page);
1366                         return 1;
1367                 }
1368         }
1369
1370         arg1 = kmap_atomic(arg1_page, KM_USER0);
1371         if (arg2_gpa)
1372                 arg2 = kmap_atomic(arg2_page, KM_USER1);
1373
1374         retval = handler(svm, arg1, arg2, opaque);
1375
1376         kunmap_atomic(arg1, KM_USER0);
1377         if (arg2_gpa)
1378                 kunmap_atomic(arg2, KM_USER1);
1379
1380         kvm_release_page_dirty(arg1_page);
1381         if (arg2_gpa)
1382                 kvm_release_page_dirty(arg2_page);
1383
1384         return retval;
1385 }
1386
1387 static int nested_svm_exit_handled_real(struct vcpu_svm *svm,
1388                                         void *arg1,
1389                                         void *arg2,
1390                                         void *opaque)
1391 {
1392         struct vmcb *nested_vmcb = (struct vmcb *)arg1;
1393         bool kvm_overrides = *(bool *)opaque;
1394         u32 exit_code = svm->vmcb->control.exit_code;
1395
1396         if (kvm_overrides) {
1397                 switch (exit_code) {
1398                 case SVM_EXIT_INTR:
1399                 case SVM_EXIT_NMI:
1400                         return 0;
1401                 /* For now we are always handling NPFs when using them */
1402                 case SVM_EXIT_NPF:
1403                         if (npt_enabled)
1404                                 return 0;
1405                         break;
1406                 /* When we're shadowing, trap PFs */
1407                 case SVM_EXIT_EXCP_BASE + PF_VECTOR:
1408                         if (!npt_enabled)
1409                                 return 0;
1410                         break;
1411                 default:
1412                         break;
1413                 }
1414         }
1415
1416         switch (exit_code) {
1417         case SVM_EXIT_READ_CR0 ... SVM_EXIT_READ_CR8: {
1418                 u32 cr_bits = 1 << (exit_code - SVM_EXIT_READ_CR0);
1419                 if (nested_vmcb->control.intercept_cr_read & cr_bits)
1420                         return 1;
1421                 break;
1422         }
1423         case SVM_EXIT_WRITE_CR0 ... SVM_EXIT_WRITE_CR8: {
1424                 u32 cr_bits = 1 << (exit_code - SVM_EXIT_WRITE_CR0);
1425                 if (nested_vmcb->control.intercept_cr_write & cr_bits)
1426                         return 1;
1427                 break;
1428         }
1429         case SVM_EXIT_READ_DR0 ... SVM_EXIT_READ_DR7: {
1430                 u32 dr_bits = 1 << (exit_code - SVM_EXIT_READ_DR0);
1431                 if (nested_vmcb->control.intercept_dr_read & dr_bits)
1432                         return 1;
1433                 break;
1434         }
1435         case SVM_EXIT_WRITE_DR0 ... SVM_EXIT_WRITE_DR7: {
1436                 u32 dr_bits = 1 << (exit_code - SVM_EXIT_WRITE_DR0);
1437                 if (nested_vmcb->control.intercept_dr_write & dr_bits)
1438                         return 1;
1439                 break;
1440         }
1441         case SVM_EXIT_EXCP_BASE ... SVM_EXIT_EXCP_BASE + 0x1f: {
1442                 u32 excp_bits = 1 << (exit_code - SVM_EXIT_EXCP_BASE);
1443                 if (nested_vmcb->control.intercept_exceptions & excp_bits)
1444                         return 1;
1445                 break;
1446         }
1447         default: {
1448                 u64 exit_bits = 1ULL << (exit_code - SVM_EXIT_INTR);
1449                 nsvm_printk("exit code: 0x%x\n", exit_code);
1450                 if (nested_vmcb->control.intercept & exit_bits)
1451                         return 1;
1452         }
1453         }
1454
1455         return 0;
1456 }
1457
1458 static int nested_svm_exit_handled_msr(struct vcpu_svm *svm,
1459                                        void *arg1, void *arg2,
1460                                        void *opaque)
1461 {
1462         struct vmcb *nested_vmcb = (struct vmcb *)arg1;
1463         u8 *msrpm = (u8 *)arg2;
1464         u32 t0, t1;
1465         u32 msr = svm->vcpu.arch.regs[VCPU_REGS_RCX];
1466         u32 param = svm->vmcb->control.exit_info_1 & 1;
1467
1468         if (!(nested_vmcb->control.intercept & (1ULL << INTERCEPT_MSR_PROT)))
1469                 return 0;
1470
1471         switch(msr) {
1472         case 0 ... 0x1fff:
1473                 t0 = (msr * 2) % 8;
1474                 t1 = msr / 8;
1475                 break;
1476         case 0xc0000000 ... 0xc0001fff:
1477                 t0 = (8192 + msr - 0xc0000000) * 2;
1478                 t1 = (t0 / 8);
1479                 t0 %= 8;
1480                 break;
1481         case 0xc0010000 ... 0xc0011fff:
1482                 t0 = (16384 + msr - 0xc0010000) * 2;
1483                 t1 = (t0 / 8);
1484                 t0 %= 8;
1485                 break;
1486         default:
1487                 return 1;
1488                 break;
1489         }
1490         if (msrpm[t1] & ((1 << param) << t0))
1491                 return 1;
1492
1493         return 0;
1494 }
1495
1496 static int nested_svm_exit_handled(struct vcpu_svm *svm, bool kvm_override)
1497 {
1498         bool k = kvm_override;
1499
1500         switch (svm->vmcb->control.exit_code) {
1501         case SVM_EXIT_MSR:
1502                 return nested_svm_do(svm, svm->nested_vmcb,
1503                                      svm->nested_vmcb_msrpm, NULL,
1504                                      nested_svm_exit_handled_msr);
1505         default: break;
1506         }
1507
1508         return nested_svm_do(svm, svm->nested_vmcb, 0, &k,
1509                              nested_svm_exit_handled_real);
1510 }
1511
1512 static int nested_svm_vmexit_real(struct vcpu_svm *svm, void *arg1,
1513                                   void *arg2, void *opaque)
1514 {
1515         struct vmcb *nested_vmcb = (struct vmcb *)arg1;
1516         struct vmcb *hsave = svm->hsave;
1517         u64 nested_save[] = { nested_vmcb->save.cr0,
1518                               nested_vmcb->save.cr3,
1519                               nested_vmcb->save.cr4,
1520                               nested_vmcb->save.efer,
1521                               nested_vmcb->control.intercept_cr_read,
1522                               nested_vmcb->control.intercept_cr_write,
1523                               nested_vmcb->control.intercept_dr_read,
1524                               nested_vmcb->control.intercept_dr_write,
1525                               nested_vmcb->control.intercept_exceptions,
1526                               nested_vmcb->control.intercept,
1527                               nested_vmcb->control.msrpm_base_pa,
1528                               nested_vmcb->control.iopm_base_pa,
1529                               nested_vmcb->control.tsc_offset };
1530
1531         /* Give the current vmcb to the guest */
1532         memcpy(nested_vmcb, svm->vmcb, sizeof(struct vmcb));
1533         nested_vmcb->save.cr0 = nested_save[0];
1534         if (!npt_enabled)
1535                 nested_vmcb->save.cr3 = nested_save[1];
1536         nested_vmcb->save.cr4 = nested_save[2];
1537         nested_vmcb->save.efer = nested_save[3];
1538         nested_vmcb->control.intercept_cr_read = nested_save[4];
1539         nested_vmcb->control.intercept_cr_write = nested_save[5];
1540         nested_vmcb->control.intercept_dr_read = nested_save[6];
1541         nested_vmcb->control.intercept_dr_write = nested_save[7];
1542         nested_vmcb->control.intercept_exceptions = nested_save[8];
1543         nested_vmcb->control.intercept = nested_save[9];
1544         nested_vmcb->control.msrpm_base_pa = nested_save[10];
1545         nested_vmcb->control.iopm_base_pa = nested_save[11];
1546         nested_vmcb->control.tsc_offset = nested_save[12];
1547
1548         /* We always set V_INTR_MASKING and remember the old value in hflags */
1549         if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
1550                 nested_vmcb->control.int_ctl &= ~V_INTR_MASKING_MASK;
1551
1552         if ((nested_vmcb->control.int_ctl & V_IRQ_MASK) &&
1553             (nested_vmcb->control.int_vector)) {
1554                 nsvm_printk("WARNING: IRQ 0x%x still enabled on #VMEXIT\n",
1555                                 nested_vmcb->control.int_vector);
1556         }
1557
1558         /* Restore the original control entries */
1559         svm->vmcb->control = hsave->control;
1560
1561         /* Kill any pending exceptions */
1562         if (svm->vcpu.arch.exception.pending == true)
1563                 nsvm_printk("WARNING: Pending Exception\n");
1564         svm->vcpu.arch.exception.pending = false;
1565
1566         /* Restore selected save entries */
1567         svm->vmcb->save.es = hsave->save.es;
1568         svm->vmcb->save.cs = hsave->save.cs;
1569         svm->vmcb->save.ss = hsave->save.ss;
1570         svm->vmcb->save.ds = hsave->save.ds;
1571         svm->vmcb->save.gdtr = hsave->save.gdtr;
1572         svm->vmcb->save.idtr = hsave->save.idtr;
1573         svm->vmcb->save.rflags = hsave->save.rflags;
1574         svm_set_efer(&svm->vcpu, hsave->save.efer);
1575         svm_set_cr0(&svm->vcpu, hsave->save.cr0 | X86_CR0_PE);
1576         svm_set_cr4(&svm->vcpu, hsave->save.cr4);
1577         if (npt_enabled) {
1578                 svm->vmcb->save.cr3 = hsave->save.cr3;
1579                 svm->vcpu.arch.cr3 = hsave->save.cr3;
1580         } else {
1581                 kvm_set_cr3(&svm->vcpu, hsave->save.cr3);
1582         }
1583         kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, hsave->save.rax);
1584         kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, hsave->save.rsp);
1585         kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, hsave->save.rip);
1586         svm->vmcb->save.dr7 = 0;
1587         svm->vmcb->save.cpl = 0;
1588         svm->vmcb->control.exit_int_info = 0;
1589
1590         svm->vcpu.arch.hflags &= ~HF_GIF_MASK;
1591         /* Exit nested SVM mode */
1592         svm->nested_vmcb = 0;
1593
1594         return 0;
1595 }
1596
1597 static int nested_svm_vmexit(struct vcpu_svm *svm)
1598 {
1599         nsvm_printk("VMexit\n");
1600         if (nested_svm_do(svm, svm->nested_vmcb, 0,
1601                           NULL, nested_svm_vmexit_real))
1602                 return 1;
1603
1604         kvm_mmu_reset_context(&svm->vcpu);
1605         kvm_mmu_load(&svm->vcpu);
1606
1607         return 0;
1608 }
1609
1610 static int nested_svm_vmrun_msrpm(struct vcpu_svm *svm, void *arg1,
1611                                   void *arg2, void *opaque)
1612 {
1613         int i;
1614         u32 *nested_msrpm = (u32*)arg1;
1615         for (i=0; i< PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER) / 4; i++)
1616                 svm->nested_msrpm[i] = svm->msrpm[i] | nested_msrpm[i];
1617         svm->vmcb->control.msrpm_base_pa = __pa(svm->nested_msrpm);
1618
1619         return 0;
1620 }
1621
1622 static int nested_svm_vmrun(struct vcpu_svm *svm, void *arg1,
1623                             void *arg2, void *opaque)
1624 {
1625         struct vmcb *nested_vmcb = (struct vmcb *)arg1;
1626         struct vmcb *hsave = svm->hsave;
1627
1628         /* nested_vmcb is our indicator if nested SVM is activated */
1629         svm->nested_vmcb = svm->vmcb->save.rax;
1630
1631         /* Clear internal status */
1632         svm->vcpu.arch.exception.pending = false;
1633
1634         /* Save the old vmcb, so we don't need to pick what we save, but
1635            can restore everything when a VMEXIT occurs */
1636         memcpy(hsave, svm->vmcb, sizeof(struct vmcb));
1637         /* We need to remember the original CR3 in the SPT case */
1638         if (!npt_enabled)
1639                 hsave->save.cr3 = svm->vcpu.arch.cr3;
1640         hsave->save.cr4 = svm->vcpu.arch.cr4;
1641         hsave->save.rip = svm->next_rip;
1642
1643         if (svm->vmcb->save.rflags & X86_EFLAGS_IF)
1644                 svm->vcpu.arch.hflags |= HF_HIF_MASK;
1645         else
1646                 svm->vcpu.arch.hflags &= ~HF_HIF_MASK;
1647
1648         /* Load the nested guest state */
1649         svm->vmcb->save.es = nested_vmcb->save.es;
1650         svm->vmcb->save.cs = nested_vmcb->save.cs;
1651         svm->vmcb->save.ss = nested_vmcb->save.ss;
1652         svm->vmcb->save.ds = nested_vmcb->save.ds;
1653         svm->vmcb->save.gdtr = nested_vmcb->save.gdtr;
1654         svm->vmcb->save.idtr = nested_vmcb->save.idtr;
1655         svm->vmcb->save.rflags = nested_vmcb->save.rflags;
1656         svm_set_efer(&svm->vcpu, nested_vmcb->save.efer);
1657         svm_set_cr0(&svm->vcpu, nested_vmcb->save.cr0);
1658         svm_set_cr4(&svm->vcpu, nested_vmcb->save.cr4);
1659         if (npt_enabled) {
1660                 svm->vmcb->save.cr3 = nested_vmcb->save.cr3;
1661                 svm->vcpu.arch.cr3 = nested_vmcb->save.cr3;
1662         } else {
1663                 kvm_set_cr3(&svm->vcpu, nested_vmcb->save.cr3);
1664                 kvm_mmu_reset_context(&svm->vcpu);
1665         }
1666         svm->vmcb->save.cr2 = nested_vmcb->save.cr2;
1667         kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, nested_vmcb->save.rax);
1668         kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, nested_vmcb->save.rsp);
1669         kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, nested_vmcb->save.rip);
1670         /* In case we don't even reach vcpu_run, the fields are not updated */
1671         svm->vmcb->save.rax = nested_vmcb->save.rax;
1672         svm->vmcb->save.rsp = nested_vmcb->save.rsp;
1673         svm->vmcb->save.rip = nested_vmcb->save.rip;
1674         svm->vmcb->save.dr7 = nested_vmcb->save.dr7;
1675         svm->vmcb->save.dr6 = nested_vmcb->save.dr6;
1676         svm->vmcb->save.cpl = nested_vmcb->save.cpl;
1677
1678         /* We don't want a nested guest to be more powerful than the guest,
1679            so all intercepts are ORed */
1680         svm->vmcb->control.intercept_cr_read |=
1681                 nested_vmcb->control.intercept_cr_read;
1682         svm->vmcb->control.intercept_cr_write |=
1683                 nested_vmcb->control.intercept_cr_write;
1684         svm->vmcb->control.intercept_dr_read |=
1685                 nested_vmcb->control.intercept_dr_read;
1686         svm->vmcb->control.intercept_dr_write |=
1687                 nested_vmcb->control.intercept_dr_write;
1688         svm->vmcb->control.intercept_exceptions |=
1689                 nested_vmcb->control.intercept_exceptions;
1690
1691         svm->vmcb->control.intercept |= nested_vmcb->control.intercept;
1692
1693         svm->nested_vmcb_msrpm = nested_vmcb->control.msrpm_base_pa;
1694
1695         force_new_asid(&svm->vcpu);
1696         svm->vmcb->control.exit_int_info = nested_vmcb->control.exit_int_info;
1697         svm->vmcb->control.exit_int_info_err = nested_vmcb->control.exit_int_info_err;
1698         svm->vmcb->control.int_ctl = nested_vmcb->control.int_ctl | V_INTR_MASKING_MASK;
1699         if (nested_vmcb->control.int_ctl & V_IRQ_MASK) {
1700                 nsvm_printk("nSVM Injecting Interrupt: 0x%x\n",
1701                                 nested_vmcb->control.int_ctl);
1702         }
1703         if (nested_vmcb->control.int_ctl & V_INTR_MASKING_MASK)
1704                 svm->vcpu.arch.hflags |= HF_VINTR_MASK;
1705         else
1706                 svm->vcpu.arch.hflags &= ~HF_VINTR_MASK;
1707
1708         nsvm_printk("nSVM exit_int_info: 0x%x | int_state: 0x%x\n",
1709                         nested_vmcb->control.exit_int_info,
1710                         nested_vmcb->control.int_state);
1711
1712         svm->vmcb->control.int_vector = nested_vmcb->control.int_vector;
1713         svm->vmcb->control.int_state = nested_vmcb->control.int_state;
1714         svm->vmcb->control.tsc_offset += nested_vmcb->control.tsc_offset;
1715         if (nested_vmcb->control.event_inj & SVM_EVTINJ_VALID)
1716                 nsvm_printk("Injecting Event: 0x%x\n",
1717                                 nested_vmcb->control.event_inj);
1718         svm->vmcb->control.event_inj = nested_vmcb->control.event_inj;
1719         svm->vmcb->control.event_inj_err = nested_vmcb->control.event_inj_err;
1720
1721         svm->vcpu.arch.hflags |= HF_GIF_MASK;
1722
1723         return 0;
1724 }
1725
1726 static int nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb)
1727 {
1728         to_vmcb->save.fs = from_vmcb->save.fs;
1729         to_vmcb->save.gs = from_vmcb->save.gs;
1730         to_vmcb->save.tr = from_vmcb->save.tr;
1731         to_vmcb->save.ldtr = from_vmcb->save.ldtr;
1732         to_vmcb->save.kernel_gs_base = from_vmcb->save.kernel_gs_base;
1733         to_vmcb->save.star = from_vmcb->save.star;
1734         to_vmcb->save.lstar = from_vmcb->save.lstar;
1735         to_vmcb->save.cstar = from_vmcb->save.cstar;
1736         to_vmcb->save.sfmask = from_vmcb->save.sfmask;
1737         to_vmcb->save.sysenter_cs = from_vmcb->save.sysenter_cs;
1738         to_vmcb->save.sysenter_esp = from_vmcb->save.sysenter_esp;
1739         to_vmcb->save.sysenter_eip = from_vmcb->save.sysenter_eip;
1740
1741         return 1;
1742 }
1743
1744 static int nested_svm_vmload(struct vcpu_svm *svm, void *nested_vmcb,
1745                              void *arg2, void *opaque)
1746 {
1747         return nested_svm_vmloadsave((struct vmcb *)nested_vmcb, svm->vmcb);
1748 }
1749
1750 static int nested_svm_vmsave(struct vcpu_svm *svm, void *nested_vmcb,
1751                              void *arg2, void *opaque)
1752 {
1753         return nested_svm_vmloadsave(svm->vmcb, (struct vmcb *)nested_vmcb);
1754 }
1755
1756 static int vmload_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1757 {
1758         if (nested_svm_check_permissions(svm))
1759                 return 1;
1760
1761         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1762         skip_emulated_instruction(&svm->vcpu);
1763
1764         nested_svm_do(svm, svm->vmcb->save.rax, 0, NULL, nested_svm_vmload);
1765
1766         return 1;
1767 }
1768
1769 static int vmsave_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1770 {
1771         if (nested_svm_check_permissions(svm))
1772                 return 1;
1773
1774         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1775         skip_emulated_instruction(&svm->vcpu);
1776
1777         nested_svm_do(svm, svm->vmcb->save.rax, 0, NULL, nested_svm_vmsave);
1778
1779         return 1;
1780 }
1781
1782 static int vmrun_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1783 {
1784         nsvm_printk("VMrun\n");
1785         if (nested_svm_check_permissions(svm))
1786                 return 1;
1787
1788         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1789         skip_emulated_instruction(&svm->vcpu);
1790
1791         if (nested_svm_do(svm, svm->vmcb->save.rax, 0,
1792                           NULL, nested_svm_vmrun))
1793                 return 1;
1794
1795         if (nested_svm_do(svm, svm->nested_vmcb_msrpm, 0,
1796                       NULL, nested_svm_vmrun_msrpm))
1797                 return 1;
1798
1799         return 1;
1800 }
1801
1802 static int stgi_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1803 {
1804         if (nested_svm_check_permissions(svm))
1805                 return 1;
1806
1807         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1808         skip_emulated_instruction(&svm->vcpu);
1809
1810         svm->vcpu.arch.hflags |= HF_GIF_MASK;
1811
1812         return 1;
1813 }
1814
1815 static int clgi_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1816 {
1817         if (nested_svm_check_permissions(svm))
1818                 return 1;
1819
1820         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1821         skip_emulated_instruction(&svm->vcpu);
1822
1823         svm->vcpu.arch.hflags &= ~HF_GIF_MASK;
1824
1825         /* After a CLGI no interrupts should come */
1826         svm_clear_vintr(svm);
1827         svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
1828
1829         return 1;
1830 }
1831
1832 static int invalid_op_interception(struct vcpu_svm *svm,
1833                                    struct kvm_run *kvm_run)
1834 {
1835         kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1836         return 1;
1837 }
1838
1839 static int task_switch_interception(struct vcpu_svm *svm,
1840                                     struct kvm_run *kvm_run)
1841 {
1842         u16 tss_selector;
1843
1844         tss_selector = (u16)svm->vmcb->control.exit_info_1;
1845         if (svm->vmcb->control.exit_info_2 &
1846             (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
1847                 return kvm_task_switch(&svm->vcpu, tss_selector,
1848                                        TASK_SWITCH_IRET);
1849         if (svm->vmcb->control.exit_info_2 &
1850             (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
1851                 return kvm_task_switch(&svm->vcpu, tss_selector,
1852                                        TASK_SWITCH_JMP);
1853         return kvm_task_switch(&svm->vcpu, tss_selector, TASK_SWITCH_CALL);
1854 }
1855
1856 static int cpuid_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1857 {
1858         svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
1859         kvm_emulate_cpuid(&svm->vcpu);
1860         return 1;
1861 }
1862
1863 static int invlpg_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1864 {
1865         if (emulate_instruction(&svm->vcpu, kvm_run, 0, 0, 0) != EMULATE_DONE)
1866                 pr_unimpl(&svm->vcpu, "%s: failed\n", __func__);
1867         return 1;
1868 }
1869
1870 static int emulate_on_interception(struct vcpu_svm *svm,
1871                                    struct kvm_run *kvm_run)
1872 {
1873         if (emulate_instruction(&svm->vcpu, NULL, 0, 0, 0) != EMULATE_DONE)
1874                 pr_unimpl(&svm->vcpu, "%s: failed\n", __func__);
1875         return 1;
1876 }
1877
1878 static int cr8_write_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1879 {
1880         emulate_instruction(&svm->vcpu, NULL, 0, 0, 0);
1881         if (irqchip_in_kernel(svm->vcpu.kvm))
1882                 return 1;
1883         kvm_run->exit_reason = KVM_EXIT_SET_TPR;
1884         return 0;
1885 }
1886
1887 static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 *data)
1888 {
1889         struct vcpu_svm *svm = to_svm(vcpu);
1890
1891         switch (ecx) {
1892         case MSR_IA32_TIME_STAMP_COUNTER: {
1893                 u64 tsc;
1894
1895                 rdtscll(tsc);
1896                 *data = svm->vmcb->control.tsc_offset + tsc;
1897                 break;
1898         }
1899         case MSR_K6_STAR:
1900                 *data = svm->vmcb->save.star;
1901                 break;
1902 #ifdef CONFIG_X86_64
1903         case MSR_LSTAR:
1904                 *data = svm->vmcb->save.lstar;
1905                 break;
1906         case MSR_CSTAR:
1907                 *data = svm->vmcb->save.cstar;
1908                 break;
1909         case MSR_KERNEL_GS_BASE:
1910                 *data = svm->vmcb->save.kernel_gs_base;
1911                 break;
1912         case MSR_SYSCALL_MASK:
1913                 *data = svm->vmcb->save.sfmask;
1914                 break;
1915 #endif
1916         case MSR_IA32_SYSENTER_CS:
1917                 *data = svm->vmcb->save.sysenter_cs;
1918                 break;
1919         case MSR_IA32_SYSENTER_EIP:
1920                 *data = svm->vmcb->save.sysenter_eip;
1921                 break;
1922         case MSR_IA32_SYSENTER_ESP:
1923                 *data = svm->vmcb->save.sysenter_esp;
1924                 break;
1925         /* Nobody will change the following 5 values in the VMCB so
1926            we can safely return them on rdmsr. They will always be 0
1927            until LBRV is implemented. */
1928         case MSR_IA32_DEBUGCTLMSR:
1929                 *data = svm->vmcb->save.dbgctl;
1930                 break;
1931         case MSR_IA32_LASTBRANCHFROMIP:
1932                 *data = svm->vmcb->save.br_from;
1933                 break;
1934         case MSR_IA32_LASTBRANCHTOIP:
1935                 *data = svm->vmcb->save.br_to;
1936                 break;
1937         case MSR_IA32_LASTINTFROMIP:
1938                 *data = svm->vmcb->save.last_excp_from;
1939                 break;
1940         case MSR_IA32_LASTINTTOIP:
1941                 *data = svm->vmcb->save.last_excp_to;
1942                 break;
1943         case MSR_VM_HSAVE_PA:
1944                 *data = svm->hsave_msr;
1945                 break;
1946         case MSR_VM_CR:
1947                 *data = 0;
1948                 break;
1949         case MSR_IA32_UCODE_REV:
1950                 *data = 0x01000065;
1951                 break;
1952         default:
1953                 return kvm_get_msr_common(vcpu, ecx, data);
1954         }
1955         return 0;
1956 }
1957
1958 static int rdmsr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1959 {
1960         u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
1961         u64 data;
1962
1963         if (svm_get_msr(&svm->vcpu, ecx, &data))
1964                 kvm_inject_gp(&svm->vcpu, 0);
1965         else {
1966                 KVMTRACE_3D(MSR_READ, &svm->vcpu, ecx, (u32)data,
1967                             (u32)(data >> 32), handler);
1968
1969                 svm->vcpu.arch.regs[VCPU_REGS_RAX] = data & 0xffffffff;
1970                 svm->vcpu.arch.regs[VCPU_REGS_RDX] = data >> 32;
1971                 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
1972                 skip_emulated_instruction(&svm->vcpu);
1973         }
1974         return 1;
1975 }
1976
1977 static int svm_set_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 data)
1978 {
1979         struct vcpu_svm *svm = to_svm(vcpu);
1980
1981         switch (ecx) {
1982         case MSR_IA32_TIME_STAMP_COUNTER: {
1983                 u64 tsc;
1984
1985                 rdtscll(tsc);
1986                 svm->vmcb->control.tsc_offset = data - tsc;
1987                 break;
1988         }
1989         case MSR_K6_STAR:
1990                 svm->vmcb->save.star = data;
1991                 break;
1992 #ifdef CONFIG_X86_64
1993         case MSR_LSTAR:
1994                 svm->vmcb->save.lstar = data;
1995                 break;
1996         case MSR_CSTAR:
1997                 svm->vmcb->save.cstar = data;
1998                 break;
1999         case MSR_KERNEL_GS_BASE:
2000                 svm->vmcb->save.kernel_gs_base = data;
2001                 break;
2002         case MSR_SYSCALL_MASK:
2003                 svm->vmcb->save.sfmask = data;
2004                 break;
2005 #endif
2006         case MSR_IA32_SYSENTER_CS:
2007                 svm->vmcb->save.sysenter_cs = data;
2008                 break;
2009         case MSR_IA32_SYSENTER_EIP:
2010                 svm->vmcb->save.sysenter_eip = data;
2011                 break;
2012         case MSR_IA32_SYSENTER_ESP:
2013                 svm->vmcb->save.sysenter_esp = data;
2014                 break;
2015         case MSR_IA32_DEBUGCTLMSR:
2016                 if (!svm_has(SVM_FEATURE_LBRV)) {
2017                         pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
2018                                         __func__, data);
2019                         break;
2020                 }
2021                 if (data & DEBUGCTL_RESERVED_BITS)
2022                         return 1;
2023
2024                 svm->vmcb->save.dbgctl = data;
2025                 if (data & (1ULL<<0))
2026                         svm_enable_lbrv(svm);
2027                 else
2028                         svm_disable_lbrv(svm);
2029                 break;
2030         case MSR_K7_EVNTSEL0:
2031         case MSR_K7_EVNTSEL1:
2032         case MSR_K7_EVNTSEL2:
2033         case MSR_K7_EVNTSEL3:
2034         case MSR_K7_PERFCTR0:
2035         case MSR_K7_PERFCTR1:
2036         case MSR_K7_PERFCTR2:
2037         case MSR_K7_PERFCTR3:
2038                 /*
2039                  * Just discard all writes to the performance counters; this
2040                  * should keep both older linux and windows 64-bit guests
2041                  * happy
2042                  */
2043                 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: 0x%x data 0x%llx\n", ecx, data);
2044
2045                 break;
2046         case MSR_VM_HSAVE_PA:
2047                 svm->hsave_msr = data;
2048                 break;
2049         default:
2050                 return kvm_set_msr_common(vcpu, ecx, data);
2051         }
2052         return 0;
2053 }
2054
2055 static int wrmsr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
2056 {
2057         u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
2058         u64 data = (svm->vcpu.arch.regs[VCPU_REGS_RAX] & -1u)
2059                 | ((u64)(svm->vcpu.arch.regs[VCPU_REGS_RDX] & -1u) << 32);
2060
2061         KVMTRACE_3D(MSR_WRITE, &svm->vcpu, ecx, (u32)data, (u32)(data >> 32),
2062                     handler);
2063
2064         svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
2065         if (svm_set_msr(&svm->vcpu, ecx, data))
2066                 kvm_inject_gp(&svm->vcpu, 0);
2067         else
2068                 skip_emulated_instruction(&svm->vcpu);
2069         return 1;
2070 }
2071
2072 static int msr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
2073 {
2074         if (svm->vmcb->control.exit_info_1)
2075                 return wrmsr_interception(svm, kvm_run);
2076         else
2077                 return rdmsr_interception(svm, kvm_run);
2078 }
2079
2080 static int interrupt_window_interception(struct vcpu_svm *svm,
2081                                    struct kvm_run *kvm_run)
2082 {
2083         KVMTRACE_0D(PEND_INTR, &svm->vcpu, handler);
2084
2085         svm_clear_vintr(svm);
2086         svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
2087         /*
2088          * If the user space waits to inject interrupts, exit as soon as
2089          * possible
2090          */
2091         if (kvm_run->request_interrupt_window &&
2092             !svm->vcpu.arch.irq_summary) {
2093                 ++svm->vcpu.stat.irq_window_exits;
2094                 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
2095                 return 0;
2096         }
2097
2098         return 1;
2099 }
2100
2101 static int (*svm_exit_handlers[])(struct vcpu_svm *svm,
2102                                       struct kvm_run *kvm_run) = {
2103         [SVM_EXIT_READ_CR0]                     = emulate_on_interception,
2104         [SVM_EXIT_READ_CR3]                     = emulate_on_interception,
2105         [SVM_EXIT_READ_CR4]                     = emulate_on_interception,
2106         [SVM_EXIT_READ_CR8]                     = emulate_on_interception,
2107         /* for now: */
2108         [SVM_EXIT_WRITE_CR0]                    = emulate_on_interception,
2109         [SVM_EXIT_WRITE_CR3]                    = emulate_on_interception,
2110         [SVM_EXIT_WRITE_CR4]                    = emulate_on_interception,
2111         [SVM_EXIT_WRITE_CR8]                    = cr8_write_interception,
2112         [SVM_EXIT_READ_DR0]                     = emulate_on_interception,
2113         [SVM_EXIT_READ_DR1]                     = emulate_on_interception,
2114         [SVM_EXIT_READ_DR2]                     = emulate_on_interception,
2115         [SVM_EXIT_READ_DR3]                     = emulate_on_interception,
2116         [SVM_EXIT_WRITE_DR0]                    = emulate_on_interception,
2117         [SVM_EXIT_WRITE_DR1]                    = emulate_on_interception,
2118         [SVM_EXIT_WRITE_DR2]                    = emulate_on_interception,
2119         [SVM_EXIT_WRITE_DR3]                    = emulate_on_interception,
2120         [SVM_EXIT_WRITE_DR5]                    = emulate_on_interception,
2121         [SVM_EXIT_WRITE_DR7]                    = emulate_on_interception,
2122         [SVM_EXIT_EXCP_BASE + DB_VECTOR]        = db_interception,
2123         [SVM_EXIT_EXCP_BASE + BP_VECTOR]        = bp_interception,
2124         [SVM_EXIT_EXCP_BASE + UD_VECTOR]        = ud_interception,
2125         [SVM_EXIT_EXCP_BASE + PF_VECTOR]        = pf_interception,
2126         [SVM_EXIT_EXCP_BASE + NM_VECTOR]        = nm_interception,
2127         [SVM_EXIT_EXCP_BASE + MC_VECTOR]        = mc_interception,
2128         [SVM_EXIT_INTR]                         = intr_interception,
2129         [SVM_EXIT_NMI]                          = nmi_interception,
2130         [SVM_EXIT_SMI]                          = nop_on_interception,
2131         [SVM_EXIT_INIT]                         = nop_on_interception,
2132         [SVM_EXIT_VINTR]                        = interrupt_window_interception,
2133         /* [SVM_EXIT_CR0_SEL_WRITE]             = emulate_on_interception, */
2134         [SVM_EXIT_CPUID]                        = cpuid_interception,
2135         [SVM_EXIT_INVD]                         = emulate_on_interception,
2136         [SVM_EXIT_HLT]                          = halt_interception,
2137         [SVM_EXIT_INVLPG]                       = invlpg_interception,
2138         [SVM_EXIT_INVLPGA]                      = invalid_op_interception,
2139         [SVM_EXIT_IOIO]                         = io_interception,
2140         [SVM_EXIT_MSR]                          = msr_interception,
2141         [SVM_EXIT_TASK_SWITCH]                  = task_switch_interception,
2142         [SVM_EXIT_SHUTDOWN]                     = shutdown_interception,
2143         [SVM_EXIT_VMRUN]                        = vmrun_interception,
2144         [SVM_EXIT_VMMCALL]                      = vmmcall_interception,
2145         [SVM_EXIT_VMLOAD]                       = vmload_interception,
2146         [SVM_EXIT_VMSAVE]                       = vmsave_interception,
2147         [SVM_EXIT_STGI]                         = stgi_interception,
2148         [SVM_EXIT_CLGI]                         = clgi_interception,
2149         [SVM_EXIT_SKINIT]                       = invalid_op_interception,
2150         [SVM_EXIT_WBINVD]                       = emulate_on_interception,
2151         [SVM_EXIT_MONITOR]                      = invalid_op_interception,
2152         [SVM_EXIT_MWAIT]                        = invalid_op_interception,
2153         [SVM_EXIT_NPF]                          = pf_interception,
2154 };
2155
2156 static int handle_exit(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu)
2157 {
2158         struct vcpu_svm *svm = to_svm(vcpu);
2159         u32 exit_code = svm->vmcb->control.exit_code;
2160
2161         KVMTRACE_3D(VMEXIT, vcpu, exit_code, (u32)svm->vmcb->save.rip,
2162                     (u32)((u64)svm->vmcb->save.rip >> 32), entryexit);
2163
2164         if (is_nested(svm)) {
2165                 nsvm_printk("nested handle_exit: 0x%x | 0x%lx | 0x%lx | 0x%lx\n",
2166                             exit_code, svm->vmcb->control.exit_info_1,
2167                             svm->vmcb->control.exit_info_2, svm->vmcb->save.rip);
2168                 if (nested_svm_exit_handled(svm, true)) {
2169                         nested_svm_vmexit(svm);
2170                         nsvm_printk("-> #VMEXIT\n");
2171                         return 1;
2172                 }
2173         }
2174
2175         if (npt_enabled) {
2176                 int mmu_reload = 0;
2177                 if ((vcpu->arch.cr0 ^ svm->vmcb->save.cr0) & X86_CR0_PG) {
2178                         svm_set_cr0(vcpu, svm->vmcb->save.cr0);
2179                         mmu_reload = 1;
2180                 }
2181                 vcpu->arch.cr0 = svm->vmcb->save.cr0;
2182                 vcpu->arch.cr3 = svm->vmcb->save.cr3;
2183                 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
2184                         if (!load_pdptrs(vcpu, vcpu->arch.cr3)) {
2185                                 kvm_inject_gp(vcpu, 0);
2186                                 return 1;
2187                         }
2188                 }
2189                 if (mmu_reload) {
2190                         kvm_mmu_reset_context(vcpu);
2191                         kvm_mmu_load(vcpu);
2192                 }
2193         }
2194
2195         kvm_reput_irq(svm);
2196
2197         if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
2198                 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
2199                 kvm_run->fail_entry.hardware_entry_failure_reason
2200                         = svm->vmcb->control.exit_code;
2201                 return 0;
2202         }
2203
2204         if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
2205             exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
2206             exit_code != SVM_EXIT_NPF)
2207                 printk(KERN_ERR "%s: unexpected exit_ini_info 0x%x "
2208                        "exit_code 0x%x\n",
2209                        __func__, svm->vmcb->control.exit_int_info,
2210                        exit_code);
2211
2212         if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
2213             || !svm_exit_handlers[exit_code]) {
2214                 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
2215                 kvm_run->hw.hardware_exit_reason = exit_code;
2216                 return 0;
2217         }
2218
2219         return svm_exit_handlers[exit_code](svm, kvm_run);
2220 }
2221
2222 static void reload_tss(struct kvm_vcpu *vcpu)
2223 {
2224         int cpu = raw_smp_processor_id();
2225
2226         struct svm_cpu_data *svm_data = per_cpu(svm_data, cpu);
2227         svm_data->tss_desc->type = 9; /* available 32/64-bit TSS */
2228         load_TR_desc();
2229 }
2230
2231 static void pre_svm_run(struct vcpu_svm *svm)
2232 {
2233         int cpu = raw_smp_processor_id();
2234
2235         struct svm_cpu_data *svm_data = per_cpu(svm_data, cpu);
2236
2237         svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
2238         if (svm->vcpu.cpu != cpu ||
2239             svm->asid_generation != svm_data->asid_generation)
2240                 new_asid(svm, svm_data);
2241 }
2242
2243
2244 static inline void svm_inject_irq(struct vcpu_svm *svm, int irq)
2245 {
2246         struct vmcb_control_area *control;
2247
2248         KVMTRACE_1D(INJ_VIRQ, &svm->vcpu, (u32)irq, handler);
2249
2250         ++svm->vcpu.stat.irq_injections;
2251         control = &svm->vmcb->control;
2252         control->int_vector = irq;
2253         control->int_ctl &= ~V_INTR_PRIO_MASK;
2254         control->int_ctl |= V_IRQ_MASK |
2255                 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
2256 }
2257
2258 static void svm_set_irq(struct kvm_vcpu *vcpu, int irq)
2259 {
2260         struct vcpu_svm *svm = to_svm(vcpu);
2261
2262         nested_svm_intr(svm);
2263
2264         svm_inject_irq(svm, irq);
2265 }
2266
2267 static void update_cr8_intercept(struct kvm_vcpu *vcpu)
2268 {
2269         struct vcpu_svm *svm = to_svm(vcpu);
2270         struct vmcb *vmcb = svm->vmcb;
2271         int max_irr, tpr;
2272
2273         if (!irqchip_in_kernel(vcpu->kvm) || vcpu->arch.apic->vapic_addr)
2274                 return;
2275
2276         vmcb->control.intercept_cr_write &= ~INTERCEPT_CR8_MASK;
2277
2278         max_irr = kvm_lapic_find_highest_irr(vcpu);
2279         if (max_irr == -1)
2280                 return;
2281
2282         tpr = kvm_lapic_get_cr8(vcpu) << 4;
2283
2284         if (tpr >= (max_irr & 0xf0))
2285                 vmcb->control.intercept_cr_write |= INTERCEPT_CR8_MASK;
2286 }
2287
2288 static void svm_intr_assist(struct kvm_vcpu *vcpu)
2289 {
2290         struct vcpu_svm *svm = to_svm(vcpu);
2291         struct vmcb *vmcb = svm->vmcb;
2292         int intr_vector = -1;
2293
2294         if ((vmcb->control.exit_int_info & SVM_EVTINJ_VALID) &&
2295             ((vmcb->control.exit_int_info & SVM_EVTINJ_TYPE_MASK) == 0)) {
2296                 intr_vector = vmcb->control.exit_int_info &
2297                               SVM_EVTINJ_VEC_MASK;
2298                 vmcb->control.exit_int_info = 0;
2299                 svm_inject_irq(svm, intr_vector);
2300                 goto out;
2301         }
2302
2303         if (vmcb->control.int_ctl & V_IRQ_MASK)
2304                 goto out;
2305
2306         if (!kvm_cpu_has_interrupt(vcpu))
2307                 goto out;
2308
2309         if (nested_svm_intr(svm))
2310                 goto out;
2311
2312         if (!(svm->vcpu.arch.hflags & HF_GIF_MASK))
2313                 goto out;
2314
2315         if (!(vmcb->save.rflags & X86_EFLAGS_IF) ||
2316             (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) ||
2317             (vmcb->control.event_inj & SVM_EVTINJ_VALID)) {
2318                 /* unable to deliver irq, set pending irq */
2319                 svm_set_vintr(svm);
2320                 svm_inject_irq(svm, 0x0);
2321                 goto out;
2322         }
2323         /* Okay, we can deliver the interrupt: grab it and update PIC state. */
2324         intr_vector = kvm_cpu_get_interrupt(vcpu);
2325         svm_inject_irq(svm, intr_vector);
2326 out:
2327         update_cr8_intercept(vcpu);
2328 }
2329
2330 static void kvm_reput_irq(struct vcpu_svm *svm)
2331 {
2332         struct vmcb_control_area *control = &svm->vmcb->control;
2333
2334         if ((control->int_ctl & V_IRQ_MASK)
2335             && !irqchip_in_kernel(svm->vcpu.kvm)) {
2336                 control->int_ctl &= ~V_IRQ_MASK;
2337                 push_irq(&svm->vcpu, control->int_vector);
2338         }
2339
2340         svm->vcpu.arch.interrupt_window_open =
2341                 !(control->int_state & SVM_INTERRUPT_SHADOW_MASK) &&
2342                  (svm->vcpu.arch.hflags & HF_GIF_MASK);
2343 }
2344
2345 static void svm_do_inject_vector(struct vcpu_svm *svm)
2346 {
2347         struct kvm_vcpu *vcpu = &svm->vcpu;
2348         int word_index = __ffs(vcpu->arch.irq_summary);
2349         int bit_index = __ffs(vcpu->arch.irq_pending[word_index]);
2350         int irq = word_index * BITS_PER_LONG + bit_index;
2351
2352         clear_bit(bit_index, &vcpu->arch.irq_pending[word_index]);
2353         if (!vcpu->arch.irq_pending[word_index])
2354                 clear_bit(word_index, &vcpu->arch.irq_summary);
2355         svm_inject_irq(svm, irq);
2356 }
2357
2358 static void do_interrupt_requests(struct kvm_vcpu *vcpu,
2359                                        struct kvm_run *kvm_run)
2360 {
2361         struct vcpu_svm *svm = to_svm(vcpu);
2362         struct vmcb_control_area *control = &svm->vmcb->control;
2363
2364         if (nested_svm_intr(svm))
2365                 return;
2366
2367         svm->vcpu.arch.interrupt_window_open =
2368                 (!(control->int_state & SVM_INTERRUPT_SHADOW_MASK) &&
2369                  (svm->vmcb->save.rflags & X86_EFLAGS_IF) &&
2370                  (svm->vcpu.arch.hflags & HF_GIF_MASK));
2371
2372         if (svm->vcpu.arch.interrupt_window_open && svm->vcpu.arch.irq_summary)
2373                 /*
2374                  * If interrupts enabled, and not blocked by sti or mov ss. Good.
2375                  */
2376                 svm_do_inject_vector(svm);
2377
2378         /*
2379          * Interrupts blocked.  Wait for unblock.
2380          */
2381         if (!svm->vcpu.arch.interrupt_window_open &&
2382             (svm->vcpu.arch.irq_summary || kvm_run->request_interrupt_window))
2383                 svm_set_vintr(svm);
2384         else
2385                 svm_clear_vintr(svm);
2386 }
2387
2388 static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
2389 {
2390         return 0;
2391 }
2392
2393 static void svm_flush_tlb(struct kvm_vcpu *vcpu)
2394 {
2395         force_new_asid(vcpu);
2396 }
2397
2398 static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
2399 {
2400 }
2401
2402 static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
2403 {
2404         struct vcpu_svm *svm = to_svm(vcpu);
2405
2406         if (!(svm->vmcb->control.intercept_cr_write & INTERCEPT_CR8_MASK)) {
2407                 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
2408                 kvm_lapic_set_tpr(vcpu, cr8);
2409         }
2410 }
2411
2412 static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
2413 {
2414         struct vcpu_svm *svm = to_svm(vcpu);
2415         u64 cr8;
2416
2417         if (!irqchip_in_kernel(vcpu->kvm))
2418                 return;
2419
2420         cr8 = kvm_get_cr8(vcpu);
2421         svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
2422         svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
2423 }
2424
2425 #ifdef CONFIG_X86_64
2426 #define R "r"
2427 #else
2428 #define R "e"
2429 #endif
2430
2431 static void svm_vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2432 {
2433         struct vcpu_svm *svm = to_svm(vcpu);
2434         u16 fs_selector;
2435         u16 gs_selector;
2436         u16 ldt_selector;
2437
2438         svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
2439         svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
2440         svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
2441
2442         pre_svm_run(svm);
2443
2444         sync_lapic_to_cr8(vcpu);
2445
2446         save_host_msrs(vcpu);
2447         fs_selector = kvm_read_fs();
2448         gs_selector = kvm_read_gs();
2449         ldt_selector = kvm_read_ldt();
2450         svm->host_cr2 = kvm_read_cr2();
2451         if (!is_nested(svm))
2452                 svm->vmcb->save.cr2 = vcpu->arch.cr2;
2453         /* required for live migration with NPT */
2454         if (npt_enabled)
2455                 svm->vmcb->save.cr3 = vcpu->arch.cr3;
2456
2457         clgi();
2458
2459         local_irq_enable();
2460
2461         asm volatile (
2462                 "push %%"R"bp; \n\t"
2463                 "mov %c[rbx](%[svm]), %%"R"bx \n\t"
2464                 "mov %c[rcx](%[svm]), %%"R"cx \n\t"
2465                 "mov %c[rdx](%[svm]), %%"R"dx \n\t"
2466                 "mov %c[rsi](%[svm]), %%"R"si \n\t"
2467                 "mov %c[rdi](%[svm]), %%"R"di \n\t"
2468                 "mov %c[rbp](%[svm]), %%"R"bp \n\t"
2469 #ifdef CONFIG_X86_64
2470                 "mov %c[r8](%[svm]),  %%r8  \n\t"
2471                 "mov %c[r9](%[svm]),  %%r9  \n\t"
2472                 "mov %c[r10](%[svm]), %%r10 \n\t"
2473                 "mov %c[r11](%[svm]), %%r11 \n\t"
2474                 "mov %c[r12](%[svm]), %%r12 \n\t"
2475                 "mov %c[r13](%[svm]), %%r13 \n\t"
2476                 "mov %c[r14](%[svm]), %%r14 \n\t"
2477                 "mov %c[r15](%[svm]), %%r15 \n\t"
2478 #endif
2479
2480                 /* Enter guest mode */
2481                 "push %%"R"ax \n\t"
2482                 "mov %c[vmcb](%[svm]), %%"R"ax \n\t"
2483                 __ex(SVM_VMLOAD) "\n\t"
2484                 __ex(SVM_VMRUN) "\n\t"
2485                 __ex(SVM_VMSAVE) "\n\t"
2486                 "pop %%"R"ax \n\t"
2487
2488                 /* Save guest registers, load host registers */
2489                 "mov %%"R"bx, %c[rbx](%[svm]) \n\t"
2490                 "mov %%"R"cx, %c[rcx](%[svm]) \n\t"
2491                 "mov %%"R"dx, %c[rdx](%[svm]) \n\t"
2492                 "mov %%"R"si, %c[rsi](%[svm]) \n\t"
2493                 "mov %%"R"di, %c[rdi](%[svm]) \n\t"
2494                 "mov %%"R"bp, %c[rbp](%[svm]) \n\t"
2495 #ifdef CONFIG_X86_64
2496                 "mov %%r8,  %c[r8](%[svm]) \n\t"
2497                 "mov %%r9,  %c[r9](%[svm]) \n\t"
2498                 "mov %%r10, %c[r10](%[svm]) \n\t"
2499                 "mov %%r11, %c[r11](%[svm]) \n\t"
2500                 "mov %%r12, %c[r12](%[svm]) \n\t"
2501                 "mov %%r13, %c[r13](%[svm]) \n\t"
2502                 "mov %%r14, %c[r14](%[svm]) \n\t"
2503                 "mov %%r15, %c[r15](%[svm]) \n\t"
2504 #endif
2505                 "pop %%"R"bp"
2506                 :
2507                 : [svm]"a"(svm),
2508                   [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)),
2509                   [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])),
2510                   [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])),
2511                   [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])),
2512                   [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])),
2513                   [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])),
2514                   [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP]))
2515 #ifdef CONFIG_X86_64
2516                   , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])),
2517                   [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])),
2518                   [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])),
2519                   [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])),
2520                   [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])),
2521                   [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])),
2522                   [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])),
2523                   [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15]))
2524 #endif
2525                 : "cc", "memory"
2526                 , R"bx", R"cx", R"dx", R"si", R"di"
2527 #ifdef CONFIG_X86_64
2528                 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
2529 #endif
2530                 );
2531
2532         vcpu->arch.cr2 = svm->vmcb->save.cr2;
2533         vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
2534         vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
2535         vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
2536
2537         kvm_write_cr2(svm->host_cr2);
2538
2539         kvm_load_fs(fs_selector);
2540         kvm_load_gs(gs_selector);
2541         kvm_load_ldt(ldt_selector);
2542         load_host_msrs(vcpu);
2543
2544         reload_tss(vcpu);
2545
2546         local_irq_disable();
2547
2548         stgi();
2549
2550         sync_cr8_to_lapic(vcpu);
2551
2552         svm->next_rip = 0;
2553 }
2554
2555 #undef R
2556
2557 static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
2558 {
2559         struct vcpu_svm *svm = to_svm(vcpu);
2560
2561         if (npt_enabled) {
2562                 svm->vmcb->control.nested_cr3 = root;
2563                 force_new_asid(vcpu);
2564                 return;
2565         }
2566
2567         svm->vmcb->save.cr3 = root;
2568         force_new_asid(vcpu);
2569
2570         if (vcpu->fpu_active) {
2571                 svm->vmcb->control.intercept_exceptions |= (1 << NM_VECTOR);
2572                 svm->vmcb->save.cr0 |= X86_CR0_TS;
2573                 vcpu->fpu_active = 0;
2574         }
2575 }
2576
2577 static int is_disabled(void)
2578 {
2579         u64 vm_cr;
2580
2581         rdmsrl(MSR_VM_CR, vm_cr);
2582         if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
2583                 return 1;
2584
2585         return 0;
2586 }
2587
2588 static void
2589 svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
2590 {
2591         /*
2592          * Patch in the VMMCALL instruction:
2593          */
2594         hypercall[0] = 0x0f;
2595         hypercall[1] = 0x01;
2596         hypercall[2] = 0xd9;
2597 }
2598
2599 static void svm_check_processor_compat(void *rtn)
2600 {
2601         *(int *)rtn = 0;
2602 }
2603
2604 static bool svm_cpu_has_accelerated_tpr(void)
2605 {
2606         return false;
2607 }
2608
2609 static int get_npt_level(void)
2610 {
2611 #ifdef CONFIG_X86_64
2612         return PT64_ROOT_LEVEL;
2613 #else
2614         return PT32E_ROOT_LEVEL;
2615 #endif
2616 }
2617
2618 static int svm_get_mt_mask_shift(void)
2619 {
2620         return 0;
2621 }
2622
2623 static struct kvm_x86_ops svm_x86_ops = {
2624         .cpu_has_kvm_support = has_svm,
2625         .disabled_by_bios = is_disabled,
2626         .hardware_setup = svm_hardware_setup,
2627         .hardware_unsetup = svm_hardware_unsetup,
2628         .check_processor_compatibility = svm_check_processor_compat,
2629         .hardware_enable = svm_hardware_enable,
2630         .hardware_disable = svm_hardware_disable,
2631         .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
2632
2633         .vcpu_create = svm_create_vcpu,
2634         .vcpu_free = svm_free_vcpu,
2635         .vcpu_reset = svm_vcpu_reset,
2636
2637         .prepare_guest_switch = svm_prepare_guest_switch,
2638         .vcpu_load = svm_vcpu_load,
2639         .vcpu_put = svm_vcpu_put,
2640
2641         .set_guest_debug = svm_guest_debug,
2642         .get_msr = svm_get_msr,
2643         .set_msr = svm_set_msr,
2644         .get_segment_base = svm_get_segment_base,
2645         .get_segment = svm_get_segment,
2646         .set_segment = svm_set_segment,
2647         .get_cpl = svm_get_cpl,
2648         .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
2649         .decache_cr4_guest_bits = svm_decache_cr4_guest_bits,
2650         .set_cr0 = svm_set_cr0,
2651         .set_cr3 = svm_set_cr3,
2652         .set_cr4 = svm_set_cr4,
2653         .set_efer = svm_set_efer,
2654         .get_idt = svm_get_idt,
2655         .set_idt = svm_set_idt,
2656         .get_gdt = svm_get_gdt,
2657         .set_gdt = svm_set_gdt,
2658         .get_dr = svm_get_dr,
2659         .set_dr = svm_set_dr,
2660         .get_rflags = svm_get_rflags,
2661         .set_rflags = svm_set_rflags,
2662
2663         .tlb_flush = svm_flush_tlb,
2664
2665         .run = svm_vcpu_run,
2666         .handle_exit = handle_exit,
2667         .skip_emulated_instruction = skip_emulated_instruction,
2668         .patch_hypercall = svm_patch_hypercall,
2669         .get_irq = svm_get_irq,
2670         .set_irq = svm_set_irq,
2671         .queue_exception = svm_queue_exception,
2672         .exception_injected = svm_exception_injected,
2673         .inject_pending_irq = svm_intr_assist,
2674         .inject_pending_vectors = do_interrupt_requests,
2675
2676         .set_tss_addr = svm_set_tss_addr,
2677         .get_tdp_level = get_npt_level,
2678         .get_mt_mask_shift = svm_get_mt_mask_shift,
2679 };
2680
2681 static int __init svm_init(void)
2682 {
2683         return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm),
2684                               THIS_MODULE);
2685 }
2686
2687 static void __exit svm_exit(void)
2688 {
2689         kvm_exit();
2690 }
2691
2692 module_init(svm_init)
2693 module_exit(svm_exit)