[SPARC64]: Beginnings of SUN4V PCI controller support.
[linux-2.6] / include / asm-i386 / mmu_context.h
1 #ifndef __I386_SCHED_H
2 #define __I386_SCHED_H
3
4 #include <linux/config.h>
5 #include <asm/desc.h>
6 #include <asm/atomic.h>
7 #include <asm/pgalloc.h>
8 #include <asm/tlbflush.h>
9
10 /*
11  * Used for LDT copy/destruction.
12  */
13 int init_new_context(struct task_struct *tsk, struct mm_struct *mm);
14 void destroy_context(struct mm_struct *mm);
15
16
17 static inline void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk)
18 {
19 #ifdef CONFIG_SMP
20         unsigned cpu = smp_processor_id();
21         if (per_cpu(cpu_tlbstate, cpu).state == TLBSTATE_OK)
22                 per_cpu(cpu_tlbstate, cpu).state = TLBSTATE_LAZY;
23 #endif
24 }
25
26 static inline void switch_mm(struct mm_struct *prev,
27                              struct mm_struct *next,
28                              struct task_struct *tsk)
29 {
30         int cpu = smp_processor_id();
31
32         if (likely(prev != next)) {
33                 /* stop flush ipis for the previous mm */
34                 cpu_clear(cpu, prev->cpu_vm_mask);
35 #ifdef CONFIG_SMP
36                 per_cpu(cpu_tlbstate, cpu).state = TLBSTATE_OK;
37                 per_cpu(cpu_tlbstate, cpu).active_mm = next;
38 #endif
39                 cpu_set(cpu, next->cpu_vm_mask);
40
41                 /* Re-load page tables */
42                 load_cr3(next->pgd);
43
44                 /*
45                  * load the LDT, if the LDT is different:
46                  */
47                 if (unlikely(prev->context.ldt != next->context.ldt))
48                         load_LDT_nolock(&next->context, cpu);
49         }
50 #ifdef CONFIG_SMP
51         else {
52                 per_cpu(cpu_tlbstate, cpu).state = TLBSTATE_OK;
53                 BUG_ON(per_cpu(cpu_tlbstate, cpu).active_mm != next);
54
55                 if (!cpu_test_and_set(cpu, next->cpu_vm_mask)) {
56                         /* We were in lazy tlb mode and leave_mm disabled 
57                          * tlb flush IPI delivery. We must reload %cr3.
58                          */
59                         load_cr3(next->pgd);
60                         load_LDT_nolock(&next->context, cpu);
61                 }
62         }
63 #endif
64 }
65
66 #define deactivate_mm(tsk, mm) \
67         asm("movl %0,%%fs ; movl %0,%%gs": :"r" (0))
68
69 #define activate_mm(prev, next) \
70         switch_mm((prev),(next),NULL)
71
72 #endif