Merge branch 'master' of master.kernel.org:/pub/scm/linux/kernel/git/cooloney/blackfi...
[linux-2.6] / arch / blackfin / kernel / setup.c
1 /*
2  * File:         arch/blackfin/kernel/setup.c
3  * Based on:
4  * Author:
5  *
6  * Created:
7  * Description:
8  *
9  * Modified:
10  *               Copyright 2004-2006 Analog Devices Inc.
11  *
12  * Bugs:         Enter bugs at http://blackfin.uclinux.org/
13  *
14  * This program is free software; you can redistribute it and/or modify
15  * it under the terms of the GNU General Public License as published by
16  * the Free Software Foundation; either version 2 of the License, or
17  * (at your option) any later version.
18  *
19  * This program is distributed in the hope that it will be useful,
20  * but WITHOUT ANY WARRANTY; without even the implied warranty of
21  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
22  * GNU General Public License for more details.
23  *
24  * You should have received a copy of the GNU General Public License
25  * along with this program; if not, see the file COPYING, or write
26  * to the Free Software Foundation, Inc.,
27  * 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
28  */
29
30 #include <linux/delay.h>
31 #include <linux/console.h>
32 #include <linux/bootmem.h>
33 #include <linux/seq_file.h>
34 #include <linux/cpu.h>
35 #include <linux/module.h>
36 #include <linux/tty.h>
37
38 #include <linux/ext2_fs.h>
39 #include <linux/cramfs_fs.h>
40 #include <linux/romfs_fs.h>
41
42 #include <asm/cacheflush.h>
43 #include <asm/blackfin.h>
44 #include <asm/cplbinit.h>
45
46 u16 _bfin_swrst;
47
48 unsigned long memory_start, memory_end, physical_mem_end;
49 unsigned long reserved_mem_dcache_on;
50 unsigned long reserved_mem_icache_on;
51 EXPORT_SYMBOL(memory_start);
52 EXPORT_SYMBOL(memory_end);
53 EXPORT_SYMBOL(physical_mem_end);
54 EXPORT_SYMBOL(_ramend);
55
56 #ifdef CONFIG_MTD_UCLINUX
57 unsigned long memory_mtd_end, memory_mtd_start, mtd_size;
58 unsigned long _ebss;
59 EXPORT_SYMBOL(memory_mtd_end);
60 EXPORT_SYMBOL(memory_mtd_start);
61 EXPORT_SYMBOL(mtd_size);
62 #endif
63
64 char __initdata command_line[COMMAND_LINE_SIZE];
65
66 #if defined(CONFIG_BLKFIN_DCACHE) || defined(CONFIG_BLKFIN_CACHE)
67 static void generate_cpl_tables(void);
68 #endif
69
70 void __init bf53x_cache_init(void)
71 {
72 #if defined(CONFIG_BLKFIN_DCACHE) || defined(CONFIG_BLKFIN_CACHE)
73         generate_cpl_tables();
74 #endif
75
76 #ifdef CONFIG_BLKFIN_CACHE
77         bfin_icache_init();
78         printk(KERN_INFO "Instruction Cache Enabled\n");
79 #endif
80
81 #ifdef CONFIG_BLKFIN_DCACHE
82         bfin_dcache_init();
83         printk(KERN_INFO "Data Cache Enabled"
84 # if defined CONFIG_BLKFIN_WB
85                 " (write-back)"
86 # elif defined CONFIG_BLKFIN_WT
87                 " (write-through)"
88 # endif
89                 "\n");
90 #endif
91 }
92
93 void __init bf53x_relocate_l1_mem(void)
94 {
95         unsigned long l1_code_length;
96         unsigned long l1_data_a_length;
97         unsigned long l1_data_b_length;
98
99         l1_code_length = _etext_l1 - _stext_l1;
100         if (l1_code_length > L1_CODE_LENGTH)
101                 l1_code_length = L1_CODE_LENGTH;
102         /* cannot complain as printk is not available as yet.
103          * But we can continue booting and complain later!
104          */
105
106         /* Copy _stext_l1 to _etext_l1 to L1 instruction SRAM */
107         dma_memcpy(_stext_l1, _l1_lma_start, l1_code_length);
108
109         l1_data_a_length = _ebss_l1 - _sdata_l1;
110         if (l1_data_a_length > L1_DATA_A_LENGTH)
111                 l1_data_a_length = L1_DATA_A_LENGTH;
112
113         /* Copy _sdata_l1 to _ebss_l1 to L1 data bank A SRAM */
114         dma_memcpy(_sdata_l1, _l1_lma_start + l1_code_length, l1_data_a_length);
115
116         l1_data_b_length = _ebss_b_l1 - _sdata_b_l1;
117         if (l1_data_b_length > L1_DATA_B_LENGTH)
118                 l1_data_b_length = L1_DATA_B_LENGTH;
119
120         /* Copy _sdata_b_l1 to _ebss_b_l1 to L1 data bank B SRAM */
121         dma_memcpy(_sdata_b_l1, _l1_lma_start + l1_code_length +
122                         l1_data_a_length, l1_data_b_length);
123
124 }
125
126 /*
127  * Initial parsing of the command line.  Currently, we support:
128  *  - Controlling the linux memory size: mem=xxx[KMG]
129  *  - Controlling the physical memory size: max_mem=xxx[KMG][$][#]
130  *       $ -> reserved memory is dcacheable
131  *       # -> reserved memory is icacheable
132  */
133 static __init void parse_cmdline_early(char *cmdline_p)
134 {
135         char c = ' ', *to = cmdline_p;
136         unsigned int memsize;
137         for (;;) {
138                 if (c == ' ') {
139
140                         if (!memcmp(to, "mem=", 4)) {
141                                 to += 4;
142                                 memsize = memparse(to, &to);
143                                 if (memsize)
144                                         _ramend = memsize;
145
146                         } else if (!memcmp(to, "max_mem=", 8)) {
147                                 to += 8;
148                                 memsize = memparse(to, &to);
149                                 if (memsize) {
150                                         physical_mem_end = memsize;
151                                         if (*to != ' ') {
152                                                 if (*to == '$'
153                                                     || *(to + 1) == '$')
154                                                         reserved_mem_dcache_on =
155                                                             1;
156                                                 if (*to == '#'
157                                                     || *(to + 1) == '#')
158                                                         reserved_mem_icache_on =
159                                                             1;
160                                         }
161                                 }
162                         }
163
164                 }
165                 c = *(to++);
166                 if (!c)
167                         break;
168         }
169 }
170
171 void __init setup_arch(char **cmdline_p)
172 {
173         int bootmap_size;
174         unsigned long l1_length, sclk, cclk;
175 #ifdef CONFIG_MTD_UCLINUX
176         unsigned long mtd_phys = 0;
177 #endif
178
179 #ifdef CONFIG_DUMMY_CONSOLE
180         conswitchp = &dummy_con;
181 #endif
182         cclk = get_cclk();
183         sclk = get_sclk();
184
185 #if !defined(CONFIG_BFIN_KERNEL_CLOCK) && defined(ANOMALY_05000273)
186         if (cclk == sclk)
187                 panic("ANOMALY 05000273, SCLK can not be same as CCLK");
188 #endif
189
190 #if defined(ANOMALY_05000266)
191         bfin_read_IMDMA_D0_IRQ_STATUS();
192         bfin_read_IMDMA_D1_IRQ_STATUS();
193 #endif
194
195 #ifdef DEBUG_SERIAL_EARLY_INIT
196         bfin_console_init();    /* early console registration */
197         /* this give a chance to get printk() working before crash. */
198 #endif
199
200 #if defined(CONFIG_CHR_DEV_FLASH) || defined(CONFIG_BLK_DEV_FLASH)
201         /* we need to initialize the Flashrom device here since we might
202          * do things with flash early on in the boot
203          */
204         flash_probe();
205 #endif
206
207 #if defined(CONFIG_CMDLINE_BOOL)
208         strncpy(&command_line[0], CONFIG_CMDLINE, sizeof(command_line));
209         command_line[sizeof(command_line) - 1] = 0;
210 #endif
211
212         /* Keep a copy of command line */
213         *cmdline_p = &command_line[0];
214         memcpy(boot_command_line, command_line, COMMAND_LINE_SIZE);
215         boot_command_line[COMMAND_LINE_SIZE - 1] = '\0';
216
217         /* setup memory defaults from the user config */
218         physical_mem_end = 0;
219         _ramend = CONFIG_MEM_SIZE * 1024 * 1024;
220
221         parse_cmdline_early(&command_line[0]);
222
223         if (physical_mem_end == 0)
224                 physical_mem_end = _ramend;
225
226         /* by now the stack is part of the init task */
227         memory_end = _ramend - DMA_UNCACHED_REGION;
228
229         _ramstart = (unsigned long)__bss_stop;
230         memory_start = PAGE_ALIGN(_ramstart);
231
232 #if defined(CONFIG_MTD_UCLINUX)
233         /* generic memory mapped MTD driver */
234         memory_mtd_end = memory_end;
235
236         mtd_phys = _ramstart;
237         mtd_size = PAGE_ALIGN(*((unsigned long *)(mtd_phys + 8)));
238
239 # if defined(CONFIG_EXT2_FS) || defined(CONFIG_EXT3_FS)
240         if (*((unsigned short *)(mtd_phys + 0x438)) == EXT2_SUPER_MAGIC)
241                 mtd_size =
242                     PAGE_ALIGN(*((unsigned long *)(mtd_phys + 0x404)) << 10);
243 # endif
244
245 # if defined(CONFIG_CRAMFS)
246         if (*((unsigned long *)(mtd_phys)) == CRAMFS_MAGIC)
247                 mtd_size = PAGE_ALIGN(*((unsigned long *)(mtd_phys + 0x4)));
248 # endif
249
250 # if defined(CONFIG_ROMFS_FS)
251         if (((unsigned long *)mtd_phys)[0] == ROMSB_WORD0
252             && ((unsigned long *)mtd_phys)[1] == ROMSB_WORD1)
253                 mtd_size =
254                     PAGE_ALIGN(be32_to_cpu(((unsigned long *)mtd_phys)[2]));
255 #  if (defined(CONFIG_BLKFIN_CACHE) && defined(ANOMALY_05000263))
256         /* Due to a Hardware Anomaly we need to limit the size of usable
257          * instruction memory to max 60MB, 56 if HUNT_FOR_ZERO is on
258          * 05000263 - Hardware loop corrupted when taking an ICPLB exception
259          */
260 #   if (defined(CONFIG_DEBUG_HUNT_FOR_ZERO))
261         if (memory_end >= 56 * 1024 * 1024)
262                 memory_end = 56 * 1024 * 1024;
263 #   else
264         if (memory_end >= 60 * 1024 * 1024)
265                 memory_end = 60 * 1024 * 1024;
266 #   endif                               /* CONFIG_DEBUG_HUNT_FOR_ZERO */
267 #  endif                                /* ANOMALY_05000263 */
268 # endif                         /* CONFIG_ROMFS_FS */
269
270         memory_end -= mtd_size;
271
272         if (mtd_size == 0) {
273                 console_init();
274                 panic("Don't boot kernel without rootfs attached.\n");
275         }
276
277         /* Relocate MTD image to the top of memory after the uncached memory area */
278         dma_memcpy((char *)memory_end, __bss_stop, mtd_size);
279
280         memory_mtd_start = memory_end;
281         _ebss = memory_mtd_start;       /* define _ebss for compatible */
282 #endif                          /* CONFIG_MTD_UCLINUX */
283
284 #if (defined(CONFIG_BLKFIN_CACHE) && defined(ANOMALY_05000263))
285         /* Due to a Hardware Anomaly we need to limit the size of usable
286          * instruction memory to max 60MB, 56 if HUNT_FOR_ZERO is on
287          * 05000263 - Hardware loop corrupted when taking an ICPLB exception
288          */
289 #if (defined(CONFIG_DEBUG_HUNT_FOR_ZERO))
290         if (memory_end >= 56 * 1024 * 1024)
291                 memory_end = 56 * 1024 * 1024;
292 #else
293         if (memory_end >= 60 * 1024 * 1024)
294                 memory_end = 60 * 1024 * 1024;
295 #endif                          /* CONFIG_DEBUG_HUNT_FOR_ZERO */
296         printk(KERN_NOTICE "Warning: limiting memory to %liMB due to hardware anomaly 05000263\n", memory_end >> 20);
297 #endif                          /* ANOMALY_05000263 */
298
299 #if !defined(CONFIG_MTD_UCLINUX)
300         memory_end -= SIZE_4K; /*In case there is no valid CPLB behind memory_end make sure we don't get to close*/
301 #endif
302         init_mm.start_code = (unsigned long)_stext;
303         init_mm.end_code = (unsigned long)_etext;
304         init_mm.end_data = (unsigned long)_edata;
305         init_mm.brk = (unsigned long)0;
306
307         init_leds();
308
309         printk(KERN_INFO "Blackfin support (C) 2004-2007 Analog Devices, Inc.\n");
310         printk(KERN_INFO "Compiled for ADSP-%s Rev 0.%d\n", CPU, bfin_compiled_revid());
311         if (bfin_revid() != bfin_compiled_revid())
312                 printk(KERN_ERR "Warning: Compiled for Rev %d, but running on Rev %d\n",
313                        bfin_compiled_revid(), bfin_revid());
314         if (bfin_revid() < SUPPORTED_REVID)
315                 printk(KERN_ERR "Warning: Unsupported Chip Revision ADSP-%s Rev 0.%d detected\n",
316                        CPU, bfin_revid());
317         printk(KERN_INFO "Blackfin Linux support by http://blackfin.uclinux.org/\n");
318
319         printk(KERN_INFO "Processor Speed: %lu MHz core clock and %lu Mhz System Clock\n",
320                cclk / 1000000,  sclk / 1000000);
321
322 #if defined(ANOMALY_05000273)
323         if ((cclk >> 1) <= sclk)
324                 printk("\n\n\nANOMALY_05000273: CCLK must be >= 2*SCLK !!!\n\n\n");
325 #endif
326
327         printk(KERN_INFO "Board Memory: %ldMB\n", physical_mem_end >> 20);
328         printk(KERN_INFO "Kernel Managed Memory: %ldMB\n", _ramend >> 20);
329
330         printk(KERN_INFO "Memory map:\n"
331                KERN_INFO "  text      = 0x%p-0x%p\n"
332                KERN_INFO "  init      = 0x%p-0x%p\n"
333                KERN_INFO "  data      = 0x%p-0x%p\n"
334                KERN_INFO "  stack     = 0x%p-0x%p\n"
335                KERN_INFO "  bss       = 0x%p-0x%p\n"
336                KERN_INFO "  available = 0x%p-0x%p\n"
337 #ifdef CONFIG_MTD_UCLINUX
338                KERN_INFO "  rootfs    = 0x%p-0x%p\n"
339 #endif
340 #if DMA_UNCACHED_REGION > 0
341                KERN_INFO "  DMA Zone  = 0x%p-0x%p\n"
342 #endif
343                , _stext, _etext,
344                __init_begin, __init_end,
345                _sdata, _edata,
346                (void*)&init_thread_union, (void*)((int)(&init_thread_union) + 0x2000),
347                __bss_start, __bss_stop,
348                (void*)_ramstart, (void*)memory_end
349 #ifdef CONFIG_MTD_UCLINUX
350                , (void*)memory_mtd_start, (void*)(memory_mtd_start + mtd_size)
351 #endif
352 #if DMA_UNCACHED_REGION > 0
353                , (void*)(_ramend - DMA_UNCACHED_REGION), (void*)(_ramend)
354 #endif
355                );
356
357         /*
358          * give all the memory to the bootmap allocator,  tell it to put the
359          * boot mem_map at the start of memory
360          */
361         bootmap_size = init_bootmem_node(NODE_DATA(0), memory_start >> PAGE_SHIFT,      /* map goes here */
362                                          PAGE_OFFSET >> PAGE_SHIFT,
363                                          memory_end >> PAGE_SHIFT);
364         /*
365          * free the usable memory,  we have to make sure we do not free
366          * the bootmem bitmap so we then reserve it after freeing it :-)
367          */
368         free_bootmem(memory_start, memory_end - memory_start);
369
370         reserve_bootmem(memory_start, bootmap_size);
371         /*
372          * get kmalloc into gear
373          */
374         paging_init();
375
376         /* check the size of the l1 area */
377         l1_length = _etext_l1 - _stext_l1;
378         if (l1_length > L1_CODE_LENGTH)
379                 panic("L1 memory overflow\n");
380
381         l1_length = _ebss_l1 - _sdata_l1;
382         if (l1_length > L1_DATA_A_LENGTH)
383                 panic("L1 memory overflow\n");
384
385 #ifdef BF561_FAMILY
386         _bfin_swrst = bfin_read_SICA_SWRST();
387 #else
388         _bfin_swrst = bfin_read_SWRST();
389 #endif
390
391         bf53x_cache_init();
392
393         printk(KERN_INFO "Hardware Trace Enabled\n");
394         bfin_write_TBUFCTL(0x03);
395 }
396
397 static int __init topology_init(void)
398 {
399 #if defined (CONFIG_BF561)
400         static struct cpu cpu[2];
401         register_cpu(&cpu[0], 0);
402         register_cpu(&cpu[1], 1);
403         return 0;
404 #else
405         static struct cpu cpu[1];
406         return register_cpu(cpu, 0);
407 #endif
408 }
409
410 subsys_initcall(topology_init);
411
412 #if defined(CONFIG_BLKFIN_DCACHE) || defined(CONFIG_BLKFIN_CACHE)
413 static u16 __init lock_kernel_check(u32 start, u32 end)
414 {
415         if ((start <= (u32) _stext && end >= (u32) _end)
416             || (start >= (u32) _stext && end <= (u32) _end))
417                 return IN_KERNEL;
418         return 0;
419 }
420
421 static unsigned short __init
422 fill_cplbtab(struct cplb_tab *table,
423              unsigned long start, unsigned long end,
424              unsigned long block_size, unsigned long cplb_data)
425 {
426         int i;
427
428         switch (block_size) {
429         case SIZE_4M:
430                 i = 3;
431                 break;
432         case SIZE_1M:
433                 i = 2;
434                 break;
435         case SIZE_4K:
436                 i = 1;
437                 break;
438         case SIZE_1K:
439         default:
440                 i = 0;
441                 break;
442         }
443
444         cplb_data = (cplb_data & ~(3 << 16)) | (i << 16);
445
446         while ((start < end) && (table->pos < table->size)) {
447
448                 table->tab[table->pos++] = start;
449
450                 if (lock_kernel_check(start, start + block_size) == IN_KERNEL)
451                         table->tab[table->pos++] =
452                             cplb_data | CPLB_LOCK | CPLB_DIRTY;
453                 else
454                         table->tab[table->pos++] = cplb_data;
455
456                 start += block_size;
457         }
458         return 0;
459 }
460
461 static unsigned short __init
462 close_cplbtab(struct cplb_tab *table)
463 {
464
465         while (table->pos < table->size) {
466
467                 table->tab[table->pos++] = 0;
468                 table->tab[table->pos++] = 0; /* !CPLB_VALID */
469         }
470         return 0;
471 }
472
473 /* helper function */
474 static void __fill_code_cplbtab(struct cplb_tab *t, int i,
475                                 u32 a_start, u32 a_end)
476 {
477         if (cplb_data[i].psize) {
478                 fill_cplbtab(t,
479                                 cplb_data[i].start,
480                                 cplb_data[i].end,
481                                 cplb_data[i].psize,
482                                 cplb_data[i].i_conf);
483         } else {
484 #if (defined(CONFIG_BLKFIN_CACHE) && defined(ANOMALY_05000263))
485                 if (i == SDRAM_KERN) {
486                         fill_cplbtab(t,
487                                         cplb_data[i].start,
488                                         cplb_data[i].end,
489                                         SIZE_4M,
490                                         cplb_data[i].i_conf);
491                 } else {
492 #endif
493                         fill_cplbtab(t,
494                                         cplb_data[i].start,
495                                         a_start,
496                                         SIZE_1M,
497                                         cplb_data[i].i_conf);
498                         fill_cplbtab(t,
499                                         a_start,
500                                         a_end,
501                                         SIZE_4M,
502                                         cplb_data[i].i_conf);
503                         fill_cplbtab(t, a_end,
504                                         cplb_data[i].end,
505                                         SIZE_1M,
506                                         cplb_data[i].i_conf);
507                 }
508         }
509 }
510
511 static void __fill_data_cplbtab(struct cplb_tab *t, int i,
512                                 u32 a_start, u32 a_end)
513 {
514         if (cplb_data[i].psize) {
515                 fill_cplbtab(t,
516                                 cplb_data[i].start,
517                                 cplb_data[i].end,
518                                 cplb_data[i].psize,
519                                 cplb_data[i].d_conf);
520         } else {
521                 fill_cplbtab(t,
522                                 cplb_data[i].start,
523                                 a_start, SIZE_1M,
524                                 cplb_data[i].d_conf);
525                 fill_cplbtab(t, a_start,
526                                 a_end, SIZE_4M,
527                                 cplb_data[i].d_conf);
528                 fill_cplbtab(t, a_end,
529                                 cplb_data[i].end,
530                                 SIZE_1M,
531                                 cplb_data[i].d_conf);
532         }
533 }
534 static void __init generate_cpl_tables(void)
535 {
536
537         u16 i, j, process;
538         u32 a_start, a_end, as, ae, as_1m;
539
540         struct cplb_tab *t_i = NULL;
541         struct cplb_tab *t_d = NULL;
542         struct s_cplb cplb;
543
544         cplb.init_i.size = MAX_CPLBS;
545         cplb.init_d.size = MAX_CPLBS;
546         cplb.switch_i.size = MAX_SWITCH_I_CPLBS;
547         cplb.switch_d.size = MAX_SWITCH_D_CPLBS;
548
549         cplb.init_i.pos = 0;
550         cplb.init_d.pos = 0;
551         cplb.switch_i.pos = 0;
552         cplb.switch_d.pos = 0;
553
554         cplb.init_i.tab = icplb_table;
555         cplb.init_d.tab = dcplb_table;
556         cplb.switch_i.tab = ipdt_table;
557         cplb.switch_d.tab = dpdt_table;
558
559         cplb_data[SDRAM_KERN].end = memory_end;
560
561 #ifdef CONFIG_MTD_UCLINUX
562         cplb_data[SDRAM_RAM_MTD].start = memory_mtd_start;
563         cplb_data[SDRAM_RAM_MTD].end = memory_mtd_start + mtd_size;
564         cplb_data[SDRAM_RAM_MTD].valid = mtd_size > 0;
565 # if defined(CONFIG_ROMFS_FS)
566         cplb_data[SDRAM_RAM_MTD].attr |= I_CPLB;
567
568         /*
569          * The ROMFS_FS size is often not multiple of 1MB.
570          * This can cause multiple CPLB sets covering the same memory area.
571          * This will then cause multiple CPLB hit exceptions.
572          * Workaround: We ensure a contiguous memory area by extending the kernel
573          * memory section over the mtd section.
574          * For ROMFS_FS memory must be covered with ICPLBs anyways.
575          * So there is no difference between kernel and mtd memory setup.
576          */
577
578         cplb_data[SDRAM_KERN].end = memory_mtd_start + mtd_size;;
579         cplb_data[SDRAM_RAM_MTD].valid = 0;
580
581 # endif
582 #else
583         cplb_data[SDRAM_RAM_MTD].valid = 0;
584 #endif
585
586         cplb_data[SDRAM_DMAZ].start = _ramend - DMA_UNCACHED_REGION;
587         cplb_data[SDRAM_DMAZ].end = _ramend;
588
589         cplb_data[RES_MEM].start = _ramend;
590         cplb_data[RES_MEM].end = physical_mem_end;
591
592         if (reserved_mem_dcache_on)
593                 cplb_data[RES_MEM].d_conf = SDRAM_DGENERIC;
594         else
595                 cplb_data[RES_MEM].d_conf = SDRAM_DNON_CHBL;
596
597         if (reserved_mem_icache_on)
598                 cplb_data[RES_MEM].i_conf = SDRAM_IGENERIC;
599         else
600                 cplb_data[RES_MEM].i_conf = SDRAM_INON_CHBL;
601
602         for (i = ZERO_P; i <= L2_MEM; i++) {
603                 if (!cplb_data[i].valid)
604                         continue;
605
606                 as_1m = cplb_data[i].start % SIZE_1M;
607
608                 /*
609                  * We need to make sure all sections are properly 1M aligned
610                  * However between Kernel Memory and the Kernel mtd section,
611                  * depending on the rootfs size, there can be overlapping
612                  * memory areas.
613                  */
614
615                 if (as_1m && i != L1I_MEM && i != L1D_MEM) {
616 #ifdef CONFIG_MTD_UCLINUX
617                         if (i == SDRAM_RAM_MTD) {
618                                 if ((cplb_data[SDRAM_KERN].end + 1) >
619                                                 cplb_data[SDRAM_RAM_MTD].start)
620                                         cplb_data[SDRAM_RAM_MTD].start =
621                                                 (cplb_data[i].start &
622                                                  (-2*SIZE_1M)) + SIZE_1M;
623                                 else
624                                         cplb_data[SDRAM_RAM_MTD].start =
625                                                 (cplb_data[i].start &
626                                                  (-2*SIZE_1M));
627                         } else
628 #endif
629                                 printk(KERN_WARNING
630                                         "Unaligned Start of %s at 0x%X\n",
631                                         cplb_data[i].name, cplb_data[i].start);
632                 }
633
634                 as = cplb_data[i].start % SIZE_4M;
635                 ae = cplb_data[i].end % SIZE_4M;
636
637                 if (as)
638                         a_start = cplb_data[i].start + (SIZE_4M - (as));
639                 else
640                         a_start = cplb_data[i].start;
641
642                 a_end = cplb_data[i].end - ae;
643
644                 for (j = INITIAL_T; j <= SWITCH_T; j++) {
645
646                         switch (j) {
647                         case INITIAL_T:
648                                 if (cplb_data[i].attr & INITIAL_T) {
649                                         t_i = &cplb.init_i;
650                                         t_d = &cplb.init_d;
651                                         process = 1;
652                                 } else
653                                         process = 0;
654                                 break;
655                         case SWITCH_T:
656                                 if (cplb_data[i].attr & SWITCH_T) {
657                                         t_i = &cplb.switch_i;
658                                         t_d = &cplb.switch_d;
659                                         process = 1;
660                                 } else
661                                         process = 0;
662                                 break;
663                         default:
664                                         process = 0;
665                                 break;
666                         }
667
668                         if (!process)
669                                 continue;
670                         if (cplb_data[i].attr & I_CPLB)
671                                 __fill_code_cplbtab(t_i, i, a_start, a_end);
672
673                         if (cplb_data[i].attr & D_CPLB)
674                                 __fill_data_cplbtab(t_d, i, a_start, a_end);
675                 }
676         }
677
678 /* close tables */
679
680         close_cplbtab(&cplb.init_i);
681         close_cplbtab(&cplb.init_d);
682
683         cplb.init_i.tab[cplb.init_i.pos] = -1;
684         cplb.init_d.tab[cplb.init_d.pos] = -1;
685         cplb.switch_i.tab[cplb.switch_i.pos] = -1;
686         cplb.switch_d.tab[cplb.switch_d.pos] = -1;
687
688 }
689
690 #endif
691
692 static u_long get_vco(void)
693 {
694         u_long msel;
695         u_long vco;
696
697         msel = (bfin_read_PLL_CTL() >> 9) & 0x3F;
698         if (0 == msel)
699                 msel = 64;
700
701         vco = CONFIG_CLKIN_HZ;
702         vco >>= (1 & bfin_read_PLL_CTL());      /* DF bit */
703         vco = msel * vco;
704         return vco;
705 }
706
707 /*Get the Core clock*/
708 u_long get_cclk(void)
709 {
710         u_long csel, ssel;
711         if (bfin_read_PLL_STAT() & 0x1)
712                 return CONFIG_CLKIN_HZ;
713
714         ssel = bfin_read_PLL_DIV();
715         csel = ((ssel >> 4) & 0x03);
716         ssel &= 0xf;
717         if (ssel && ssel < (1 << csel)) /* SCLK > CCLK */
718                 return get_vco() / ssel;
719         return get_vco() >> csel;
720 }
721
722 EXPORT_SYMBOL(get_cclk);
723
724 /* Get the System clock */
725 u_long get_sclk(void)
726 {
727         u_long ssel;
728
729         if (bfin_read_PLL_STAT() & 0x1)
730                 return CONFIG_CLKIN_HZ;
731
732         ssel = (bfin_read_PLL_DIV() & 0xf);
733         if (0 == ssel) {
734                 printk(KERN_WARNING "Invalid System Clock\n");
735                 ssel = 1;
736         }
737
738         return get_vco() / ssel;
739 }
740
741 EXPORT_SYMBOL(get_sclk);
742
743 /*
744  *      Get CPU information for use by the procfs.
745  */
746 static int show_cpuinfo(struct seq_file *m, void *v)
747 {
748         char *cpu, *mmu, *fpu, *name;
749         uint32_t revid;
750
751         u_long cclk = 0, sclk = 0;
752         u_int dcache_size = 0, dsup_banks = 0;
753
754         cpu = CPU;
755         mmu = "none";
756         fpu = "none";
757         revid = bfin_revid();
758         name = bfin_board_name;
759
760         cclk = get_cclk();
761         sclk = get_sclk();
762
763         seq_printf(m, "CPU:\t\tADSP-%s Rev. 0.%d\n"
764                    "MMU:\t\t%s\n"
765                    "FPU:\t\t%s\n"
766                    "Core Clock:\t%9lu Hz\n"
767                    "System Clock:\t%9lu Hz\n"
768                    "BogoMips:\t%lu.%02lu\n"
769                    "Calibration:\t%lu loops\n",
770                    cpu, revid, mmu, fpu,
771                    cclk,
772                    sclk,
773                    (loops_per_jiffy * HZ) / 500000,
774                    ((loops_per_jiffy * HZ) / 5000) % 100,
775                    (loops_per_jiffy * HZ));
776         seq_printf(m, "Board Name:\t%s\n", name);
777         seq_printf(m, "Board Memory:\t%ld MB\n", physical_mem_end >> 20);
778         seq_printf(m, "Kernel Memory:\t%ld MB\n", (unsigned long)_ramend >> 20);
779         if (bfin_read_IMEM_CONTROL() & (ENICPLB | IMC))
780                 seq_printf(m, "I-CACHE:\tON\n");
781         else
782                 seq_printf(m, "I-CACHE:\tOFF\n");
783         if ((bfin_read_DMEM_CONTROL()) & (ENDCPLB | DMC_ENABLE))
784                 seq_printf(m, "D-CACHE:\tON"
785 #if defined CONFIG_BLKFIN_WB
786                            " (write-back)"
787 #elif defined CONFIG_BLKFIN_WT
788                            " (write-through)"
789 #endif
790                            "\n");
791         else
792                 seq_printf(m, "D-CACHE:\tOFF\n");
793
794
795         switch(bfin_read_DMEM_CONTROL() & (1 << DMC0_P | 1 << DMC1_P)) {
796                 case ACACHE_BSRAM:
797                         seq_printf(m, "DBANK-A:\tCACHE\n" "DBANK-B:\tSRAM\n");
798                         dcache_size = 16;
799                         dsup_banks = 1;
800                         break;
801                 case ACACHE_BCACHE:
802                         seq_printf(m, "DBANK-A:\tCACHE\n" "DBANK-B:\tCACHE\n");
803                         dcache_size = 32;
804                         dsup_banks = 2;
805                         break;
806                 case ASRAM_BSRAM:
807                         seq_printf(m, "DBANK-A:\tSRAM\n" "DBANK-B:\tSRAM\n");
808                         dcache_size = 0;
809                         dsup_banks = 0;
810                         break;
811                 default:
812                 break;
813         }
814
815
816         seq_printf(m, "I-CACHE Size:\t%dKB\n", BLKFIN_ICACHESIZE / 1024);
817         seq_printf(m, "D-CACHE Size:\t%dKB\n", dcache_size);
818         seq_printf(m, "I-CACHE Setup:\t%d Sub-banks/%d Ways, %d Lines/Way\n",
819                    BLKFIN_ISUBBANKS, BLKFIN_IWAYS, BLKFIN_ILINES);
820         seq_printf(m,
821                    "D-CACHE Setup:\t%d Super-banks/%d Sub-banks/%d Ways, %d Lines/Way\n",
822                    dsup_banks, BLKFIN_DSUBBANKS, BLKFIN_DWAYS,
823                    BLKFIN_DLINES);
824 #ifdef CONFIG_BLKFIN_CACHE_LOCK
825         switch (read_iloc()) {
826         case WAY0_L:
827                 seq_printf(m, "Way0 Locked-Down\n");
828                 break;
829         case WAY1_L:
830                 seq_printf(m, "Way1 Locked-Down\n");
831                 break;
832         case WAY01_L:
833                 seq_printf(m, "Way0,Way1 Locked-Down\n");
834                 break;
835         case WAY2_L:
836                 seq_printf(m, "Way2 Locked-Down\n");
837                 break;
838         case WAY02_L:
839                 seq_printf(m, "Way0,Way2 Locked-Down\n");
840                 break;
841         case WAY12_L:
842                 seq_printf(m, "Way1,Way2 Locked-Down\n");
843                 break;
844         case WAY012_L:
845                 seq_printf(m, "Way0,Way1 & Way2 Locked-Down\n");
846                 break;
847         case WAY3_L:
848                 seq_printf(m, "Way3 Locked-Down\n");
849                 break;
850         case WAY03_L:
851                 seq_printf(m, "Way0,Way3 Locked-Down\n");
852                 break;
853         case WAY13_L:
854                 seq_printf(m, "Way1,Way3 Locked-Down\n");
855                 break;
856         case WAY013_L:
857                 seq_printf(m, "Way 0,Way1,Way3 Locked-Down\n");
858                 break;
859         case WAY32_L:
860                 seq_printf(m, "Way3,Way2 Locked-Down\n");
861                 break;
862         case WAY320_L:
863                 seq_printf(m, "Way3,Way2,Way0 Locked-Down\n");
864                 break;
865         case WAY321_L:
866                 seq_printf(m, "Way3,Way2,Way1 Locked-Down\n");
867                 break;
868         case WAYALL_L:
869                 seq_printf(m, "All Ways are locked\n");
870                 break;
871         default:
872                 seq_printf(m, "No Ways are locked\n");
873         }
874 #endif
875         return 0;
876 }
877
878 static void *c_start(struct seq_file *m, loff_t *pos)
879 {
880         return *pos < NR_CPUS ? ((void *)0x12345678) : NULL;
881 }
882
883 static void *c_next(struct seq_file *m, void *v, loff_t *pos)
884 {
885         ++*pos;
886         return c_start(m, pos);
887 }
888
889 static void c_stop(struct seq_file *m, void *v)
890 {
891 }
892
893 struct seq_operations cpuinfo_op = {
894         .start = c_start,
895         .next = c_next,
896         .stop = c_stop,
897         .show = show_cpuinfo,
898 };
899
900 void __init cmdline_init(const char *r0)
901 {
902         if (r0)
903                 strncpy(command_line, r0, COMMAND_LINE_SIZE);
904 }