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   1 /*
   2  * arch/arm/mach-pnx4008/irq.c
   3  *
   4  * PNX4008 IRQ controller driver
   5  *
   6  * Author: Dmitry Chigirev <source@mvista.com>
   7  *
   8  * Based on reference code received from Philips:
   9  * Copyright (C) 2003 Philips Semiconductors
  10  *
  11  * 2005 (c) MontaVista Software, Inc. This file is licensed under
  12  * the terms of the GNU General Public License version 2. This program
  13  * is licensed "as is" without any warranty of any kind, whether express
  14  * or implied.
  15  */
  16
  17 #include <linux/kernel.h>
  18 #include <linux/types.h>
  19 #include <linux/mm.h>
  20 #include <linux/interrupt.h>
  21 #include <linux/list.h>
  22 #include <linux/init.h>
  23 #include <linux/ioport.h>
  24 #include <linux/device.h>
  25 #include <linux/irq.h>
  26 #include <asm/hardware.h>
  27 #include <asm/io.h>
  28 #include <asm/setup.h>
  29 #include <asm/mach-types.h>
  30 #include <asm/pgtable.h>
  31 #include <asm/page.h>
  32 #include <asm/system.h>
  33 #include <asm/mach/arch.h>
  34 #include <asm/mach/irq.h>
  35 #include <asm/mach/map.h>
  36 #include <asm/arch/irq.h>
  37
  38 static u8 pnx4008_irq_type[NR_IRQS] = PNX4008_IRQ_TYPES;
  39
  40 static void pnx4008_mask_irq(unsigned int irq)
  41 {
  42         __raw_writel(__raw_readl(INTC_ER(irq)) & ~INTC_BIT(irq), INTC_ER(irq)); /* mask interrupt */
  43 }
  44
  45 static void pnx4008_unmask_irq(unsigned int irq)
  46 {
  47         __raw_writel(__raw_readl(INTC_ER(irq)) | INTC_BIT(irq), INTC_ER(irq));  /* unmask interrupt */
  48 }
  49
  50 static void pnx4008_mask_ack_irq(unsigned int irq)
  51 {
  52         __raw_writel(__raw_readl(INTC_ER(irq)) & ~INTC_BIT(irq), INTC_ER(irq)); /* mask interrupt */
  53         __raw_writel(INTC_BIT(irq), INTC_SR(irq));      /* clear interrupt status */
  54 }
  55
  56 static int pnx4008_set_irq_type(unsigned int irq, unsigned int type)
  57 {
  58         switch (type) {
  59         case IRQT_RISING:
  60                 __raw_writel(__raw_readl(INTC_ATR(irq)) | INTC_BIT(irq), INTC_ATR(irq));        /*edge sensitive */
  61                 __raw_writel(__raw_readl(INTC_APR(irq)) | INTC_BIT(irq), INTC_APR(irq));        /*rising edge */
  62                 set_irq_handler(irq, handle_edge_irq);
  63                 break;
  64         case IRQT_FALLING:
  65                 __raw_writel(__raw_readl(INTC_ATR(irq)) | INTC_BIT(irq), INTC_ATR(irq));        /*edge sensitive */
  66                 __raw_writel(__raw_readl(INTC_APR(irq)) & ~INTC_BIT(irq), INTC_APR(irq));       /*falling edge */
  67                 set_irq_handler(irq, handle_edge_irq);
  68                 break;
  69         case IRQT_LOW:
  70                 __raw_writel(__raw_readl(INTC_ATR(irq)) & ~INTC_BIT(irq), INTC_ATR(irq));       /*level sensitive */
  71                 __raw_writel(__raw_readl(INTC_APR(irq)) & ~INTC_BIT(irq), INTC_APR(irq));       /*low level */
  72                 set_irq_handler(irq, handle_level_irq);
  73                 break;
  74         case IRQT_HIGH:
  75                 __raw_writel(__raw_readl(INTC_ATR(irq)) & ~INTC_BIT(irq), INTC_ATR(irq));       /*level sensitive */
  76                 __raw_writel(__raw_readl(INTC_APR(irq)) | INTC_BIT(irq), INTC_APR(irq));        /* high level */
  77                 set_irq_handler(irq, handle_level_irq);
  78                 break;
  79
  80         /* IRQT_BOTHEDGE is not supported */
  81         default:
  82                 printk(KERN_ERR "PNX4008 IRQ: Unsupported irq type %d\n", type);
  83                 return -1;
  84         }
  85         return 0;
  86 }
  87
  88 static struct irq_chip pnx4008_irq_chip = {
  89         .ack = pnx4008_mask_ack_irq,
  90         .mask = pnx4008_mask_irq,
  91         .unmask = pnx4008_unmask_irq,
  92         .set_type = pnx4008_set_irq_type,
  93 };
  94
  95 void __init pnx4008_init_irq(void)
  96 {
  97         unsigned int i;
  98
  99         /* configure IRQ's */
 100         for (i = 0; i < NR_IRQS; i++) {
 101                 set_irq_flags(i, IRQF_VALID);
 102                 set_irq_chip(i, &pnx4008_irq_chip);
 103                 pnx4008_set_irq_type(i, pnx4008_irq_type[i]);
 104         }
 105
 106         /* configure and enable IRQ 0,1,30,31 (cascade interrupts) */
 107         pnx4008_set_irq_type(SUB1_IRQ_N, pnx4008_irq_type[SUB1_IRQ_N]);
 108         pnx4008_set_irq_type(SUB2_IRQ_N, pnx4008_irq_type[SUB2_IRQ_N]);
 109         pnx4008_set_irq_type(SUB1_FIQ_N, pnx4008_irq_type[SUB1_FIQ_N]);
 110         pnx4008_set_irq_type(SUB2_FIQ_N, pnx4008_irq_type[SUB2_FIQ_N]);
 111
 112         /* mask all others */
 113         __raw_writel((1 << SUB2_FIQ_N) | (1 << SUB1_FIQ_N) |
 114                         (1 << SUB2_IRQ_N) | (1 << SUB1_IRQ_N),
 115                 INTC_ER(MAIN_BASE_INT));
 116         __raw_writel(0, INTC_ER(SIC1_BASE_INT));
 117         __raw_writel(0, INTC_ER(SIC2_BASE_INT));
 118 }
 119