Merge master.kernel.org:/pub/scm/linux/kernel/git/torvalds/linux-2.6 into next
[linux-2.6] / drivers / media / video / cx18 / cx18-firmware.c
1 /*
2  *  cx18 firmware functions
3  *
4  *  Copyright (C) 2007  Hans Verkuil <hverkuil@xs4all.nl>
5  *
6  *  This program is free software; you can redistribute it and/or modify
7  *  it under the terms of the GNU General Public License as published by
8  *  the Free Software Foundation; either version 2 of the License, or
9  *  (at your option) any later version.
10  *
11  *  This program is distributed in the hope that it will be useful,
12  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
13  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14  *  GNU General Public License for more details.
15  *
16  *  You should have received a copy of the GNU General Public License
17  *  along with this program; if not, write to the Free Software
18  *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
19  *  02111-1307  USA
20  */
21
22 #include "cx18-driver.h"
23 #include "cx18-scb.h"
24 #include "cx18-irq.h"
25 #include "cx18-firmware.h"
26 #include "cx18-cards.h"
27 #include <linux/firmware.h>
28
29 #define CX18_PROC_SOFT_RESET            0xc70010
30 #define CX18_DDR_SOFT_RESET             0xc70014
31 #define CX18_CLOCK_SELECT1              0xc71000
32 #define CX18_CLOCK_SELECT2              0xc71004
33 #define CX18_HALF_CLOCK_SELECT1         0xc71008
34 #define CX18_HALF_CLOCK_SELECT2         0xc7100C
35 #define CX18_CLOCK_POLARITY1            0xc71010
36 #define CX18_CLOCK_POLARITY2            0xc71014
37 #define CX18_ADD_DELAY_ENABLE1          0xc71018
38 #define CX18_ADD_DELAY_ENABLE2          0xc7101C
39 #define CX18_CLOCK_ENABLE1              0xc71020
40 #define CX18_CLOCK_ENABLE2              0xc71024
41
42 #define CX18_REG_BUS_TIMEOUT_EN         0xc72024
43
44 #define CX18_FAST_CLOCK_PLL_INT         0xc78000
45 #define CX18_FAST_CLOCK_PLL_FRAC        0xc78004
46 #define CX18_FAST_CLOCK_PLL_POST        0xc78008
47 #define CX18_FAST_CLOCK_PLL_PRESCALE    0xc7800C
48 #define CX18_FAST_CLOCK_PLL_ADJUST_BANDWIDTH 0xc78010
49
50 #define CX18_SLOW_CLOCK_PLL_INT         0xc78014
51 #define CX18_SLOW_CLOCK_PLL_FRAC        0xc78018
52 #define CX18_SLOW_CLOCK_PLL_POST        0xc7801C
53 #define CX18_MPEG_CLOCK_PLL_INT         0xc78040
54 #define CX18_MPEG_CLOCK_PLL_FRAC        0xc78044
55 #define CX18_MPEG_CLOCK_PLL_POST        0xc78048
56 #define CX18_PLL_POWER_DOWN             0xc78088
57 #define CX18_SW1_INT_STATUS             0xc73104
58 #define CX18_SW1_INT_ENABLE_PCI         0xc7311C
59 #define CX18_SW2_INT_SET                0xc73140
60 #define CX18_SW2_INT_STATUS             0xc73144
61 #define CX18_ADEC_CONTROL               0xc78120
62
63 #define CX18_DDR_REQUEST_ENABLE         0xc80000
64 #define CX18_DDR_CHIP_CONFIG            0xc80004
65 #define CX18_DDR_REFRESH                0xc80008
66 #define CX18_DDR_TIMING1                0xc8000C
67 #define CX18_DDR_TIMING2                0xc80010
68 #define CX18_DDR_POWER_REG              0xc8001C
69
70 #define CX18_DDR_TUNE_LANE              0xc80048
71 #define CX18_DDR_INITIAL_EMRS           0xc80054
72 #define CX18_DDR_MB_PER_ROW_7           0xc8009C
73 #define CX18_DDR_BASE_63_ADDR           0xc804FC
74
75 #define CX18_WMB_CLIENT02               0xc90108
76 #define CX18_WMB_CLIENT05               0xc90114
77 #define CX18_WMB_CLIENT06               0xc90118
78 #define CX18_WMB_CLIENT07               0xc9011C
79 #define CX18_WMB_CLIENT08               0xc90120
80 #define CX18_WMB_CLIENT09               0xc90124
81 #define CX18_WMB_CLIENT10               0xc90128
82 #define CX18_WMB_CLIENT11               0xc9012C
83 #define CX18_WMB_CLIENT12               0xc90130
84 #define CX18_WMB_CLIENT13               0xc90134
85 #define CX18_WMB_CLIENT14               0xc90138
86
87 #define CX18_DSP0_INTERRUPT_MASK        0xd0004C
88
89 /* Encoder/decoder firmware sizes */
90 #define CX18_FW_CPU_SIZE                (158332)
91 #define CX18_FW_APU_SIZE                (141200)
92
93 #define APU_ROM_SYNC1 0x6D676553 /* "mgeS" */
94 #define APU_ROM_SYNC2 0x72646548 /* "rdeH" */
95
96 struct cx18_apu_rom_seghdr {
97         u32 sync1;
98         u32 sync2;
99         u32 addr;
100         u32 size;
101 };
102
103 static int load_cpu_fw_direct(const char *fn, u8 __iomem *mem, struct cx18 *cx, long size)
104 {
105         const struct firmware *fw = NULL;
106         int retries = 3;
107         int i, j;
108         u32 __iomem *dst = (u32 __iomem *)mem;
109         const u32 *src;
110
111 retry:
112         if (!retries || request_firmware(&fw, fn, &cx->dev->dev)) {
113                 CX18_ERR("Unable to open firmware %s (must be %ld bytes)\n",
114                                 fn, size);
115                 CX18_ERR("Did you put the firmware in the hotplug firmware directory?\n");
116                 return -ENOMEM;
117         }
118
119         src = (const u32 *)fw->data;
120
121         if (fw->size != size) {
122                 /* Due to race conditions in firmware loading (esp. with
123                    udev <0.95) the wrong file was sometimes loaded. So we check
124                    filesizes to see if at least the right-sized file was
125                    loaded. If not, then we retry. */
126                 CX18_INFO("retry: file loaded was not %s (expected size %ld, got %zd)\n",
127                                 fn, size, fw->size);
128                 release_firmware(fw);
129                 retries--;
130                 goto retry;
131         }
132         for (i = 0; i < fw->size; i += 4096) {
133                 setup_page(i);
134                 for (j = i; j < fw->size && j < i + 4096; j += 4) {
135                         /* no need for endianness conversion on the ppc */
136                         __raw_writel(*src, dst);
137                         if (__raw_readl(dst) != *src) {
138                                 CX18_ERR("Mismatch at offset %x\n", i);
139                                 release_firmware(fw);
140                                 return -EIO;
141                         }
142                         dst++;
143                         src++;
144                 }
145         }
146         if (!test_bit(CX18_F_I_LOADED_FW, &cx->i_flags))
147                 CX18_INFO("loaded %s firmware (%zd bytes)\n", fn, fw->size);
148         release_firmware(fw);
149         return size;
150 }
151
152 static int load_apu_fw_direct(const char *fn, u8 __iomem *dst, struct cx18 *cx, long size)
153 {
154         const struct firmware *fw = NULL;
155         int retries = 3;
156         int i, j;
157         const u32 *src;
158         struct cx18_apu_rom_seghdr seghdr;
159         const u8 *vers;
160         u32 offset = 0;
161         u32 apu_version = 0;
162         int sz;
163
164 retry:
165         if (!retries || request_firmware(&fw, fn, &cx->dev->dev)) {
166                 CX18_ERR("unable to open firmware %s (must be %ld bytes)\n",
167                                 fn, size);
168                 CX18_ERR("did you put the firmware in the hotplug firmware directory?\n");
169                 return -ENOMEM;
170         }
171
172         src = (const u32 *)fw->data;
173         vers = fw->data + sizeof(seghdr);
174         sz = fw->size;
175
176         if (fw->size != size) {
177                 /* Due to race conditions in firmware loading (esp. with
178                    udev <0.95) the wrong file was sometimes loaded. So we check
179                    filesizes to see if at least the right-sized file was
180                    loaded. If not, then we retry. */
181                 CX18_INFO("retry: file loaded was not %s (expected size %ld, got %zd)\n",
182                                fn, size, fw->size);
183                 release_firmware(fw);
184                 retries--;
185                 goto retry;
186         }
187         apu_version = (vers[0] << 24) | (vers[4] << 16) | vers[32];
188         while (offset + sizeof(seghdr) < size) {
189                 /* TODO: byteswapping */
190                 memcpy(&seghdr, src + offset / 4, sizeof(seghdr));
191                 offset += sizeof(seghdr);
192                 if (seghdr.sync1 != APU_ROM_SYNC1 ||
193                     seghdr.sync2 != APU_ROM_SYNC2) {
194                         offset += seghdr.size;
195                         continue;
196                 }
197                 CX18_DEBUG_INFO("load segment %x-%x\n", seghdr.addr,
198                                 seghdr.addr + seghdr.size - 1);
199                 if (offset + seghdr.size > sz)
200                         break;
201                 for (i = 0; i < seghdr.size; i += 4096) {
202                         setup_page(offset + i);
203                         for (j = i; j < seghdr.size && j < i + 4096; j += 4) {
204                                 /* no need for endianness conversion on the ppc */
205                                 __raw_writel(src[(offset + j) / 4], dst + seghdr.addr + j);
206                                 if (__raw_readl(dst + seghdr.addr + j) != src[(offset + j) / 4]) {
207                                         CX18_ERR("Mismatch at offset %x\n", offset + j);
208                                         release_firmware(fw);
209                                         return -EIO;
210                                 }
211                         }
212                 }
213                 offset += seghdr.size;
214         }
215         if (!test_bit(CX18_F_I_LOADED_FW, &cx->i_flags))
216                 CX18_INFO("loaded %s firmware V%08x (%zd bytes)\n",
217                                 fn, apu_version, fw->size);
218         release_firmware(fw);
219         /* Clear bit0 for APU to start from 0 */
220         write_reg(read_reg(0xc72030) & ~1, 0xc72030);
221         return size;
222 }
223
224 void cx18_halt_firmware(struct cx18 *cx)
225 {
226         CX18_DEBUG_INFO("Preparing for firmware halt.\n");
227         write_reg(0x000F000F, CX18_PROC_SOFT_RESET); /* stop the fw */
228         write_reg(0x00020002, CX18_ADEC_CONTROL);
229 }
230
231 void cx18_init_power(struct cx18 *cx, int lowpwr)
232 {
233         /* power-down Spare and AOM PLLs */
234         /* power-up fast, slow and mpeg PLLs */
235         write_reg(0x00000008, CX18_PLL_POWER_DOWN);
236
237         /* ADEC out of sleep */
238         write_reg(0x00020000, CX18_ADEC_CONTROL);
239
240         /* The fast clock is at 200/245 MHz */
241         write_reg(lowpwr ? 0xD : 0x11, CX18_FAST_CLOCK_PLL_INT);
242         write_reg(lowpwr ? 0x1EFBF37 : 0x038E3D7, CX18_FAST_CLOCK_PLL_FRAC);
243
244         write_reg(2, CX18_FAST_CLOCK_PLL_POST);
245         write_reg(1, CX18_FAST_CLOCK_PLL_PRESCALE);
246         write_reg(4, CX18_FAST_CLOCK_PLL_ADJUST_BANDWIDTH);
247
248         /* set slow clock to 125/120 MHz */
249         write_reg(lowpwr ? 0x11 : 0x10, CX18_SLOW_CLOCK_PLL_INT);
250         write_reg(lowpwr ? 0xEBAF05 : 0x18618A8, CX18_SLOW_CLOCK_PLL_FRAC);
251         write_reg(4, CX18_SLOW_CLOCK_PLL_POST);
252
253         /* mpeg clock pll 54MHz */
254         write_reg(0xF, CX18_MPEG_CLOCK_PLL_INT);
255         write_reg(0x2BCFEF, CX18_MPEG_CLOCK_PLL_FRAC);
256         write_reg(8, CX18_MPEG_CLOCK_PLL_POST);
257
258         /* Defaults */
259         /* APU = SC or SC/2 = 125/62.5 */
260         /* EPU = SC = 125 */
261         /* DDR = FC = 180 */
262         /* ENC = SC = 125 */
263         /* AI1 = SC = 125 */
264         /* VIM2 = disabled */
265         /* PCI = FC/2 = 90 */
266         /* AI2 = disabled */
267         /* DEMUX = disabled */
268         /* AO = SC/2 = 62.5 */
269         /* SER = 54MHz */
270         /* VFC = disabled */
271         /* USB = disabled */
272
273         write_reg(lowpwr ? 0xFFFF0020 : 0x00060004, CX18_CLOCK_SELECT1);
274         write_reg(lowpwr ? 0xFFFF0004 : 0x00060006, CX18_CLOCK_SELECT2);
275
276         write_reg(0xFFFF0002, CX18_HALF_CLOCK_SELECT1);
277         write_reg(0xFFFF0104, CX18_HALF_CLOCK_SELECT2);
278
279         write_reg(0xFFFF9026, CX18_CLOCK_ENABLE1);
280         write_reg(0xFFFF3105, CX18_CLOCK_ENABLE2);
281 }
282
283 void cx18_init_memory(struct cx18 *cx)
284 {
285         cx18_msleep_timeout(10, 0);
286         write_reg(0x10000, CX18_DDR_SOFT_RESET);
287         cx18_msleep_timeout(10, 0);
288
289         write_reg(cx->card->ddr.chip_config, CX18_DDR_CHIP_CONFIG);
290
291         cx18_msleep_timeout(10, 0);
292
293         write_reg(cx->card->ddr.refresh, CX18_DDR_REFRESH);
294         write_reg(cx->card->ddr.timing1, CX18_DDR_TIMING1);
295         write_reg(cx->card->ddr.timing2, CX18_DDR_TIMING2);
296
297         cx18_msleep_timeout(10, 0);
298
299         /* Initialize DQS pad time */
300         write_reg(cx->card->ddr.tune_lane, CX18_DDR_TUNE_LANE);
301         write_reg(cx->card->ddr.initial_emrs, CX18_DDR_INITIAL_EMRS);
302
303         cx18_msleep_timeout(10, 0);
304
305         write_reg(0x20000, CX18_DDR_SOFT_RESET);
306         cx18_msleep_timeout(10, 0);
307
308         /* use power-down mode when idle */
309         write_reg(0x00000010, CX18_DDR_POWER_REG);
310
311         write_reg(0x10001, CX18_REG_BUS_TIMEOUT_EN);
312
313         write_reg(0x48, CX18_DDR_MB_PER_ROW_7);
314         write_reg(0xE0000, CX18_DDR_BASE_63_ADDR);
315
316         write_reg(0x00000101, CX18_WMB_CLIENT02);  /* AO */
317         write_reg(0x00000101, CX18_WMB_CLIENT09);  /* AI2 */
318         write_reg(0x00000101, CX18_WMB_CLIENT05);  /* VIM1 */
319         write_reg(0x00000101, CX18_WMB_CLIENT06);  /* AI1 */
320         write_reg(0x00000101, CX18_WMB_CLIENT07);  /* 3D comb */
321         write_reg(0x00000101, CX18_WMB_CLIENT10);  /* ME */
322         write_reg(0x00000101, CX18_WMB_CLIENT12);  /* ENC */
323         write_reg(0x00000101, CX18_WMB_CLIENT13);  /* PK */
324         write_reg(0x00000101, CX18_WMB_CLIENT11);  /* RC */
325         write_reg(0x00000101, CX18_WMB_CLIENT14);  /* AVO */
326 }
327
328 int cx18_firmware_init(struct cx18 *cx)
329 {
330         /* Allow chip to control CLKRUN */
331         write_reg(0x5, CX18_DSP0_INTERRUPT_MASK);
332
333         write_reg(0x000F000F, CX18_PROC_SOFT_RESET); /* stop the fw */
334
335         cx18_msleep_timeout(1, 0);
336
337         sw1_irq_enable(IRQ_CPU_TO_EPU | IRQ_APU_TO_EPU);
338         sw2_irq_enable(IRQ_CPU_TO_EPU_ACK | IRQ_APU_TO_EPU_ACK);
339
340         /* Only if the processor is not running */
341         if (read_reg(CX18_PROC_SOFT_RESET) & 8) {
342                 int sz = load_apu_fw_direct("v4l-cx23418-apu.fw",
343                                cx->enc_mem, cx, CX18_FW_APU_SIZE);
344
345                 write_enc(0xE51FF004, 0);
346                 write_enc(0xa00000, 4);  /* todo: not hardcoded */
347                 write_reg(0x00010000, CX18_PROC_SOFT_RESET); /* Start APU */
348                 cx18_msleep_timeout(500, 0);
349
350                 sz = sz <= 0 ? sz : load_cpu_fw_direct("v4l-cx23418-cpu.fw",
351                                         cx->enc_mem, cx, CX18_FW_CPU_SIZE);
352
353                 if (sz > 0) {
354                         int retries = 0;
355
356                         /* start the CPU */
357                         write_reg(0x00080000, CX18_PROC_SOFT_RESET);
358                         while (retries++ < 50) { /* Loop for max 500mS */
359                                 if ((read_reg(CX18_PROC_SOFT_RESET) & 1) == 0)
360                                         break;
361                                 cx18_msleep_timeout(10, 0);
362                         }
363                         cx18_msleep_timeout(200, 0);
364                         if (retries == 51) {
365                                 CX18_ERR("Could not start the CPU\n");
366                                 return -EIO;
367                         }
368                 }
369                 if (sz <= 0)
370                         return -EIO;
371         }
372         /* initialize GPIO */
373         write_reg(0x14001400, 0xC78110);
374         return 0;
375 }