Merge master.kernel.org:/pub/scm/linux/kernel/git/torvalds/linux-2.6 into next
[linux-2.6] / drivers / mmc / host / imxmmc.c
1 /*
2  *  linux/drivers/mmc/host/imxmmc.c - Motorola i.MX MMCI driver
3  *
4  *  Copyright (C) 2004 Sascha Hauer, Pengutronix <sascha@saschahauer.de>
5  *  Copyright (C) 2006 Pavel Pisa, PiKRON <ppisa@pikron.com>
6  *
7  *  derived from pxamci.c by Russell King
8  *
9  * This program is free software; you can redistribute it and/or modify
10  * it under the terms of the GNU General Public License version 2 as
11  * published by the Free Software Foundation.
12  *
13  *  2005-04-17 Pavel Pisa <pisa@cmp.felk.cvut.cz>
14  *             Changed to conform redesigned i.MX scatter gather DMA interface
15  *
16  *  2005-11-04 Pavel Pisa <pisa@cmp.felk.cvut.cz>
17  *             Updated for 2.6.14 kernel
18  *
19  *  2005-12-13 Jay Monkman <jtm@smoothsmoothie.com>
20  *             Found and corrected problems in the write path
21  *
22  *  2005-12-30 Pavel Pisa <pisa@cmp.felk.cvut.cz>
23  *             The event handling rewritten right way in softirq.
24  *             Added many ugly hacks and delays to overcome SDHC
25  *             deficiencies
26  *
27  */
28
29 #ifdef CONFIG_MMC_DEBUG
30 #define DEBUG
31 #else
32 #undef  DEBUG
33 #endif
34
35 #include <linux/module.h>
36 #include <linux/init.h>
37 #include <linux/ioport.h>
38 #include <linux/platform_device.h>
39 #include <linux/interrupt.h>
40 #include <linux/blkdev.h>
41 #include <linux/dma-mapping.h>
42 #include <linux/mmc/host.h>
43 #include <linux/mmc/card.h>
44 #include <linux/delay.h>
45 #include <linux/clk.h>
46
47 #include <asm/dma.h>
48 #include <asm/io.h>
49 #include <asm/irq.h>
50 #include <asm/sizes.h>
51 #include <asm/arch/mmc.h>
52 #include <asm/arch/imx-dma.h>
53
54 #include "imxmmc.h"
55
56 #define DRIVER_NAME "imx-mmc"
57
58 #define IMXMCI_INT_MASK_DEFAULT (INT_MASK_BUF_READY | INT_MASK_DATA_TRAN | \
59                       INT_MASK_WRITE_OP_DONE | INT_MASK_END_CMD_RES | \
60                       INT_MASK_AUTO_CARD_DETECT | INT_MASK_DAT0_EN | INT_MASK_SDIO)
61
62 struct imxmci_host {
63         struct mmc_host         *mmc;
64         spinlock_t              lock;
65         struct resource         *res;
66         int                     irq;
67         imx_dmach_t             dma;
68         unsigned int            clkrt;
69         unsigned int            cmdat;
70         volatile unsigned int   imask;
71         unsigned int            power_mode;
72         unsigned int            present;
73         struct imxmmc_platform_data *pdata;
74
75         struct mmc_request      *req;
76         struct mmc_command      *cmd;
77         struct mmc_data         *data;
78
79         struct timer_list       timer;
80         struct tasklet_struct   tasklet;
81         unsigned int            status_reg;
82         unsigned long           pending_events;
83         /* Next to fields are there for CPU driven transfers to overcome SDHC deficiencies */
84         u16                     *data_ptr;
85         unsigned int            data_cnt;
86         atomic_t                stuck_timeout;
87
88         unsigned int            dma_nents;
89         unsigned int            dma_size;
90         unsigned int            dma_dir;
91         int                     dma_allocated;
92
93         unsigned char           actual_bus_width;
94
95         int                     prev_cmd_code;
96
97         struct clk              *clk;
98 };
99
100 #define IMXMCI_PEND_IRQ_b       0
101 #define IMXMCI_PEND_DMA_END_b   1
102 #define IMXMCI_PEND_DMA_ERR_b   2
103 #define IMXMCI_PEND_WAIT_RESP_b 3
104 #define IMXMCI_PEND_DMA_DATA_b  4
105 #define IMXMCI_PEND_CPU_DATA_b  5
106 #define IMXMCI_PEND_CARD_XCHG_b 6
107 #define IMXMCI_PEND_SET_INIT_b  7
108 #define IMXMCI_PEND_STARTED_b   8
109
110 #define IMXMCI_PEND_IRQ_m       (1 << IMXMCI_PEND_IRQ_b)
111 #define IMXMCI_PEND_DMA_END_m   (1 << IMXMCI_PEND_DMA_END_b)
112 #define IMXMCI_PEND_DMA_ERR_m   (1 << IMXMCI_PEND_DMA_ERR_b)
113 #define IMXMCI_PEND_WAIT_RESP_m (1 << IMXMCI_PEND_WAIT_RESP_b)
114 #define IMXMCI_PEND_DMA_DATA_m  (1 << IMXMCI_PEND_DMA_DATA_b)
115 #define IMXMCI_PEND_CPU_DATA_m  (1 << IMXMCI_PEND_CPU_DATA_b)
116 #define IMXMCI_PEND_CARD_XCHG_m (1 << IMXMCI_PEND_CARD_XCHG_b)
117 #define IMXMCI_PEND_SET_INIT_m  (1 << IMXMCI_PEND_SET_INIT_b)
118 #define IMXMCI_PEND_STARTED_m   (1 << IMXMCI_PEND_STARTED_b)
119
120 static void imxmci_stop_clock(struct imxmci_host *host)
121 {
122         int i = 0;
123         MMC_STR_STP_CLK &= ~STR_STP_CLK_START_CLK;
124         while(i < 0x1000) {
125                 if(!(i & 0x7f))
126                         MMC_STR_STP_CLK |= STR_STP_CLK_STOP_CLK;
127
128                 if(!(MMC_STATUS & STATUS_CARD_BUS_CLK_RUN)) {
129                         /* Check twice before cut */
130                         if(!(MMC_STATUS & STATUS_CARD_BUS_CLK_RUN))
131                                 return;
132                 }
133
134                 i++;
135         }
136         dev_dbg(mmc_dev(host->mmc), "imxmci_stop_clock blocked, no luck\n");
137 }
138
139 static int imxmci_start_clock(struct imxmci_host *host)
140 {
141         unsigned int trials = 0;
142         unsigned int delay_limit = 128;
143         unsigned long flags;
144
145         MMC_STR_STP_CLK &= ~STR_STP_CLK_STOP_CLK;
146
147         clear_bit(IMXMCI_PEND_STARTED_b, &host->pending_events);
148
149         /*
150          * Command start of the clock, this usually succeeds in less
151          * then 6 delay loops, but during card detection (low clockrate)
152          * it takes up to 5000 delay loops and sometimes fails for the first time
153          */
154         MMC_STR_STP_CLK |= STR_STP_CLK_START_CLK;
155
156         do {
157                 unsigned int delay = delay_limit;
158
159                 while(delay--){
160                         if(MMC_STATUS & STATUS_CARD_BUS_CLK_RUN)
161                                 /* Check twice before cut */
162                                 if(MMC_STATUS & STATUS_CARD_BUS_CLK_RUN)
163                                         return 0;
164
165                         if(test_bit(IMXMCI_PEND_STARTED_b, &host->pending_events))
166                                 return 0;
167                 }
168
169                 local_irq_save(flags);
170                 /*
171                  * Ensure, that request is not doubled under all possible circumstances.
172                  * It is possible, that cock running state is missed, because some other
173                  * IRQ or schedule delays this function execution and the clocks has
174                  * been already stopped by other means (response processing, SDHC HW)
175                  */
176                 if(!test_bit(IMXMCI_PEND_STARTED_b, &host->pending_events))
177                         MMC_STR_STP_CLK |= STR_STP_CLK_START_CLK;
178                 local_irq_restore(flags);
179
180         } while(++trials<256);
181
182         dev_err(mmc_dev(host->mmc), "imxmci_start_clock blocked, no luck\n");
183
184         return -1;
185 }
186
187 static void imxmci_softreset(void)
188 {
189         /* reset sequence */
190         MMC_STR_STP_CLK = 0x8;
191         MMC_STR_STP_CLK = 0xD;
192         MMC_STR_STP_CLK = 0x5;
193         MMC_STR_STP_CLK = 0x5;
194         MMC_STR_STP_CLK = 0x5;
195         MMC_STR_STP_CLK = 0x5;
196         MMC_STR_STP_CLK = 0x5;
197         MMC_STR_STP_CLK = 0x5;
198         MMC_STR_STP_CLK = 0x5;
199         MMC_STR_STP_CLK = 0x5;
200
201         MMC_RES_TO = 0xff;
202         MMC_BLK_LEN = 512;
203         MMC_NOB = 1;
204 }
205
206 static int imxmci_busy_wait_for_status(struct imxmci_host *host,
207                         unsigned int *pstat, unsigned int stat_mask,
208                         int timeout, const char *where)
209 {
210         int loops=0;
211         while(!(*pstat & stat_mask)) {
212                 loops+=2;
213                 if(loops >= timeout) {
214                         dev_dbg(mmc_dev(host->mmc), "busy wait timeout in %s, STATUS = 0x%x (0x%x)\n",
215                                 where, *pstat, stat_mask);
216                         return -1;
217                 }
218                 udelay(2);
219                 *pstat |= MMC_STATUS;
220         }
221         if(!loops)
222                 return 0;
223
224         /* The busy-wait is expected there for clock <8MHz due to SDHC hardware flaws */
225         if(!(stat_mask & STATUS_END_CMD_RESP) || (host->mmc->ios.clock>=8000000))
226                 dev_info(mmc_dev(host->mmc), "busy wait for %d usec in %s, STATUS = 0x%x (0x%x)\n",
227                         loops, where, *pstat, stat_mask);
228         return loops;
229 }
230
231 static void imxmci_setup_data(struct imxmci_host *host, struct mmc_data *data)
232 {
233         unsigned int nob = data->blocks;
234         unsigned int blksz = data->blksz;
235         unsigned int datasz = nob * blksz;
236         int i;
237
238         if (data->flags & MMC_DATA_STREAM)
239                 nob = 0xffff;
240
241         host->data = data;
242         data->bytes_xfered = 0;
243
244         MMC_NOB = nob;
245         MMC_BLK_LEN = blksz;
246
247         /*
248          * DMA cannot be used for small block sizes, we have to use CPU driven transfers otherwise.
249          * We are in big troubles for non-512 byte transfers according to note in the paragraph
250          * 20.6.7 of User Manual anyway, but we need to be able to transfer SCR at least.
251          * The situation is even more complex in reality. The SDHC in not able to handle wll
252          * partial FIFO fills and reads. The length has to be rounded up to burst size multiple.
253          * This is required for SCR read at least.
254          */
255         if (datasz < 512) {
256                 host->dma_size = datasz;
257                 if (data->flags & MMC_DATA_READ) {
258                         host->dma_dir = DMA_FROM_DEVICE;
259
260                         /* Hack to enable read SCR */
261                         MMC_NOB = 1;
262                         MMC_BLK_LEN = 512;
263                 } else {
264                         host->dma_dir = DMA_TO_DEVICE;
265                 }
266
267                 /* Convert back to virtual address */
268                 host->data_ptr = (u16*)sg_virt(data->sg);
269                 host->data_cnt = 0;
270
271                 clear_bit(IMXMCI_PEND_DMA_DATA_b, &host->pending_events);
272                 set_bit(IMXMCI_PEND_CPU_DATA_b, &host->pending_events);
273
274                 return;
275         }
276
277         if (data->flags & MMC_DATA_READ) {
278                 host->dma_dir = DMA_FROM_DEVICE;
279                 host->dma_nents = dma_map_sg(mmc_dev(host->mmc), data->sg,
280                                                 data->sg_len,  host->dma_dir);
281
282                 imx_dma_setup_sg(host->dma, data->sg, data->sg_len, datasz,
283                         host->res->start + MMC_BUFFER_ACCESS_OFS, DMA_MODE_READ);
284
285                 /*imx_dma_setup_mem2dev_ccr(host->dma, DMA_MODE_READ, IMX_DMA_WIDTH_16, CCR_REN);*/
286                 CCR(host->dma) = CCR_DMOD_LINEAR | CCR_DSIZ_32 | CCR_SMOD_FIFO | CCR_SSIZ_16 | CCR_REN;
287         } else {
288                 host->dma_dir = DMA_TO_DEVICE;
289
290                 host->dma_nents = dma_map_sg(mmc_dev(host->mmc), data->sg,
291                                                 data->sg_len,  host->dma_dir);
292
293                 imx_dma_setup_sg(host->dma, data->sg, data->sg_len, datasz,
294                         host->res->start + MMC_BUFFER_ACCESS_OFS, DMA_MODE_WRITE);
295
296                 /*imx_dma_setup_mem2dev_ccr(host->dma, DMA_MODE_WRITE, IMX_DMA_WIDTH_16, CCR_REN);*/
297                 CCR(host->dma) = CCR_SMOD_LINEAR | CCR_SSIZ_32 | CCR_DMOD_FIFO | CCR_DSIZ_16 | CCR_REN;
298         }
299
300 #if 1   /* This code is there only for consistency checking and can be disabled in future */
301         host->dma_size = 0;
302         for(i=0; i<host->dma_nents; i++)
303                 host->dma_size+=data->sg[i].length;
304
305         if (datasz > host->dma_size) {
306                 dev_err(mmc_dev(host->mmc), "imxmci_setup_data datasz 0x%x > 0x%x dm_size\n",
307                        datasz, host->dma_size);
308         }
309 #endif
310
311         host->dma_size = datasz;
312
313         wmb();
314
315         if(host->actual_bus_width == MMC_BUS_WIDTH_4)
316                 BLR(host->dma) = 0;     /* burst 64 byte read / 64 bytes write */
317         else
318                 BLR(host->dma) = 16;    /* burst 16 byte read / 16 bytes write */
319
320         RSSR(host->dma) = DMA_REQ_SDHC;
321
322         set_bit(IMXMCI_PEND_DMA_DATA_b, &host->pending_events);
323         clear_bit(IMXMCI_PEND_CPU_DATA_b, &host->pending_events);
324
325         /* start DMA engine for read, write is delayed after initial response */
326         if (host->dma_dir == DMA_FROM_DEVICE) {
327                 imx_dma_enable(host->dma);
328         }
329 }
330
331 static void imxmci_start_cmd(struct imxmci_host *host, struct mmc_command *cmd, unsigned int cmdat)
332 {
333         unsigned long flags;
334         u32 imask;
335
336         WARN_ON(host->cmd != NULL);
337         host->cmd = cmd;
338
339         /* Ensure, that clock are stopped else command programming and start fails */
340         imxmci_stop_clock(host);
341
342         if (cmd->flags & MMC_RSP_BUSY)
343                 cmdat |= CMD_DAT_CONT_BUSY;
344
345         switch (mmc_resp_type(cmd)) {
346         case MMC_RSP_R1: /* short CRC, OPCODE */
347         case MMC_RSP_R1B:/* short CRC, OPCODE, BUSY */
348                 cmdat |= CMD_DAT_CONT_RESPONSE_FORMAT_R1;
349                 break;
350         case MMC_RSP_R2: /* long 136 bit + CRC */
351                 cmdat |= CMD_DAT_CONT_RESPONSE_FORMAT_R2;
352                 break;
353         case MMC_RSP_R3: /* short */
354                 cmdat |= CMD_DAT_CONT_RESPONSE_FORMAT_R3;
355                 break;
356         default:
357                 break;
358         }
359
360         if ( test_and_clear_bit(IMXMCI_PEND_SET_INIT_b, &host->pending_events) )
361                 cmdat |= CMD_DAT_CONT_INIT; /* This command needs init */
362
363         if ( host->actual_bus_width == MMC_BUS_WIDTH_4 )
364                 cmdat |= CMD_DAT_CONT_BUS_WIDTH_4;
365
366         MMC_CMD = cmd->opcode;
367         MMC_ARGH = cmd->arg >> 16;
368         MMC_ARGL = cmd->arg & 0xffff;
369         MMC_CMD_DAT_CONT = cmdat;
370
371         atomic_set(&host->stuck_timeout, 0);
372         set_bit(IMXMCI_PEND_WAIT_RESP_b, &host->pending_events);
373
374
375         imask = IMXMCI_INT_MASK_DEFAULT;
376         imask &= ~INT_MASK_END_CMD_RES;
377         if ( cmdat & CMD_DAT_CONT_DATA_ENABLE ) {
378                 /*imask &= ~INT_MASK_BUF_READY;*/
379                 imask &= ~INT_MASK_DATA_TRAN;
380                 if ( cmdat & CMD_DAT_CONT_WRITE )
381                         imask &= ~INT_MASK_WRITE_OP_DONE;
382                 if(test_bit(IMXMCI_PEND_CPU_DATA_b, &host->pending_events))
383                         imask &= ~INT_MASK_BUF_READY;
384         }
385
386         spin_lock_irqsave(&host->lock, flags);
387         host->imask = imask;
388         MMC_INT_MASK = host->imask;
389         spin_unlock_irqrestore(&host->lock, flags);
390
391         dev_dbg(mmc_dev(host->mmc), "CMD%02d (0x%02x) mask set to 0x%04x\n",
392                 cmd->opcode, cmd->opcode, imask);
393
394         imxmci_start_clock(host);
395 }
396
397 static void imxmci_finish_request(struct imxmci_host *host, struct mmc_request *req)
398 {
399         unsigned long flags;
400
401         spin_lock_irqsave(&host->lock, flags);
402
403         host->pending_events &= ~(IMXMCI_PEND_WAIT_RESP_m | IMXMCI_PEND_DMA_END_m |
404                         IMXMCI_PEND_DMA_DATA_m | IMXMCI_PEND_CPU_DATA_m);
405
406         host->imask = IMXMCI_INT_MASK_DEFAULT;
407         MMC_INT_MASK = host->imask;
408
409         spin_unlock_irqrestore(&host->lock, flags);
410
411         if(req && req->cmd)
412                 host->prev_cmd_code = req->cmd->opcode;
413
414         host->req = NULL;
415         host->cmd = NULL;
416         host->data = NULL;
417         mmc_request_done(host->mmc, req);
418 }
419
420 static int imxmci_finish_data(struct imxmci_host *host, unsigned int stat)
421 {
422         struct mmc_data *data = host->data;
423         int data_error;
424
425         if(test_and_clear_bit(IMXMCI_PEND_DMA_DATA_b, &host->pending_events)){
426                 imx_dma_disable(host->dma);
427                 dma_unmap_sg(mmc_dev(host->mmc), data->sg, host->dma_nents,
428                              host->dma_dir);
429         }
430
431         if ( stat & STATUS_ERR_MASK ) {
432                 dev_dbg(mmc_dev(host->mmc), "request failed. status: 0x%08x\n",stat);
433                 if(stat & (STATUS_CRC_READ_ERR | STATUS_CRC_WRITE_ERR))
434                         data->error = -EILSEQ;
435                 else if(stat & STATUS_TIME_OUT_READ)
436                         data->error = -ETIMEDOUT;
437                 else
438                         data->error = -EIO;
439         } else {
440                 data->bytes_xfered = host->dma_size;
441         }
442
443         data_error = data->error;
444
445         host->data = NULL;
446
447         return data_error;
448 }
449
450 static int imxmci_cmd_done(struct imxmci_host *host, unsigned int stat)
451 {
452         struct mmc_command *cmd = host->cmd;
453         int i;
454         u32 a,b,c;
455         struct mmc_data *data = host->data;
456
457         if (!cmd)
458                 return 0;
459
460         host->cmd = NULL;
461
462         if (stat & STATUS_TIME_OUT_RESP) {
463                 dev_dbg(mmc_dev(host->mmc), "CMD TIMEOUT\n");
464                 cmd->error = -ETIMEDOUT;
465         } else if (stat & STATUS_RESP_CRC_ERR && cmd->flags & MMC_RSP_CRC) {
466                 dev_dbg(mmc_dev(host->mmc), "cmd crc error\n");
467                 cmd->error = -EILSEQ;
468         }
469
470         if(cmd->flags & MMC_RSP_PRESENT) {
471                 if(cmd->flags & MMC_RSP_136) {
472                         for (i = 0; i < 4; i++) {
473                                 u32 a = MMC_RES_FIFO & 0xffff;
474                                 u32 b = MMC_RES_FIFO & 0xffff;
475                                 cmd->resp[i] = a<<16 | b;
476                         }
477                 } else {
478                         a = MMC_RES_FIFO & 0xffff;
479                         b = MMC_RES_FIFO & 0xffff;
480                         c = MMC_RES_FIFO & 0xffff;
481                         cmd->resp[0] = a<<24 | b<<8 | c>>8;
482                 }
483         }
484
485         dev_dbg(mmc_dev(host->mmc), "RESP 0x%08x, 0x%08x, 0x%08x, 0x%08x, error %d\n",
486                 cmd->resp[0], cmd->resp[1], cmd->resp[2], cmd->resp[3], cmd->error);
487
488         if (data && !cmd->error && !(stat & STATUS_ERR_MASK)) {
489                 if (host->req->data->flags & MMC_DATA_WRITE) {
490
491                         /* Wait for FIFO to be empty before starting DMA write */
492
493                         stat = MMC_STATUS;
494                         if(imxmci_busy_wait_for_status(host, &stat,
495                                 STATUS_APPL_BUFF_FE,
496                                 40, "imxmci_cmd_done DMA WR") < 0) {
497                                 cmd->error = -EIO;
498                                 imxmci_finish_data(host, stat);
499                                 if(host->req)
500                                         imxmci_finish_request(host, host->req);
501                                 dev_warn(mmc_dev(host->mmc), "STATUS = 0x%04x\n",
502                                        stat);
503                                 return 0;
504                         }
505
506                         if(test_bit(IMXMCI_PEND_DMA_DATA_b, &host->pending_events)) {
507                                 imx_dma_enable(host->dma);
508                         }
509                 }
510         } else {
511                 struct mmc_request *req;
512                 imxmci_stop_clock(host);
513                 req = host->req;
514
515                 if(data)
516                         imxmci_finish_data(host, stat);
517
518                 if( req ) {
519                         imxmci_finish_request(host, req);
520                 } else {
521                         dev_warn(mmc_dev(host->mmc), "imxmci_cmd_done: no request to finish\n");
522                 }
523         }
524
525         return 1;
526 }
527
528 static int imxmci_data_done(struct imxmci_host *host, unsigned int stat)
529 {
530         struct mmc_data *data = host->data;
531         int data_error;
532
533         if (!data)
534                 return 0;
535
536         data_error = imxmci_finish_data(host, stat);
537
538         if (host->req->stop) {
539                 imxmci_stop_clock(host);
540                 imxmci_start_cmd(host, host->req->stop, 0);
541         } else {
542                 struct mmc_request *req;
543                 req = host->req;
544                 if( req ) {
545                         imxmci_finish_request(host, req);
546                 } else {
547                         dev_warn(mmc_dev(host->mmc), "imxmci_data_done: no request to finish\n");
548                 }
549         }
550
551         return 1;
552 }
553
554 static int imxmci_cpu_driven_data(struct imxmci_host *host, unsigned int *pstat)
555 {
556         int i;
557         int burst_len;
558         int trans_done = 0;
559         unsigned int stat = *pstat;
560
561         if(host->actual_bus_width != MMC_BUS_WIDTH_4)
562                 burst_len = 16;
563         else
564                 burst_len = 64;
565
566         /* This is unfortunately required */
567         dev_dbg(mmc_dev(host->mmc), "imxmci_cpu_driven_data running STATUS = 0x%x\n",
568                 stat);
569
570         udelay(20);     /* required for clocks < 8MHz*/
571
572         if(host->dma_dir == DMA_FROM_DEVICE) {
573                 imxmci_busy_wait_for_status(host, &stat,
574                                 STATUS_APPL_BUFF_FF | STATUS_DATA_TRANS_DONE |
575                                 STATUS_TIME_OUT_READ,
576                                 50, "imxmci_cpu_driven_data read");
577
578                 while((stat & (STATUS_APPL_BUFF_FF |  STATUS_DATA_TRANS_DONE)) &&
579                       !(stat & STATUS_TIME_OUT_READ) &&
580                       (host->data_cnt < 512)) {
581
582                         udelay(20);     /* required for clocks < 8MHz*/
583
584                         for(i = burst_len; i>=2 ; i-=2) {
585                                 u16 data;
586                                 data = MMC_BUFFER_ACCESS;
587                                 udelay(10);     /* required for clocks < 8MHz*/
588                                 if(host->data_cnt+2 <= host->dma_size) {
589                                         *(host->data_ptr++) = data;
590                                 } else {
591                                         if(host->data_cnt < host->dma_size)
592                                                 *(u8*)(host->data_ptr) = data;
593                                 }
594                                 host->data_cnt += 2;
595                         }
596
597                         stat = MMC_STATUS;
598
599                         dev_dbg(mmc_dev(host->mmc), "imxmci_cpu_driven_data read %d burst %d STATUS = 0x%x\n",
600                                 host->data_cnt, burst_len, stat);
601                 }
602
603                 if((stat & STATUS_DATA_TRANS_DONE) && (host->data_cnt >= 512))
604                         trans_done = 1;
605
606                 if(host->dma_size & 0x1ff)
607                         stat &= ~STATUS_CRC_READ_ERR;
608
609                 if(stat & STATUS_TIME_OUT_READ) {
610                         dev_dbg(mmc_dev(host->mmc), "imxmci_cpu_driven_data read timeout STATUS = 0x%x\n",
611                                 stat);
612                         trans_done = -1;
613                 }
614
615         } else {
616                 imxmci_busy_wait_for_status(host, &stat,
617                                 STATUS_APPL_BUFF_FE,
618                                 20, "imxmci_cpu_driven_data write");
619
620                 while((stat & STATUS_APPL_BUFF_FE) &&
621                       (host->data_cnt < host->dma_size)) {
622                         if(burst_len >= host->dma_size - host->data_cnt) {
623                                 burst_len = host->dma_size - host->data_cnt;
624                                 host->data_cnt = host->dma_size;
625                                 trans_done = 1;
626                         } else {
627                                 host->data_cnt += burst_len;
628                         }
629
630                         for(i = burst_len; i>0 ; i-=2)
631                                 MMC_BUFFER_ACCESS = *(host->data_ptr++);
632
633                         stat = MMC_STATUS;
634
635                         dev_dbg(mmc_dev(host->mmc), "imxmci_cpu_driven_data write burst %d STATUS = 0x%x\n",
636                                 burst_len, stat);
637                 }
638         }
639
640         *pstat = stat;
641
642         return trans_done;
643 }
644
645 static void imxmci_dma_irq(int dma, void *devid)
646 {
647         struct imxmci_host *host = devid;
648         uint32_t stat = MMC_STATUS;
649
650         atomic_set(&host->stuck_timeout, 0);
651         host->status_reg = stat;
652         set_bit(IMXMCI_PEND_DMA_END_b, &host->pending_events);
653         tasklet_schedule(&host->tasklet);
654 }
655
656 static irqreturn_t imxmci_irq(int irq, void *devid)
657 {
658         struct imxmci_host *host = devid;
659         uint32_t stat = MMC_STATUS;
660         int handled = 1;
661
662         MMC_INT_MASK = host->imask | INT_MASK_SDIO | INT_MASK_AUTO_CARD_DETECT;
663
664         atomic_set(&host->stuck_timeout, 0);
665         host->status_reg = stat;
666         set_bit(IMXMCI_PEND_IRQ_b, &host->pending_events);
667         set_bit(IMXMCI_PEND_STARTED_b, &host->pending_events);
668         tasklet_schedule(&host->tasklet);
669
670         return IRQ_RETVAL(handled);;
671 }
672
673 static void imxmci_tasklet_fnc(unsigned long data)
674 {
675         struct imxmci_host *host = (struct imxmci_host *)data;
676         u32 stat;
677         unsigned int data_dir_mask = 0; /* STATUS_WR_CRC_ERROR_CODE_MASK */
678         int timeout = 0;
679
680         if(atomic_read(&host->stuck_timeout) > 4) {
681                 char *what;
682                 timeout = 1;
683                 stat = MMC_STATUS;
684                 host->status_reg = stat;
685                 if (test_bit(IMXMCI_PEND_WAIT_RESP_b, &host->pending_events))
686                         if (test_bit(IMXMCI_PEND_DMA_DATA_b, &host->pending_events))
687                                 what = "RESP+DMA";
688                         else
689                                 what = "RESP";
690                 else
691                         if (test_bit(IMXMCI_PEND_DMA_DATA_b, &host->pending_events))
692                                 if(test_bit(IMXMCI_PEND_DMA_END_b, &host->pending_events))
693                                         what = "DATA";
694                                 else
695                                         what = "DMA";
696                         else
697                                 what = "???";
698
699                 dev_err(mmc_dev(host->mmc), "%s TIMEOUT, hardware stucked STATUS = 0x%04x IMASK = 0x%04x\n",
700                        what, stat, MMC_INT_MASK);
701                 dev_err(mmc_dev(host->mmc), "CMD_DAT_CONT = 0x%04x, MMC_BLK_LEN = 0x%04x, MMC_NOB = 0x%04x, DMA_CCR = 0x%08x\n",
702                        MMC_CMD_DAT_CONT, MMC_BLK_LEN, MMC_NOB, CCR(host->dma));
703                 dev_err(mmc_dev(host->mmc), "CMD%d, prevCMD%d, bus %d-bit, dma_size = 0x%x\n",
704                        host->cmd?host->cmd->opcode:0, host->prev_cmd_code, 1<<host->actual_bus_width, host->dma_size);
705         }
706
707         if(!host->present || timeout)
708                 host->status_reg = STATUS_TIME_OUT_RESP | STATUS_TIME_OUT_READ |
709                                     STATUS_CRC_READ_ERR | STATUS_CRC_WRITE_ERR;
710
711         if(test_bit(IMXMCI_PEND_IRQ_b, &host->pending_events) || timeout) {
712                 clear_bit(IMXMCI_PEND_IRQ_b, &host->pending_events);
713
714                 stat = MMC_STATUS;
715                 /*
716                  * This is not required in theory, but there is chance to miss some flag
717                  * which clears automatically by mask write, FreeScale original code keeps
718                  * stat from IRQ time so do I
719                  */
720                 stat |= host->status_reg;
721
722                 if(test_bit(IMXMCI_PEND_CPU_DATA_b, &host->pending_events))
723                         stat &= ~STATUS_CRC_READ_ERR;
724
725                 if(test_bit(IMXMCI_PEND_WAIT_RESP_b, &host->pending_events)) {
726                         imxmci_busy_wait_for_status(host, &stat,
727                                         STATUS_END_CMD_RESP | STATUS_ERR_MASK,
728                                         20, "imxmci_tasklet_fnc resp (ERRATUM #4)");
729                 }
730
731                 if(stat & (STATUS_END_CMD_RESP | STATUS_ERR_MASK)) {
732                         if(test_and_clear_bit(IMXMCI_PEND_WAIT_RESP_b, &host->pending_events))
733                                 imxmci_cmd_done(host, stat);
734                         if(host->data && (stat & STATUS_ERR_MASK))
735                                 imxmci_data_done(host, stat);
736                 }
737
738                 if(test_bit(IMXMCI_PEND_CPU_DATA_b, &host->pending_events)) {
739                         stat |= MMC_STATUS;
740                         if(imxmci_cpu_driven_data(host, &stat)){
741                                 if(test_and_clear_bit(IMXMCI_PEND_WAIT_RESP_b, &host->pending_events))
742                                         imxmci_cmd_done(host, stat);
743                                 atomic_clear_mask(IMXMCI_PEND_IRQ_m|IMXMCI_PEND_CPU_DATA_m,
744                                                         &host->pending_events);
745                                 imxmci_data_done(host, stat);
746                         }
747                 }
748         }
749
750         if(test_bit(IMXMCI_PEND_DMA_END_b, &host->pending_events) &&
751            !test_bit(IMXMCI_PEND_WAIT_RESP_b, &host->pending_events)) {
752
753                 stat = MMC_STATUS;
754                 /* Same as above */
755                 stat |= host->status_reg;
756
757                 if(host->dma_dir == DMA_TO_DEVICE) {
758                         data_dir_mask = STATUS_WRITE_OP_DONE;
759                 } else {
760                         data_dir_mask = STATUS_DATA_TRANS_DONE;
761                 }
762
763                 if(stat & data_dir_mask) {
764                         clear_bit(IMXMCI_PEND_DMA_END_b, &host->pending_events);
765                         imxmci_data_done(host, stat);
766                 }
767         }
768
769         if(test_and_clear_bit(IMXMCI_PEND_CARD_XCHG_b, &host->pending_events)) {
770
771                 if(host->cmd)
772                         imxmci_cmd_done(host, STATUS_TIME_OUT_RESP);
773
774                 if(host->data)
775                         imxmci_data_done(host, STATUS_TIME_OUT_READ |
776                                          STATUS_CRC_READ_ERR | STATUS_CRC_WRITE_ERR);
777
778                 if(host->req)
779                         imxmci_finish_request(host, host->req);
780
781                 mmc_detect_change(host->mmc, msecs_to_jiffies(100));
782
783         }
784 }
785
786 static void imxmci_request(struct mmc_host *mmc, struct mmc_request *req)
787 {
788         struct imxmci_host *host = mmc_priv(mmc);
789         unsigned int cmdat;
790
791         WARN_ON(host->req != NULL);
792
793         host->req = req;
794
795         cmdat = 0;
796
797         if (req->data) {
798                 imxmci_setup_data(host, req->data);
799
800                 cmdat |= CMD_DAT_CONT_DATA_ENABLE;
801
802                 if (req->data->flags & MMC_DATA_WRITE)
803                         cmdat |= CMD_DAT_CONT_WRITE;
804
805                 if (req->data->flags & MMC_DATA_STREAM) {
806                         cmdat |= CMD_DAT_CONT_STREAM_BLOCK;
807                 }
808         }
809
810         imxmci_start_cmd(host, req->cmd, cmdat);
811 }
812
813 #define CLK_RATE 19200000
814
815 static void imxmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
816 {
817         struct imxmci_host *host = mmc_priv(mmc);
818         int prescaler;
819
820         if( ios->bus_width==MMC_BUS_WIDTH_4 ) {
821                 host->actual_bus_width = MMC_BUS_WIDTH_4;
822                 imx_gpio_mode(PB11_PF_SD_DAT3);
823         }else{
824                 host->actual_bus_width = MMC_BUS_WIDTH_1;
825                 imx_gpio_mode(GPIO_PORTB | GPIO_IN | GPIO_PUEN | 11);
826         }
827
828         if ( host->power_mode != ios->power_mode ) {
829                 switch (ios->power_mode) {
830                 case MMC_POWER_OFF:
831                         break;
832                 case MMC_POWER_UP:
833                         set_bit(IMXMCI_PEND_SET_INIT_b, &host->pending_events);
834                         break;
835                 case MMC_POWER_ON:
836                         break;
837                 }
838                 host->power_mode = ios->power_mode;
839         }
840
841         if ( ios->clock ) {
842                 unsigned int clk;
843
844                 /* The prescaler is 5 for PERCLK2 equal to 96MHz
845                  * then 96MHz / 5 = 19.2 MHz
846                  */
847                 clk = clk_get_rate(host->clk);
848                 prescaler=(clk+(CLK_RATE*7)/8)/CLK_RATE;
849                 switch(prescaler) {
850                 case 0:
851                 case 1: prescaler = 0;
852                         break;
853                 case 2: prescaler = 1;
854                         break;
855                 case 3: prescaler = 2;
856                         break;
857                 case 4: prescaler = 4;
858                         break;
859                 default:
860                 case 5: prescaler = 5;
861                         break;
862                 }
863
864                 dev_dbg(mmc_dev(host->mmc), "PERCLK2 %d MHz -> prescaler %d\n",
865                         clk, prescaler);
866
867                 for(clk=0; clk<8; clk++) {
868                         int x;
869                         x = CLK_RATE / (1<<clk);
870                         if( x <= ios->clock)
871                                 break;
872                 }
873
874                 MMC_STR_STP_CLK |= STR_STP_CLK_ENABLE; /* enable controller */
875
876                 imxmci_stop_clock(host);
877                 MMC_CLK_RATE = (prescaler<<3) | clk;
878                 /*
879                  * Under my understanding, clock should not be started there, because it would
880                  * initiate SDHC sequencer and send last or random command into card
881                  */
882                 /*imxmci_start_clock(host);*/
883
884                 dev_dbg(mmc_dev(host->mmc), "MMC_CLK_RATE: 0x%08x\n", MMC_CLK_RATE);
885         } else {
886                 imxmci_stop_clock(host);
887         }
888 }
889
890 static int imxmci_get_ro(struct mmc_host *mmc)
891 {
892         struct imxmci_host *host = mmc_priv(mmc);
893
894         if (host->pdata && host->pdata->get_ro)
895                 return !!host->pdata->get_ro(mmc_dev(mmc));
896         /*
897          * Board doesn't support read only detection; let the mmc core
898          * decide what to do.
899          */
900         return -ENOSYS;
901 }
902
903
904 static const struct mmc_host_ops imxmci_ops = {
905         .request        = imxmci_request,
906         .set_ios        = imxmci_set_ios,
907         .get_ro         = imxmci_get_ro,
908 };
909
910 static struct resource *platform_device_resource(struct platform_device *dev, unsigned int mask, int nr)
911 {
912         int i;
913
914         for (i = 0; i < dev->num_resources; i++)
915                 if (dev->resource[i].flags == mask && nr-- == 0)
916                         return &dev->resource[i];
917         return NULL;
918 }
919
920 static int platform_device_irq(struct platform_device *dev, int nr)
921 {
922         int i;
923
924         for (i = 0; i < dev->num_resources; i++)
925                 if (dev->resource[i].flags == IORESOURCE_IRQ && nr-- == 0)
926                         return dev->resource[i].start;
927         return NO_IRQ;
928 }
929
930 static void imxmci_check_status(unsigned long data)
931 {
932         struct imxmci_host *host = (struct imxmci_host *)data;
933
934         if( host->pdata->card_present(mmc_dev(host->mmc)) != host->present ) {
935                 host->present ^= 1;
936                 dev_info(mmc_dev(host->mmc), "card %s\n",
937                       host->present ? "inserted" : "removed");
938
939                 set_bit(IMXMCI_PEND_CARD_XCHG_b, &host->pending_events);
940                 tasklet_schedule(&host->tasklet);
941         }
942
943         if(test_bit(IMXMCI_PEND_WAIT_RESP_b, &host->pending_events) ||
944            test_bit(IMXMCI_PEND_DMA_DATA_b, &host->pending_events)) {
945                 atomic_inc(&host->stuck_timeout);
946                 if(atomic_read(&host->stuck_timeout) > 4)
947                         tasklet_schedule(&host->tasklet);
948         } else {
949                 atomic_set(&host->stuck_timeout, 0);
950
951         }
952
953         mod_timer(&host->timer, jiffies + (HZ>>1));
954 }
955
956 static int imxmci_probe(struct platform_device *pdev)
957 {
958         struct mmc_host *mmc;
959         struct imxmci_host *host = NULL;
960         struct resource *r;
961         int ret = 0, irq;
962
963         printk(KERN_INFO "i.MX mmc driver\n");
964
965         r = platform_device_resource(pdev, IORESOURCE_MEM, 0);
966         irq = platform_device_irq(pdev, 0);
967         if (!r || irq == NO_IRQ)
968                 return -ENXIO;
969
970         r = request_mem_region(r->start, 0x100, "IMXMCI");
971         if (!r)
972                 return -EBUSY;
973
974         mmc = mmc_alloc_host(sizeof(struct imxmci_host), &pdev->dev);
975         if (!mmc) {
976                 ret = -ENOMEM;
977                 goto out;
978         }
979
980         mmc->ops = &imxmci_ops;
981         mmc->f_min = 150000;
982         mmc->f_max = CLK_RATE/2;
983         mmc->ocr_avail = MMC_VDD_32_33;
984         mmc->caps = MMC_CAP_4_BIT_DATA;
985
986         /* MMC core transfer sizes tunable parameters */
987         mmc->max_hw_segs = 64;
988         mmc->max_phys_segs = 64;
989         mmc->max_seg_size = 64*512;     /* default PAGE_CACHE_SIZE */
990         mmc->max_req_size = 64*512;     /* default PAGE_CACHE_SIZE */
991         mmc->max_blk_size = 2048;
992         mmc->max_blk_count = 65535;
993
994         host = mmc_priv(mmc);
995         host->mmc = mmc;
996         host->dma_allocated = 0;
997         host->pdata = pdev->dev.platform_data;
998
999         spin_lock_init(&host->lock);
1000         host->res = r;
1001         host->irq = irq;
1002
1003         host->clk = clk_get(&pdev->dev, "perclk2");
1004         if (IS_ERR(host->clk)) {
1005                 ret = PTR_ERR(host->clk);
1006                 goto out;
1007         }
1008         clk_enable(host->clk);
1009
1010         imx_gpio_mode(PB8_PF_SD_DAT0);
1011         imx_gpio_mode(PB9_PF_SD_DAT1);
1012         imx_gpio_mode(PB10_PF_SD_DAT2);
1013         /* Configured as GPIO with pull-up to ensure right MCC card mode */
1014         /* Switched to PB11_PF_SD_DAT3 if 4 bit bus is configured */
1015         imx_gpio_mode(GPIO_PORTB | GPIO_IN | GPIO_PUEN | 11);
1016         /* imx_gpio_mode(PB11_PF_SD_DAT3); */
1017         imx_gpio_mode(PB12_PF_SD_CLK);
1018         imx_gpio_mode(PB13_PF_SD_CMD);
1019
1020         imxmci_softreset();
1021
1022         if ( MMC_REV_NO != 0x390 ) {
1023                 dev_err(mmc_dev(host->mmc), "wrong rev.no. 0x%08x. aborting.\n",
1024                         MMC_REV_NO);
1025                 goto out;
1026         }
1027
1028         MMC_READ_TO = 0x2db4; /* recommended in data sheet */
1029
1030         host->imask = IMXMCI_INT_MASK_DEFAULT;
1031         MMC_INT_MASK = host->imask;
1032
1033         host->dma = imx_dma_request_by_prio(DRIVER_NAME, DMA_PRIO_LOW);
1034         if(host->dma < 0) {
1035                 dev_err(mmc_dev(host->mmc), "imx_dma_request_by_prio failed\n");
1036                 ret = -EBUSY;
1037                 goto out;
1038         }
1039         host->dma_allocated=1;
1040         imx_dma_setup_handlers(host->dma, imxmci_dma_irq, NULL, host);
1041
1042         tasklet_init(&host->tasklet, imxmci_tasklet_fnc, (unsigned long)host);
1043         host->status_reg=0;
1044         host->pending_events=0;
1045
1046         ret = request_irq(host->irq, imxmci_irq, 0, DRIVER_NAME, host);
1047         if (ret)
1048                 goto out;
1049
1050         host->present = host->pdata->card_present(mmc_dev(mmc));
1051         init_timer(&host->timer);
1052         host->timer.data = (unsigned long)host;
1053         host->timer.function = imxmci_check_status;
1054         add_timer(&host->timer);
1055         mod_timer(&host->timer, jiffies + (HZ>>1));
1056
1057         platform_set_drvdata(pdev, mmc);
1058
1059         mmc_add_host(mmc);
1060
1061         return 0;
1062
1063 out:
1064         if (host) {
1065                 if(host->dma_allocated){
1066                         imx_dma_free(host->dma);
1067                         host->dma_allocated=0;
1068                 }
1069                 if (host->clk) {
1070                         clk_disable(host->clk);
1071                         clk_put(host->clk);
1072                 }
1073         }
1074         if (mmc)
1075                 mmc_free_host(mmc);
1076         release_resource(r);
1077         return ret;
1078 }
1079
1080 static int imxmci_remove(struct platform_device *pdev)
1081 {
1082         struct mmc_host *mmc = platform_get_drvdata(pdev);
1083
1084         platform_set_drvdata(pdev, NULL);
1085
1086         if (mmc) {
1087                 struct imxmci_host *host = mmc_priv(mmc);
1088
1089                 tasklet_disable(&host->tasklet);
1090
1091                 del_timer_sync(&host->timer);
1092                 mmc_remove_host(mmc);
1093
1094                 free_irq(host->irq, host);
1095                 if(host->dma_allocated){
1096                         imx_dma_free(host->dma);
1097                         host->dma_allocated=0;
1098                 }
1099
1100                 tasklet_kill(&host->tasklet);
1101
1102                 clk_disable(host->clk);
1103                 clk_put(host->clk);
1104
1105                 release_resource(host->res);
1106
1107                 mmc_free_host(mmc);
1108         }
1109         return 0;
1110 }
1111
1112 #ifdef CONFIG_PM
1113 static int imxmci_suspend(struct platform_device *dev, pm_message_t state)
1114 {
1115         struct mmc_host *mmc = platform_get_drvdata(dev);
1116         int ret = 0;
1117
1118         if (mmc)
1119                 ret = mmc_suspend_host(mmc, state);
1120
1121         return ret;
1122 }
1123
1124 static int imxmci_resume(struct platform_device *dev)
1125 {
1126         struct mmc_host *mmc = platform_get_drvdata(dev);
1127         struct imxmci_host *host;
1128         int ret = 0;
1129
1130         if (mmc) {
1131                 host = mmc_priv(mmc);
1132                 if(host)
1133                         set_bit(IMXMCI_PEND_SET_INIT_b, &host->pending_events);
1134                 ret = mmc_resume_host(mmc);
1135         }
1136
1137         return ret;
1138 }
1139 #else
1140 #define imxmci_suspend  NULL
1141 #define imxmci_resume   NULL
1142 #endif /* CONFIG_PM */
1143
1144 static struct platform_driver imxmci_driver = {
1145         .probe          = imxmci_probe,
1146         .remove         = imxmci_remove,
1147         .suspend        = imxmci_suspend,
1148         .resume         = imxmci_resume,
1149         .driver         = {
1150                 .name           = DRIVER_NAME,
1151                 .owner          = THIS_MODULE,
1152         }
1153 };
1154
1155 static int __init imxmci_init(void)
1156 {
1157         return platform_driver_register(&imxmci_driver);
1158 }
1159
1160 static void __exit imxmci_exit(void)
1161 {
1162         platform_driver_unregister(&imxmci_driver);
1163 }
1164
1165 module_init(imxmci_init);
1166 module_exit(imxmci_exit);
1167
1168 MODULE_DESCRIPTION("i.MX Multimedia Card Interface Driver");
1169 MODULE_AUTHOR("Sascha Hauer, Pengutronix");
1170 MODULE_LICENSE("GPL");
1171 MODULE_ALIAS("platform:imx-mmc");