2 * linux/arch/arm/mach-omap1/clock.h
4 * Copyright (C) 2004 - 2005 Nokia corporation
5 * Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
6 * Based on clocks.h by Tony Lindgren, Gordon McNutt and RidgeRun, Inc
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 #ifndef __ARCH_ARM_MACH_OMAP1_CLOCK_H
14 #define __ARCH_ARM_MACH_OMAP1_CLOCK_H
16 static unsigned long omap1_ckctl_recalc(struct clk *clk);
17 static unsigned long omap1_watchdog_recalc(struct clk *clk);
18 static int omap1_set_sossi_rate(struct clk *clk, unsigned long rate);
19 static unsigned long omap1_sossi_recalc(struct clk *clk);
20 static unsigned long omap1_ckctl_recalc_dsp_domain(struct clk *clk);
21 static int omap1_clk_set_rate_dsp_domain(struct clk * clk, unsigned long rate);
22 static int omap1_set_uart_rate(struct clk * clk, unsigned long rate);
23 static unsigned long omap1_uart_recalc(struct clk *clk);
24 static int omap1_set_ext_clk_rate(struct clk * clk, unsigned long rate);
25 static long omap1_round_ext_clk_rate(struct clk * clk, unsigned long rate);
26 static void omap1_init_ext_clk(struct clk * clk);
27 static int omap1_select_table_rate(struct clk * clk, unsigned long rate);
28 static long omap1_round_to_table_rate(struct clk * clk, unsigned long rate);
30 static int omap1_clk_set_rate_ckctl_arm(struct clk *clk, unsigned long rate);
31 static long omap1_clk_round_rate_ckctl_arm(struct clk *clk, unsigned long rate);
36 unsigned long pll_rate;
43 unsigned long sysc_addr;
46 /* Provide a method for preventing idling some ARM IDLECT clocks */
47 struct arm_idlect1_clk {
49 unsigned long no_idle_count;
53 /* ARM_CKCTL bit shifts */
54 #define CKCTL_PERDIV_OFFSET 0
55 #define CKCTL_LCDDIV_OFFSET 2
56 #define CKCTL_ARMDIV_OFFSET 4
57 #define CKCTL_DSPDIV_OFFSET 6
58 #define CKCTL_TCDIV_OFFSET 8
59 #define CKCTL_DSPMMUDIV_OFFSET 10
60 /*#define ARM_TIMXO 12*/
62 /*#define ARM_INTHCK_SEL 14*/ /* Divide-by-2 for mpu inth_ck */
63 /* DSP_CKCTL bit shifts */
64 #define CKCTL_DSPPERDIV_OFFSET 0
66 /* ARM_IDLECT2 bit shifts */
71 #define EN_LBCK 4 /* Not on 1610/1710 */
72 /*#define EN_HSABCK 5*/
76 #define EN_GPIOCK 9 /* Not on 1610/1710 */
77 /*#define EN_LBFREECK 10*/
78 #define EN_CKOUT_ARM 11
80 /* ARM_IDLECT3 bit shifts */
85 /* DSP_IDLECT2 bit shifts (0,1,2 are same as for ARM_IDLECT2) */
88 /* Various register defines for clock controls scattered around OMAP chip */
89 #define SDW_MCLK_INV_BIT 2 /* In ULPD_CLKC_CTRL */
90 #define USB_MCLK_EN_BIT 4 /* In ULPD_CLKC_CTRL */
91 #define USB_HOST_HHC_UHOST_EN 9 /* In MOD_CONF_CTRL_0 */
92 #define SWD_ULPD_PLL_CLK_REQ 1 /* In SWD_CLK_DIV_CTRL_SEL */
93 #define COM_ULPD_PLL_CLK_REQ 1 /* In COM_CLK_DIV_CTRL_SEL */
94 #define SWD_CLK_DIV_CTRL_SEL 0xfffe0874
95 #define COM_CLK_DIV_CTRL_SEL 0xfffe0878
96 #define SOFT_REQ_REG 0xfffe0834
97 #define SOFT_REQ_REG2 0xfffe0880
99 /*-------------------------------------------------------------------------
100 * Omap1 MPU rate table
101 *-------------------------------------------------------------------------*/
102 static struct mpu_rate rate_table[] = {
103 /* MPU MHz, xtal MHz, dpll1 MHz, CKCTL, DPLL_CTL
104 * NOTE: Comment order here is different from bits in CKCTL value:
105 * armdiv, dspdiv, dspmmu, tcdiv, perdiv, lcddiv
107 #if defined(CONFIG_OMAP_ARM_216MHZ)
108 { 216000000, 12000000, 216000000, 0x050d, 0x2910 }, /* 1/1/2/2/2/8 */
110 #if defined(CONFIG_OMAP_ARM_195MHZ)
111 { 195000000, 13000000, 195000000, 0x050e, 0x2790 }, /* 1/1/2/2/4/8 */
113 #if defined(CONFIG_OMAP_ARM_192MHZ)
114 { 192000000, 19200000, 192000000, 0x050f, 0x2510 }, /* 1/1/2/2/8/8 */
115 { 192000000, 12000000, 192000000, 0x050f, 0x2810 }, /* 1/1/2/2/8/8 */
116 { 96000000, 12000000, 192000000, 0x055f, 0x2810 }, /* 2/2/2/2/8/8 */
117 { 48000000, 12000000, 192000000, 0x0baf, 0x2810 }, /* 4/4/4/8/8/8 */
118 { 24000000, 12000000, 192000000, 0x0fff, 0x2810 }, /* 8/8/8/8/8/8 */
120 #if defined(CONFIG_OMAP_ARM_182MHZ)
121 { 182000000, 13000000, 182000000, 0x050e, 0x2710 }, /* 1/1/2/2/4/8 */
123 #if defined(CONFIG_OMAP_ARM_168MHZ)
124 { 168000000, 12000000, 168000000, 0x010f, 0x2710 }, /* 1/1/1/2/8/8 */
126 #if defined(CONFIG_OMAP_ARM_150MHZ)
127 { 150000000, 12000000, 150000000, 0x010a, 0x2cb0 }, /* 1/1/1/2/4/4 */
129 #if defined(CONFIG_OMAP_ARM_120MHZ)
130 { 120000000, 12000000, 120000000, 0x010a, 0x2510 }, /* 1/1/1/2/4/4 */
132 #if defined(CONFIG_OMAP_ARM_96MHZ)
133 { 96000000, 12000000, 96000000, 0x0005, 0x2410 }, /* 1/1/1/1/2/2 */
135 #if defined(CONFIG_OMAP_ARM_60MHZ)
136 { 60000000, 12000000, 60000000, 0x0005, 0x2290 }, /* 1/1/1/1/2/2 */
138 #if defined(CONFIG_OMAP_ARM_30MHZ)
139 { 30000000, 12000000, 60000000, 0x0555, 0x2290 }, /* 2/2/2/2/2/2 */
144 /*-------------------------------------------------------------------------
146 *-------------------------------------------------------------------------*/
148 static struct clk ck_ref = {
154 static struct clk ck_dpll1 = {
160 static struct arm_idlect1_clk ck_dpll1out = {
162 .name = "ck_dpll1out",
163 .ops = &clkops_generic,
165 .flags = CLOCK_IDLE_CONTROL | ENABLE_REG_32BIT,
166 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
167 .enable_bit = EN_CKOUT_ARM,
168 .recalc = &followparent_recalc,
173 static struct clk sossi_ck = {
175 .ops = &clkops_generic,
176 .parent = &ck_dpll1out.clk,
177 .flags = CLOCK_NO_IDLE_PARENT | ENABLE_REG_32BIT,
178 .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_1),
180 .recalc = &omap1_sossi_recalc,
181 .set_rate = &omap1_set_sossi_rate,
184 static struct clk arm_ck = {
188 .rate_offset = CKCTL_ARMDIV_OFFSET,
189 .recalc = &omap1_ckctl_recalc,
190 .round_rate = omap1_clk_round_rate_ckctl_arm,
191 .set_rate = omap1_clk_set_rate_ckctl_arm,
194 static struct arm_idlect1_clk armper_ck = {
197 .ops = &clkops_generic,
199 .flags = CLOCK_IDLE_CONTROL,
200 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
201 .enable_bit = EN_PERCK,
202 .rate_offset = CKCTL_PERDIV_OFFSET,
203 .recalc = &omap1_ckctl_recalc,
204 .round_rate = omap1_clk_round_rate_ckctl_arm,
205 .set_rate = omap1_clk_set_rate_ckctl_arm,
210 static struct clk arm_gpio_ck = {
211 .name = "arm_gpio_ck",
212 .ops = &clkops_generic,
214 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
215 .enable_bit = EN_GPIOCK,
216 .recalc = &followparent_recalc,
219 static struct arm_idlect1_clk armxor_ck = {
222 .ops = &clkops_generic,
224 .flags = CLOCK_IDLE_CONTROL,
225 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
226 .enable_bit = EN_XORPCK,
227 .recalc = &followparent_recalc,
232 static struct arm_idlect1_clk armtim_ck = {
235 .ops = &clkops_generic,
237 .flags = CLOCK_IDLE_CONTROL,
238 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
239 .enable_bit = EN_TIMCK,
240 .recalc = &followparent_recalc,
245 static struct arm_idlect1_clk armwdt_ck = {
248 .ops = &clkops_generic,
250 .flags = CLOCK_IDLE_CONTROL,
251 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
252 .enable_bit = EN_WDTCK,
253 .recalc = &omap1_watchdog_recalc,
258 static struct clk arminth_ck16xx = {
259 .name = "arminth_ck",
262 .recalc = &followparent_recalc,
263 /* Note: On 16xx the frequency can be divided by 2 by programming
264 * ARM_CKCTL:ARM_INTHCK_SEL(14) to 1
266 * 1510 version is in TC clocks.
270 static struct clk dsp_ck = {
272 .ops = &clkops_generic,
274 .enable_reg = OMAP1_IO_ADDRESS(ARM_CKCTL),
275 .enable_bit = EN_DSPCK,
276 .rate_offset = CKCTL_DSPDIV_OFFSET,
277 .recalc = &omap1_ckctl_recalc,
278 .round_rate = omap1_clk_round_rate_ckctl_arm,
279 .set_rate = omap1_clk_set_rate_ckctl_arm,
282 static struct clk dspmmu_ck = {
286 .rate_offset = CKCTL_DSPMMUDIV_OFFSET,
287 .recalc = &omap1_ckctl_recalc,
288 .round_rate = omap1_clk_round_rate_ckctl_arm,
289 .set_rate = omap1_clk_set_rate_ckctl_arm,
292 static struct clk dspper_ck = {
294 .ops = &clkops_dspck,
296 .enable_reg = DSP_IDLECT2,
297 .enable_bit = EN_PERCK,
298 .rate_offset = CKCTL_PERDIV_OFFSET,
299 .recalc = &omap1_ckctl_recalc_dsp_domain,
300 .round_rate = omap1_clk_round_rate_ckctl_arm,
301 .set_rate = &omap1_clk_set_rate_dsp_domain,
304 static struct clk dspxor_ck = {
306 .ops = &clkops_dspck,
308 .enable_reg = DSP_IDLECT2,
309 .enable_bit = EN_XORPCK,
310 .recalc = &followparent_recalc,
313 static struct clk dsptim_ck = {
315 .ops = &clkops_dspck,
317 .enable_reg = DSP_IDLECT2,
318 .enable_bit = EN_DSPTIMCK,
319 .recalc = &followparent_recalc,
322 /* Tie ARM_IDLECT1:IDLIF_ARM to this logical clock structure */
323 static struct arm_idlect1_clk tc_ck = {
328 .flags = CLOCK_IDLE_CONTROL,
329 .rate_offset = CKCTL_TCDIV_OFFSET,
330 .recalc = &omap1_ckctl_recalc,
331 .round_rate = omap1_clk_round_rate_ckctl_arm,
332 .set_rate = omap1_clk_set_rate_ckctl_arm,
337 static struct clk arminth_ck1510 = {
338 .name = "arminth_ck",
340 .parent = &tc_ck.clk,
341 .recalc = &followparent_recalc,
342 /* Note: On 1510 the frequency follows TC_CK
344 * 16xx version is in MPU clocks.
348 static struct clk tipb_ck = {
349 /* No-idle controlled by "tc_ck" */
352 .parent = &tc_ck.clk,
353 .recalc = &followparent_recalc,
356 static struct clk l3_ocpi_ck = {
357 /* No-idle controlled by "tc_ck" */
358 .name = "l3_ocpi_ck",
359 .ops = &clkops_generic,
360 .parent = &tc_ck.clk,
361 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT3),
362 .enable_bit = EN_OCPI_CK,
363 .recalc = &followparent_recalc,
366 static struct clk tc1_ck = {
368 .ops = &clkops_generic,
369 .parent = &tc_ck.clk,
370 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT3),
371 .enable_bit = EN_TC1_CK,
372 .recalc = &followparent_recalc,
375 static struct clk tc2_ck = {
377 .ops = &clkops_generic,
378 .parent = &tc_ck.clk,
379 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT3),
380 .enable_bit = EN_TC2_CK,
381 .recalc = &followparent_recalc,
384 static struct clk dma_ck = {
385 /* No-idle controlled by "tc_ck" */
388 .parent = &tc_ck.clk,
389 .recalc = &followparent_recalc,
392 static struct clk dma_lcdfree_ck = {
393 .name = "dma_lcdfree_ck",
395 .parent = &tc_ck.clk,
396 .recalc = &followparent_recalc,
399 static struct arm_idlect1_clk api_ck = {
402 .ops = &clkops_generic,
403 .parent = &tc_ck.clk,
404 .flags = CLOCK_IDLE_CONTROL,
405 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
406 .enable_bit = EN_APICK,
407 .recalc = &followparent_recalc,
412 static struct arm_idlect1_clk lb_ck = {
415 .ops = &clkops_generic,
416 .parent = &tc_ck.clk,
417 .flags = CLOCK_IDLE_CONTROL,
418 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
419 .enable_bit = EN_LBCK,
420 .recalc = &followparent_recalc,
425 static struct clk rhea1_ck = {
428 .parent = &tc_ck.clk,
429 .recalc = &followparent_recalc,
432 static struct clk rhea2_ck = {
435 .parent = &tc_ck.clk,
436 .recalc = &followparent_recalc,
439 static struct clk lcd_ck_16xx = {
441 .ops = &clkops_generic,
443 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
444 .enable_bit = EN_LCDCK,
445 .rate_offset = CKCTL_LCDDIV_OFFSET,
446 .recalc = &omap1_ckctl_recalc,
447 .round_rate = omap1_clk_round_rate_ckctl_arm,
448 .set_rate = omap1_clk_set_rate_ckctl_arm,
451 static struct arm_idlect1_clk lcd_ck_1510 = {
454 .ops = &clkops_generic,
456 .flags = CLOCK_IDLE_CONTROL,
457 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
458 .enable_bit = EN_LCDCK,
459 .rate_offset = CKCTL_LCDDIV_OFFSET,
460 .recalc = &omap1_ckctl_recalc,
461 .round_rate = omap1_clk_round_rate_ckctl_arm,
462 .set_rate = omap1_clk_set_rate_ckctl_arm,
467 static struct clk uart1_1510 = {
470 /* Direct from ULPD, no real parent */
471 .parent = &armper_ck.clk,
473 .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
474 .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
475 .enable_bit = 29, /* Chooses between 12MHz and 48MHz */
476 .set_rate = &omap1_set_uart_rate,
477 .recalc = &omap1_uart_recalc,
480 static struct uart_clk uart1_16xx = {
484 /* Direct from ULPD, no real parent */
485 .parent = &armper_ck.clk,
487 .flags = RATE_FIXED | ENABLE_REG_32BIT |
488 CLOCK_NO_IDLE_PARENT,
489 .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
492 .sysc_addr = 0xfffb0054,
495 static struct clk uart2_ck = {
498 /* Direct from ULPD, no real parent */
499 .parent = &armper_ck.clk,
501 .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
502 .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
503 .enable_bit = 30, /* Chooses between 12MHz and 48MHz */
504 .set_rate = &omap1_set_uart_rate,
505 .recalc = &omap1_uart_recalc,
508 static struct clk uart3_1510 = {
511 /* Direct from ULPD, no real parent */
512 .parent = &armper_ck.clk,
514 .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
515 .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
516 .enable_bit = 31, /* Chooses between 12MHz and 48MHz */
517 .set_rate = &omap1_set_uart_rate,
518 .recalc = &omap1_uart_recalc,
521 static struct uart_clk uart3_16xx = {
525 /* Direct from ULPD, no real parent */
526 .parent = &armper_ck.clk,
528 .flags = RATE_FIXED | ENABLE_REG_32BIT |
529 CLOCK_NO_IDLE_PARENT,
530 .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
533 .sysc_addr = 0xfffb9854,
536 static struct clk usb_clko = { /* 6 MHz output on W4_USB_CLKO */
538 .ops = &clkops_generic,
539 /* Direct from ULPD, no parent */
541 .flags = RATE_FIXED | ENABLE_REG_32BIT,
542 .enable_reg = OMAP1_IO_ADDRESS(ULPD_CLOCK_CTRL),
543 .enable_bit = USB_MCLK_EN_BIT,
546 static struct clk usb_hhc_ck1510 = {
547 .name = "usb_hhc_ck",
548 .ops = &clkops_generic,
549 /* Direct from ULPD, no parent */
550 .rate = 48000000, /* Actually 2 clocks, 12MHz and 48MHz */
551 .flags = RATE_FIXED | ENABLE_REG_32BIT,
552 .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
553 .enable_bit = USB_HOST_HHC_UHOST_EN,
556 static struct clk usb_hhc_ck16xx = {
557 .name = "usb_hhc_ck",
558 .ops = &clkops_generic,
559 /* Direct from ULPD, no parent */
561 /* OTG_SYSCON_2.OTG_PADEN == 0 (not 1510-compatible) */
562 .flags = RATE_FIXED | ENABLE_REG_32BIT,
563 .enable_reg = OMAP1_IO_ADDRESS(OTG_BASE + 0x08), /* OTG_SYSCON_2 */
564 .enable_bit = 8 /* UHOST_EN */,
567 static struct clk usb_dc_ck = {
569 .ops = &clkops_generic,
570 /* Direct from ULPD, no parent */
573 .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG),
577 static struct clk mclk_1510 = {
579 .ops = &clkops_generic,
580 /* Direct from ULPD, no parent. May be enabled by ext hardware. */
583 .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG),
587 static struct clk mclk_16xx = {
589 .ops = &clkops_generic,
590 /* Direct from ULPD, no parent. May be enabled by ext hardware. */
591 .enable_reg = OMAP1_IO_ADDRESS(COM_CLK_DIV_CTRL_SEL),
592 .enable_bit = COM_ULPD_PLL_CLK_REQ,
593 .set_rate = &omap1_set_ext_clk_rate,
594 .round_rate = &omap1_round_ext_clk_rate,
595 .init = &omap1_init_ext_clk,
598 static struct clk bclk_1510 = {
600 .ops = &clkops_generic,
601 /* Direct from ULPD, no parent. May be enabled by ext hardware. */
606 static struct clk bclk_16xx = {
608 .ops = &clkops_generic,
609 /* Direct from ULPD, no parent. May be enabled by ext hardware. */
610 .enable_reg = OMAP1_IO_ADDRESS(SWD_CLK_DIV_CTRL_SEL),
611 .enable_bit = SWD_ULPD_PLL_CLK_REQ,
612 .set_rate = &omap1_set_ext_clk_rate,
613 .round_rate = &omap1_round_ext_clk_rate,
614 .init = &omap1_init_ext_clk,
617 static struct clk mmc1_ck = {
619 .ops = &clkops_generic,
620 /* Functional clock is direct from ULPD, interface clock is ARMPER */
621 .parent = &armper_ck.clk,
623 .flags = RATE_FIXED | ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
624 .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
628 static struct clk mmc2_ck = {
631 .ops = &clkops_generic,
632 /* Functional clock is direct from ULPD, interface clock is ARMPER */
633 .parent = &armper_ck.clk,
635 .flags = RATE_FIXED | ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
636 .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
640 static struct clk virtual_ck_mpu = {
643 .parent = &arm_ck, /* Is smarter alias for */
644 .recalc = &followparent_recalc,
645 .set_rate = &omap1_select_table_rate,
646 .round_rate = &omap1_round_to_table_rate,
649 /* virtual functional clock domain for I2C. Just for making sure that ARMXOR_CK
650 remains active during MPU idle whenever this is enabled */
651 static struct clk i2c_fck = {
655 .flags = CLOCK_NO_IDLE_PARENT,
656 .parent = &armxor_ck.clk,
657 .recalc = &followparent_recalc,
660 static struct clk i2c_ick = {
664 .flags = CLOCK_NO_IDLE_PARENT,
665 .parent = &armper_ck.clk,
666 .recalc = &followparent_recalc,