1 #ifndef __ASM_MACH_REGS_OST_H
2 #define __ASM_MACH_REGS_OST_H
4 #include <mach/hardware.h>
7 * OS Timer & Match Registers
10 #define OSMR0 __REG(0x40A00000) /* */
11 #define OSMR1 __REG(0x40A00004) /* */
12 #define OSMR2 __REG(0x40A00008) /* */
13 #define OSMR3 __REG(0x40A0000C) /* */
14 #define OSMR4 __REG(0x40A00080) /* */
15 #define OSCR __REG(0x40A00010) /* OS Timer Counter Register */
16 #define OSCR4 __REG(0x40A00040) /* OS Timer Counter Register */
17 #define OMCR4 __REG(0x40A000C0) /* */
18 #define OSSR __REG(0x40A00014) /* OS Timer Status Register */
19 #define OWER __REG(0x40A00018) /* OS Timer Watchdog Enable Register */
20 #define OIER __REG(0x40A0001C) /* OS Timer Interrupt Enable Register */
22 #define OSSR_M3 (1 << 3) /* Match status channel 3 */
23 #define OSSR_M2 (1 << 2) /* Match status channel 2 */
24 #define OSSR_M1 (1 << 1) /* Match status channel 1 */
25 #define OSSR_M0 (1 << 0) /* Match status channel 0 */
27 #define OWER_WME (1 << 0) /* Watchdog Match Enable */
29 #define OIER_E3 (1 << 3) /* Interrupt enable channel 3 */
30 #define OIER_E2 (1 << 2) /* Interrupt enable channel 2 */
31 #define OIER_E1 (1 << 1) /* Interrupt enable channel 1 */
32 #define OIER_E0 (1 << 0) /* Interrupt enable channel 0 */
34 #endif /* __ASM_MACH_REGS_OST_H */