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   1 /*
   2  * wm8580.c  --  WM8580 ALSA Soc Audio driver
   3  *
   4  * Copyright 2008 Wolfson Microelectronics PLC.
   5  *
   6  *  This program is free software; you can redistribute  it and/or modify it
   7  *  under  the terms of  the GNU General  Public License as published by the
   8  *  Free Software Foundation;  either version 2 of the  License, or (at your
   9  *  option) any later version.
  10  *
  11  * Notes:
  12  *  The WM8580 is a multichannel codec with S/PDIF support, featuring six
  13  *  DAC channels and two ADC channels.
  14  *
  15  *  Currently only the primary audio interface is supported - S/PDIF and
  16  *  the secondary audio interfaces are not.
  17  */
  18
  19 #include <linux/module.h>
  20 #include <linux/moduleparam.h>
  21 #include <linux/kernel.h>
  22 #include <linux/init.h>
  23 #include <linux/delay.h>
  24 #include <linux/pm.h>
  25 #include <linux/i2c.h>
  26 #include <linux/platform_device.h>
  27 #include <sound/core.h>
  28 #include <sound/pcm.h>
  29 #include <sound/pcm_params.h>
  30 #include <sound/soc.h>
  31 #include <sound/soc-dapm.h>
  32 #include <sound/tlv.h>
  33 #include <sound/initval.h>
  34 #include <asm/div64.h>
  35
  36 #include "wm8580.h"
  37
  38 #define WM8580_VERSION "0.1"
  39
  40 struct pll_state {
  41         unsigned int in;
  42         unsigned int out;
  43 };
  44
  45 /* codec private data */
  46 struct wm8580_priv {
  47         struct pll_state a;
  48         struct pll_state b;
  49 };
  50
  51 /* WM8580 register space */
  52 #define WM8580_PLLA1                         0x00
  53 #define WM8580_PLLA2                         0x01
  54 #define WM8580_PLLA3                         0x02
  55 #define WM8580_PLLA4                         0x03
  56 #define WM8580_PLLB1                         0x04
  57 #define WM8580_PLLB2                         0x05
  58 #define WM8580_PLLB3                         0x06
  59 #define WM8580_PLLB4                         0x07
  60 #define WM8580_CLKSEL                        0x08
  61 #define WM8580_PAIF1                         0x09
  62 #define WM8580_PAIF2                         0x0A
  63 #define WM8580_SAIF1                         0x0B
  64 #define WM8580_PAIF3                         0x0C
  65 #define WM8580_PAIF4                         0x0D
  66 #define WM8580_SAIF2                         0x0E
  67 #define WM8580_DAC_CONTROL1                  0x0F
  68 #define WM8580_DAC_CONTROL2                  0x10
  69 #define WM8580_DAC_CONTROL3                  0x11
  70 #define WM8580_DAC_CONTROL4                  0x12
  71 #define WM8580_DAC_CONTROL5                  0x13
  72 #define WM8580_DIGITAL_ATTENUATION_DACL1     0x14
  73 #define WM8580_DIGITAL_ATTENUATION_DACR1     0x15
  74 #define WM8580_DIGITAL_ATTENUATION_DACL2     0x16
  75 #define WM8580_DIGITAL_ATTENUATION_DACR2     0x17
  76 #define WM8580_DIGITAL_ATTENUATION_DACL3     0x18
  77 #define WM8580_DIGITAL_ATTENUATION_DACR3     0x19
  78 #define WM8580_MASTER_DIGITAL_ATTENUATION    0x1C
  79 #define WM8580_ADC_CONTROL1                  0x1D
  80 #define WM8580_SPDTXCHAN0                    0x1E
  81 #define WM8580_SPDTXCHAN1                    0x1F
  82 #define WM8580_SPDTXCHAN2                    0x20
  83 #define WM8580_SPDTXCHAN3                    0x21
  84 #define WM8580_SPDTXCHAN4                    0x22
  85 #define WM8580_SPDTXCHAN5                    0x23
  86 #define WM8580_SPDMODE                       0x24
  87 #define WM8580_INTMASK                       0x25
  88 #define WM8580_GPO1                          0x26
  89 #define WM8580_GPO2                          0x27
  90 #define WM8580_GPO3                          0x28
  91 #define WM8580_GPO4                          0x29
  92 #define WM8580_GPO5                          0x2A
  93 #define WM8580_INTSTAT                       0x2B
  94 #define WM8580_SPDRXCHAN1                    0x2C
  95 #define WM8580_SPDRXCHAN2                    0x2D
  96 #define WM8580_SPDRXCHAN3                    0x2E
  97 #define WM8580_SPDRXCHAN4                    0x2F
  98 #define WM8580_SPDRXCHAN5                    0x30
  99 #define WM8580_SPDSTAT                       0x31
 100 #define WM8580_PWRDN1                        0x32
 101 #define WM8580_PWRDN2                        0x33
 102 #define WM8580_READBACK                      0x34
 103 #define WM8580_RESET                         0x35
 104
 105 /* PLLB4 (register 7h) */
 106 #define WM8580_PLLB4_MCLKOUTSRC_MASK   0x60
 107 #define WM8580_PLLB4_MCLKOUTSRC_PLLA   0x20
 108 #define WM8580_PLLB4_MCLKOUTSRC_PLLB   0x40
 109 #define WM8580_PLLB4_MCLKOUTSRC_OSC    0x60
 110
 111 #define WM8580_PLLB4_CLKOUTSRC_MASK    0x180
 112 #define WM8580_PLLB4_CLKOUTSRC_PLLACLK 0x080
 113 #define WM8580_PLLB4_CLKOUTSRC_PLLBCLK 0x100
 114 #define WM8580_PLLB4_CLKOUTSRC_OSCCLK  0x180
 115
 116 /* CLKSEL (register 8h) */
 117 #define WM8580_CLKSEL_DAC_CLKSEL_MASK 0x03
 118 #define WM8580_CLKSEL_DAC_CLKSEL_PLLA 0x01
 119 #define WM8580_CLKSEL_DAC_CLKSEL_PLLB 0x02
 120
 121 /* AIF control 1 (registers 9h-bh) */
 122 #define WM8580_AIF_RATE_MASK       0x7
 123 #define WM8580_AIF_RATE_128        0x0
 124 #define WM8580_AIF_RATE_192        0x1
 125 #define WM8580_AIF_RATE_256        0x2
 126 #define WM8580_AIF_RATE_384        0x3
 127 #define WM8580_AIF_RATE_512        0x4
 128 #define WM8580_AIF_RATE_768        0x5
 129 #define WM8580_AIF_RATE_1152       0x6
 130
 131 #define WM8580_AIF_BCLKSEL_MASK   0x18
 132 #define WM8580_AIF_BCLKSEL_64     0x00
 133 #define WM8580_AIF_BCLKSEL_128    0x08
 134 #define WM8580_AIF_BCLKSEL_256    0x10
 135 #define WM8580_AIF_BCLKSEL_SYSCLK 0x18
 136
 137 #define WM8580_AIF_MS             0x20
 138
 139 #define WM8580_AIF_CLKSRC_MASK    0xc0
 140 #define WM8580_AIF_CLKSRC_PLLA    0x40
 141 #define WM8580_AIF_CLKSRC_PLLB    0x40
 142 #define WM8580_AIF_CLKSRC_MCLK    0xc0
 143
 144 /* AIF control 2 (registers ch-eh) */
 145 #define WM8580_AIF_FMT_MASK    0x03
 146 #define WM8580_AIF_FMT_RIGHTJ  0x00
 147 #define WM8580_AIF_FMT_LEFTJ   0x01
 148 #define WM8580_AIF_FMT_I2S     0x02
 149 #define WM8580_AIF_FMT_DSP     0x03
 150
 151 #define WM8580_AIF_LENGTH_MASK   0x0c
 152 #define WM8580_AIF_LENGTH_16     0x00
 153 #define WM8580_AIF_LENGTH_20     0x04
 154 #define WM8580_AIF_LENGTH_24     0x08
 155 #define WM8580_AIF_LENGTH_32     0x0c
 156
 157 #define WM8580_AIF_LRP         0x10
 158 #define WM8580_AIF_BCP         0x20
 159
 160 /* Powerdown Register 1 (register 32h) */
 161 #define WM8580_PWRDN1_PWDN     0x001
 162 #define WM8580_PWRDN1_ALLDACPD 0x040
 163
 164 /* Powerdown Register 2 (register 33h) */
 165 #define WM8580_PWRDN2_OSSCPD   0x001
 166 #define WM8580_PWRDN2_PLLAPD   0x002
 167 #define WM8580_PWRDN2_PLLBPD   0x004
 168 #define WM8580_PWRDN2_SPDIFPD  0x008
 169 #define WM8580_PWRDN2_SPDIFTXD 0x010
 170 #define WM8580_PWRDN2_SPDIFRXD 0x020
 171
 172 #define WM8580_DAC_CONTROL5_MUTEALL 0x10
 173
 174 /*
 175  * wm8580 register cache
 176  * We can't read the WM8580 register space when we
 177  * are using 2 wire for device control, so we cache them instead.
 178  */
 179 static const u16 wm8580_reg[] = {
 180         0x0121, 0x017e, 0x007d, 0x0014, /*R3*/
 181         0x0121, 0x017e, 0x007d, 0x0194, /*R7*/
 182         0x001c, 0x0002, 0x0002, 0x00c2, /*R11*/
 183         0x0182, 0x0082, 0x000a, 0x0024, /*R15*/
 184         0x0009, 0x0000, 0x00ff, 0x0000, /*R19*/
 185         0x00ff, 0x00ff, 0x00ff, 0x00ff, /*R23*/
 186         0x00ff, 0x00ff, 0x00ff, 0x00ff, /*R27*/
 187         0x01f0, 0x0040, 0x0000, 0x0000, /*R31(0x1F)*/
 188         0x0000, 0x0000, 0x0031, 0x000b, /*R35*/
 189         0x0039, 0x0000, 0x0010, 0x0032, /*R39*/
 190         0x0054, 0x0076, 0x0098, 0x0000, /*R43(0x2B)*/
 191         0x0000, 0x0000, 0x0000, 0x0000, /*R47*/
 192         0x0000, 0x0000, 0x005e, 0x003e, /*R51(0x33)*/
 193         0x0000, 0x0000 /*R53*/
 194 };
 195
 196 /*
 197  * read wm8580 register cache
 198  */
 199 static inline unsigned int wm8580_read_reg_cache(struct snd_soc_codec *codec,
 200         unsigned int reg)
 201 {
 202         u16 *cache = codec->reg_cache;
 203         BUG_ON(reg >= ARRAY_SIZE(wm8580_reg));
 204         return cache[reg];
 205 }
 206
 207 /*
 208  * write wm8580 register cache
 209  */
 210 static inline void wm8580_write_reg_cache(struct snd_soc_codec *codec,
 211         unsigned int reg, unsigned int value)
 212 {
 213         u16 *cache = codec->reg_cache;
 214
 215         cache[reg] = value;
 216 }
 217
 218 /*
 219  * write to the WM8580 register space
 220  */
 221 static int wm8580_write(struct snd_soc_codec *codec, unsigned int reg,
 222         unsigned int value)
 223 {
 224         u8 data[2];
 225
 226         BUG_ON(reg >= ARRAY_SIZE(wm8580_reg));
 227
 228         /* Registers are 9 bits wide */
 229         value &= 0x1ff;
 230
 231         switch (reg) {
 232         case WM8580_RESET:
 233                 /* Uncached */
 234                 break;
 235         default:
 236                 if (value == wm8580_read_reg_cache(codec, reg))
 237                         return 0;
 238         }
 239
 240         /* data is
 241          *   D15..D9 WM8580 register offset
 242          *   D8...D0 register data
 243          */
 244         data[0] = (reg << 1) | ((value >> 8) & 0x0001);
 245         data[1] = value & 0x00ff;
 246
 247         wm8580_write_reg_cache(codec, reg, value);
 248         if (codec->hw_write(codec->control_data, data, 2) == 2)
 249                 return 0;
 250         else
 251                 return -EIO;
 252 }
 253
 254 static inline unsigned int wm8580_read(struct snd_soc_codec *codec,
 255                                        unsigned int reg)
 256 {
 257         switch (reg) {
 258         default:
 259                 return wm8580_read_reg_cache(codec, reg);
 260         }
 261 }
 262
 263 static const DECLARE_TLV_DB_SCALE(dac_tlv, -12750, 50, 1);
 264
 265 static int wm8580_out_vu(struct snd_kcontrol *kcontrol,
 266                          struct snd_ctl_elem_value *ucontrol)
 267 {
 268         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
 269         int reg = kcontrol->private_value & 0xff;
 270         int reg2 = (kcontrol->private_value >> 24) & 0xff;
 271         int ret;
 272         u16 val;
 273
 274         /* Clear the register cache so we write without VU set */
 275         wm8580_write_reg_cache(codec, reg, 0);
 276         wm8580_write_reg_cache(codec, reg2, 0);
 277
 278         ret = snd_soc_put_volsw_2r(kcontrol, ucontrol);
 279         if (ret < 0)
 280                 return ret;
 281
 282         /* Now write again with the volume update bit set */
 283         val = wm8580_read_reg_cache(codec, reg);
 284         wm8580_write(codec, reg, val | 0x0100);
 285
 286         val = wm8580_read_reg_cache(codec, reg2);
 287         wm8580_write(codec, reg2, val | 0x0100);
 288
 289         return 0;
 290 }
 291
 292 #define SOC_WM8580_OUT_DOUBLE_R_TLV(xname, reg_left, reg_right, shift, max, invert, tlv_array) \
 293 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \
 294         .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\
 295                 SNDRV_CTL_ELEM_ACCESS_READWRITE,  \
 296         .tlv.p = (tlv_array), \
 297         .info = snd_soc_info_volsw_2r, \
 298         .get = snd_soc_get_volsw_2r, .put = wm8580_out_vu, \
 299         .private_value = (reg_left) | ((shift) << 8)  |         \
 300                 ((max) << 12) | ((invert) << 20) | ((reg_right) << 24) }
 301
 302 static const struct snd_kcontrol_new wm8580_snd_controls[] = {
 303 SOC_WM8580_OUT_DOUBLE_R_TLV("DAC1 Playback Volume",
 304                             WM8580_DIGITAL_ATTENUATION_DACL1,
 305                             WM8580_DIGITAL_ATTENUATION_DACR1,
 306                             0, 0xff, 0, dac_tlv),
 307 SOC_WM8580_OUT_DOUBLE_R_TLV("DAC2 Playback Volume",
 308                             WM8580_DIGITAL_ATTENUATION_DACL2,
 309                             WM8580_DIGITAL_ATTENUATION_DACR2,
 310                             0, 0xff, 0, dac_tlv),
 311 SOC_WM8580_OUT_DOUBLE_R_TLV("DAC3 Playback Volume",
 312                             WM8580_DIGITAL_ATTENUATION_DACL3,
 313                             WM8580_DIGITAL_ATTENUATION_DACR3,
 314                             0, 0xff, 0, dac_tlv),
 315
 316 SOC_SINGLE("DAC1 Deemphasis Switch", WM8580_DAC_CONTROL3, 0, 1, 0),
 317 SOC_SINGLE("DAC2 Deemphasis Switch", WM8580_DAC_CONTROL3, 1, 1, 0),
 318 SOC_SINGLE("DAC3 Deemphasis Switch", WM8580_DAC_CONTROL3, 2, 1, 0),
 319
 320 SOC_DOUBLE("DAC1 Invert Switch", WM8580_DAC_CONTROL4,  0, 1, 1, 0),
 321 SOC_DOUBLE("DAC2 Invert Switch", WM8580_DAC_CONTROL4,  2, 3, 1, 0),
 322 SOC_DOUBLE("DAC3 Invert Switch", WM8580_DAC_CONTROL4,  4, 5, 1, 0),
 323
 324 SOC_SINGLE("DAC ZC Switch", WM8580_DAC_CONTROL5, 5, 1, 0),
 325 SOC_SINGLE("DAC1 Switch", WM8580_DAC_CONTROL5, 0, 1, 0),
 326 SOC_SINGLE("DAC2 Switch", WM8580_DAC_CONTROL5, 1, 1, 0),
 327 SOC_SINGLE("DAC3 Switch", WM8580_DAC_CONTROL5, 2, 1, 0),
 328
 329 SOC_DOUBLE("ADC Mute Switch", WM8580_ADC_CONTROL1, 0, 1, 1, 0),
 330 SOC_SINGLE("ADC High-Pass Filter Switch", WM8580_ADC_CONTROL1, 4, 1, 0),
 331 };
 332
 333 static const struct snd_soc_dapm_widget wm8580_dapm_widgets[] = {
 334 SND_SOC_DAPM_DAC("DAC1", "Playback", WM8580_PWRDN1, 2, 1),
 335 SND_SOC_DAPM_DAC("DAC2", "Playback", WM8580_PWRDN1, 3, 1),
 336 SND_SOC_DAPM_DAC("DAC3", "Playback", WM8580_PWRDN1, 4, 1),
 337
 338 SND_SOC_DAPM_OUTPUT("VOUT1L"),
 339 SND_SOC_DAPM_OUTPUT("VOUT1R"),
 340 SND_SOC_DAPM_OUTPUT("VOUT2L"),
 341 SND_SOC_DAPM_OUTPUT("VOUT2R"),
 342 SND_SOC_DAPM_OUTPUT("VOUT3L"),
 343 SND_SOC_DAPM_OUTPUT("VOUT3R"),
 344
 345 SND_SOC_DAPM_ADC("ADC", "Capture", WM8580_PWRDN1, 1, 1),
 346
 347 SND_SOC_DAPM_INPUT("AINL"),
 348 SND_SOC_DAPM_INPUT("AINR"),
 349 };
 350
 351 static const struct snd_soc_dapm_route audio_map[] = {
 352         { "VOUT1L", NULL, "DAC1" },
 353         { "VOUT1R", NULL, "DAC1" },
 354
 355         { "VOUT2L", NULL, "DAC2" },
 356         { "VOUT2R", NULL, "DAC2" },
 357
 358         { "VOUT3L", NULL, "DAC3" },
 359         { "VOUT3R", NULL, "DAC3" },
 360
 361         { "ADC", NULL, "AINL" },
 362         { "ADC", NULL, "AINR" },
 363 };
 364
 365 static int wm8580_add_widgets(struct snd_soc_codec *codec)
 366 {
 367         snd_soc_dapm_new_controls(codec, wm8580_dapm_widgets,
 368                                   ARRAY_SIZE(wm8580_dapm_widgets));
 369
 370         snd_soc_dapm_add_routes(codec, audio_map, ARRAY_SIZE(audio_map));
 371
 372         snd_soc_dapm_new_widgets(codec);
 373         return 0;
 374 }
 375
 376 /* PLL divisors */
 377 struct _pll_div {
 378         u32 prescale:1;
 379         u32 postscale:1;
 380         u32 freqmode:2;
 381         u32 n:4;
 382         u32 k:24;
 383 };
 384
 385 /* The size in bits of the pll divide */
 386 #define FIXED_PLL_SIZE (1 << 22)
 387
 388 /* PLL rate to output rate divisions */
 389 static struct {
 390         unsigned int div;
 391         unsigned int freqmode;
 392         unsigned int postscale;
 393 } post_table[] = {
 394         {  2,  0, 0 },
 395         {  4,  0, 1 },
 396         {  4,  1, 0 },
 397         {  8,  1, 1 },
 398         {  8,  2, 0 },
 399         { 16,  2, 1 },
 400         { 12,  3, 0 },
 401         { 24,  3, 1 }
 402 };
 403
 404 static int pll_factors(struct _pll_div *pll_div, unsigned int target,
 405                        unsigned int source)
 406 {
 407         u64 Kpart;
 408         unsigned int K, Ndiv, Nmod;
 409         int i;
 410
 411         pr_debug("wm8580: PLL %dHz->%dHz\n", source, target);
 412
 413         /* Scale the output frequency up; the PLL should run in the
 414          * region of 90-100MHz.
 415          */
 416         for (i = 0; i < ARRAY_SIZE(post_table); i++) {
 417                 if (target * post_table[i].div >=  90000000 &&
 418                     target * post_table[i].div <= 100000000) {
 419                         pll_div->freqmode = post_table[i].freqmode;
 420                         pll_div->postscale = post_table[i].postscale;
 421                         target *= post_table[i].div;
 422                         break;
 423                 }
 424         }
 425
 426         if (i == ARRAY_SIZE(post_table)) {
 427                 printk(KERN_ERR "wm8580: Unable to scale output frequency "
 428                        "%u\n", target);
 429                 return -EINVAL;
 430         }
 431
 432         Ndiv = target / source;
 433
 434         if (Ndiv < 5) {
 435                 source /= 2;
 436                 pll_div->prescale = 1;
 437                 Ndiv = target / source;
 438         } else
 439                 pll_div->prescale = 0;
 440
 441         if ((Ndiv < 5) || (Ndiv > 13)) {
 442                 printk(KERN_ERR
 443                         "WM8580 N=%d outside supported range\n", Ndiv);
 444                 return -EINVAL;
 445         }
 446
 447         pll_div->n = Ndiv;
 448         Nmod = target % source;
 449         Kpart = FIXED_PLL_SIZE * (long long)Nmod;
 450
 451         do_div(Kpart, source);
 452
 453         K = Kpart & 0xFFFFFFFF;
 454
 455         pll_div->k = K;
 456
 457         pr_debug("PLL %x.%x prescale %d freqmode %d postscale %d\n",
 458                  pll_div->n, pll_div->k, pll_div->prescale, pll_div->freqmode,
 459                  pll_div->postscale);
 460
 461         return 0;
 462 }
 463
 464 static int wm8580_set_dai_pll(struct snd_soc_dai *codec_dai,
 465                 int pll_id, unsigned int freq_in, unsigned int freq_out)
 466 {
 467         int offset;
 468         struct snd_soc_codec *codec = codec_dai->codec;
 469         struct wm8580_priv *wm8580 = codec->private_data;
 470         struct pll_state *state;
 471         struct _pll_div pll_div;
 472         unsigned int reg;
 473         unsigned int pwr_mask;
 474         int ret;
 475
 476         /* GCC isn't able to work out the ifs below for initialising/using
 477          * pll_div so suppress warnings.
 478          */
 479         memset(&pll_div, 0, sizeof(pll_div));
 480
 481         switch (pll_id) {
 482         case WM8580_PLLA:
 483                 state = &wm8580->a;
 484                 offset = 0;
 485                 pwr_mask = WM8580_PWRDN2_PLLAPD;
 486                 break;
 487         case WM8580_PLLB:
 488                 state = &wm8580->b;
 489                 offset = 4;
 490                 pwr_mask = WM8580_PWRDN2_PLLBPD;
 491                 break;
 492         default:
 493                 return -ENODEV;
 494         }
 495
 496         if (freq_in && freq_out) {
 497                 ret = pll_factors(&pll_div, freq_out, freq_in);
 498                 if (ret != 0)
 499                         return ret;
 500         }
 501
 502         state->in = freq_in;
 503         state->out = freq_out;
 504
 505         /* Always disable the PLL - it is not safe to leave it running
 506          * while reprogramming it.
 507          */
 508         reg = wm8580_read(codec, WM8580_PWRDN2);
 509         wm8580_write(codec, WM8580_PWRDN2, reg | pwr_mask);
 510
 511         if (!freq_in || !freq_out)
 512                 return 0;
 513
 514         wm8580_write(codec, WM8580_PLLA1 + offset, pll_div.k & 0x1ff);
 515         wm8580_write(codec, WM8580_PLLA2 + offset, (pll_div.k >> 9) & 0xff);
 516         wm8580_write(codec, WM8580_PLLA3 + offset,
 517                      (pll_div.k >> 18 & 0xf) | (pll_div.n << 4));
 518
 519         reg = wm8580_read(codec, WM8580_PLLA4 + offset);
 520         reg &= ~0x3f;
 521         reg |= pll_div.prescale | pll_div.postscale << 1 |
 522                 pll_div.freqmode << 4;
 523
 524         wm8580_write(codec, WM8580_PLLA4 + offset, reg);
 525
 526         /* All done, turn it on */
 527         reg = wm8580_read(codec, WM8580_PWRDN2);
 528         wm8580_write(codec, WM8580_PWRDN2, reg & ~pwr_mask);
 529
 530         return 0;
 531 }
 532
 533 /*
 534  * Set PCM DAI bit size and sample rate.
 535  */
 536 static int wm8580_paif_hw_params(struct snd_pcm_substream *substream,
 537                                  struct snd_pcm_hw_params *params,
 538                                  struct snd_soc_dai *dai)
 539 {
 540         struct snd_soc_pcm_runtime *rtd = substream->private_data;
 541         struct snd_soc_device *socdev = rtd->socdev;
 542         struct snd_soc_codec *codec = socdev->codec;
 543         u16 paifb = wm8580_read(codec, WM8580_PAIF3 + dai->id);
 544
 545         paifb &= ~WM8580_AIF_LENGTH_MASK;
 546         /* bit size */
 547         switch (params_format(params)) {
 548         case SNDRV_PCM_FORMAT_S16_LE:
 549                 break;
 550         case SNDRV_PCM_FORMAT_S20_3LE:
 551                 paifb |= WM8580_AIF_LENGTH_20;
 552                 break;
 553         case SNDRV_PCM_FORMAT_S24_LE:
 554                 paifb |= WM8580_AIF_LENGTH_24;
 555                 break;
 556         case SNDRV_PCM_FORMAT_S32_LE:
 557                 paifb |= WM8580_AIF_LENGTH_24;
 558                 break;
 559         default:
 560                 return -EINVAL;
 561         }
 562
 563         wm8580_write(codec, WM8580_PAIF3 + dai->id, paifb);
 564         return 0;
 565 }
 566
 567 static int wm8580_set_paif_dai_fmt(struct snd_soc_dai *codec_dai,
 568                                       unsigned int fmt)
 569 {
 570         struct snd_soc_codec *codec = codec_dai->codec;
 571         unsigned int aifa;
 572         unsigned int aifb;
 573         int can_invert_lrclk;
 574
 575         aifa = wm8580_read(codec, WM8580_PAIF1 + codec_dai->id);
 576         aifb = wm8580_read(codec, WM8580_PAIF3 + codec_dai->id);
 577
 578         aifb &= ~(WM8580_AIF_FMT_MASK | WM8580_AIF_LRP | WM8580_AIF_BCP);
 579
 580         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
 581         case SND_SOC_DAIFMT_CBS_CFS:
 582                 aifa &= ~WM8580_AIF_MS;
 583                 break;
 584         case SND_SOC_DAIFMT_CBM_CFM:
 585                 aifa |= WM8580_AIF_MS;
 586                 break;
 587         default:
 588                 return -EINVAL;
 589         }
 590
 591         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
 592         case SND_SOC_DAIFMT_I2S:
 593                 can_invert_lrclk = 1;
 594                 aifb |= WM8580_AIF_FMT_I2S;
 595                 break;
 596         case SND_SOC_DAIFMT_RIGHT_J:
 597                 can_invert_lrclk = 1;
 598                 aifb |= WM8580_AIF_FMT_RIGHTJ;
 599                 break;
 600         case SND_SOC_DAIFMT_LEFT_J:
 601                 can_invert_lrclk = 1;
 602                 aifb |= WM8580_AIF_FMT_LEFTJ;
 603                 break;
 604         case SND_SOC_DAIFMT_DSP_A:
 605                 can_invert_lrclk = 0;
 606                 aifb |= WM8580_AIF_FMT_DSP;
 607                 break;
 608         case SND_SOC_DAIFMT_DSP_B:
 609                 can_invert_lrclk = 0;
 610                 aifb |= WM8580_AIF_FMT_DSP;
 611                 aifb |= WM8580_AIF_LRP;
 612                 break;
 613         default:
 614                 return -EINVAL;
 615         }
 616
 617         switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
 618         case SND_SOC_DAIFMT_NB_NF:
 619                 break;
 620
 621         case SND_SOC_DAIFMT_IB_IF:
 622                 if (!can_invert_lrclk)
 623                         return -EINVAL;
 624                 aifb |= WM8580_AIF_BCP;
 625                 aifb |= WM8580_AIF_LRP;
 626                 break;
 627
 628         case SND_SOC_DAIFMT_IB_NF:
 629                 aifb |= WM8580_AIF_BCP;
 630                 break;
 631
 632         case SND_SOC_DAIFMT_NB_IF:
 633                 if (!can_invert_lrclk)
 634                         return -EINVAL;
 635                 aifb |= WM8580_AIF_LRP;
 636                 break;
 637
 638         default:
 639                 return -EINVAL;
 640         }
 641
 642         wm8580_write(codec, WM8580_PAIF1 + codec_dai->id, aifa);
 643         wm8580_write(codec, WM8580_PAIF3 + codec_dai->id, aifb);
 644
 645         return 0;
 646 }
 647
 648 static int wm8580_set_dai_clkdiv(struct snd_soc_dai *codec_dai,
 649                                  int div_id, int div)
 650 {
 651         struct snd_soc_codec *codec = codec_dai->codec;
 652         unsigned int reg;
 653
 654         switch (div_id) {
 655         case WM8580_MCLK:
 656                 reg = wm8580_read(codec, WM8580_PLLB4);
 657                 reg &= ~WM8580_PLLB4_MCLKOUTSRC_MASK;
 658
 659                 switch (div) {
 660                 case WM8580_CLKSRC_MCLK:
 661                         /* Input */
 662                         break;
 663
 664                 case WM8580_CLKSRC_PLLA:
 665                         reg |= WM8580_PLLB4_MCLKOUTSRC_PLLA;
 666                         break;
 667                 case WM8580_CLKSRC_PLLB:
 668                         reg |= WM8580_PLLB4_MCLKOUTSRC_PLLB;
 669                         break;
 670
 671                 case WM8580_CLKSRC_OSC:
 672                         reg |= WM8580_PLLB4_MCLKOUTSRC_OSC;
 673                         break;
 674
 675                 default:
 676                         return -EINVAL;
 677                 }
 678                 wm8580_write(codec, WM8580_PLLB4, reg);
 679                 break;
 680
 681         case WM8580_DAC_CLKSEL:
 682                 reg = wm8580_read(codec, WM8580_CLKSEL);
 683                 reg &= ~WM8580_CLKSEL_DAC_CLKSEL_MASK;
 684
 685                 switch (div) {
 686                 case WM8580_CLKSRC_MCLK:
 687                         break;
 688
 689                 case WM8580_CLKSRC_PLLA:
 690                         reg |= WM8580_CLKSEL_DAC_CLKSEL_PLLA;
 691                         break;
 692
 693                 case WM8580_CLKSRC_PLLB:
 694                         reg |= WM8580_CLKSEL_DAC_CLKSEL_PLLB;
 695                         break;
 696
 697                 default:
 698                         return -EINVAL;
 699                 }
 700                 wm8580_write(codec, WM8580_CLKSEL, reg);
 701                 break;
 702
 703         case WM8580_CLKOUTSRC:
 704                 reg = wm8580_read(codec, WM8580_PLLB4);
 705                 reg &= ~WM8580_PLLB4_CLKOUTSRC_MASK;
 706
 707                 switch (div) {
 708                 case WM8580_CLKSRC_NONE:
 709                         break;
 710
 711                 case WM8580_CLKSRC_PLLA:
 712                         reg |= WM8580_PLLB4_CLKOUTSRC_PLLACLK;
 713                         break;
 714
 715                 case WM8580_CLKSRC_PLLB:
 716                         reg |= WM8580_PLLB4_CLKOUTSRC_PLLBCLK;
 717                         break;
 718
 719                 case WM8580_CLKSRC_OSC:
 720                         reg |= WM8580_PLLB4_CLKOUTSRC_OSCCLK;
 721                         break;
 722
 723                 default:
 724                         return -EINVAL;
 725                 }
 726                 wm8580_write(codec, WM8580_PLLB4, reg);
 727                 break;
 728
 729         default:
 730                 return -EINVAL;
 731         }
 732
 733         return 0;
 734 }
 735
 736 static int wm8580_digital_mute(struct snd_soc_dai *codec_dai, int mute)
 737 {
 738         struct snd_soc_codec *codec = codec_dai->codec;
 739         unsigned int reg;
 740
 741         reg = wm8580_read(codec, WM8580_DAC_CONTROL5);
 742
 743         if (mute)
 744                 reg |= WM8580_DAC_CONTROL5_MUTEALL;
 745         else
 746                 reg &= ~WM8580_DAC_CONTROL5_MUTEALL;
 747
 748         wm8580_write(codec, WM8580_DAC_CONTROL5, reg);
 749
 750         return 0;
 751 }
 752
 753 static int wm8580_set_bias_level(struct snd_soc_codec *codec,
 754         enum snd_soc_bias_level level)
 755 {
 756         u16 reg;
 757         switch (level) {
 758         case SND_SOC_BIAS_ON:
 759         case SND_SOC_BIAS_PREPARE:
 760         case SND_SOC_BIAS_STANDBY:
 761                 break;
 762         case SND_SOC_BIAS_OFF:
 763                 reg = wm8580_read(codec, WM8580_PWRDN1);
 764                 wm8580_write(codec, WM8580_PWRDN1, reg | WM8580_PWRDN1_PWDN);
 765                 break;
 766         }
 767         codec->bias_level = level;
 768         return 0;
 769 }
 770
 771 #define WM8580_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
 772                         SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
 773
 774 struct snd_soc_dai wm8580_dai[] = {
 775         {
 776                 .name = "WM8580 PAIFRX",
 777                 .id = 0,
 778                 .playback = {
 779                         .stream_name = "Playback",
 780                         .channels_min = 1,
 781                         .channels_max = 6,
 782                         .rates = SNDRV_PCM_RATE_8000_192000,
 783                         .formats = WM8580_FORMATS,
 784                 },
 785                 .ops = {
 786                          .hw_params = wm8580_paif_hw_params,
 787                          .set_fmt = wm8580_set_paif_dai_fmt,
 788                          .set_clkdiv = wm8580_set_dai_clkdiv,
 789                          .set_pll = wm8580_set_dai_pll,
 790                          .digital_mute = wm8580_digital_mute,
 791                  },
 792         },
 793         {
 794                 .name = "WM8580 PAIFTX",
 795                 .id = 1,
 796                 .capture = {
 797                         .stream_name = "Capture",
 798                         .channels_min = 2,
 799                         .channels_max = 2,
 800                         .rates = SNDRV_PCM_RATE_8000_192000,
 801                         .formats = WM8580_FORMATS,
 802                 },
 803                 .ops = {
 804                          .hw_params = wm8580_paif_hw_params,
 805                          .set_fmt = wm8580_set_paif_dai_fmt,
 806                          .set_clkdiv = wm8580_set_dai_clkdiv,
 807                          .set_pll = wm8580_set_dai_pll,
 808                  },
 809         },
 810 };
 811 EXPORT_SYMBOL_GPL(wm8580_dai);
 812
 813 /*
 814  * initialise the WM8580 driver
 815  * register the mixer and dsp interfaces with the kernel
 816  */
 817 static int wm8580_init(struct snd_soc_device *socdev)
 818 {
 819         struct snd_soc_codec *codec = socdev->codec;
 820         int ret = 0;
 821
 822         codec->name = "WM8580";
 823         codec->owner = THIS_MODULE;
 824         codec->read = wm8580_read_reg_cache;
 825         codec->write = wm8580_write;
 826         codec->set_bias_level = wm8580_set_bias_level;
 827         codec->dai = wm8580_dai;
 828         codec->num_dai = ARRAY_SIZE(wm8580_dai);
 829         codec->reg_cache_size = ARRAY_SIZE(wm8580_reg);
 830         codec->reg_cache = kmemdup(wm8580_reg, sizeof(wm8580_reg),
 831                                    GFP_KERNEL);
 832
 833         if (codec->reg_cache == NULL)
 834                 return -ENOMEM;
 835
 836         /* Get the codec into a known state */
 837         wm8580_write(codec, WM8580_RESET, 0);
 838
 839         /* Power up and get individual control of the DACs */
 840         wm8580_write(codec, WM8580_PWRDN1, wm8580_read(codec, WM8580_PWRDN1) &
 841                      ~(WM8580_PWRDN1_PWDN | WM8580_PWRDN1_ALLDACPD));
 842
 843         /* Make VMID high impedence */
 844         wm8580_write(codec, WM8580_ADC_CONTROL1,
 845                      wm8580_read(codec,  WM8580_ADC_CONTROL1) & ~0x100);
 846
 847         /* register pcms */
 848         ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1,
 849                                SNDRV_DEFAULT_STR1);
 850         if (ret < 0) {
 851                 printk(KERN_ERR "wm8580: failed to create pcms\n");
 852                 goto pcm_err;
 853         }
 854
 855         snd_soc_add_controls(codec, wm8580_snd_controls,
 856                                 ARRAY_SIZE(wm8580_snd_controls));
 857         wm8580_add_widgets(codec);
 858
 859         ret = snd_soc_init_card(socdev);
 860         if (ret < 0) {
 861                 printk(KERN_ERR "wm8580: failed to register card\n");
 862                 goto card_err;
 863         }
 864         return ret;
 865
 866 card_err:
 867         snd_soc_free_pcms(socdev);
 868         snd_soc_dapm_free(socdev);
 869 pcm_err:
 870         kfree(codec->reg_cache);
 871         return ret;
 872 }
 873
 874 /* If the i2c layer weren't so broken, we could pass this kind of data
 875    around */
 876 static struct snd_soc_device *wm8580_socdev;
 877
 878 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
 879
 880 /*
 881  * WM8580 2 wire address is determined by GPIO5
 882  * state during powerup.
 883  *    low  = 0x1a
 884  *    high = 0x1b
 885  */
 886
 887 static int wm8580_i2c_probe(struct i2c_client *i2c,
 888                             const struct i2c_device_id *id)
 889 {
 890         struct snd_soc_device *socdev = wm8580_socdev;
 891         struct snd_soc_codec *codec = socdev->codec;
 892         int ret;
 893
 894         i2c_set_clientdata(i2c, codec);
 895         codec->control_data = i2c;
 896
 897         ret = wm8580_init(socdev);
 898         if (ret < 0)
 899                 dev_err(&i2c->dev, "failed to initialise WM8580\n");
 900         return ret;
 901 }
 902
 903 static int wm8580_i2c_remove(struct i2c_client *client)
 904 {
 905         struct snd_soc_codec *codec = i2c_get_clientdata(client);
 906         kfree(codec->reg_cache);
 907         return 0;
 908 }
 909
 910 static const struct i2c_device_id wm8580_i2c_id[] = {
 911         { "wm8580", 0 },
 912         { }
 913 };
 914 MODULE_DEVICE_TABLE(i2c, wm8580_i2c_id);
 915
 916 static struct i2c_driver wm8580_i2c_driver = {
 917         .driver = {
 918                 .name = "WM8580 I2C Codec",
 919                 .owner = THIS_MODULE,
 920         },
 921         .probe =    wm8580_i2c_probe,
 922         .remove =   wm8580_i2c_remove,
 923         .id_table = wm8580_i2c_id,
 924 };
 925
 926 static int wm8580_add_i2c_device(struct platform_device *pdev,
 927                                  const struct wm8580_setup_data *setup)
 928 {
 929         struct i2c_board_info info;
 930         struct i2c_adapter *adapter;
 931         struct i2c_client *client;
 932         int ret;
 933
 934         ret = i2c_add_driver(&wm8580_i2c_driver);
 935         if (ret != 0) {
 936                 dev_err(&pdev->dev, "can't add i2c driver\n");
 937                 return ret;
 938         }
 939
 940         memset(&info, 0, sizeof(struct i2c_board_info));
 941         info.addr = setup->i2c_address;
 942         strlcpy(info.type, "wm8580", I2C_NAME_SIZE);
 943
 944         adapter = i2c_get_adapter(setup->i2c_bus);
 945         if (!adapter) {
 946                 dev_err(&pdev->dev, "can't get i2c adapter %d\n",
 947                         setup->i2c_bus);
 948                 goto err_driver;
 949         }
 950
 951         client = i2c_new_device(adapter, &info);
 952         i2c_put_adapter(adapter);
 953         if (!client) {
 954                 dev_err(&pdev->dev, "can't add i2c device at 0x%x\n",
 955                         (unsigned int)info.addr);
 956                 goto err_driver;
 957         }
 958
 959         return 0;
 960
 961 err_driver:
 962         i2c_del_driver(&wm8580_i2c_driver);
 963         return -ENODEV;
 964 }
 965 #endif
 966
 967 static int wm8580_probe(struct platform_device *pdev)
 968 {
 969         struct snd_soc_device *socdev = platform_get_drvdata(pdev);
 970         struct wm8580_setup_data *setup;
 971         struct snd_soc_codec *codec;
 972         struct wm8580_priv *wm8580;
 973         int ret = 0;
 974
 975         pr_info("WM8580 Audio Codec %s\n", WM8580_VERSION);
 976
 977         setup = socdev->codec_data;
 978         codec = kzalloc(sizeof(struct snd_soc_codec), GFP_KERNEL);
 979         if (codec == NULL)
 980                 return -ENOMEM;
 981
 982         wm8580 = kzalloc(sizeof(struct wm8580_priv), GFP_KERNEL);
 983         if (wm8580 == NULL) {
 984                 kfree(codec);
 985                 return -ENOMEM;
 986         }
 987
 988         codec->private_data = wm8580;
 989         socdev->codec = codec;
 990         mutex_init(&codec->mutex);
 991         INIT_LIST_HEAD(&codec->dapm_widgets);
 992         INIT_LIST_HEAD(&codec->dapm_paths);
 993         wm8580_socdev = socdev;
 994
 995 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
 996         if (setup->i2c_address) {
 997                 codec->hw_write = (hw_write_t)i2c_master_send;
 998                 ret = wm8580_add_i2c_device(pdev, setup);
 999         }
1000 #else
1001                 /* Add other interfaces here */
1002 #endif
1003         return ret;
1004 }
1005
1006 /* power down chip */
1007 static int wm8580_remove(struct platform_device *pdev)
1008 {
1009         struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1010         struct snd_soc_codec *codec = socdev->codec;
1011
1012         if (codec->control_data)
1013                 wm8580_set_bias_level(codec, SND_SOC_BIAS_OFF);
1014         snd_soc_free_pcms(socdev);
1015         snd_soc_dapm_free(socdev);
1016 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1017         i2c_unregister_device(codec->control_data);
1018         i2c_del_driver(&wm8580_i2c_driver);
1019 #endif
1020         kfree(codec->private_data);
1021         kfree(codec);
1022
1023         return 0;
1024 }
1025
1026 struct snd_soc_codec_device soc_codec_dev_wm8580 = {
1027         .probe =        wm8580_probe,
1028         .remove =       wm8580_remove,
1029 };
1030 EXPORT_SYMBOL_GPL(soc_codec_dev_wm8580);
1031
1032 static int __init wm8580_modinit(void)
1033 {
1034         return snd_soc_register_dais(wm8580_dai, ARRAY_SIZE(wm8580_dai));
1035 }
1036 module_init(wm8580_modinit);
1037
1038 static void __exit wm8580_exit(void)
1039 {
1040         snd_soc_unregister_dais(wm8580_dai, ARRAY_SIZE(wm8580_dai));
1041 }
1042 module_exit(wm8580_exit);
1043
1044 MODULE_DESCRIPTION("ASoC WM8580 driver");
1045 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
1046 MODULE_LICENSE("GPL");