2 * Local APIC handling, local APIC timers
4 * (c) 1999, 2000 Ingo Molnar <mingo@redhat.com>
7 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
8 * thanks to Eric Gilmore
10 * for testing these extensively.
11 * Maciej W. Rozycki : Various updates and fixes.
12 * Mikael Pettersson : Power Management for UP-APIC.
14 * Mikael Pettersson : PM converted to driver model.
17 #include <linux/config.h>
18 #include <linux/init.h>
21 #include <linux/delay.h>
22 #include <linux/bootmem.h>
23 #include <linux/smp_lock.h>
24 #include <linux/interrupt.h>
25 #include <linux/mc146818rtc.h>
26 #include <linux/kernel_stat.h>
27 #include <linux/sysdev.h>
28 #include <linux/module.h>
30 #include <asm/atomic.h>
33 #include <asm/mpspec.h>
34 #include <asm/pgalloc.h>
35 #include <asm/mach_apic.h>
38 #include <asm/proto.h>
39 #include <asm/timex.h>
42 int apic_runs_main_timer;
43 int apic_calibrate_pmtmr __initdata;
45 int disable_apic_timer __initdata;
48 * cpu_mask that denotes the CPUs that needs timer interrupt coming in as
49 * IPIs in place of local APIC timers
51 static cpumask_t timer_interrupt_broadcast_ipi_mask;
53 /* Using APIC to generate smp_local_timer_interrupt? */
54 int using_apic_timer = 0;
56 static void apic_pm_activate(void);
58 void enable_NMI_through_LVT0 (void * dummy)
62 v = APIC_DM_NMI; /* unmask and set to NMI */
63 apic_write(APIC_LVT0, v);
68 unsigned int v, maxlvt;
70 v = apic_read(APIC_LVR);
71 maxlvt = GET_APIC_MAXLVT(v);
75 void clear_local_APIC(void)
80 maxlvt = get_maxlvt();
83 * Masking an LVT entry on a P6 can trigger a local APIC error
84 * if the vector is zero. Mask LVTERR first to prevent this.
87 v = ERROR_APIC_VECTOR; /* any non-zero vector will do */
88 apic_write(APIC_LVTERR, v | APIC_LVT_MASKED);
91 * Careful: we have to set masks only first to deassert
92 * any level-triggered sources.
94 v = apic_read(APIC_LVTT);
95 apic_write(APIC_LVTT, v | APIC_LVT_MASKED);
96 v = apic_read(APIC_LVT0);
97 apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
98 v = apic_read(APIC_LVT1);
99 apic_write(APIC_LVT1, v | APIC_LVT_MASKED);
101 v = apic_read(APIC_LVTPC);
102 apic_write(APIC_LVTPC, v | APIC_LVT_MASKED);
106 * Clean APIC state for other OSs:
108 apic_write(APIC_LVTT, APIC_LVT_MASKED);
109 apic_write(APIC_LVT0, APIC_LVT_MASKED);
110 apic_write(APIC_LVT1, APIC_LVT_MASKED);
112 apic_write(APIC_LVTERR, APIC_LVT_MASKED);
114 apic_write(APIC_LVTPC, APIC_LVT_MASKED);
115 v = GET_APIC_VERSION(apic_read(APIC_LVR));
116 apic_write(APIC_ESR, 0);
120 void __init connect_bsp_APIC(void)
124 * Do not trust the local APIC being empty at bootup.
128 * PIC mode, enable APIC mode in the IMCR, i.e.
129 * connect BSP's local APIC to INT and NMI lines.
131 apic_printk(APIC_VERBOSE, "leaving PIC mode, enabling APIC mode.\n");
137 void disconnect_bsp_APIC(int virt_wire_setup)
141 * Put the board back into PIC mode (has an effect
142 * only on certain older boards). Note that APIC
143 * interrupts, including IPIs, won't work beyond
144 * this point! The only exception are INIT IPIs.
146 apic_printk(APIC_QUIET, "disabling APIC mode, entering PIC mode.\n");
151 /* Go back to Virtual Wire compatibility mode */
154 /* For the spurious interrupt use vector F, and enable it */
155 value = apic_read(APIC_SPIV);
156 value &= ~APIC_VECTOR_MASK;
157 value |= APIC_SPIV_APIC_ENABLED;
159 apic_write(APIC_SPIV, value);
161 if (!virt_wire_setup) {
162 /* For LVT0 make it edge triggered, active high, external and enabled */
163 value = apic_read(APIC_LVT0);
164 value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING |
165 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
166 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED );
167 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
168 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT);
169 apic_write(APIC_LVT0, value);
173 apic_write(APIC_LVT0, APIC_LVT_MASKED);
176 /* For LVT1 make it edge triggered, active high, nmi and enabled */
177 value = apic_read(APIC_LVT1);
179 APIC_MODE_MASK | APIC_SEND_PENDING |
180 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
181 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED);
182 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
183 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI);
184 apic_write(APIC_LVT1, value);
188 void disable_local_APIC(void)
195 * Disable APIC (implies clearing of registers
198 value = apic_read(APIC_SPIV);
199 value &= ~APIC_SPIV_APIC_ENABLED;
200 apic_write(APIC_SPIV, value);
204 * This is to verify that we're looking at a real local APIC.
205 * Check these against your board if the CPUs aren't getting
206 * started for no apparent reason.
208 int __init verify_local_APIC(void)
210 unsigned int reg0, reg1;
213 * The version register is read-only in a real APIC.
215 reg0 = apic_read(APIC_LVR);
216 apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg0);
217 apic_write(APIC_LVR, reg0 ^ APIC_LVR_MASK);
218 reg1 = apic_read(APIC_LVR);
219 apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg1);
222 * The two version reads above should print the same
223 * numbers. If the second one is different, then we
224 * poke at a non-APIC.
230 * Check if the version looks reasonably.
232 reg1 = GET_APIC_VERSION(reg0);
233 if (reg1 == 0x00 || reg1 == 0xff)
236 if (reg1 < 0x02 || reg1 == 0xff)
240 * The ID register is read/write in a real APIC.
242 reg0 = apic_read(APIC_ID);
243 apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg0);
244 apic_write(APIC_ID, reg0 ^ APIC_ID_MASK);
245 reg1 = apic_read(APIC_ID);
246 apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg1);
247 apic_write(APIC_ID, reg0);
248 if (reg1 != (reg0 ^ APIC_ID_MASK))
252 * The next two are just to see if we have sane values.
253 * They're only really relevant if we're in Virtual Wire
254 * compatibility mode, but most boxes are anymore.
256 reg0 = apic_read(APIC_LVT0);
257 apic_printk(APIC_DEBUG,"Getting LVT0: %x\n", reg0);
258 reg1 = apic_read(APIC_LVT1);
259 apic_printk(APIC_DEBUG, "Getting LVT1: %x\n", reg1);
264 void __init sync_Arb_IDs(void)
266 /* Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 */
267 unsigned int ver = GET_APIC_VERSION(apic_read(APIC_LVR));
268 if (ver >= 0x14) /* P4 or higher */
274 apic_wait_icr_idle();
276 apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n");
277 apic_write(APIC_ICR, APIC_DEST_ALLINC | APIC_INT_LEVELTRIG
281 extern void __error_in_apic_c (void);
284 * An initial setup of the virtual wire mode.
286 void __init init_bsp_APIC(void)
291 * Don't do the setup now if we have a SMP BIOS as the
292 * through-I/O-APIC virtual wire mode might be active.
294 if (smp_found_config || !cpu_has_apic)
297 value = apic_read(APIC_LVR);
300 * Do not trust the local APIC being empty at bootup.
307 value = apic_read(APIC_SPIV);
308 value &= ~APIC_VECTOR_MASK;
309 value |= APIC_SPIV_APIC_ENABLED;
310 value |= APIC_SPIV_FOCUS_DISABLED;
311 value |= SPURIOUS_APIC_VECTOR;
312 apic_write(APIC_SPIV, value);
315 * Set up the virtual wire mode.
317 apic_write(APIC_LVT0, APIC_DM_EXTINT);
319 apic_write(APIC_LVT1, value);
322 void __cpuinit setup_local_APIC (void)
324 unsigned int value, maxlvt;
326 value = apic_read(APIC_LVR);
328 if ((SPURIOUS_APIC_VECTOR & 0x0f) != 0x0f)
332 * Double-check whether this APIC is really registered.
333 * This is meaningless in clustered apic mode, so we skip it.
335 if (!apic_id_registered())
339 * Intel recommends to set DFR, LDR and TPR before enabling
340 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
341 * document number 292116). So here it goes...
346 * Set Task Priority to 'accept all'. We never change this
349 value = apic_read(APIC_TASKPRI);
350 value &= ~APIC_TPRI_MASK;
351 apic_write(APIC_TASKPRI, value);
354 * Now that we are all set up, enable the APIC
356 value = apic_read(APIC_SPIV);
357 value &= ~APIC_VECTOR_MASK;
361 value |= APIC_SPIV_APIC_ENABLED;
364 * Some unknown Intel IO/APIC (or APIC) errata is biting us with
365 * certain networking cards. If high frequency interrupts are
366 * happening on a particular IOAPIC pin, plus the IOAPIC routing
367 * entry is masked/unmasked at a high rate as well then sooner or
368 * later IOAPIC line gets 'stuck', no more interrupts are received
369 * from the device. If focus CPU is disabled then the hang goes
372 * [ This bug can be reproduced easily with a level-triggered
373 * PCI Ne2000 networking cards and PII/PIII processors, dual
377 * Actually disabling the focus CPU check just makes the hang less
378 * frequent as it makes the interrupt distributon model be more
379 * like LRU than MRU (the short-term load is more even across CPUs).
380 * See also the comment in end_level_ioapic_irq(). --macro
383 /* Enable focus processor (bit==0) */
384 value &= ~APIC_SPIV_FOCUS_DISABLED;
386 /* Disable focus processor (bit==1) */
387 value |= APIC_SPIV_FOCUS_DISABLED;
390 * Set spurious IRQ vector
392 value |= SPURIOUS_APIC_VECTOR;
393 apic_write(APIC_SPIV, value);
398 * set up through-local-APIC on the BP's LINT0. This is not
399 * strictly necessary in pure symmetric-IO mode, but sometimes
400 * we delegate interrupts to the 8259A.
403 * TODO: set up through-local-APIC from through-I/O-APIC? --macro
405 value = apic_read(APIC_LVT0) & APIC_LVT_MASKED;
406 if (!smp_processor_id() && (pic_mode || !value)) {
407 value = APIC_DM_EXTINT;
408 apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n", smp_processor_id());
410 value = APIC_DM_EXTINT | APIC_LVT_MASKED;
411 apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n", smp_processor_id());
413 apic_write(APIC_LVT0, value);
416 * only the BP should see the LINT1 NMI signal, obviously.
418 if (!smp_processor_id())
421 value = APIC_DM_NMI | APIC_LVT_MASKED;
422 apic_write(APIC_LVT1, value);
426 maxlvt = get_maxlvt();
427 oldvalue = apic_read(APIC_ESR);
428 value = ERROR_APIC_VECTOR; // enables sending errors
429 apic_write(APIC_LVTERR, value);
431 * spec says clear errors after enabling vector.
434 apic_write(APIC_ESR, 0);
435 value = apic_read(APIC_ESR);
436 if (value != oldvalue)
437 apic_printk(APIC_VERBOSE,
438 "ESR value after enabling vector: %08x, after %08x\n",
442 nmi_watchdog_default();
443 if (nmi_watchdog == NMI_LOCAL_APIC)
444 setup_apic_nmi_watchdog();
451 /* 'active' is true if the local APIC was enabled by us and
452 not the BIOS; this signifies that we are also responsible
453 for disabling it before entering apm/acpi suspend */
455 /* r/w apic fields */
456 unsigned int apic_id;
457 unsigned int apic_taskpri;
458 unsigned int apic_ldr;
459 unsigned int apic_dfr;
460 unsigned int apic_spiv;
461 unsigned int apic_lvtt;
462 unsigned int apic_lvtpc;
463 unsigned int apic_lvt0;
464 unsigned int apic_lvt1;
465 unsigned int apic_lvterr;
466 unsigned int apic_tmict;
467 unsigned int apic_tdcr;
468 unsigned int apic_thmr;
471 static int lapic_suspend(struct sys_device *dev, pm_message_t state)
475 if (!apic_pm_state.active)
478 apic_pm_state.apic_id = apic_read(APIC_ID);
479 apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI);
480 apic_pm_state.apic_ldr = apic_read(APIC_LDR);
481 apic_pm_state.apic_dfr = apic_read(APIC_DFR);
482 apic_pm_state.apic_spiv = apic_read(APIC_SPIV);
483 apic_pm_state.apic_lvtt = apic_read(APIC_LVTT);
484 apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC);
485 apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0);
486 apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1);
487 apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR);
488 apic_pm_state.apic_tmict = apic_read(APIC_TMICT);
489 apic_pm_state.apic_tdcr = apic_read(APIC_TDCR);
490 apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR);
491 local_save_flags(flags);
493 disable_local_APIC();
494 local_irq_restore(flags);
498 static int lapic_resume(struct sys_device *dev)
503 if (!apic_pm_state.active)
506 local_irq_save(flags);
507 rdmsr(MSR_IA32_APICBASE, l, h);
508 l &= ~MSR_IA32_APICBASE_BASE;
509 l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr;
510 wrmsr(MSR_IA32_APICBASE, l, h);
511 apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED);
512 apic_write(APIC_ID, apic_pm_state.apic_id);
513 apic_write(APIC_DFR, apic_pm_state.apic_dfr);
514 apic_write(APIC_LDR, apic_pm_state.apic_ldr);
515 apic_write(APIC_TASKPRI, apic_pm_state.apic_taskpri);
516 apic_write(APIC_SPIV, apic_pm_state.apic_spiv);
517 apic_write(APIC_LVT0, apic_pm_state.apic_lvt0);
518 apic_write(APIC_LVT1, apic_pm_state.apic_lvt1);
519 apic_write(APIC_LVTTHMR, apic_pm_state.apic_thmr);
520 apic_write(APIC_LVTPC, apic_pm_state.apic_lvtpc);
521 apic_write(APIC_LVTT, apic_pm_state.apic_lvtt);
522 apic_write(APIC_TDCR, apic_pm_state.apic_tdcr);
523 apic_write(APIC_TMICT, apic_pm_state.apic_tmict);
524 apic_write(APIC_ESR, 0);
526 apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr);
527 apic_write(APIC_ESR, 0);
529 local_irq_restore(flags);
533 static struct sysdev_class lapic_sysclass = {
534 set_kset_name("lapic"),
535 .resume = lapic_resume,
536 .suspend = lapic_suspend,
539 static struct sys_device device_lapic = {
541 .cls = &lapic_sysclass,
544 static void __cpuinit apic_pm_activate(void)
546 apic_pm_state.active = 1;
549 static int __init init_lapic_sysfs(void)
554 /* XXX: remove suspend/resume procs if !apic_pm_state.active? */
555 error = sysdev_class_register(&lapic_sysclass);
557 error = sysdev_register(&device_lapic);
560 device_initcall(init_lapic_sysfs);
562 #else /* CONFIG_PM */
564 static void apic_pm_activate(void) { }
566 #endif /* CONFIG_PM */
568 static int __init apic_set_verbosity(char *str)
570 if (strcmp("debug", str) == 0)
571 apic_verbosity = APIC_DEBUG;
572 else if (strcmp("verbose", str) == 0)
573 apic_verbosity = APIC_VERBOSE;
575 printk(KERN_WARNING "APIC Verbosity level %s not recognised"
576 " use apic=verbose or apic=debug", str);
581 __setup("apic=", apic_set_verbosity);
584 * Detect and enable local APICs on non-SMP boards.
585 * Original code written by Keir Fraser.
586 * On AMD64 we trust the BIOS - if it says no APIC it is likely
587 * not correctly set up (usually the APIC timer won't work etc.)
590 static int __init detect_init_APIC (void)
593 printk(KERN_INFO "No local APIC present\n");
597 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
602 void __init init_apic_mappings(void)
604 unsigned long apic_phys;
607 * If no local APIC can be found then set up a fake all
608 * zeroes page to simulate the local APIC and another
609 * one for the IO-APIC.
611 if (!smp_found_config && detect_init_APIC()) {
612 apic_phys = (unsigned long) alloc_bootmem_pages(PAGE_SIZE);
613 apic_phys = __pa(apic_phys);
615 apic_phys = mp_lapic_addr;
617 set_fixmap_nocache(FIX_APIC_BASE, apic_phys);
618 apic_printk(APIC_VERBOSE,"mapped APIC to %16lx (%16lx)\n", APIC_BASE, apic_phys);
621 * Fetch the APIC ID of the BSP in case we have a
622 * default configuration (or the MP table is broken).
624 boot_cpu_id = GET_APIC_ID(apic_read(APIC_ID));
626 #ifdef CONFIG_X86_IO_APIC
628 unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0;
631 for (i = 0; i < nr_ioapics; i++) {
632 if (smp_found_config) {
633 ioapic_phys = mp_ioapics[i].mpc_apicaddr;
635 ioapic_phys = (unsigned long) alloc_bootmem_pages(PAGE_SIZE);
636 ioapic_phys = __pa(ioapic_phys);
638 set_fixmap_nocache(idx, ioapic_phys);
639 apic_printk(APIC_VERBOSE,"mapped IOAPIC to %016lx (%016lx)\n",
640 __fix_to_virt(idx), ioapic_phys);
648 * This function sets up the local APIC timer, with a timeout of
649 * 'clocks' APIC bus clock. During calibration we actually call
650 * this function twice on the boot CPU, once with a bogus timeout
651 * value, second time for real. The other (noncalibrating) CPUs
652 * call this function only once, with the real, calibrated value.
654 * We do reads before writes even if unnecessary, to get around the
655 * P5 APIC double write bug.
658 #define APIC_DIVISOR 16
660 static void __setup_APIC_LVTT(unsigned int clocks)
662 unsigned int lvtt_value, tmp_value, ver;
663 int cpu = smp_processor_id();
665 ver = GET_APIC_VERSION(apic_read(APIC_LVR));
666 lvtt_value = APIC_LVT_TIMER_PERIODIC | LOCAL_TIMER_VECTOR;
668 if (cpu_isset(cpu, timer_interrupt_broadcast_ipi_mask))
669 lvtt_value |= APIC_LVT_MASKED;
671 apic_write(APIC_LVTT, lvtt_value);
676 tmp_value = apic_read(APIC_TDCR);
677 apic_write(APIC_TDCR, (tmp_value
678 & ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE))
681 apic_write(APIC_TMICT, clocks/APIC_DIVISOR);
684 static void setup_APIC_timer(unsigned int clocks)
688 local_irq_save(flags);
690 /* wait for irq slice */
691 if (vxtime.hpet_address) {
692 int trigger = hpet_readl(HPET_T0_CMP);
693 while (hpet_readl(HPET_COUNTER) >= trigger)
695 while (hpet_readl(HPET_COUNTER) < trigger)
701 c2 |= inb_p(0x40) << 8;
706 c2 |= inb_p(0x40) << 8;
707 } while (c2 - c1 < 300);
709 __setup_APIC_LVTT(clocks);
710 /* Turn off PIT interrupt if we use APIC timer as main timer.
711 Only works with the PM timer right now
712 TBD fix it for HPET too. */
713 if (vxtime.mode == VXTIME_PMTMR &&
714 smp_processor_id() == boot_cpu_id &&
715 apic_runs_main_timer == 1 &&
716 !cpu_isset(boot_cpu_id, timer_interrupt_broadcast_ipi_mask)) {
717 stop_timer_interrupt();
718 apic_runs_main_timer++;
720 local_irq_restore(flags);
724 * In this function we calibrate APIC bus clocks to the external
725 * timer. Unfortunately we cannot use jiffies and the timer irq
726 * to calibrate, since some later bootup code depends on getting
727 * the first irq? Ugh.
729 * We want to do the calibration only once since we
730 * want to have local timer irqs syncron. CPUs connected
731 * by the same APIC bus have the very same bus frequency.
732 * And we want to have irqs off anyways, no accidental
736 #define TICK_COUNT 100000000
738 static int __init calibrate_APIC_clock(void)
740 int apic, apic_start, tsc, tsc_start;
743 * Put whatever arbitrary (but long enough) timeout
744 * value into the APIC clock, we just want to get the
745 * counter running for calibration.
747 __setup_APIC_LVTT(1000000000);
749 apic_start = apic_read(APIC_TMCCT);
750 #ifdef CONFIG_X86_PM_TIMER
751 if (apic_calibrate_pmtmr && pmtmr_ioport) {
752 pmtimer_wait(5000); /* 5ms wait */
753 apic = apic_read(APIC_TMCCT);
754 result = (apic_start - apic) * 1000L / 5;
761 apic = apic_read(APIC_TMCCT);
763 } while ((tsc - tsc_start) < TICK_COUNT &&
764 (apic - apic_start) < TICK_COUNT);
766 result = (apic_start - apic) * 1000L * cpu_khz /
769 printk("result %d\n", result);
772 printk(KERN_INFO "Detected %d.%03d MHz APIC timer.\n",
773 result / 1000 / 1000, result / 1000 % 1000);
775 return result * APIC_DIVISOR / HZ;
778 static unsigned int calibration_result;
780 void __init setup_boot_APIC_clock (void)
782 if (disable_apic_timer) {
783 printk(KERN_INFO "Disabling APIC timer\n");
787 printk(KERN_INFO "Using local APIC timer interrupts.\n");
788 using_apic_timer = 1;
792 calibration_result = calibrate_APIC_clock();
794 * Now set up the timer for real.
796 setup_APIC_timer(calibration_result);
801 void __cpuinit setup_secondary_APIC_clock(void)
803 local_irq_disable(); /* FIXME: Do we need this? --RR */
804 setup_APIC_timer(calibration_result);
808 void disable_APIC_timer(void)
810 if (using_apic_timer) {
813 v = apic_read(APIC_LVTT);
814 apic_write(APIC_LVTT, v | APIC_LVT_MASKED);
818 void enable_APIC_timer(void)
820 int cpu = smp_processor_id();
822 if (using_apic_timer &&
823 !cpu_isset(cpu, timer_interrupt_broadcast_ipi_mask)) {
826 v = apic_read(APIC_LVTT);
827 apic_write(APIC_LVTT, v & ~APIC_LVT_MASKED);
831 void switch_APIC_timer_to_ipi(void *cpumask)
833 cpumask_t mask = *(cpumask_t *)cpumask;
834 int cpu = smp_processor_id();
836 if (cpu_isset(cpu, mask) &&
837 !cpu_isset(cpu, timer_interrupt_broadcast_ipi_mask)) {
838 disable_APIC_timer();
839 cpu_set(cpu, timer_interrupt_broadcast_ipi_mask);
842 EXPORT_SYMBOL(switch_APIC_timer_to_ipi);
844 void smp_send_timer_broadcast_ipi(void)
848 cpus_and(mask, cpu_online_map, timer_interrupt_broadcast_ipi_mask);
849 if (!cpus_empty(mask)) {
850 send_IPI_mask(mask, LOCAL_TIMER_VECTOR);
854 void switch_ipi_to_APIC_timer(void *cpumask)
856 cpumask_t mask = *(cpumask_t *)cpumask;
857 int cpu = smp_processor_id();
859 if (cpu_isset(cpu, mask) &&
860 cpu_isset(cpu, timer_interrupt_broadcast_ipi_mask)) {
861 cpu_clear(cpu, timer_interrupt_broadcast_ipi_mask);
865 EXPORT_SYMBOL(switch_ipi_to_APIC_timer);
867 int setup_profiling_timer(unsigned int multiplier)
872 #ifdef CONFIG_X86_MCE_AMD
873 void setup_threshold_lvt(unsigned long lvt_off)
876 unsigned long reg = (lvt_off << 4) + 0x500;
877 v |= THRESHOLD_APIC_VECTOR;
880 #endif /* CONFIG_X86_MCE_AMD */
885 * Local timer interrupt handler. It does both profiling and
886 * process statistics/rescheduling.
888 * We do profiling in every local tick, statistics/rescheduling
889 * happen only every 'profiling multiplier' ticks. The default
890 * multiplier is 1 and it can be changed by writing the new multiplier
891 * value into /proc/profile.
894 void smp_local_timer_interrupt(struct pt_regs *regs)
896 profile_tick(CPU_PROFILING, regs);
898 update_process_times(user_mode(regs));
900 if (apic_runs_main_timer > 1 && smp_processor_id() == boot_cpu_id)
901 main_timer_handler(regs);
903 * We take the 'long' return path, and there every subsystem
904 * grabs the appropriate locks (kernel lock/ irq lock).
906 * we might want to decouple profiling from the 'long path',
907 * and do the profiling totally in assembly.
909 * Currently this isn't too much of an issue (performance wise),
910 * we can take more than 100K local irqs per second on a 100 MHz P5.
915 * Local APIC timer interrupt. This is the most natural way for doing
916 * local interrupts, but local timer interrupts can be emulated by
917 * broadcast interrupts too. [in case the hw doesn't support APIC timers]
919 * [ if a single-CPU system runs an SMP kernel then we call the local
920 * interrupt as well. Thus we cannot inline the local irq ... ]
922 void smp_apic_timer_interrupt(struct pt_regs *regs)
925 * the NMI deadlock-detector uses this.
927 add_pda(apic_timer_irqs, 1);
930 * NOTE! We'd better ACK the irq immediately,
931 * because timer handling can be slow.
935 * update_process_times() expects us to have done irq_enter().
936 * Besides, if we don't timer interrupts ignore the global
937 * interrupt lock, which is the WrongThing (tm) to do.
941 smp_local_timer_interrupt(regs);
946 * oem_force_hpet_timer -- force HPET mode for some boxes.
948 * Thus far, the major user of this is IBM's Summit2 series:
950 * Clustered boxes may have unsynced TSC problems if they are
951 * multi-chassis. Use available data to take a good guess.
952 * If in doubt, go HPET.
954 __cpuinit int oem_force_hpet_timer(void)
956 int i, clusters, zeros;
958 DECLARE_BITMAP(clustermap, NUM_APIC_CLUSTERS);
960 bitmap_zero(clustermap, NUM_APIC_CLUSTERS);
962 for (i = 0; i < NR_CPUS; i++) {
963 id = bios_cpu_apicid[i];
964 if (id != BAD_APICID)
965 __set_bit(APIC_CLUSTERID(id), clustermap);
968 /* Problem: Partially populated chassis may not have CPUs in some of
969 * the APIC clusters they have been allocated. Only present CPUs have
970 * bios_cpu_apicid entries, thus causing zeroes in the bitmap. Since
971 * clusters are allocated sequentially, count zeros only if they are
976 for (i = 0; i < NUM_APIC_CLUSTERS; i++) {
977 if (test_bit(i, clustermap)) {
978 clusters += 1 + zeros;
985 * If clusters > 2, then should be multi-chassis. Return 1 for HPET.
986 * Else return 0 to use TSC.
987 * May have to revisit this when multi-core + hyperthreaded CPUs come
988 * out, but AFAIK this will work even for them.
990 return (clusters > 2);
994 * This interrupt should _never_ happen with our APIC/SMP architecture
996 asmlinkage void smp_spurious_interrupt(void)
1002 * Check if this really is a spurious interrupt and ACK it
1003 * if it is a vectored one. Just in case...
1004 * Spurious interrupts should not be ACKed.
1006 v = apic_read(APIC_ISR + ((SPURIOUS_APIC_VECTOR & ~0x1f) >> 1));
1007 if (v & (1 << (SPURIOUS_APIC_VECTOR & 0x1f)))
1011 static unsigned long last_warning;
1012 static unsigned long skipped;
1014 /* see sw-dev-man vol 3, chapter 7.4.13.5 */
1015 if (time_before(last_warning+30*HZ,jiffies)) {
1016 printk(KERN_INFO "spurious APIC interrupt on CPU#%d, %ld skipped.\n",
1017 smp_processor_id(), skipped);
1018 last_warning = jiffies;
1028 * This interrupt should never happen with our APIC/SMP architecture
1031 asmlinkage void smp_error_interrupt(void)
1037 /* First tickle the hardware, only then report what went on. -- REW */
1038 v = apic_read(APIC_ESR);
1039 apic_write(APIC_ESR, 0);
1040 v1 = apic_read(APIC_ESR);
1042 atomic_inc(&irq_err_count);
1044 /* Here is what the APIC error bits mean:
1047 2: Send accept error
1048 3: Receive accept error
1050 5: Send illegal vector
1051 6: Received illegal vector
1052 7: Illegal register address
1054 printk (KERN_DEBUG "APIC error on CPU%d: %02x(%02x)\n",
1055 smp_processor_id(), v , v1);
1062 * This initializes the IO-APIC and APIC hardware if this is
1065 int __init APIC_init_uniprocessor (void)
1068 printk(KERN_INFO "Apic disabled\n");
1071 if (!cpu_has_apic) {
1073 printk(KERN_INFO "Apic disabled by BIOS\n");
1077 verify_local_APIC();
1081 phys_cpu_present_map = physid_mask_of_physid(boot_cpu_id);
1082 apic_write(APIC_ID, SET_APIC_ID(boot_cpu_id));
1086 #ifdef CONFIG_X86_IO_APIC
1087 if (smp_found_config && !skip_ioapic_setup && nr_ioapics)
1092 setup_boot_APIC_clock();
1093 check_nmi_watchdog();
1097 static __init int setup_disableapic(char *str)
1103 static __init int setup_nolapic(char *str)
1109 static __init int setup_noapictimer(char *str)
1111 if (str[0] != ' ' && str[0] != 0)
1113 disable_apic_timer = 1;
1117 static __init int setup_apicmaintimer(char *str)
1119 apic_runs_main_timer = 1;
1123 __setup("apicmaintimer", setup_apicmaintimer);
1125 static __init int setup_noapicmaintimer(char *str)
1127 apic_runs_main_timer = -1;
1130 __setup("noapicmaintimer", setup_noapicmaintimer);
1132 static __init int setup_apicpmtimer(char *s)
1134 apic_calibrate_pmtmr = 1;
1135 return setup_apicmaintimer(NULL);
1137 __setup("apicpmtimer", setup_apicpmtimer);
1139 /* dummy parsing: see setup.c */
1141 __setup("disableapic", setup_disableapic);
1142 __setup("nolapic", setup_nolapic); /* same as disableapic, for compatibility */
1144 __setup("noapictimer", setup_noapictimer);
1146 /* no "lapic" flag - we only use the lapic when the BIOS tells us so. */