git.oblomov.eu Git - linux-2.6/blob - drivers/net/irda/smsc-ircc2.c

   1 /*********************************************************************
   2  * $Id: smsc-ircc2.c,v 1.19.2.5 2002/10/27 11:34:26 dip Exp $
   3  *
   4  * Description:   Driver for the SMC Infrared Communications Controller
   5  * Status:        Experimental.
   6  * Author:        Daniele Peri (peri@csai.unipa.it)
   7  * Created at:
   8  * Modified at:
   9  * Modified by:
  10  *
  11  *     Copyright (c) 2002      Daniele Peri
  12  *     All Rights Reserved.
  13  *     Copyright (c) 2002      Jean Tourrilhes
  14  *     Copyright (c) 2006      Linus Walleij
  15  *
  16  *
  17  * Based on smc-ircc.c:
  18  *
  19  *     Copyright (c) 2001      Stefani Seibold
  20  *     Copyright (c) 1999-2001 Dag Brattli
  21  *     Copyright (c) 1998-1999 Thomas Davis,
  22  *
  23  *      and irport.c:
  24  *
  25  *     Copyright (c) 1997, 1998, 1999-2000 Dag Brattli, All Rights Reserved.
  26  *
  27  *
  28  *     This program is free software; you can redistribute it and/or
  29  *     modify it under the terms of the GNU General Public License as
  30  *     published by the Free Software Foundation; either version 2 of
  31  *     the License, or (at your option) any later version.
  32  *
  33  *     This program is distributed in the hope that it will be useful,
  34  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  35  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  36  *     GNU General Public License for more details.
  37  *
  38  *     You should have received a copy of the GNU General Public License
  39  *     along with this program; if not, write to the Free Software
  40  *     Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  41  *     MA 02111-1307 USA
  42  *
  43  ********************************************************************/
  44
  45 #include <linux/module.h>
  46 #include <linux/kernel.h>
  47 #include <linux/types.h>
  48 #include <linux/skbuff.h>
  49 #include <linux/netdevice.h>
  50 #include <linux/ioport.h>
  51 #include <linux/delay.h>
  52 #include <linux/slab.h>
  53 #include <linux/init.h>
  54 #include <linux/rtnetlink.h>
  55 #include <linux/serial_reg.h>
  56 #include <linux/dma-mapping.h>
  57 #include <linux/pnp.h>
  58 #include <linux/platform_device.h>
  59
  60 #include <asm/io.h>
  61 #include <asm/dma.h>
  62 #include <asm/byteorder.h>
  63
  64 #include <linux/spinlock.h>
  65 #include <linux/pm.h>
  66 #ifdef CONFIG_PCI
  67 #include <linux/pci.h>
  68 #endif
  69
  70 #include <net/irda/wrapper.h>
  71 #include <net/irda/irda.h>
  72 #include <net/irda/irda_device.h>
  73
  74 #include "smsc-ircc2.h"
  75 #include "smsc-sio.h"
  76
  77
  78 MODULE_AUTHOR("Daniele Peri <peri@csai.unipa.it>");
  79 MODULE_DESCRIPTION("SMC IrCC SIR/FIR controller driver");
  80 MODULE_LICENSE("GPL");
  81
  82 #define DMA_INVAL 255
  83 static int ircc_dma = DMA_INVAL;
  84 module_param(ircc_dma, int, 0);
  85 MODULE_PARM_DESC(ircc_dma, "DMA channel");
  86
  87 #define IRQ_INVAL 255
  88 static int ircc_irq = IRQ_INVAL;
  89 module_param(ircc_irq, int, 0);
  90 MODULE_PARM_DESC(ircc_irq, "IRQ line");
  91
  92 static int ircc_fir;
  93 module_param(ircc_fir, int, 0);
  94 MODULE_PARM_DESC(ircc_fir, "FIR Base Address");
  95
  96 static int ircc_sir;
  97 module_param(ircc_sir, int, 0);
  98 MODULE_PARM_DESC(ircc_sir, "SIR Base Address");
  99
 100 static int ircc_cfg;
 101 module_param(ircc_cfg, int, 0);
 102 MODULE_PARM_DESC(ircc_cfg, "Configuration register base address");
 103
 104 static int ircc_transceiver;
 105 module_param(ircc_transceiver, int, 0);
 106 MODULE_PARM_DESC(ircc_transceiver, "Transceiver type");
 107
 108 /* Types */
 109
 110 #ifdef CONFIG_PCI
 111 struct smsc_ircc_subsystem_configuration {
 112         unsigned short vendor; /* PCI vendor ID */
 113         unsigned short device; /* PCI vendor ID */
 114         unsigned short subvendor; /* PCI subsystem vendor ID */
 115         unsigned short subdevice; /* PCI sybsystem device ID */
 116         unsigned short sir_io; /* I/O port for SIR */
 117         unsigned short fir_io; /* I/O port for FIR */
 118         unsigned char  fir_irq; /* FIR IRQ */
 119         unsigned char  fir_dma; /* FIR DMA */
 120         unsigned short cfg_base; /* I/O port for chip configuration */
 121         int (*preconfigure)(struct pci_dev *dev, struct smsc_ircc_subsystem_configuration *conf); /* Preconfig function */
 122         const char *name;       /* name shown as info */
 123 };
 124 #endif
 125
 126 struct smsc_transceiver {
 127         char *name;
 128         void (*set_for_speed)(int fir_base, u32 speed);
 129         int  (*probe)(int fir_base);
 130 };
 131
 132 struct smsc_chip {
 133         char *name;
 134         #if 0
 135         u8      type;
 136         #endif
 137         u16 flags;
 138         u8 devid;
 139         u8 rev;
 140 };
 141
 142 struct smsc_chip_address {
 143         unsigned int cfg_base;
 144         unsigned int type;
 145 };
 146
 147 /* Private data for each instance */
 148 struct smsc_ircc_cb {
 149         struct net_device *netdev;     /* Yes! we are some kind of netdevice */
 150         struct net_device_stats stats;
 151         struct irlap_cb    *irlap; /* The link layer we are binded to */
 152
 153         chipio_t io;               /* IrDA controller information */
 154         iobuff_t tx_buff;          /* Transmit buffer */
 155         iobuff_t rx_buff;          /* Receive buffer */
 156         dma_addr_t tx_buff_dma;
 157         dma_addr_t rx_buff_dma;
 158
 159         struct qos_info qos;       /* QoS capabilities for this device */
 160
 161         spinlock_t lock;           /* For serializing operations */
 162
 163         __u32 new_speed;
 164         __u32 flags;               /* Interface flags */
 165
 166         int tx_buff_offsets[10];   /* Offsets between frames in tx_buff */
 167         int tx_len;                /* Number of frames in tx_buff */
 168
 169         int transceiver;
 170         struct platform_device *pldev;
 171 };
 172
 173 /* Constants */
 174
 175 #define SMSC_IRCC2_DRIVER_NAME                  "smsc-ircc2"
 176
 177 #define SMSC_IRCC2_C_IRDA_FALLBACK_SPEED        9600
 178 #define SMSC_IRCC2_C_DEFAULT_TRANSCEIVER        1
 179 #define SMSC_IRCC2_C_NET_TIMEOUT                0
 180 #define SMSC_IRCC2_C_SIR_STOP                   0
 181
 182 static const char *driver_name = SMSC_IRCC2_DRIVER_NAME;
 183
 184 /* Prototypes */
 185
 186 static int smsc_ircc_open(unsigned int firbase, unsigned int sirbase, u8 dma, u8 irq);
 187 static int smsc_ircc_present(unsigned int fir_base, unsigned int sir_base);
 188 static void smsc_ircc_setup_io(struct smsc_ircc_cb *self, unsigned int fir_base, unsigned int sir_base, u8 dma, u8 irq);
 189 static void smsc_ircc_setup_qos(struct smsc_ircc_cb *self);
 190 static void smsc_ircc_init_chip(struct smsc_ircc_cb *self);
 191 static int __exit smsc_ircc_close(struct smsc_ircc_cb *self);
 192 static int  smsc_ircc_dma_receive(struct smsc_ircc_cb *self);
 193 static void smsc_ircc_dma_receive_complete(struct smsc_ircc_cb *self);
 194 static void smsc_ircc_sir_receive(struct smsc_ircc_cb *self);
 195 static int  smsc_ircc_hard_xmit_sir(struct sk_buff *skb, struct net_device *dev);
 196 static int  smsc_ircc_hard_xmit_fir(struct sk_buff *skb, struct net_device *dev);
 197 static void smsc_ircc_dma_xmit(struct smsc_ircc_cb *self, int bofs);
 198 static void smsc_ircc_dma_xmit_complete(struct smsc_ircc_cb *self);
 199 static void smsc_ircc_change_speed(struct smsc_ircc_cb *self, u32 speed);
 200 static void smsc_ircc_set_sir_speed(struct smsc_ircc_cb *self, u32 speed);
 201 static irqreturn_t smsc_ircc_interrupt(int irq, void *dev_id);
 202 static irqreturn_t smsc_ircc_interrupt_sir(struct net_device *dev);
 203 static void smsc_ircc_sir_start(struct smsc_ircc_cb *self);
 204 #if SMSC_IRCC2_C_SIR_STOP
 205 static void smsc_ircc_sir_stop(struct smsc_ircc_cb *self);
 206 #endif
 207 static void smsc_ircc_sir_write_wakeup(struct smsc_ircc_cb *self);
 208 static int  smsc_ircc_sir_write(int iobase, int fifo_size, __u8 *buf, int len);
 209 static int  smsc_ircc_net_open(struct net_device *dev);
 210 static int  smsc_ircc_net_close(struct net_device *dev);
 211 static int  smsc_ircc_net_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
 212 #if SMSC_IRCC2_C_NET_TIMEOUT
 213 static void smsc_ircc_timeout(struct net_device *dev);
 214 #endif
 215 static struct net_device_stats *smsc_ircc_net_get_stats(struct net_device *dev);
 216 static int smsc_ircc_is_receiving(struct smsc_ircc_cb *self);
 217 static void smsc_ircc_probe_transceiver(struct smsc_ircc_cb *self);
 218 static void smsc_ircc_set_transceiver_for_speed(struct smsc_ircc_cb *self, u32 speed);
 219 static void smsc_ircc_sir_wait_hw_transmitter_finish(struct smsc_ircc_cb *self);
 220
 221 /* Probing */
 222 static int __init smsc_ircc_look_for_chips(void);
 223 static const struct smsc_chip * __init smsc_ircc_probe(unsigned short cfg_base, u8 reg, const struct smsc_chip *chip, char *type);
 224 static int __init smsc_superio_flat(const struct smsc_chip *chips, unsigned short cfg_base, char *type);
 225 static int __init smsc_superio_paged(const struct smsc_chip *chips, unsigned short cfg_base, char *type);
 226 static int __init smsc_superio_fdc(unsigned short cfg_base);
 227 static int __init smsc_superio_lpc(unsigned short cfg_base);
 228 #ifdef CONFIG_PCI
 229 static int __init preconfigure_smsc_chip(struct smsc_ircc_subsystem_configuration *conf);
 230 static int __init preconfigure_through_82801(struct pci_dev *dev, struct smsc_ircc_subsystem_configuration *conf);
 231 static void __init preconfigure_ali_port(struct pci_dev *dev,
 232                                          unsigned short port);
 233 static int __init preconfigure_through_ali(struct pci_dev *dev, struct smsc_ircc_subsystem_configuration *conf);
 234 static int __init smsc_ircc_preconfigure_subsystems(unsigned short ircc_cfg,
 235                                                     unsigned short ircc_fir,
 236                                                     unsigned short ircc_sir,
 237                                                     unsigned char ircc_dma,
 238                                                     unsigned char ircc_irq);
 239 #endif
 240
 241 /* Transceivers specific functions */
 242
 243 static void smsc_ircc_set_transceiver_toshiba_sat1800(int fir_base, u32 speed);
 244 static int  smsc_ircc_probe_transceiver_toshiba_sat1800(int fir_base);
 245 static void smsc_ircc_set_transceiver_smsc_ircc_fast_pin_select(int fir_base, u32 speed);
 246 static int  smsc_ircc_probe_transceiver_smsc_ircc_fast_pin_select(int fir_base);
 247 static void smsc_ircc_set_transceiver_smsc_ircc_atc(int fir_base, u32 speed);
 248 static int  smsc_ircc_probe_transceiver_smsc_ircc_atc(int fir_base);
 249
 250 /* Power Management */
 251
 252 static int smsc_ircc_suspend(struct platform_device *dev, pm_message_t state);
 253 static int smsc_ircc_resume(struct platform_device *dev);
 254
 255 static struct platform_driver smsc_ircc_driver = {
 256         .suspend        = smsc_ircc_suspend,
 257         .resume         = smsc_ircc_resume,
 258         .driver         = {
 259                 .name   = SMSC_IRCC2_DRIVER_NAME,
 260         },
 261 };
 262
 263 /* Transceivers for SMSC-ircc */
 264
 265 static struct smsc_transceiver smsc_transceivers[] =
 266 {
 267         { "Toshiba Satellite 1800 (GP data pin select)", smsc_ircc_set_transceiver_toshiba_sat1800, smsc_ircc_probe_transceiver_toshiba_sat1800 },
 268         { "Fast pin select", smsc_ircc_set_transceiver_smsc_ircc_fast_pin_select, smsc_ircc_probe_transceiver_smsc_ircc_fast_pin_select },
 269         { "ATC IRMode", smsc_ircc_set_transceiver_smsc_ircc_atc, smsc_ircc_probe_transceiver_smsc_ircc_atc },
 270         { NULL, NULL }
 271 };
 272 #define SMSC_IRCC2_C_NUMBER_OF_TRANSCEIVERS (ARRAY_SIZE(smsc_transceivers) - 1)
 273
 274 /*  SMC SuperIO chipsets definitions */
 275
 276 #define KEY55_1 0       /* SuperIO Configuration mode with Key <0x55> */
 277 #define KEY55_2 1       /* SuperIO Configuration mode with Key <0x55,0x55> */
 278 #define NoIRDA  2       /* SuperIO Chip has no IRDA Port */
 279 #define SIR     0       /* SuperIO Chip has only slow IRDA */
 280 #define FIR     4       /* SuperIO Chip has fast IRDA */
 281 #define SERx4   8       /* SuperIO Chip supports 115,2 KBaud * 4=460,8 KBaud */
 282
 283 static struct smsc_chip __initdata fdc_chips_flat[] =
 284 {
 285         /* Base address 0x3f0 or 0x370 */
 286         { "37C44",      KEY55_1|NoIRDA,         0x00, 0x00 }, /* This chip cannot be detected */
 287         { "37C665GT",   KEY55_2|NoIRDA,         0x65, 0x01 },
 288         { "37C665GT",   KEY55_2|NoIRDA,         0x66, 0x01 },
 289         { "37C669",     KEY55_2|SIR|SERx4,      0x03, 0x02 },
 290         { "37C669",     KEY55_2|SIR|SERx4,      0x04, 0x02 }, /* ID? */
 291         { "37C78",      KEY55_2|NoIRDA,         0x78, 0x00 },
 292         { "37N769",     KEY55_1|FIR|SERx4,      0x28, 0x00 },
 293         { "37N869",     KEY55_1|FIR|SERx4,      0x29, 0x00 },
 294         { NULL }
 295 };
 296
 297 static struct smsc_chip __initdata fdc_chips_paged[] =
 298 {
 299         /* Base address 0x3f0 or 0x370 */
 300         { "37B72X",     KEY55_1|SIR|SERx4,      0x4c, 0x00 },
 301         { "37B77X",     KEY55_1|SIR|SERx4,      0x43, 0x00 },
 302         { "37B78X",     KEY55_1|SIR|SERx4,      0x44, 0x00 },
 303         { "37B80X",     KEY55_1|SIR|SERx4,      0x42, 0x00 },
 304         { "37C67X",     KEY55_1|FIR|SERx4,      0x40, 0x00 },
 305         { "37C93X",     KEY55_2|SIR|SERx4,      0x02, 0x01 },
 306         { "37C93XAPM",  KEY55_1|SIR|SERx4,      0x30, 0x01 },
 307         { "37C93XFR",   KEY55_2|FIR|SERx4,      0x03, 0x01 },
 308         { "37M707",     KEY55_1|SIR|SERx4,      0x42, 0x00 },
 309         { "37M81X",     KEY55_1|SIR|SERx4,      0x4d, 0x00 },
 310         { "37N958FR",   KEY55_1|FIR|SERx4,      0x09, 0x04 },
 311         { "37N971",     KEY55_1|FIR|SERx4,      0x0a, 0x00 },
 312         { "37N972",     KEY55_1|FIR|SERx4,      0x0b, 0x00 },
 313         { NULL }
 314 };
 315
 316 static struct smsc_chip __initdata lpc_chips_flat[] =
 317 {
 318         /* Base address 0x2E or 0x4E */
 319         { "47N227",     KEY55_1|FIR|SERx4,      0x5a, 0x00 },
 320         { "47N227",     KEY55_1|FIR|SERx4,      0x7a, 0x00 },
 321         { "47N267",     KEY55_1|FIR|SERx4,      0x5e, 0x00 },
 322         { NULL }
 323 };
 324
 325 static struct smsc_chip __initdata lpc_chips_paged[] =
 326 {
 327         /* Base address 0x2E or 0x4E */
 328         { "47B27X",     KEY55_1|SIR|SERx4,      0x51, 0x00 },
 329         { "47B37X",     KEY55_1|SIR|SERx4,      0x52, 0x00 },
 330         { "47M10X",     KEY55_1|SIR|SERx4,      0x59, 0x00 },
 331         { "47M120",     KEY55_1|NoIRDA|SERx4,   0x5c, 0x00 },
 332         { "47M13X",     KEY55_1|SIR|SERx4,      0x59, 0x00 },
 333         { "47M14X",     KEY55_1|SIR|SERx4,      0x5f, 0x00 },
 334         { "47N252",     KEY55_1|FIR|SERx4,      0x0e, 0x00 },
 335         { "47S42X",     KEY55_1|SIR|SERx4,      0x57, 0x00 },
 336         { NULL }
 337 };
 338
 339 #define SMSCSIO_TYPE_FDC        1
 340 #define SMSCSIO_TYPE_LPC        2
 341 #define SMSCSIO_TYPE_FLAT       4
 342 #define SMSCSIO_TYPE_PAGED      8
 343
 344 static struct smsc_chip_address __initdata possible_addresses[] =
 345 {
 346         { 0x3f0, SMSCSIO_TYPE_FDC|SMSCSIO_TYPE_FLAT|SMSCSIO_TYPE_PAGED },
 347         { 0x370, SMSCSIO_TYPE_FDC|SMSCSIO_TYPE_FLAT|SMSCSIO_TYPE_PAGED },
 348         { 0xe0,  SMSCSIO_TYPE_FDC|SMSCSIO_TYPE_FLAT|SMSCSIO_TYPE_PAGED },
 349         { 0x2e,  SMSCSIO_TYPE_LPC|SMSCSIO_TYPE_FLAT|SMSCSIO_TYPE_PAGED },
 350         { 0x4e,  SMSCSIO_TYPE_LPC|SMSCSIO_TYPE_FLAT|SMSCSIO_TYPE_PAGED },
 351         { 0, 0 }
 352 };
 353
 354 /* Globals */
 355
 356 static struct smsc_ircc_cb *dev_self[] = { NULL, NULL };
 357 static unsigned short dev_count;
 358
 359 static inline void register_bank(int iobase, int bank)
 360 {
 361         outb(((inb(iobase + IRCC_MASTER) & 0xf0) | (bank & 0x07)),
 362                iobase + IRCC_MASTER);
 363 }
 364
 365 #ifdef  CONFIG_PNP
 366 /* PNP hotplug support */
 367 static const struct pnp_device_id smsc_ircc_pnp_table[] = {
 368         { .id = "SMCf010", .driver_data = 0 },
 369         /* and presumably others */
 370         { }
 371 };
 372 MODULE_DEVICE_TABLE(pnp, smsc_ircc_pnp_table);
 373 #endif
 374
 375
 376 /*******************************************************************************
 377  *
 378  *
 379  * SMSC-ircc stuff
 380  *
 381  *
 382  *******************************************************************************/
 383
 384 /*
 385  * Function smsc_ircc_init ()
 386  *
 387  *    Initialize chip. Just try to find out how many chips we are dealing with
 388  *    and where they are
 389  */
 390 static int __init smsc_ircc_init(void)
 391 {
 392         int ret;
 393
 394         IRDA_DEBUG(1, "%s\n", __FUNCTION__);
 395
 396         ret = platform_driver_register(&smsc_ircc_driver);
 397         if (ret) {
 398                 IRDA_ERROR("%s, Can't register driver!\n", driver_name);
 399                 return ret;
 400         }
 401
 402 #ifdef CONFIG_PCI
 403         if (smsc_ircc_preconfigure_subsystems(ircc_cfg, ircc_fir, ircc_sir, ircc_dma, ircc_irq) < 0) {
 404                 /* Ignore errors from preconfiguration */
 405                 IRDA_ERROR("%s, Preconfiguration failed !\n", driver_name);
 406         }
 407 #endif
 408
 409         dev_count = 0;
 410
 411         if (ircc_fir > 0 && ircc_sir > 0) {
 412                 IRDA_MESSAGE(" Overriding FIR address 0x%04x\n", ircc_fir);
 413                 IRDA_MESSAGE(" Overriding SIR address 0x%04x\n", ircc_sir);
 414
 415                 if (smsc_ircc_open(ircc_fir, ircc_sir, ircc_dma, ircc_irq))
 416                         ret = -ENODEV;
 417         } else {
 418                 ret = -ENODEV;
 419
 420                 /* try user provided configuration register base address */
 421                 if (ircc_cfg > 0) {
 422                         IRDA_MESSAGE(" Overriding configuration address "
 423                                      "0x%04x\n", ircc_cfg);
 424                         if (!smsc_superio_fdc(ircc_cfg))
 425                                 ret = 0;
 426                         if (!smsc_superio_lpc(ircc_cfg))
 427                                 ret = 0;
 428                 }
 429
 430                 if (smsc_ircc_look_for_chips() > 0)
 431                         ret = 0;
 432         }
 433
 434         if (ret)
 435                 platform_driver_unregister(&smsc_ircc_driver);
 436
 437         return ret;
 438 }
 439
 440 /*
 441  * Function smsc_ircc_open (firbase, sirbase, dma, irq)
 442  *
 443  *    Try to open driver instance
 444  *
 445  */
 446 static int __init smsc_ircc_open(unsigned int fir_base, unsigned int sir_base, u8 dma, u8 irq)
 447 {
 448         struct smsc_ircc_cb *self;
 449         struct net_device *dev;
 450         int err;
 451
 452         IRDA_DEBUG(1, "%s\n", __FUNCTION__);
 453
 454         err = smsc_ircc_present(fir_base, sir_base);
 455         if (err)
 456                 goto err_out;
 457
 458         err = -ENOMEM;
 459         if (dev_count >= ARRAY_SIZE(dev_self)) {
 460                 IRDA_WARNING("%s(), too many devices!\n", __FUNCTION__);
 461                 goto err_out1;
 462         }
 463
 464         /*
 465          *  Allocate new instance of the driver
 466          */
 467         dev = alloc_irdadev(sizeof(struct smsc_ircc_cb));
 468         if (!dev) {
 469                 IRDA_WARNING("%s() can't allocate net device\n", __FUNCTION__);
 470                 goto err_out1;
 471         }
 472
 473         SET_MODULE_OWNER(dev);
 474
 475         dev->hard_start_xmit = smsc_ircc_hard_xmit_sir;
 476 #if SMSC_IRCC2_C_NET_TIMEOUT
 477         dev->tx_timeout      = smsc_ircc_timeout;
 478         dev->watchdog_timeo  = HZ * 2;  /* Allow enough time for speed change */
 479 #endif
 480         dev->open            = smsc_ircc_net_open;
 481         dev->stop            = smsc_ircc_net_close;
 482         dev->do_ioctl        = smsc_ircc_net_ioctl;
 483         dev->get_stats       = smsc_ircc_net_get_stats;
 484
 485         self = netdev_priv(dev);
 486         self->netdev = dev;
 487
 488         /* Make ifconfig display some details */
 489         dev->base_addr = self->io.fir_base = fir_base;
 490         dev->irq = self->io.irq = irq;
 491
 492         /* Need to store self somewhere */
 493         dev_self[dev_count] = self;
 494         spin_lock_init(&self->lock);
 495
 496         self->rx_buff.truesize = SMSC_IRCC2_RX_BUFF_TRUESIZE;
 497         self->tx_buff.truesize = SMSC_IRCC2_TX_BUFF_TRUESIZE;
 498
 499         self->rx_buff.head =
 500                 dma_alloc_coherent(NULL, self->rx_buff.truesize,
 501                                    &self->rx_buff_dma, GFP_KERNEL);
 502         if (self->rx_buff.head == NULL) {
 503                 IRDA_ERROR("%s, Can't allocate memory for receive buffer!\n",
 504                            driver_name);
 505                 goto err_out2;
 506         }
 507
 508         self->tx_buff.head =
 509                 dma_alloc_coherent(NULL, self->tx_buff.truesize,
 510                                    &self->tx_buff_dma, GFP_KERNEL);
 511         if (self->tx_buff.head == NULL) {
 512                 IRDA_ERROR("%s, Can't allocate memory for transmit buffer!\n",
 513                            driver_name);
 514                 goto err_out3;
 515         }
 516
 517         memset(self->rx_buff.head, 0, self->rx_buff.truesize);
 518         memset(self->tx_buff.head, 0, self->tx_buff.truesize);
 519
 520         self->rx_buff.in_frame = FALSE;
 521         self->rx_buff.state = OUTSIDE_FRAME;
 522         self->tx_buff.data = self->tx_buff.head;
 523         self->rx_buff.data = self->rx_buff.head;
 524
 525         smsc_ircc_setup_io(self, fir_base, sir_base, dma, irq);
 526         smsc_ircc_setup_qos(self);
 527         smsc_ircc_init_chip(self);
 528
 529         if (ircc_transceiver > 0  &&
 530             ircc_transceiver < SMSC_IRCC2_C_NUMBER_OF_TRANSCEIVERS)
 531                 self->transceiver = ircc_transceiver;
 532         else
 533                 smsc_ircc_probe_transceiver(self);
 534
 535         err = register_netdev(self->netdev);
 536         if (err) {
 537                 IRDA_ERROR("%s, Network device registration failed!\n",
 538                            driver_name);
 539                 goto err_out4;
 540         }
 541
 542         self->pldev = platform_device_register_simple(SMSC_IRCC2_DRIVER_NAME,
 543                                                       dev_count, NULL, 0);
 544         if (IS_ERR(self->pldev)) {
 545                 err = PTR_ERR(self->pldev);
 546                 goto err_out5;
 547         }
 548         platform_set_drvdata(self->pldev, self);
 549
 550         IRDA_MESSAGE("IrDA: Registered device %s\n", dev->name);
 551         dev_count++;
 552
 553         return 0;
 554
 555  err_out5:
 556         unregister_netdev(self->netdev);
 557
 558  err_out4:
 559         dma_free_coherent(NULL, self->tx_buff.truesize,
 560                           self->tx_buff.head, self->tx_buff_dma);
 561  err_out3:
 562         dma_free_coherent(NULL, self->rx_buff.truesize,
 563                           self->rx_buff.head, self->rx_buff_dma);
 564  err_out2:
 565         free_netdev(self->netdev);
 566         dev_self[dev_count] = NULL;
 567  err_out1:
 568         release_region(fir_base, SMSC_IRCC2_FIR_CHIP_IO_EXTENT);
 569         release_region(sir_base, SMSC_IRCC2_SIR_CHIP_IO_EXTENT);
 570  err_out:
 571         return err;
 572 }
 573
 574 /*
 575  * Function smsc_ircc_present(fir_base, sir_base)
 576  *
 577  *    Check the smsc-ircc chip presence
 578  *
 579  */
 580 static int smsc_ircc_present(unsigned int fir_base, unsigned int sir_base)
 581 {
 582         unsigned char low, high, chip, config, dma, irq, version;
 583
 584         if (!request_region(fir_base, SMSC_IRCC2_FIR_CHIP_IO_EXTENT,
 585                             driver_name)) {
 586                 IRDA_WARNING("%s: can't get fir_base of 0x%03x\n",
 587                              __FUNCTION__, fir_base);
 588                 goto out1;
 589         }
 590
 591         if (!request_region(sir_base, SMSC_IRCC2_SIR_CHIP_IO_EXTENT,
 592                             driver_name)) {
 593                 IRDA_WARNING("%s: can't get sir_base of 0x%03x\n",
 594                              __FUNCTION__, sir_base);
 595                 goto out2;
 596         }
 597
 598         register_bank(fir_base, 3);
 599
 600         high    = inb(fir_base + IRCC_ID_HIGH);
 601         low     = inb(fir_base + IRCC_ID_LOW);
 602         chip    = inb(fir_base + IRCC_CHIP_ID);
 603         version = inb(fir_base + IRCC_VERSION);
 604         config  = inb(fir_base + IRCC_INTERFACE);
 605         dma     = config & IRCC_INTERFACE_DMA_MASK;
 606         irq     = (config & IRCC_INTERFACE_IRQ_MASK) >> 4;
 607
 608         if (high != 0x10 || low != 0xb8 || (chip != 0xf1 && chip != 0xf2)) {
 609                 IRDA_WARNING("%s(), addr 0x%04x - no device found!\n",
 610                              __FUNCTION__, fir_base);
 611                 goto out3;
 612         }
 613         IRDA_MESSAGE("SMsC IrDA Controller found\n IrCC version %d.%d, "
 614                      "firport 0x%03x, sirport 0x%03x dma=%d, irq=%d\n",
 615                      chip & 0x0f, version, fir_base, sir_base, dma, irq);
 616
 617         return 0;
 618
 619  out3:
 620         release_region(sir_base, SMSC_IRCC2_SIR_CHIP_IO_EXTENT);
 621  out2:
 622         release_region(fir_base, SMSC_IRCC2_FIR_CHIP_IO_EXTENT);
 623  out1:
 624         return -ENODEV;
 625 }
 626
 627 /*
 628  * Function smsc_ircc_setup_io(self, fir_base, sir_base, dma, irq)
 629  *
 630  *    Setup I/O
 631  *
 632  */
 633 static void smsc_ircc_setup_io(struct smsc_ircc_cb *self,
 634                                unsigned int fir_base, unsigned int sir_base,
 635                                u8 dma, u8 irq)
 636 {
 637         unsigned char config, chip_dma, chip_irq;
 638
 639         register_bank(fir_base, 3);
 640         config = inb(fir_base + IRCC_INTERFACE);
 641         chip_dma = config & IRCC_INTERFACE_DMA_MASK;
 642         chip_irq = (config & IRCC_INTERFACE_IRQ_MASK) >> 4;
 643
 644         self->io.fir_base  = fir_base;
 645         self->io.sir_base  = sir_base;
 646         self->io.fir_ext   = SMSC_IRCC2_FIR_CHIP_IO_EXTENT;
 647         self->io.sir_ext   = SMSC_IRCC2_SIR_CHIP_IO_EXTENT;
 648         self->io.fifo_size = SMSC_IRCC2_FIFO_SIZE;
 649         self->io.speed = SMSC_IRCC2_C_IRDA_FALLBACK_SPEED;
 650
 651         if (irq != IRQ_INVAL) {
 652                 if (irq != chip_irq)
 653                         IRDA_MESSAGE("%s, Overriding IRQ - chip says %d, using %d\n",
 654                                      driver_name, chip_irq, irq);
 655                 self->io.irq = irq;
 656         } else
 657                 self->io.irq = chip_irq;
 658
 659         if (dma != DMA_INVAL) {
 660                 if (dma != chip_dma)
 661                         IRDA_MESSAGE("%s, Overriding DMA - chip says %d, using %d\n",
 662                                      driver_name, chip_dma, dma);
 663                 self->io.dma = dma;
 664         } else
 665                 self->io.dma = chip_dma;
 666
 667 }
 668
 669 /*
 670  * Function smsc_ircc_setup_qos(self)
 671  *
 672  *    Setup qos
 673  *
 674  */
 675 static void smsc_ircc_setup_qos(struct smsc_ircc_cb *self)
 676 {
 677         /* Initialize QoS for this device */
 678         irda_init_max_qos_capabilies(&self->qos);
 679
 680         self->qos.baud_rate.bits = IR_9600|IR_19200|IR_38400|IR_57600|
 681                 IR_115200|IR_576000|IR_1152000|(IR_4000000 << 8);
 682
 683         self->qos.min_turn_time.bits = SMSC_IRCC2_MIN_TURN_TIME;
 684         self->qos.window_size.bits = SMSC_IRCC2_WINDOW_SIZE;
 685         irda_qos_bits_to_value(&self->qos);
 686 }
 687
 688 /*
 689  * Function smsc_ircc_init_chip(self)
 690  *
 691  *    Init chip
 692  *
 693  */
 694 static void smsc_ircc_init_chip(struct smsc_ircc_cb *self)
 695 {
 696         int iobase = self->io.fir_base;
 697
 698         register_bank(iobase, 0);
 699         outb(IRCC_MASTER_RESET, iobase + IRCC_MASTER);
 700         outb(0x00, iobase + IRCC_MASTER);
 701
 702         register_bank(iobase, 1);
 703         outb(((inb(iobase + IRCC_SCE_CFGA) & 0x87) | IRCC_CFGA_IRDA_SIR_A),
 704              iobase + IRCC_SCE_CFGA);
 705
 706 #ifdef smsc_669 /* Uses pin 88/89 for Rx/Tx */
 707         outb(((inb(iobase + IRCC_SCE_CFGB) & 0x3f) | IRCC_CFGB_MUX_COM),
 708              iobase + IRCC_SCE_CFGB);
 709 #else
 710         outb(((inb(iobase + IRCC_SCE_CFGB) & 0x3f) | IRCC_CFGB_MUX_IR),
 711              iobase + IRCC_SCE_CFGB);
 712 #endif
 713         (void) inb(iobase + IRCC_FIFO_THRESHOLD);
 714         outb(SMSC_IRCC2_FIFO_THRESHOLD, iobase + IRCC_FIFO_THRESHOLD);
 715
 716         register_bank(iobase, 4);
 717         outb((inb(iobase + IRCC_CONTROL) & 0x30), iobase + IRCC_CONTROL);
 718
 719         register_bank(iobase, 0);
 720         outb(0, iobase + IRCC_LCR_A);
 721
 722         smsc_ircc_set_sir_speed(self, SMSC_IRCC2_C_IRDA_FALLBACK_SPEED);
 723
 724         /* Power on device */
 725         outb(0x00, iobase + IRCC_MASTER);
 726 }
 727
 728 /*
 729  * Function smsc_ircc_net_ioctl (dev, rq, cmd)
 730  *
 731  *    Process IOCTL commands for this device
 732  *
 733  */
 734 static int smsc_ircc_net_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
 735 {
 736         struct if_irda_req *irq = (struct if_irda_req *) rq;
 737         struct smsc_ircc_cb *self;
 738         unsigned long flags;
 739         int ret = 0;
 740
 741         IRDA_ASSERT(dev != NULL, return -1;);
 742
 743         self = netdev_priv(dev);
 744
 745         IRDA_ASSERT(self != NULL, return -1;);
 746
 747         IRDA_DEBUG(2, "%s(), %s, (cmd=0x%X)\n", __FUNCTION__, dev->name, cmd);
 748
 749         switch (cmd) {
 750         case SIOCSBANDWIDTH: /* Set bandwidth */
 751                 if (!capable(CAP_NET_ADMIN))
 752                         ret = -EPERM;
 753                 else {
 754                         /* Make sure we are the only one touching
 755                          * self->io.speed and the hardware - Jean II */
 756                         spin_lock_irqsave(&self->lock, flags);
 757                         smsc_ircc_change_speed(self, irq->ifr_baudrate);
 758                         spin_unlock_irqrestore(&self->lock, flags);
 759                 }
 760                 break;
 761         case SIOCSMEDIABUSY: /* Set media busy */
 762                 if (!capable(CAP_NET_ADMIN)) {
 763                         ret = -EPERM;
 764                         break;
 765                 }
 766
 767                 irda_device_set_media_busy(self->netdev, TRUE);
 768                 break;
 769         case SIOCGRECEIVING: /* Check if we are receiving right now */
 770                 irq->ifr_receiving = smsc_ircc_is_receiving(self);
 771                 break;
 772         #if 0
 773         case SIOCSDTRRTS:
 774                 if (!capable(CAP_NET_ADMIN)) {
 775                         ret = -EPERM;
 776                         break;
 777                 }
 778                 smsc_ircc_sir_set_dtr_rts(dev, irq->ifr_dtr, irq->ifr_rts);
 779                 break;
 780         #endif
 781         default:
 782                 ret = -EOPNOTSUPP;
 783         }
 784
 785         return ret;
 786 }
 787
 788 static struct net_device_stats *smsc_ircc_net_get_stats(struct net_device *dev)
 789 {
 790         struct smsc_ircc_cb *self = netdev_priv(dev);
 791
 792         return &self->stats;
 793 }
 794
 795 #if SMSC_IRCC2_C_NET_TIMEOUT
 796 /*
 797  * Function smsc_ircc_timeout (struct net_device *dev)
 798  *
 799  *    The networking timeout management.
 800  *
 801  */
 802
 803 static void smsc_ircc_timeout(struct net_device *dev)
 804 {
 805         struct smsc_ircc_cb *self = netdev_priv(dev);
 806         unsigned long flags;
 807
 808         IRDA_WARNING("%s: transmit timed out, changing speed to: %d\n",
 809                      dev->name, self->io.speed);
 810         spin_lock_irqsave(&self->lock, flags);
 811         smsc_ircc_sir_start(self);
 812         smsc_ircc_change_speed(self, self->io.speed);
 813         dev->trans_start = jiffies;
 814         netif_wake_queue(dev);
 815         spin_unlock_irqrestore(&self->lock, flags);
 816 }
 817 #endif
 818
 819 /*
 820  * Function smsc_ircc_hard_xmit_sir (struct sk_buff *skb, struct net_device *dev)
 821  *
 822  *    Transmits the current frame until FIFO is full, then
 823  *    waits until the next transmit interrupt, and continues until the
 824  *    frame is transmitted.
 825  */
 826 int smsc_ircc_hard_xmit_sir(struct sk_buff *skb, struct net_device *dev)
 827 {
 828         struct smsc_ircc_cb *self;
 829         unsigned long flags;
 830         s32 speed;
 831
 832         IRDA_DEBUG(1, "%s\n", __FUNCTION__);
 833
 834         IRDA_ASSERT(dev != NULL, return 0;);
 835
 836         self = netdev_priv(dev);
 837         IRDA_ASSERT(self != NULL, return 0;);
 838
 839         netif_stop_queue(dev);
 840
 841         /* Make sure test of self->io.speed & speed change are atomic */
 842         spin_lock_irqsave(&self->lock, flags);
 843
 844         /* Check if we need to change the speed */
 845         speed = irda_get_next_speed(skb);
 846         if (speed != self->io.speed && speed != -1) {
 847                 /* Check for empty frame */
 848                 if (!skb->len) {
 849                         /*
 850                          * We send frames one by one in SIR mode (no
 851                          * pipelining), so at this point, if we were sending
 852                          * a previous frame, we just received the interrupt
 853                          * telling us it is finished (UART_IIR_THRI).
 854                          * Therefore, waiting for the transmitter to really
 855                          * finish draining the fifo won't take too long.
 856                          * And the interrupt handler is not expected to run.
 857                          * - Jean II */
 858                         smsc_ircc_sir_wait_hw_transmitter_finish(self);
 859                         smsc_ircc_change_speed(self, speed);
 860                         spin_unlock_irqrestore(&self->lock, flags);
 861                         dev_kfree_skb(skb);
 862                         return 0;
 863                 }
 864                 self->new_speed = speed;
 865         }
 866
 867         /* Init tx buffer */
 868         self->tx_buff.data = self->tx_buff.head;
 869
 870         /* Copy skb to tx_buff while wrapping, stuffing and making CRC */
 871         self->tx_buff.len = async_wrap_skb(skb, self->tx_buff.data,
 872                                            self->tx_buff.truesize);
 873
 874         self->stats.tx_bytes += self->tx_buff.len;
 875
 876         /* Turn on transmit finished interrupt. Will fire immediately!  */
 877         outb(UART_IER_THRI, self->io.sir_base + UART_IER);
 878
 879         spin_unlock_irqrestore(&self->lock, flags);
 880
 881         dev_kfree_skb(skb);
 882
 883         return 0;
 884 }
 885
 886 /*
 887  * Function smsc_ircc_set_fir_speed (self, baud)
 888  *
 889  *    Change the speed of the device
 890  *
 891  */
 892 static void smsc_ircc_set_fir_speed(struct smsc_ircc_cb *self, u32 speed)
 893 {
 894         int fir_base, ir_mode, ctrl, fast;
 895
 896         IRDA_ASSERT(self != NULL, return;);
 897         fir_base = self->io.fir_base;
 898
 899         self->io.speed = speed;
 900
 901         switch (speed) {
 902         default:
 903         case 576000:
 904                 ir_mode = IRCC_CFGA_IRDA_HDLC;
 905                 ctrl = IRCC_CRC;
 906                 fast = 0;
 907                 IRDA_DEBUG(0, "%s(), handling baud of 576000\n", __FUNCTION__);
 908                 break;
 909         case 1152000:
 910                 ir_mode = IRCC_CFGA_IRDA_HDLC;
 911                 ctrl = IRCC_1152 | IRCC_CRC;
 912                 fast = IRCC_LCR_A_FAST | IRCC_LCR_A_GP_DATA;
 913                 IRDA_DEBUG(0, "%s(), handling baud of 1152000\n",
 914                            __FUNCTION__);
 915                 break;
 916         case 4000000:
 917                 ir_mode = IRCC_CFGA_IRDA_4PPM;
 918                 ctrl = IRCC_CRC;
 919                 fast = IRCC_LCR_A_FAST;
 920                 IRDA_DEBUG(0, "%s(), handling baud of 4000000\n",
 921                            __FUNCTION__);
 922                 break;
 923         }
 924         #if 0
 925         Now in tranceiver!
 926         /* This causes an interrupt */
 927         register_bank(fir_base, 0);
 928         outb((inb(fir_base + IRCC_LCR_A) &  0xbf) | fast, fir_base + IRCC_LCR_A);
 929         #endif
 930
 931         register_bank(fir_base, 1);
 932         outb(((inb(fir_base + IRCC_SCE_CFGA) & IRCC_SCE_CFGA_BLOCK_CTRL_BITS_MASK) | ir_mode), fir_base + IRCC_SCE_CFGA);
 933
 934         register_bank(fir_base, 4);
 935         outb((inb(fir_base + IRCC_CONTROL) & 0x30) | ctrl, fir_base + IRCC_CONTROL);
 936 }
 937
 938 /*
 939  * Function smsc_ircc_fir_start(self)
 940  *
 941  *    Change the speed of the device
 942  *
 943  */
 944 static void smsc_ircc_fir_start(struct smsc_ircc_cb *self)
 945 {
 946         struct net_device *dev;
 947         int fir_base;
 948
 949         IRDA_DEBUG(1, "%s\n", __FUNCTION__);
 950
 951         IRDA_ASSERT(self != NULL, return;);
 952         dev = self->netdev;
 953         IRDA_ASSERT(dev != NULL, return;);
 954
 955         fir_base = self->io.fir_base;
 956
 957         /* Reset everything */
 958
 959         /* Install FIR transmit handler */
 960         dev->hard_start_xmit = smsc_ircc_hard_xmit_fir;
 961
 962         /* Clear FIFO */
 963         outb(inb(fir_base + IRCC_LCR_A) | IRCC_LCR_A_FIFO_RESET, fir_base + IRCC_LCR_A);
 964
 965         /* Enable interrupt */
 966         /*outb(IRCC_IER_ACTIVE_FRAME|IRCC_IER_EOM, fir_base + IRCC_IER);*/
 967
 968         register_bank(fir_base, 1);
 969
 970         /* Select the TX/RX interface */
 971 #ifdef SMSC_669 /* Uses pin 88/89 for Rx/Tx */
 972         outb(((inb(fir_base + IRCC_SCE_CFGB) & 0x3f) | IRCC_CFGB_MUX_COM),
 973              fir_base + IRCC_SCE_CFGB);
 974 #else
 975         outb(((inb(fir_base + IRCC_SCE_CFGB) & 0x3f) | IRCC_CFGB_MUX_IR),
 976              fir_base + IRCC_SCE_CFGB);
 977 #endif
 978         (void) inb(fir_base + IRCC_FIFO_THRESHOLD);
 979
 980         /* Enable SCE interrupts */
 981         outb(0, fir_base + IRCC_MASTER);
 982         register_bank(fir_base, 0);
 983         outb(IRCC_IER_ACTIVE_FRAME | IRCC_IER_EOM, fir_base + IRCC_IER);
 984         outb(IRCC_MASTER_INT_EN, fir_base + IRCC_MASTER);
 985 }
 986
 987 /*
 988  * Function smsc_ircc_fir_stop(self, baud)
 989  *
 990  *    Change the speed of the device
 991  *
 992  */
 993 static void smsc_ircc_fir_stop(struct smsc_ircc_cb *self)
 994 {
 995         int fir_base;
 996
 997         IRDA_DEBUG(1, "%s\n", __FUNCTION__);
 998
 999         IRDA_ASSERT(self != NULL, return;);
1000
1001         fir_base = self->io.fir_base;
1002         register_bank(fir_base, 0);
1003         /*outb(IRCC_MASTER_RESET, fir_base + IRCC_MASTER);*/
1004         outb(inb(fir_base + IRCC_LCR_B) & IRCC_LCR_B_SIP_ENABLE, fir_base + IRCC_LCR_B);
1005 }
1006
1007
1008 /*
1009  * Function smsc_ircc_change_speed(self, baud)
1010  *
1011  *    Change the speed of the device
1012  *
1013  * This function *must* be called with spinlock held, because it may
1014  * be called from the irq handler. - Jean II
1015  */
1016 static void smsc_ircc_change_speed(struct smsc_ircc_cb *self, u32 speed)
1017 {
1018         struct net_device *dev;
1019         int last_speed_was_sir;
1020
1021         IRDA_DEBUG(0, "%s() changing speed to: %d\n", __FUNCTION__, speed);
1022
1023         IRDA_ASSERT(self != NULL, return;);
1024         dev = self->netdev;
1025
1026         last_speed_was_sir = self->io.speed <= SMSC_IRCC2_MAX_SIR_SPEED;
1027
1028         #if 0
1029         /* Temp Hack */
1030         speed= 1152000;
1031         self->io.speed = speed;
1032         last_speed_was_sir = 0;
1033         smsc_ircc_fir_start(self);
1034         #endif
1035
1036         if (self->io.speed == 0)
1037                 smsc_ircc_sir_start(self);
1038
1039         #if 0
1040         if (!last_speed_was_sir) speed = self->io.speed;
1041         #endif
1042
1043         if (self->io.speed != speed)
1044                 smsc_ircc_set_transceiver_for_speed(self, speed);
1045
1046         self->io.speed = speed;
1047
1048         if (speed <= SMSC_IRCC2_MAX_SIR_SPEED) {
1049                 if (!last_speed_was_sir) {
1050                         smsc_ircc_fir_stop(self);
1051                         smsc_ircc_sir_start(self);
1052                 }
1053                 smsc_ircc_set_sir_speed(self, speed);
1054         } else {
1055                 if (last_speed_was_sir) {
1056                         #if SMSC_IRCC2_C_SIR_STOP
1057                         smsc_ircc_sir_stop(self);
1058                         #endif
1059                         smsc_ircc_fir_start(self);
1060                 }
1061                 smsc_ircc_set_fir_speed(self, speed);
1062
1063                 #if 0
1064                 self->tx_buff.len = 10;
1065                 self->tx_buff.data = self->tx_buff.head;
1066
1067                 smsc_ircc_dma_xmit(self, 4000);
1068                 #endif
1069                 /* Be ready for incoming frames */
1070                 smsc_ircc_dma_receive(self);
1071         }
1072
1073         netif_wake_queue(dev);
1074 }
1075
1076 /*
1077  * Function smsc_ircc_set_sir_speed (self, speed)
1078  *
1079  *    Set speed of IrDA port to specified baudrate
1080  *
1081  */
1082 void smsc_ircc_set_sir_speed(struct smsc_ircc_cb *self, __u32 speed)
1083 {
1084         int iobase;
1085         int fcr;    /* FIFO control reg */
1086         int lcr;    /* Line control reg */
1087         int divisor;
1088
1089         IRDA_DEBUG(0, "%s(), Setting speed to: %d\n", __FUNCTION__, speed);
1090
1091         IRDA_ASSERT(self != NULL, return;);
1092         iobase = self->io.sir_base;
1093
1094         /* Update accounting for new speed */
1095         self->io.speed = speed;
1096
1097         /* Turn off interrupts */
1098         outb(0, iobase + UART_IER);
1099
1100         divisor = SMSC_IRCC2_MAX_SIR_SPEED / speed;
1101
1102         fcr = UART_FCR_ENABLE_FIFO;
1103
1104         /*
1105          * Use trigger level 1 to avoid 3 ms. timeout delay at 9600 bps, and
1106          * almost 1,7 ms at 19200 bps. At speeds above that we can just forget
1107          * about this timeout since it will always be fast enough.
1108          */
1109         fcr |= self->io.speed < 38400 ?
1110                 UART_FCR_TRIGGER_1 : UART_FCR_TRIGGER_14;
1111
1112         /* IrDA ports use 8N1 */
1113         lcr = UART_LCR_WLEN8;
1114
1115         outb(UART_LCR_DLAB | lcr, iobase + UART_LCR); /* Set DLAB */
1116         outb(divisor & 0xff,      iobase + UART_DLL); /* Set speed */
1117         outb(divisor >> 8,        iobase + UART_DLM);
1118         outb(lcr,                 iobase + UART_LCR); /* Set 8N1 */
1119         outb(fcr,                 iobase + UART_FCR); /* Enable FIFO's */
1120
1121         /* Turn on interrups */
1122         outb(UART_IER_RLSI | UART_IER_RDI | UART_IER_THRI, iobase + UART_IER);
1123
1124         IRDA_DEBUG(2, "%s() speed changed to: %d\n", __FUNCTION__, speed);
1125 }
1126
1127
1128 /*
1129  * Function smsc_ircc_hard_xmit_fir (skb, dev)
1130  *
1131  *    Transmit the frame!
1132  *
1133  */
1134 static int smsc_ircc_hard_xmit_fir(struct sk_buff *skb, struct net_device *dev)
1135 {
1136         struct smsc_ircc_cb *self;
1137         unsigned long flags;
1138         s32 speed;
1139         int mtt;
1140
1141         IRDA_ASSERT(dev != NULL, return 0;);
1142         self = netdev_priv(dev);
1143         IRDA_ASSERT(self != NULL, return 0;);
1144
1145         netif_stop_queue(dev);
1146
1147         /* Make sure test of self->io.speed & speed change are atomic */
1148         spin_lock_irqsave(&self->lock, flags);
1149
1150         /* Check if we need to change the speed after this frame */
1151         speed = irda_get_next_speed(skb);
1152         if (speed != self->io.speed && speed != -1) {
1153                 /* Check for empty frame */
1154                 if (!skb->len) {
1155                         /* Note : you should make sure that speed changes
1156                          * are not going to corrupt any outgoing frame.
1157                          * Look at nsc-ircc for the gory details - Jean II */
1158                         smsc_ircc_change_speed(self, speed);
1159                         spin_unlock_irqrestore(&self->lock, flags);
1160                         dev_kfree_skb(skb);
1161                         return 0;
1162                 }
1163
1164                 self->new_speed = speed;
1165         }
1166
1167         skb_copy_from_linear_data(skb, self->tx_buff.head, skb->len);
1168
1169         self->tx_buff.len = skb->len;
1170         self->tx_buff.data = self->tx_buff.head;
1171
1172         mtt = irda_get_mtt(skb);
1173         if (mtt) {
1174                 int bofs;
1175
1176                 /*
1177                  * Compute how many BOFs (STA or PA's) we need to waste the
1178                  * min turn time given the speed of the link.
1179                  */
1180                 bofs = mtt * (self->io.speed / 1000) / 8000;
1181                 if (bofs > 4095)
1182                         bofs = 4095;
1183
1184                 smsc_ircc_dma_xmit(self, bofs);
1185         } else {
1186                 /* Transmit frame */
1187                 smsc_ircc_dma_xmit(self, 0);
1188         }
1189
1190         spin_unlock_irqrestore(&self->lock, flags);
1191         dev_kfree_skb(skb);
1192
1193         return 0;
1194 }
1195
1196 /*
1197  * Function smsc_ircc_dma_xmit (self, bofs)
1198  *
1199  *    Transmit data using DMA
1200  *
1201  */
1202 static void smsc_ircc_dma_xmit(struct smsc_ircc_cb *self, int bofs)
1203 {
1204         int iobase = self->io.fir_base;
1205         u8 ctrl;
1206
1207         IRDA_DEBUG(3, "%s\n", __FUNCTION__);
1208 #if 1
1209         /* Disable Rx */
1210         register_bank(iobase, 0);
1211         outb(0x00, iobase + IRCC_LCR_B);
1212 #endif
1213         register_bank(iobase, 1);
1214         outb(inb(iobase + IRCC_SCE_CFGB) & ~IRCC_CFGB_DMA_ENABLE,
1215              iobase + IRCC_SCE_CFGB);
1216
1217         self->io.direction = IO_XMIT;
1218
1219         /* Set BOF additional count for generating the min turn time */
1220         register_bank(iobase, 4);
1221         outb(bofs & 0xff, iobase + IRCC_BOF_COUNT_LO);
1222         ctrl = inb(iobase + IRCC_CONTROL) & 0xf0;
1223         outb(ctrl | ((bofs >> 8) & 0x0f), iobase + IRCC_BOF_COUNT_HI);
1224
1225         /* Set max Tx frame size */
1226         outb(self->tx_buff.len >> 8, iobase + IRCC_TX_SIZE_HI);
1227         outb(self->tx_buff.len & 0xff, iobase + IRCC_TX_SIZE_LO);
1228
1229         /*outb(UART_MCR_OUT2, self->io.sir_base + UART_MCR);*/
1230
1231         /* Enable burst mode chip Tx DMA */
1232         register_bank(iobase, 1);
1233         outb(inb(iobase + IRCC_SCE_CFGB) | IRCC_CFGB_DMA_ENABLE |
1234              IRCC_CFGB_DMA_BURST, iobase + IRCC_SCE_CFGB);
1235
1236         /* Setup DMA controller (must be done after enabling chip DMA) */
1237         irda_setup_dma(self->io.dma, self->tx_buff_dma, self->tx_buff.len,
1238                        DMA_TX_MODE);
1239
1240         /* Enable interrupt */
1241
1242         register_bank(iobase, 0);
1243         outb(IRCC_IER_ACTIVE_FRAME | IRCC_IER_EOM, iobase + IRCC_IER);
1244         outb(IRCC_MASTER_INT_EN, iobase + IRCC_MASTER);
1245
1246         /* Enable transmit */
1247         outb(IRCC_LCR_B_SCE_TRANSMIT | IRCC_LCR_B_SIP_ENABLE, iobase + IRCC_LCR_B);
1248 }
1249
1250 /*
1251  * Function smsc_ircc_dma_xmit_complete (self)
1252  *
1253  *    The transfer of a frame in finished. This function will only be called
1254  *    by the interrupt handler
1255  *
1256  */
1257 static void smsc_ircc_dma_xmit_complete(struct smsc_ircc_cb *self)
1258 {
1259         int iobase = self->io.fir_base;
1260
1261         IRDA_DEBUG(3, "%s\n", __FUNCTION__);
1262 #if 0
1263         /* Disable Tx */
1264         register_bank(iobase, 0);
1265         outb(0x00, iobase + IRCC_LCR_B);
1266 #endif
1267         register_bank(iobase, 1);
1268         outb(inb(iobase + IRCC_SCE_CFGB) & ~IRCC_CFGB_DMA_ENABLE,
1269              iobase + IRCC_SCE_CFGB);
1270
1271         /* Check for underrun! */
1272         register_bank(iobase, 0);
1273         if (inb(iobase + IRCC_LSR) & IRCC_LSR_UNDERRUN) {
1274                 self->stats.tx_errors++;
1275                 self->stats.tx_fifo_errors++;
1276
1277                 /* Reset error condition */
1278                 register_bank(iobase, 0);
1279                 outb(IRCC_MASTER_ERROR_RESET, iobase + IRCC_MASTER);
1280                 outb(0x00, iobase + IRCC_MASTER);
1281         } else {
1282                 self->stats.tx_packets++;
1283                 self->stats.tx_bytes += self->tx_buff.len;
1284         }
1285
1286         /* Check if it's time to change the speed */
1287         if (self->new_speed) {
1288                 smsc_ircc_change_speed(self, self->new_speed);
1289                 self->new_speed = 0;
1290         }
1291
1292         netif_wake_queue(self->netdev);
1293 }
1294
1295 /*
1296  * Function smsc_ircc_dma_receive(self)
1297  *
1298  *    Get ready for receiving a frame. The device will initiate a DMA
1299  *    if it starts to receive a frame.
1300  *
1301  */
1302 static int smsc_ircc_dma_receive(struct smsc_ircc_cb *self)
1303 {
1304         int iobase = self->io.fir_base;
1305 #if 0
1306         /* Turn off chip DMA */
1307         register_bank(iobase, 1);
1308         outb(inb(iobase + IRCC_SCE_CFGB) & ~IRCC_CFGB_DMA_ENABLE,
1309              iobase + IRCC_SCE_CFGB);
1310 #endif
1311
1312         /* Disable Tx */
1313         register_bank(iobase, 0);
1314         outb(0x00, iobase + IRCC_LCR_B);
1315
1316         /* Turn off chip DMA */
1317         register_bank(iobase, 1);
1318         outb(inb(iobase + IRCC_SCE_CFGB) & ~IRCC_CFGB_DMA_ENABLE,
1319              iobase + IRCC_SCE_CFGB);
1320
1321         self->io.direction = IO_RECV;
1322         self->rx_buff.data = self->rx_buff.head;
1323
1324         /* Set max Rx frame size */
1325         register_bank(iobase, 4);
1326         outb((2050 >> 8) & 0x0f, iobase + IRCC_RX_SIZE_HI);
1327         outb(2050 & 0xff, iobase + IRCC_RX_SIZE_LO);
1328
1329         /* Setup DMA controller */
1330         irda_setup_dma(self->io.dma, self->rx_buff_dma, self->rx_buff.truesize,
1331                        DMA_RX_MODE);
1332
1333         /* Enable burst mode chip Rx DMA */
1334         register_bank(iobase, 1);
1335         outb(inb(iobase + IRCC_SCE_CFGB) | IRCC_CFGB_DMA_ENABLE |
1336              IRCC_CFGB_DMA_BURST, iobase + IRCC_SCE_CFGB);
1337
1338         /* Enable interrupt */
1339         register_bank(iobase, 0);
1340         outb(IRCC_IER_ACTIVE_FRAME | IRCC_IER_EOM, iobase + IRCC_IER);
1341         outb(IRCC_MASTER_INT_EN, iobase + IRCC_MASTER);
1342
1343         /* Enable receiver */
1344         register_bank(iobase, 0);
1345         outb(IRCC_LCR_B_SCE_RECEIVE | IRCC_LCR_B_SIP_ENABLE,
1346              iobase + IRCC_LCR_B);
1347
1348         return 0;
1349 }
1350
1351 /*
1352  * Function smsc_ircc_dma_receive_complete(self)
1353  *
1354  *    Finished with receiving frames
1355  *
1356  */
1357 static void smsc_ircc_dma_receive_complete(struct smsc_ircc_cb *self)
1358 {
1359         struct sk_buff *skb;
1360         int len, msgcnt, lsr;
1361         int iobase = self->io.fir_base;
1362
1363         register_bank(iobase, 0);
1364
1365         IRDA_DEBUG(3, "%s\n", __FUNCTION__);
1366 #if 0
1367         /* Disable Rx */
1368         register_bank(iobase, 0);
1369         outb(0x00, iobase + IRCC_LCR_B);
1370 #endif
1371         register_bank(iobase, 0);
1372         outb(inb(iobase + IRCC_LSAR) & ~IRCC_LSAR_ADDRESS_MASK, iobase + IRCC_LSAR);
1373         lsr= inb(iobase + IRCC_LSR);
1374         msgcnt = inb(iobase + IRCC_LCR_B) & 0x08;
1375
1376         IRDA_DEBUG(2, "%s: dma count = %d\n", __FUNCTION__,
1377                    get_dma_residue(self->io.dma));
1378
1379         len = self->rx_buff.truesize - get_dma_residue(self->io.dma);
1380
1381         /* Look for errors */
1382         if (lsr & (IRCC_LSR_FRAME_ERROR | IRCC_LSR_CRC_ERROR | IRCC_LSR_SIZE_ERROR)) {
1383                 self->stats.rx_errors++;
1384                 if (lsr & IRCC_LSR_FRAME_ERROR)
1385                         self->stats.rx_frame_errors++;
1386                 if (lsr & IRCC_LSR_CRC_ERROR)
1387                         self->stats.rx_crc_errors++;
1388                 if (lsr & IRCC_LSR_SIZE_ERROR)
1389                         self->stats.rx_length_errors++;
1390                 if (lsr & (IRCC_LSR_UNDERRUN | IRCC_LSR_OVERRUN))
1391                         self->stats.rx_length_errors++;
1392                 return;
1393         }
1394
1395         /* Remove CRC */
1396         len -= self->io.speed < 4000000 ? 2 : 4;
1397
1398         if (len < 2 || len > 2050) {
1399                 IRDA_WARNING("%s(), bogus len=%d\n", __FUNCTION__, len);
1400                 return;
1401         }
1402         IRDA_DEBUG(2, "%s: msgcnt = %d, len=%d\n", __FUNCTION__, msgcnt, len);
1403
1404         skb = dev_alloc_skb(len + 1);
1405         if (!skb) {
1406                 IRDA_WARNING("%s(), memory squeeze, dropping frame.\n",
1407                              __FUNCTION__);
1408                 return;
1409         }
1410         /* Make sure IP header gets aligned */
1411         skb_reserve(skb, 1);
1412
1413         memcpy(skb_put(skb, len), self->rx_buff.data, len);
1414         self->stats.rx_packets++;
1415         self->stats.rx_bytes += len;
1416
1417         skb->dev = self->netdev;
1418         skb_reset_mac_header(skb);
1419         skb->protocol = htons(ETH_P_IRDA);
1420         netif_rx(skb);
1421 }
1422
1423 /*
1424  * Function smsc_ircc_sir_receive (self)
1425  *
1426  *    Receive one frame from the infrared port
1427  *
1428  */
1429 static void smsc_ircc_sir_receive(struct smsc_ircc_cb *self)
1430 {
1431         int boguscount = 0;
1432         int iobase;
1433
1434         IRDA_ASSERT(self != NULL, return;);
1435
1436         iobase = self->io.sir_base;
1437
1438         /*
1439          * Receive all characters in Rx FIFO, unwrap and unstuff them.
1440          * async_unwrap_char will deliver all found frames
1441          */
1442         do {
1443                 async_unwrap_char(self->netdev, &self->stats, &self->rx_buff,
1444                                   inb(iobase + UART_RX));
1445
1446                 /* Make sure we don't stay here to long */
1447                 if (boguscount++ > 32) {
1448                         IRDA_DEBUG(2, "%s(), breaking!\n", __FUNCTION__);
1449                         break;
1450                 }
1451         } while (inb(iobase + UART_LSR) & UART_LSR_DR);
1452 }
1453
1454
1455 /*
1456  * Function smsc_ircc_interrupt (irq, dev_id, regs)
1457  *
1458  *    An interrupt from the chip has arrived. Time to do some work
1459  *
1460  */
1461 static irqreturn_t smsc_ircc_interrupt(int irq, void *dev_id)
1462 {
1463         struct net_device *dev = (struct net_device *) dev_id;
1464         struct smsc_ircc_cb *self;
1465         int iobase, iir, lcra, lsr;
1466         irqreturn_t ret = IRQ_NONE;
1467
1468         if (dev == NULL) {
1469                 printk(KERN_WARNING "%s: irq %d for unknown device.\n",
1470                        driver_name, irq);
1471                 goto irq_ret;
1472         }
1473
1474         self = netdev_priv(dev);
1475         IRDA_ASSERT(self != NULL, return IRQ_NONE;);
1476
1477         /* Serialise the interrupt handler in various CPUs, stop Tx path */
1478         spin_lock(&self->lock);
1479
1480         /* Check if we should use the SIR interrupt handler */
1481         if (self->io.speed <= SMSC_IRCC2_MAX_SIR_SPEED) {
1482                 ret = smsc_ircc_interrupt_sir(dev);
1483                 goto irq_ret_unlock;
1484         }
1485
1486         iobase = self->io.fir_base;
1487
1488         register_bank(iobase, 0);
1489         iir = inb(iobase + IRCC_IIR);
1490         if (iir == 0)
1491                 goto irq_ret_unlock;
1492         ret = IRQ_HANDLED;
1493
1494         /* Disable interrupts */
1495         outb(0, iobase + IRCC_IER);
1496         lcra = inb(iobase + IRCC_LCR_A);
1497         lsr = inb(iobase + IRCC_LSR);
1498
1499         IRDA_DEBUG(2, "%s(), iir = 0x%02x\n", __FUNCTION__, iir);
1500
1501         if (iir & IRCC_IIR_EOM) {
1502                 if (self->io.direction == IO_RECV)
1503                         smsc_ircc_dma_receive_complete(self);
1504                 else
1505                         smsc_ircc_dma_xmit_complete(self);
1506
1507                 smsc_ircc_dma_receive(self);
1508         }
1509
1510         if (iir & IRCC_IIR_ACTIVE_FRAME) {
1511                 /*printk(KERN_WARNING "%s(): Active Frame\n", __FUNCTION__);*/
1512         }
1513
1514         /* Enable interrupts again */
1515
1516         register_bank(iobase, 0);
1517         outb(IRCC_IER_ACTIVE_FRAME | IRCC_IER_EOM, iobase + IRCC_IER);
1518
1519  irq_ret_unlock:
1520         spin_unlock(&self->lock);
1521  irq_ret:
1522         return ret;
1523 }
1524
1525 /*
1526  * Function irport_interrupt_sir (irq, dev_id)
1527  *
1528  *    Interrupt handler for SIR modes
1529  */
1530 static irqreturn_t smsc_ircc_interrupt_sir(struct net_device *dev)
1531 {
1532         struct smsc_ircc_cb *self = netdev_priv(dev);
1533         int boguscount = 0;
1534         int iobase;
1535         int iir, lsr;
1536
1537         /* Already locked comming here in smsc_ircc_interrupt() */
1538         /*spin_lock(&self->lock);*/
1539
1540         iobase = self->io.sir_base;
1541
1542         iir = inb(iobase + UART_IIR) & UART_IIR_ID;
1543         if (iir == 0)
1544                 return IRQ_NONE;
1545         while (iir) {
1546                 /* Clear interrupt */
1547                 lsr = inb(iobase + UART_LSR);
1548
1549                 IRDA_DEBUG(4, "%s(), iir=%02x, lsr=%02x, iobase=%#x\n",
1550                             __FUNCTION__, iir, lsr, iobase);
1551
1552                 switch (iir) {
1553                 case UART_IIR_RLSI:
1554                         IRDA_DEBUG(2, "%s(), RLSI\n", __FUNCTION__);
1555                         break;
1556                 case UART_IIR_RDI:
1557                         /* Receive interrupt */
1558                         smsc_ircc_sir_receive(self);
1559                         break;
1560                 case UART_IIR_THRI:
1561                         if (lsr & UART_LSR_THRE)
1562                                 /* Transmitter ready for data */
1563                                 smsc_ircc_sir_write_wakeup(self);
1564                         break;
1565                 default:
1566                         IRDA_DEBUG(0, "%s(), unhandled IIR=%#x\n",
1567                                    __FUNCTION__, iir);
1568                         break;
1569                 }
1570
1571                 /* Make sure we don't stay here to long */
1572                 if (boguscount++ > 100)
1573                         break;
1574
1575                 iir = inb(iobase + UART_IIR) & UART_IIR_ID;
1576         }
1577         /*spin_unlock(&self->lock);*/
1578         return IRQ_HANDLED;
1579 }
1580
1581
1582 #if 0 /* unused */
1583 /*
1584  * Function ircc_is_receiving (self)
1585  *
1586  *    Return TRUE is we are currently receiving a frame
1587  *
1588  */
1589 static int ircc_is_receiving(struct smsc_ircc_cb *self)
1590 {
1591         int status = FALSE;
1592         /* int iobase; */
1593
1594         IRDA_DEBUG(1, "%s\n", __FUNCTION__);
1595
1596         IRDA_ASSERT(self != NULL, return FALSE;);
1597
1598         IRDA_DEBUG(0, "%s: dma count = %d\n", __FUNCTION__,
1599                    get_dma_residue(self->io.dma));
1600
1601         status = (self->rx_buff.state != OUTSIDE_FRAME);
1602
1603         return status;
1604 }
1605 #endif /* unused */
1606
1607 static int smsc_ircc_request_irq(struct smsc_ircc_cb *self)
1608 {
1609         int error;
1610
1611         error = request_irq(self->io.irq, smsc_ircc_interrupt, 0,
1612                             self->netdev->name, self->netdev);
1613         if (error)
1614                 IRDA_DEBUG(0, "%s(), unable to allocate irq=%d, err=%d\n",
1615                            __FUNCTION__, self->io.irq, error);
1616
1617         return error;
1618 }
1619
1620 static void smsc_ircc_start_interrupts(struct smsc_ircc_cb *self)
1621 {
1622         unsigned long flags;
1623
1624         spin_lock_irqsave(&self->lock, flags);
1625
1626         self->io.speed = 0;
1627         smsc_ircc_change_speed(self, SMSC_IRCC2_C_IRDA_FALLBACK_SPEED);
1628
1629         spin_unlock_irqrestore(&self->lock, flags);
1630 }
1631
1632 static void smsc_ircc_stop_interrupts(struct smsc_ircc_cb *self)
1633 {
1634         int iobase = self->io.fir_base;
1635         unsigned long flags;
1636
1637         spin_lock_irqsave(&self->lock, flags);
1638
1639         register_bank(iobase, 0);
1640         outb(0, iobase + IRCC_IER);
1641         outb(IRCC_MASTER_RESET, iobase + IRCC_MASTER);
1642         outb(0x00, iobase + IRCC_MASTER);
1643
1644         spin_unlock_irqrestore(&self->lock, flags);
1645 }
1646
1647
1648 /*
1649  * Function smsc_ircc_net_open (dev)
1650  *
1651  *    Start the device
1652  *
1653  */
1654 static int smsc_ircc_net_open(struct net_device *dev)
1655 {
1656         struct smsc_ircc_cb *self;
1657         char hwname[16];
1658
1659         IRDA_DEBUG(1, "%s\n", __FUNCTION__);
1660
1661         IRDA_ASSERT(dev != NULL, return -1;);
1662         self = netdev_priv(dev);
1663         IRDA_ASSERT(self != NULL, return 0;);
1664
1665         if (self->io.suspended) {
1666                 IRDA_DEBUG(0, "%s(), device is suspended\n", __FUNCTION__);
1667                 return -EAGAIN;
1668         }
1669
1670         if (request_irq(self->io.irq, smsc_ircc_interrupt, 0, dev->name,
1671                         (void *) dev)) {
1672                 IRDA_DEBUG(0, "%s(), unable to allocate irq=%d\n",
1673                            __FUNCTION__, self->io.irq);
1674                 return -EAGAIN;
1675         }
1676
1677         smsc_ircc_start_interrupts(self);
1678
1679         /* Give self a hardware name */
1680         /* It would be cool to offer the chip revision here - Jean II */
1681         sprintf(hwname, "SMSC @ 0x%03x", self->io.fir_base);
1682
1683         /*
1684          * Open new IrLAP layer instance, now that everything should be
1685          * initialized properly
1686          */
1687         self->irlap = irlap_open(dev, &self->qos, hwname);
1688
1689         /*
1690          * Always allocate the DMA channel after the IRQ,
1691          * and clean up on failure.
1692          */
1693         if (request_dma(self->io.dma, dev->name)) {
1694                 smsc_ircc_net_close(dev);
1695
1696                 IRDA_WARNING("%s(), unable to allocate DMA=%d\n",
1697                              __FUNCTION__, self->io.dma);
1698                 return -EAGAIN;
1699         }
1700
1701         netif_start_queue(dev);
1702
1703         return 0;
1704 }
1705
1706 /*
1707  * Function smsc_ircc_net_close (dev)
1708  *
1709  *    Stop the device
1710  *
1711  */
1712 static int smsc_ircc_net_close(struct net_device *dev)
1713 {
1714         struct smsc_ircc_cb *self;
1715
1716         IRDA_DEBUG(1, "%s\n", __FUNCTION__);
1717
1718         IRDA_ASSERT(dev != NULL, return -1;);
1719         self = netdev_priv(dev);
1720         IRDA_ASSERT(self != NULL, return 0;);
1721
1722         /* Stop device */
1723         netif_stop_queue(dev);
1724
1725         /* Stop and remove instance of IrLAP */
1726         if (self->irlap)
1727                 irlap_close(self->irlap);
1728         self->irlap = NULL;
1729
1730         smsc_ircc_stop_interrupts(self);
1731
1732         /* if we are called from smsc_ircc_resume we don't have IRQ reserved */
1733         if (!self->io.suspended)
1734                 free_irq(self->io.irq, dev);
1735
1736         disable_dma(self->io.dma);
1737         free_dma(self->io.dma);
1738
1739         return 0;
1740 }
1741
1742 static int smsc_ircc_suspend(struct platform_device *dev, pm_message_t state)
1743 {
1744         struct smsc_ircc_cb *self = platform_get_drvdata(dev);
1745
1746         if (!self->io.suspended) {
1747                 IRDA_DEBUG(1, "%s, Suspending\n", driver_name);
1748
1749                 rtnl_lock();
1750                 if (netif_running(self->netdev)) {
1751                         netif_device_detach(self->netdev);
1752                         smsc_ircc_stop_interrupts(self);
1753                         free_irq(self->io.irq, self->netdev);
1754                         disable_dma(self->io.dma);
1755                 }
1756                 self->io.suspended = 1;
1757                 rtnl_unlock();
1758         }
1759
1760         return 0;
1761 }
1762
1763 static int smsc_ircc_resume(struct platform_device *dev)
1764 {
1765         struct smsc_ircc_cb *self = platform_get_drvdata(dev);
1766
1767         if (self->io.suspended) {
1768                 IRDA_DEBUG(1, "%s, Waking up\n", driver_name);
1769
1770                 rtnl_lock();
1771                 smsc_ircc_init_chip(self);
1772                 if (netif_running(self->netdev)) {
1773                         if (smsc_ircc_request_irq(self)) {
1774                                 /*
1775                                  * Don't fail resume process, just kill this
1776                                  * network interface
1777                                  */
1778                                 unregister_netdevice(self->netdev);
1779                         } else {
1780                                 enable_dma(self->io.dma);
1781                                 smsc_ircc_start_interrupts(self);
1782                                 netif_device_attach(self->netdev);
1783                         }
1784                 }
1785                 self->io.suspended = 0;
1786                 rtnl_unlock();
1787         }
1788         return 0;
1789 }
1790
1791 /*
1792  * Function smsc_ircc_close (self)
1793  *
1794  *    Close driver instance
1795  *
1796  */
1797 static int __exit smsc_ircc_close(struct smsc_ircc_cb *self)
1798 {
1799         IRDA_DEBUG(1, "%s\n", __FUNCTION__);
1800
1801         IRDA_ASSERT(self != NULL, return -1;);
1802
1803         platform_device_unregister(self->pldev);
1804
1805         /* Remove netdevice */
1806         unregister_netdev(self->netdev);
1807
1808         smsc_ircc_stop_interrupts(self);
1809
1810         /* Release the PORTS that this driver is using */
1811         IRDA_DEBUG(0, "%s(), releasing 0x%03x\n",  __FUNCTION__,
1812                    self->io.fir_base);
1813
1814         release_region(self->io.fir_base, self->io.fir_ext);
1815
1816         IRDA_DEBUG(0, "%s(), releasing 0x%03x\n", __FUNCTION__,
1817                    self->io.sir_base);
1818
1819         release_region(self->io.sir_base, self->io.sir_ext);
1820
1821         if (self->tx_buff.head)
1822                 dma_free_coherent(NULL, self->tx_buff.truesize,
1823                                   self->tx_buff.head, self->tx_buff_dma);
1824
1825         if (self->rx_buff.head)
1826                 dma_free_coherent(NULL, self->rx_buff.truesize,
1827                                   self->rx_buff.head, self->rx_buff_dma);
1828
1829         free_netdev(self->netdev);
1830
1831         return 0;
1832 }
1833
1834 static void __exit smsc_ircc_cleanup(void)
1835 {
1836         int i;
1837
1838         IRDA_DEBUG(1, "%s\n", __FUNCTION__);
1839
1840         for (i = 0; i < 2; i++) {
1841                 if (dev_self[i])
1842                         smsc_ircc_close(dev_self[i]);
1843         }
1844
1845         platform_driver_unregister(&smsc_ircc_driver);
1846 }
1847
1848 /*
1849  *      Start SIR operations
1850  *
1851  * This function *must* be called with spinlock held, because it may
1852  * be called from the irq handler (via smsc_ircc_change_speed()). - Jean II
1853  */
1854 void smsc_ircc_sir_start(struct smsc_ircc_cb *self)
1855 {
1856         struct net_device *dev;
1857         int fir_base, sir_base;
1858
1859         IRDA_DEBUG(3, "%s\n", __FUNCTION__);
1860
1861         IRDA_ASSERT(self != NULL, return;);
1862         dev = self->netdev;
1863         IRDA_ASSERT(dev != NULL, return;);
1864         dev->hard_start_xmit = &smsc_ircc_hard_xmit_sir;
1865
1866         fir_base = self->io.fir_base;
1867         sir_base = self->io.sir_base;
1868
1869         /* Reset everything */
1870         outb(IRCC_MASTER_RESET, fir_base + IRCC_MASTER);
1871
1872         #if SMSC_IRCC2_C_SIR_STOP
1873         /*smsc_ircc_sir_stop(self);*/
1874         #endif
1875
1876         register_bank(fir_base, 1);
1877         outb(((inb(fir_base + IRCC_SCE_CFGA) & IRCC_SCE_CFGA_BLOCK_CTRL_BITS_MASK) | IRCC_CFGA_IRDA_SIR_A), fir_base + IRCC_SCE_CFGA);
1878
1879         /* Initialize UART */
1880         outb(UART_LCR_WLEN8, sir_base + UART_LCR);  /* Reset DLAB */
1881         outb((UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2), sir_base + UART_MCR);
1882
1883         /* Turn on interrups */
1884         outb(UART_IER_RLSI | UART_IER_RDI |UART_IER_THRI, sir_base + UART_IER);
1885
1886         IRDA_DEBUG(3, "%s() - exit\n", __FUNCTION__);
1887
1888         outb(0x00, fir_base + IRCC_MASTER);
1889 }
1890
1891 #if SMSC_IRCC2_C_SIR_STOP
1892 void smsc_ircc_sir_stop(struct smsc_ircc_cb *self)
1893 {
1894         int iobase;
1895
1896         IRDA_DEBUG(3, "%s\n", __FUNCTION__);
1897         iobase = self->io.sir_base;
1898
1899         /* Reset UART */
1900         outb(0, iobase + UART_MCR);
1901
1902         /* Turn off interrupts */
1903         outb(0, iobase + UART_IER);
1904 }
1905 #endif
1906
1907 /*
1908  * Function smsc_sir_write_wakeup (self)
1909  *
1910  *    Called by the SIR interrupt handler when there's room for more data.
1911  *    If we have more packets to send, we send them here.
1912  *
1913  */
1914 static void smsc_ircc_sir_write_wakeup(struct smsc_ircc_cb *self)
1915 {
1916         int actual = 0;
1917         int iobase;
1918         int fcr;
1919
1920         IRDA_ASSERT(self != NULL, return;);
1921
1922         IRDA_DEBUG(4, "%s\n", __FUNCTION__);
1923
1924         iobase = self->io.sir_base;
1925
1926         /* Finished with frame?  */
1927         if (self->tx_buff.len > 0)  {
1928                 /* Write data left in transmit buffer */
1929                 actual = smsc_ircc_sir_write(iobase, self->io.fifo_size,
1930                                       self->tx_buff.data, self->tx_buff.len);
1931                 self->tx_buff.data += actual;
1932                 self->tx_buff.len  -= actual;
1933         } else {
1934
1935         /*if (self->tx_buff.len ==0)  {*/
1936
1937                 /*
1938                  *  Now serial buffer is almost free & we can start
1939                  *  transmission of another packet. But first we must check
1940                  *  if we need to change the speed of the hardware
1941                  */
1942                 if (self->new_speed) {
1943                         IRDA_DEBUG(5, "%s(), Changing speed to %d.\n",
1944                                    __FUNCTION__, self->new_speed);
1945                         smsc_ircc_sir_wait_hw_transmitter_finish(self);
1946                         smsc_ircc_change_speed(self, self->new_speed);
1947                         self->new_speed = 0;
1948                 } else {
1949                         /* Tell network layer that we want more frames */
1950                         netif_wake_queue(self->netdev);
1951                 }
1952                 self->stats.tx_packets++;
1953
1954                 if (self->io.speed <= 115200) {
1955                         /*
1956                          * Reset Rx FIFO to make sure that all reflected transmit data
1957                          * is discarded. This is needed for half duplex operation
1958                          */
1959                         fcr = UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR;
1960                         fcr |= self->io.speed < 38400 ?
1961                                         UART_FCR_TRIGGER_1 : UART_FCR_TRIGGER_14;
1962
1963                         outb(fcr, iobase + UART_FCR);
1964
1965                         /* Turn on receive interrupts */
1966                         outb(UART_IER_RDI, iobase + UART_IER);
1967                 }
1968         }
1969 }
1970
1971 /*
1972  * Function smsc_ircc_sir_write (iobase, fifo_size, buf, len)
1973  *
1974  *    Fill Tx FIFO with transmit data
1975  *
1976  */
1977 static int smsc_ircc_sir_write(int iobase, int fifo_size, __u8 *buf, int len)
1978 {
1979         int actual = 0;
1980
1981         /* Tx FIFO should be empty! */
1982         if (!(inb(iobase + UART_LSR) & UART_LSR_THRE)) {
1983                 IRDA_WARNING("%s(), failed, fifo not empty!\n", __FUNCTION__);
1984                 return 0;
1985         }
1986
1987         /* Fill FIFO with current frame */
1988         while (fifo_size-- > 0 && actual < len) {
1989                 /* Transmit next byte */
1990                 outb(buf[actual], iobase + UART_TX);
1991                 actual++;
1992         }
1993         return actual;
1994 }
1995
1996 /*
1997  * Function smsc_ircc_is_receiving (self)
1998  *
1999  *    Returns true is we are currently receiving data
2000  *
2001  */
2002 static int smsc_ircc_is_receiving(struct smsc_ircc_cb *self)
2003 {
2004         return (self->rx_buff.state != OUTSIDE_FRAME);
2005 }
2006
2007
2008 /*
2009  * Function smsc_ircc_probe_transceiver(self)
2010  *
2011  *    Tries to find the used Transceiver
2012  *
2013  */
2014 static void smsc_ircc_probe_transceiver(struct smsc_ircc_cb *self)
2015 {
2016         unsigned int    i;
2017
2018         IRDA_ASSERT(self != NULL, return;);
2019
2020         for (i = 0; smsc_transceivers[i].name != NULL; i++)
2021                 if (smsc_transceivers[i].probe(self->io.fir_base)) {
2022                         IRDA_MESSAGE(" %s transceiver found\n",
2023                                      smsc_transceivers[i].name);
2024                         self->transceiver= i + 1;
2025                         return;
2026                 }
2027
2028         IRDA_MESSAGE("No transceiver found. Defaulting to %s\n",
2029                      smsc_transceivers[SMSC_IRCC2_C_DEFAULT_TRANSCEIVER].name);
2030
2031         self->transceiver = SMSC_IRCC2_C_DEFAULT_TRANSCEIVER;
2032 }
2033
2034
2035 /*
2036  * Function smsc_ircc_set_transceiver_for_speed(self, speed)
2037  *
2038  *    Set the transceiver according to the speed
2039  *
2040  */
2041 static void smsc_ircc_set_transceiver_for_speed(struct smsc_ircc_cb *self, u32 speed)
2042 {
2043         unsigned int trx;
2044
2045         trx = self->transceiver;
2046         if (trx > 0)
2047                 smsc_transceivers[trx - 1].set_for_speed(self->io.fir_base, speed);
2048 }
2049
2050 /*
2051  * Function smsc_ircc_wait_hw_transmitter_finish ()
2052  *
2053  *    Wait for the real end of HW transmission
2054  *
2055  * The UART is a strict FIFO, and we get called only when we have finished
2056  * pushing data to the FIFO, so the maximum amount of time we must wait
2057  * is only for the FIFO to drain out.
2058  *
2059  * We use a simple calibrated loop. We may need to adjust the loop
2060  * delay (udelay) to balance I/O traffic and latency. And we also need to
2061  * adjust the maximum timeout.
2062  * It would probably be better to wait for the proper interrupt,
2063  * but it doesn't seem to be available.
2064  *
2065  * We can't use jiffies or kernel timers because :
2066  * 1) We are called from the interrupt handler, which disable softirqs,
2067  * so jiffies won't be increased
2068  * 2) Jiffies granularity is usually very coarse (10ms), and we don't
2069  * want to wait that long to detect stuck hardware.
2070  * Jean II
2071  */
2072
2073 static void smsc_ircc_sir_wait_hw_transmitter_finish(struct smsc_ircc_cb *self)
2074 {
2075         int iobase = self->io.sir_base;
2076         int count = SMSC_IRCC2_HW_TRANSMITTER_TIMEOUT_US;
2077
2078         /* Calibrated busy loop */
2079         while (count-- > 0 && !(inb(iobase + UART_LSR) & UART_LSR_TEMT))
2080                 udelay(1);
2081
2082         if (count == 0)
2083                 IRDA_DEBUG(0, "%s(): stuck transmitter\n", __FUNCTION__);
2084 }
2085
2086
2087 /* PROBING
2088  *
2089  * REVISIT we can be told about the device by PNP, and should use that info
2090  * instead of probing hardware and creating a platform_device ...
2091  */
2092
2093 static int __init smsc_ircc_look_for_chips(void)
2094 {
2095         struct smsc_chip_address *address;
2096         char *type;
2097         unsigned int cfg_base, found;
2098
2099         found = 0;
2100         address = possible_addresses;
2101
2102         while (address->cfg_base) {
2103                 cfg_base = address->cfg_base;
2104
2105                 /*printk(KERN_WARNING "%s(): probing: 0x%02x for: 0x%02x\n", __FUNCTION__, cfg_base, address->type);*/
2106
2107                 if (address->type & SMSCSIO_TYPE_FDC) {
2108                         type = "FDC";
2109                         if (address->type & SMSCSIO_TYPE_FLAT)
2110                                 if (!smsc_superio_flat(fdc_chips_flat, cfg_base, type))
2111                                         found++;
2112
2113                         if (address->type & SMSCSIO_TYPE_PAGED)
2114                                 if (!smsc_superio_paged(fdc_chips_paged, cfg_base, type))
2115                                         found++;
2116                 }
2117                 if (address->type & SMSCSIO_TYPE_LPC) {
2118                         type = "LPC";
2119                         if (address->type & SMSCSIO_TYPE_FLAT)
2120                                 if (!smsc_superio_flat(lpc_chips_flat, cfg_base, type))
2121                                         found++;
2122
2123                         if (address->type & SMSCSIO_TYPE_PAGED)
2124                                 if (!smsc_superio_paged(lpc_chips_paged, cfg_base, type))
2125                                         found++;
2126                 }
2127                 address++;
2128         }
2129         return found;
2130 }
2131
2132 /*
2133  * Function smsc_superio_flat (chip, base, type)
2134  *
2135  *    Try to get configuration of a smc SuperIO chip with flat register model
2136  *
2137  */
2138 static int __init smsc_superio_flat(const struct smsc_chip *chips, unsigned short cfgbase, char *type)
2139 {
2140         unsigned short firbase, sirbase;
2141         u8 mode, dma, irq;
2142         int ret = -ENODEV;
2143
2144         IRDA_DEBUG(1, "%s\n", __FUNCTION__);
2145
2146         if (smsc_ircc_probe(cfgbase, SMSCSIOFLAT_DEVICEID_REG, chips, type) == NULL)
2147                 return ret;
2148
2149         outb(SMSCSIOFLAT_UARTMODE0C_REG, cfgbase);
2150         mode = inb(cfgbase + 1);
2151
2152         /*printk(KERN_WARNING "%s(): mode: 0x%02x\n", __FUNCTION__, mode);*/
2153
2154         if (!(mode & SMSCSIOFLAT_UART2MODE_VAL_IRDA))
2155                 IRDA_WARNING("%s(): IrDA not enabled\n", __FUNCTION__);
2156
2157         outb(SMSCSIOFLAT_UART2BASEADDR_REG, cfgbase);
2158         sirbase = inb(cfgbase + 1) << 2;
2159
2160         /* FIR iobase */
2161         outb(SMSCSIOFLAT_FIRBASEADDR_REG, cfgbase);
2162         firbase = inb(cfgbase + 1) << 3;
2163
2164         /* DMA */
2165         outb(SMSCSIOFLAT_FIRDMASELECT_REG, cfgbase);
2166         dma = inb(cfgbase + 1) & SMSCSIOFLAT_FIRDMASELECT_MASK;
2167
2168         /* IRQ */
2169         outb(SMSCSIOFLAT_UARTIRQSELECT_REG, cfgbase);
2170         irq = inb(cfgbase + 1) & SMSCSIOFLAT_UART2IRQSELECT_MASK;
2171
2172         IRDA_MESSAGE("%s(): fir: 0x%02x, sir: 0x%02x, dma: %02d, irq: %d, mode: 0x%02x\n", __FUNCTION__, firbase, sirbase, dma, irq, mode);
2173
2174         if (firbase && smsc_ircc_open(firbase, sirbase, dma, irq) == 0)
2175                 ret = 0;
2176
2177         /* Exit configuration */
2178         outb(SMSCSIO_CFGEXITKEY, cfgbase);
2179
2180         return ret;
2181 }
2182
2183 /*
2184  * Function smsc_superio_paged (chip, base, type)
2185  *
2186  *    Try  to get configuration of a smc SuperIO chip with paged register model
2187  *
2188  */
2189 static int __init smsc_superio_paged(const struct smsc_chip *chips, unsigned short cfg_base, char *type)
2190 {
2191         unsigned short fir_io, sir_io;
2192         int ret = -ENODEV;
2193
2194         IRDA_DEBUG(1, "%s\n", __FUNCTION__);
2195
2196         if (smsc_ircc_probe(cfg_base, 0x20, chips, type) == NULL)
2197                 return ret;
2198
2199         /* Select logical device (UART2) */
2200         outb(0x07, cfg_base);
2201         outb(0x05, cfg_base + 1);
2202
2203         /* SIR iobase */
2204         outb(0x60, cfg_base);
2205         sir_io = inb(cfg_base + 1) << 8;
2206         outb(0x61, cfg_base);
2207         sir_io |= inb(cfg_base + 1);
2208
2209         /* Read FIR base */
2210         outb(0x62, cfg_base);
2211         fir_io = inb(cfg_base + 1) << 8;
2212         outb(0x63, cfg_base);
2213         fir_io |= inb(cfg_base + 1);
2214         outb(0x2b, cfg_base); /* ??? */
2215
2216         if (fir_io && smsc_ircc_open(fir_io, sir_io, ircc_dma, ircc_irq) == 0)
2217                 ret = 0;
2218
2219         /* Exit configuration */
2220         outb(SMSCSIO_CFGEXITKEY, cfg_base);
2221
2222         return ret;
2223 }
2224
2225
2226 static int __init smsc_access(unsigned short cfg_base, unsigned char reg)
2227 {
2228         IRDA_DEBUG(1, "%s\n", __FUNCTION__);
2229
2230         outb(reg, cfg_base);
2231         return inb(cfg_base) != reg ? -1 : 0;
2232 }
2233
2234 static const struct smsc_chip * __init smsc_ircc_probe(unsigned short cfg_base, u8 reg, const struct smsc_chip *chip, char *type)
2235 {
2236         u8 devid, xdevid, rev;
2237
2238         IRDA_DEBUG(1, "%s\n", __FUNCTION__);
2239
2240         /* Leave configuration */
2241
2242         outb(SMSCSIO_CFGEXITKEY, cfg_base);
2243
2244         if (inb(cfg_base) == SMSCSIO_CFGEXITKEY)        /* not a smc superio chip */
2245                 return NULL;
2246
2247         outb(reg, cfg_base);
2248
2249         xdevid = inb(cfg_base + 1);
2250
2251         /* Enter configuration */
2252
2253         outb(SMSCSIO_CFGACCESSKEY, cfg_base);
2254
2255         #if 0
2256         if (smsc_access(cfg_base,0x55)) /* send second key and check */
2257                 return NULL;
2258         #endif
2259
2260         /* probe device ID */
2261
2262         if (smsc_access(cfg_base, reg))
2263                 return NULL;
2264
2265         devid = inb(cfg_base + 1);
2266
2267         if (devid == 0 || devid == 0xff)        /* typical values for unused port */
2268                 return NULL;
2269
2270         /* probe revision ID */
2271
2272         if (smsc_access(cfg_base, reg + 1))
2273                 return NULL;
2274
2275         rev = inb(cfg_base + 1);
2276
2277         if (rev >= 128)                 /* i think this will make no sense */
2278                 return NULL;
2279
2280         if (devid == xdevid)            /* protection against false positives */
2281                 return NULL;
2282
2283         /* Check for expected device ID; are there others? */
2284
2285         while (chip->devid != devid) {
2286
2287                 chip++;
2288
2289                 if (chip->name == NULL)
2290                         return NULL;
2291         }
2292
2293         IRDA_MESSAGE("found SMC SuperIO Chip (devid=0x%02x rev=%02X base=0x%04x): %s%s\n",
2294                      devid, rev, cfg_base, type, chip->name);
2295
2296         if (chip->rev > rev) {
2297                 IRDA_MESSAGE("Revision higher than expected\n");
2298                 return NULL;
2299         }
2300
2301         if (chip->flags & NoIRDA)
2302                 IRDA_MESSAGE("chipset does not support IRDA\n");
2303
2304         return chip;
2305 }
2306
2307 static int __init smsc_superio_fdc(unsigned short cfg_base)
2308 {
2309         int ret = -1;
2310
2311         if (!request_region(cfg_base, 2, driver_name)) {
2312                 IRDA_WARNING("%s: can't get cfg_base of 0x%03x\n",
2313                              __FUNCTION__, cfg_base);
2314         } else {
2315                 if (!smsc_superio_flat(fdc_chips_flat, cfg_base, "FDC") ||
2316                     !smsc_superio_paged(fdc_chips_paged, cfg_base, "FDC"))
2317                         ret =  0;
2318
2319                 release_region(cfg_base, 2);
2320         }
2321
2322         return ret;
2323 }
2324
2325 static int __init smsc_superio_lpc(unsigned short cfg_base)
2326 {
2327         int ret = -1;
2328
2329         if (!request_region(cfg_base, 2, driver_name)) {
2330                 IRDA_WARNING("%s: can't get cfg_base of 0x%03x\n",
2331                              __FUNCTION__, cfg_base);
2332         } else {
2333                 if (!smsc_superio_flat(lpc_chips_flat, cfg_base, "LPC") ||
2334                     !smsc_superio_paged(lpc_chips_paged, cfg_base, "LPC"))
2335                         ret = 0;
2336
2337                 release_region(cfg_base, 2);
2338         }
2339         return ret;
2340 }
2341
2342 /*
2343  * Look for some specific subsystem setups that need
2344  * pre-configuration not properly done by the BIOS (especially laptops)
2345  * This code is based in part on smcinit.c, tosh1800-smcinit.c
2346  * and tosh2450-smcinit.c. The table lists the device entries
2347  * for ISA bridges with an LPC (Low Pin Count) controller which
2348  * handles the communication with the SMSC device. After the LPC
2349  * controller is initialized through PCI, the SMSC device is initialized
2350  * through a dedicated port in the ISA port-mapped I/O area, this latter
2351  * area is used to configure the SMSC device with default
2352  * SIR and FIR I/O ports, DMA and IRQ. Different vendors have
2353  * used different sets of parameters and different control port
2354  * addresses making a subsystem device table necessary.
2355  */
2356 #ifdef CONFIG_PCI
2357 #define PCIID_VENDOR_INTEL 0x8086
2358 #define PCIID_VENDOR_ALI 0x10b9
2359 static struct smsc_ircc_subsystem_configuration subsystem_configurations[] __initdata = {
2360         /*
2361          * Subsystems needing entries:
2362          * 0x10b9:0x1533 0x103c:0x0850 HP nx9010 family
2363          * 0x10b9:0x1533 0x0e11:0x005a Compaq nc4000 family
2364          * 0x8086:0x24cc 0x0e11:0x002a HP nx9000 family
2365          */
2366         {
2367                 /* Guessed entry */
2368                 .vendor = PCIID_VENDOR_INTEL, /* Intel 82801DBM LPC bridge */
2369                 .device = 0x24cc,
2370                 .subvendor = 0x103c,
2371                 .subdevice = 0x08bc,
2372                 .sir_io = 0x02f8,
2373                 .fir_io = 0x0130,
2374                 .fir_irq = 0x05,
2375                 .fir_dma = 0x03,
2376                 .cfg_base = 0x004e,
2377                 .preconfigure = preconfigure_through_82801,
2378                 .name = "HP nx5000 family",
2379         },
2380         {
2381                 .vendor = PCIID_VENDOR_INTEL, /* Intel 82801DBM LPC bridge */
2382                 .device = 0x24cc,
2383                 .subvendor = 0x103c,
2384                 .subdevice = 0x088c,
2385                 /* Quite certain these are the same for nc8000 as for nc6000 */
2386                 .sir_io = 0x02f8,
2387                 .fir_io = 0x0130,
2388                 .fir_irq = 0x05,
2389                 .fir_dma = 0x03,
2390                 .cfg_base = 0x004e,
2391                 .preconfigure = preconfigure_through_82801,
2392                 .name = "HP nc8000 family",
2393         },
2394         {
2395                 .vendor = PCIID_VENDOR_INTEL, /* Intel 82801DBM LPC bridge */
2396                 .device = 0x24cc,
2397                 .subvendor = 0x103c,
2398                 .subdevice = 0x0890,
2399                 .sir_io = 0x02f8,
2400                 .fir_io = 0x0130,
2401                 .fir_irq = 0x05,
2402                 .fir_dma = 0x03,
2403                 .cfg_base = 0x004e,
2404                 .preconfigure = preconfigure_through_82801,
2405                 .name = "HP nc6000 family",
2406         },
2407         {
2408                 .vendor = PCIID_VENDOR_INTEL, /* Intel 82801DBM LPC bridge */
2409                 .device = 0x24cc,
2410                 .subvendor = 0x0e11,
2411                 .subdevice = 0x0860,
2412                 /* I assume these are the same for x1000 as for the others */
2413                 .sir_io = 0x02e8,
2414                 .fir_io = 0x02f8,
2415                 .fir_irq = 0x07,
2416                 .fir_dma = 0x03,
2417                 .cfg_base = 0x002e,
2418                 .preconfigure = preconfigure_through_82801,
2419                 .name = "Compaq x1000 family",
2420         },
2421         {
2422                 /* Intel 82801DB/DBL (ICH4/ICH4-L) LPC Interface Bridge */
2423                 .vendor = PCIID_VENDOR_INTEL,
2424                 .device = 0x24c0,
2425                 .subvendor = 0x1179,
2426                 .subdevice = 0xffff, /* 0xffff is "any" */
2427                 .sir_io = 0x03f8,
2428                 .fir_io = 0x0130,
2429                 .fir_irq = 0x07,
2430                 .fir_dma = 0x01,
2431                 .cfg_base = 0x002e,
2432                 .preconfigure = preconfigure_through_82801,
2433                 .name = "Toshiba laptop with Intel 82801DB/DBL LPC bridge",
2434         },
2435         {
2436                 .vendor = PCIID_VENDOR_INTEL, /* Intel 82801CAM ISA bridge */
2437                 .device = 0x248c,
2438                 .subvendor = 0x1179,
2439                 .subdevice = 0xffff, /* 0xffff is "any" */
2440                 .sir_io = 0x03f8,
2441                 .fir_io = 0x0130,
2442                 .fir_irq = 0x03,
2443                 .fir_dma = 0x03,
2444                 .cfg_base = 0x002e,
2445                 .preconfigure = preconfigure_through_82801,
2446                 .name = "Toshiba laptop with Intel 82801CAM ISA bridge",
2447         },
2448         {
2449                 /* 82801DBM (ICH4-M) LPC Interface Bridge */
2450                 .vendor = PCIID_VENDOR_INTEL,
2451                 .device = 0x24cc,
2452                 .subvendor = 0x1179,
2453                 .subdevice = 0xffff, /* 0xffff is "any" */
2454                 .sir_io = 0x03f8,
2455                 .fir_io = 0x0130,
2456                 .fir_irq = 0x03,
2457                 .fir_dma = 0x03,
2458                 .cfg_base = 0x002e,
2459                 .preconfigure = preconfigure_through_82801,
2460                 .name = "Toshiba laptop with Intel 8281DBM LPC bridge",
2461         },
2462         {
2463                 /* ALi M1533/M1535 PCI to ISA Bridge [Aladdin IV/V/V+] */
2464                 .vendor = PCIID_VENDOR_ALI,
2465                 .device = 0x1533,
2466                 .subvendor = 0x1179,
2467                 .subdevice = 0xffff, /* 0xffff is "any" */
2468                 .sir_io = 0x02e8,
2469                 .fir_io = 0x02f8,
2470                 .fir_irq = 0x07,
2471                 .fir_dma = 0x03,
2472                 .cfg_base = 0x002e,
2473                 .preconfigure = preconfigure_through_ali,
2474                 .name = "Toshiba laptop with ALi ISA bridge",
2475         },
2476         { } // Terminator
2477 };
2478
2479
2480 /*
2481  * This sets up the basic SMSC parameters
2482  * (FIR port, SIR port, FIR DMA, FIR IRQ)
2483  * through the chip configuration port.
2484  */
2485 static int __init preconfigure_smsc_chip(struct
2486                                          smsc_ircc_subsystem_configuration
2487                                          *conf)
2488 {
2489         unsigned short iobase = conf->cfg_base;
2490         unsigned char tmpbyte;
2491
2492         outb(LPC47N227_CFGACCESSKEY, iobase); // enter configuration state
2493         outb(SMSCSIOFLAT_DEVICEID_REG, iobase); // set for device ID
2494         tmpbyte = inb(iobase +1); // Read device ID
2495         IRDA_DEBUG(0,
2496                    "Detected Chip id: 0x%02x, setting up registers...\n",
2497                    tmpbyte);
2498
2499         /* Disable UART1 and set up SIR I/O port */
2500         outb(0x24, iobase);  // select CR24 - UART1 base addr
2501         outb(0x00, iobase + 1); // disable UART1
2502         outb(SMSCSIOFLAT_UART2BASEADDR_REG, iobase);  // select CR25 - UART2 base addr
2503         outb( (conf->sir_io >> 2), iobase + 1); // bits 2-9 of 0x3f8
2504         tmpbyte = inb(iobase + 1);
2505         if (tmpbyte != (conf->sir_io >> 2) ) {
2506                 IRDA_WARNING("ERROR: could not configure SIR ioport.\n");
2507                 IRDA_WARNING("Try to supply ircc_cfg argument.\n");
2508                 return -ENXIO;
2509         }
2510
2511         /* Set up FIR IRQ channel for UART2 */
2512         outb(SMSCSIOFLAT_UARTIRQSELECT_REG, iobase); // select CR28 - UART1,2 IRQ select
2513         tmpbyte = inb(iobase + 1);
2514         tmpbyte &= SMSCSIOFLAT_UART1IRQSELECT_MASK; // Do not touch the UART1 portion
2515         tmpbyte |= (conf->fir_irq & SMSCSIOFLAT_UART2IRQSELECT_MASK);
2516         outb(tmpbyte, iobase + 1);
2517         tmpbyte = inb(iobase + 1) & SMSCSIOFLAT_UART2IRQSELECT_MASK;
2518         if (tmpbyte != conf->fir_irq) {
2519                 IRDA_WARNING("ERROR: could not configure FIR IRQ channel.\n");
2520                 return -ENXIO;
2521         }
2522
2523         /* Set up FIR I/O port */
2524         outb(SMSCSIOFLAT_FIRBASEADDR_REG, iobase);  // CR2B - SCE (FIR) base addr
2525         outb((conf->fir_io >> 3), iobase + 1);
2526         tmpbyte = inb(iobase + 1);
2527         if (tmpbyte != (conf->fir_io >> 3) ) {
2528                 IRDA_WARNING("ERROR: could not configure FIR I/O port.\n");
2529                 return -ENXIO;
2530         }
2531
2532         /* Set up FIR DMA channel */
2533         outb(SMSCSIOFLAT_FIRDMASELECT_REG, iobase);  // CR2C - SCE (FIR) DMA select
2534         outb((conf->fir_dma & LPC47N227_FIRDMASELECT_MASK), iobase + 1); // DMA
2535         tmpbyte = inb(iobase + 1) & LPC47N227_FIRDMASELECT_MASK;
2536         if (tmpbyte != (conf->fir_dma & LPC47N227_FIRDMASELECT_MASK)) {
2537                 IRDA_WARNING("ERROR: could not configure FIR DMA channel.\n");
2538                 return -ENXIO;
2539         }
2540
2541         outb(SMSCSIOFLAT_UARTMODE0C_REG, iobase);  // CR0C - UART mode
2542         tmpbyte = inb(iobase + 1);
2543         tmpbyte &= ~SMSCSIOFLAT_UART2MODE_MASK |
2544                 SMSCSIOFLAT_UART2MODE_VAL_IRDA;
2545         outb(tmpbyte, iobase + 1); // enable IrDA (HPSIR) mode, high speed
2546
2547         outb(LPC47N227_APMBOOTDRIVE_REG, iobase);  // CR07 - Auto Pwr Mgt/boot drive sel
2548         tmpbyte = inb(iobase + 1);
2549         outb(tmpbyte | LPC47N227_UART2AUTOPWRDOWN_MASK, iobase + 1); // enable UART2 autopower down
2550
2551         /* This one was not part of tosh1800 */
2552         outb(0x0a, iobase);  // CR0a - ecp fifo / ir mux
2553         tmpbyte = inb(iobase + 1);
2554         outb(tmpbyte | 0x40, iobase + 1); // send active device to ir port
2555
2556         outb(LPC47N227_UART12POWER_REG, iobase);  // CR02 - UART 1,2 power
2557         tmpbyte = inb(iobase + 1);
2558         outb(tmpbyte | LPC47N227_UART2POWERDOWN_MASK, iobase + 1); // UART2 power up mode, UART1 power down
2559
2560         outb(LPC47N227_FDCPOWERVALIDCONF_REG, iobase);  // CR00 - FDC Power/valid config cycle
2561         tmpbyte = inb(iobase + 1);
2562         outb(tmpbyte | LPC47N227_VALID_MASK, iobase + 1); // valid config cycle done
2563
2564         outb(LPC47N227_CFGEXITKEY, iobase);  // Exit configuration
2565
2566         return 0;
2567 }
2568
2569 /* 82801CAM generic registers */
2570 #define VID 0x00
2571 #define DID 0x02
2572 #define PIRQ_A_D_ROUT 0x60
2573 #define SIRQ_CNTL 0x64
2574 #define PIRQ_E_H_ROUT 0x68
2575 #define PCI_DMA_C 0x90
2576 /* LPC-specific registers */
2577 #define COM_DEC 0xe0
2578 #define GEN1_DEC 0xe4
2579 #define LPC_EN 0xe6
2580 #define GEN2_DEC 0xec
2581 /*
2582  * Sets up the I/O range using the 82801CAM ISA bridge, 82801DBM LPC bridge
2583  * or Intel 82801DB/DBL (ICH4/ICH4-L) LPC Interface Bridge.
2584  * They all work the same way!
2585  */
2586 static int __init preconfigure_through_82801(struct pci_dev *dev,
2587                                              struct
2588                                              smsc_ircc_subsystem_configuration
2589                                              *conf)
2590 {
2591         unsigned short tmpword;
2592         unsigned char tmpbyte;
2593
2594         IRDA_MESSAGE("Setting up Intel 82801 controller and SMSC device\n");
2595         /*
2596          * Select the range for the COMA COM port (SIR)
2597          * Register COM_DEC:
2598          * Bit 7: reserved
2599          * Bit 6-4, COMB decode range
2600          * Bit 3: reserved
2601          * Bit 2-0, COMA decode range
2602          *
2603          * Decode ranges:
2604          *   000 = 0x3f8-0x3ff (COM1)
2605          *   001 = 0x2f8-0x2ff (COM2)
2606          *   010 = 0x220-0x227
2607          *   011 = 0x228-0x22f
2608          *   100 = 0x238-0x23f
2609          *   101 = 0x2e8-0x2ef (COM4)
2610          *   110 = 0x338-0x33f
2611          *   111 = 0x3e8-0x3ef (COM3)
2612          */
2613         pci_read_config_byte(dev, COM_DEC, &tmpbyte);
2614         tmpbyte &= 0xf8; /* mask COMA bits */
2615         switch(conf->sir_io) {
2616         case 0x3f8:
2617                 tmpbyte |= 0x00;
2618                 break;
2619         case 0x2f8:
2620                 tmpbyte |= 0x01;
2621                 break;
2622         case 0x220:
2623                 tmpbyte |= 0x02;
2624                 break;
2625         case 0x228:
2626                 tmpbyte |= 0x03;
2627                 break;
2628         case 0x238:
2629                 tmpbyte |= 0x04;
2630                 break;
2631         case 0x2e8:
2632                 tmpbyte |= 0x05;
2633                 break;
2634         case 0x338:
2635                 tmpbyte |= 0x06;
2636                 break;
2637         case 0x3e8:
2638                 tmpbyte |= 0x07;
2639                 break;
2640         default:
2641                 tmpbyte |= 0x01; /* COM2 default */
2642         }
2643         IRDA_DEBUG(1, "COM_DEC (write): 0x%02x\n", tmpbyte);
2644         pci_write_config_byte(dev, COM_DEC, tmpbyte);
2645
2646         /* Enable Low Pin Count interface */
2647         pci_read_config_word(dev, LPC_EN, &tmpword);
2648         /* These seem to be set up at all times,
2649          * just make sure it is properly set.
2650          */
2651         switch(conf->cfg_base) {
2652         case 0x04e:
2653                 tmpword |= 0x2000;
2654                 break;
2655         case 0x02e:
2656                 tmpword |= 0x1000;
2657                 break;
2658         case 0x062:
2659                 tmpword |= 0x0800;
2660                 break;
2661         case 0x060:
2662                 tmpword |= 0x0400;
2663                 break;
2664         default:
2665                 IRDA_WARNING("Uncommon I/O base address: 0x%04x\n",
2666                              conf->cfg_base);
2667                 break;
2668         }
2669         tmpword &= 0xfffd; /* disable LPC COMB */
2670         tmpword |= 0x0001; /* set bit 0 : enable LPC COMA addr range (GEN2) */
2671         IRDA_DEBUG(1, "LPC_EN (write): 0x%04x\n", tmpword);
2672         pci_write_config_word(dev, LPC_EN, tmpword);
2673
2674         /*
2675          * Configure LPC DMA channel
2676          * PCI_DMA_C bits:
2677          * Bit 15-14: DMA channel 7 select
2678          * Bit 13-12: DMA channel 6 select
2679          * Bit 11-10: DMA channel 5 select
2680          * Bit 9-8:   Reserved
2681          * Bit 7-6:   DMA channel 3 select
2682          * Bit 5-4:   DMA channel 2 select
2683          * Bit 3-2:   DMA channel 1 select
2684          * Bit 1-0:   DMA channel 0 select
2685          *  00 = Reserved value
2686          *  01 = PC/PCI DMA
2687          *  10 = Reserved value
2688          *  11 = LPC I/F DMA
2689          */
2690         pci_read_config_word(dev, PCI_DMA_C, &tmpword);
2691         switch(conf->fir_dma) {
2692         case 0x07:
2693                 tmpword |= 0xc000;
2694                 break;
2695         case 0x06:
2696                 tmpword |= 0x3000;
2697                 break;
2698         case 0x05:
2699                 tmpword |= 0x0c00;
2700                 break;
2701         case 0x03:
2702                 tmpword |= 0x00c0;
2703                 break;
2704         case 0x02:
2705                 tmpword |= 0x0030;
2706                 break;
2707         case 0x01:
2708                 tmpword |= 0x000c;
2709                 break;
2710         case 0x00:
2711                 tmpword |= 0x0003;
2712                 break;
2713         default:
2714                 break; /* do not change settings */
2715         }
2716         IRDA_DEBUG(1, "PCI_DMA_C (write): 0x%04x\n", tmpword);
2717         pci_write_config_word(dev, PCI_DMA_C, tmpword);
2718
2719         /*
2720          * GEN2_DEC bits:
2721          * Bit 15-4: Generic I/O range
2722          * Bit 3-1: reserved (read as 0)
2723          * Bit 0: enable GEN2 range on LPC I/F
2724          */
2725         tmpword = conf->fir_io & 0xfff8;
2726         tmpword |= 0x0001;
2727         IRDA_DEBUG(1, "GEN2_DEC (write): 0x%04x\n", tmpword);
2728         pci_write_config_word(dev, GEN2_DEC, tmpword);
2729
2730         /* Pre-configure chip */
2731         return preconfigure_smsc_chip(conf);
2732 }
2733
2734 /*
2735  * Pre-configure a certain port on the ALi 1533 bridge.
2736  * This is based on reverse-engineering since ALi does not
2737  * provide any data sheet for the 1533 chip.
2738  */
2739 static void __init preconfigure_ali_port(struct pci_dev *dev,
2740                                          unsigned short port)
2741 {
2742         unsigned char reg;
2743         /* These bits obviously control the different ports */
2744         unsigned char mask;
2745         unsigned char tmpbyte;
2746
2747         switch(port) {
2748         case 0x0130:
2749         case 0x0178:
2750                 reg = 0xb0;
2751                 mask = 0x80;
2752                 break;
2753         case 0x03f8:
2754                 reg = 0xb4;
2755                 mask = 0x80;
2756                 break;
2757         case 0x02f8:
2758                 reg = 0xb4;
2759                 mask = 0x30;
2760                 break;
2761         case 0x02e8:
2762                 reg = 0xb4;
2763                 mask = 0x08;
2764                 break;
2765         default:
2766                 IRDA_ERROR("Failed to configure unsupported port on ALi 1533 bridge: 0x%04x\n", port);
2767                 return;
2768         }
2769
2770         pci_read_config_byte(dev, reg, &tmpbyte);
2771         /* Turn on the right bits */
2772         tmpbyte |= mask;
2773         pci_write_config_byte(dev, reg, tmpbyte);
2774         IRDA_MESSAGE("Activated ALi 1533 ISA bridge port 0x%04x.\n", port);
2775         return;
2776 }
2777
2778 static int __init preconfigure_through_ali(struct pci_dev *dev,
2779                                            struct
2780                                            smsc_ircc_subsystem_configuration
2781                                            *conf)
2782 {
2783         /* Configure the two ports on the ALi 1533 */
2784         preconfigure_ali_port(dev, conf->sir_io);
2785         preconfigure_ali_port(dev, conf->fir_io);
2786
2787         /* Pre-configure chip */
2788         return preconfigure_smsc_chip(conf);
2789 }
2790
2791 static int __init smsc_ircc_preconfigure_subsystems(unsigned short ircc_cfg,
2792                                                     unsigned short ircc_fir,
2793                                                     unsigned short ircc_sir,
2794                                                     unsigned char ircc_dma,
2795                                                     unsigned char ircc_irq)
2796 {
2797         struct pci_dev *dev = NULL;
2798         unsigned short ss_vendor = 0x0000;
2799         unsigned short ss_device = 0x0000;
2800         int ret = 0;
2801
2802         dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev);
2803
2804         while (dev != NULL) {
2805                 struct smsc_ircc_subsystem_configuration *conf;
2806
2807                 /*
2808                  * Cache the subsystem vendor/device:
2809                  * some manufacturers fail to set this for all components,
2810                  * so we save it in case there is just 0x0000 0x0000 on the
2811                  * device we want to check.
2812                  */
2813                 if (dev->subsystem_vendor != 0x0000U) {
2814                         ss_vendor = dev->subsystem_vendor;
2815                         ss_device = dev->subsystem_device;
2816                 }
2817                 conf = subsystem_configurations;
2818                 for( ; conf->subvendor; conf++) {
2819                         if(conf->vendor == dev->vendor &&
2820                            conf->device == dev->device &&
2821                            conf->subvendor == ss_vendor &&
2822                            /* Sometimes these are cached values */
2823                            (conf->subdevice == ss_device ||
2824                             conf->subdevice == 0xffff)) {
2825                                 struct smsc_ircc_subsystem_configuration
2826                                         tmpconf;
2827
2828                                 memcpy(&tmpconf, conf,
2829                                        sizeof(struct smsc_ircc_subsystem_configuration));
2830
2831                                 /*
2832                                  * Override the default values with anything
2833                                  * passed in as parameter
2834                                  */
2835                                 if (ircc_cfg != 0)
2836                                         tmpconf.cfg_base = ircc_cfg;
2837                                 if (ircc_fir != 0)
2838                                         tmpconf.fir_io = ircc_fir;
2839                                 if (ircc_sir != 0)
2840                                         tmpconf.sir_io = ircc_sir;
2841                                 if (ircc_dma != DMA_INVAL)
2842                                         tmpconf.fir_dma = ircc_dma;
2843                                 if (ircc_irq != IRQ_INVAL)
2844                                         tmpconf.fir_irq = ircc_irq;
2845
2846                                 IRDA_MESSAGE("Detected unconfigured %s SMSC IrDA chip, pre-configuring device.\n", conf->name);
2847                                 if (conf->preconfigure)
2848                                         ret = conf->preconfigure(dev, &tmpconf);
2849                                 else
2850                                         ret = -ENODEV;
2851                         }
2852                 }
2853                 dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev);
2854         }
2855
2856         return ret;
2857 }
2858 #endif // CONFIG_PCI
2859
2860 /************************************************
2861  *
2862  * Transceivers specific functions
2863  *
2864  ************************************************/
2865
2866
2867 /*
2868  * Function smsc_ircc_set_transceiver_smsc_ircc_atc(fir_base, speed)
2869  *
2870  *    Program transceiver through smsc-ircc ATC circuitry
2871  *
2872  */
2873
2874 static void smsc_ircc_set_transceiver_smsc_ircc_atc(int fir_base, u32 speed)
2875 {
2876         unsigned long jiffies_now, jiffies_timeout;
2877         u8 val;
2878
2879         jiffies_now = jiffies;
2880         jiffies_timeout = jiffies + SMSC_IRCC2_ATC_PROGRAMMING_TIMEOUT_JIFFIES;
2881
2882         /* ATC */
2883         register_bank(fir_base, 4);
2884         outb((inb(fir_base + IRCC_ATC) & IRCC_ATC_MASK) | IRCC_ATC_nPROGREADY|IRCC_ATC_ENABLE,
2885              fir_base + IRCC_ATC);
2886
2887         while ((val = (inb(fir_base + IRCC_ATC) & IRCC_ATC_nPROGREADY)) &&
2888                 !time_after(jiffies, jiffies_timeout))
2889                 /* empty */;
2890
2891         if (val)
2892                 IRDA_WARNING("%s(): ATC: 0x%02x\n", __FUNCTION__,
2893                              inb(fir_base + IRCC_ATC));
2894 }
2895
2896 /*
2897  * Function smsc_ircc_probe_transceiver_smsc_ircc_atc(fir_base)
2898  *
2899  *    Probe transceiver smsc-ircc ATC circuitry
2900  *
2901  */
2902
2903 static int smsc_ircc_probe_transceiver_smsc_ircc_atc(int fir_base)
2904 {
2905         return 0;
2906 }
2907
2908 /*
2909  * Function smsc_ircc_set_transceiver_smsc_ircc_fast_pin_select(self, speed)
2910  *
2911  *    Set transceiver
2912  *
2913  */
2914
2915 static void smsc_ircc_set_transceiver_smsc_ircc_fast_pin_select(int fir_base, u32 speed)
2916 {
2917         u8 fast_mode;
2918
2919         switch (speed) {
2920         default:
2921         case 576000 :
2922                 fast_mode = 0;
2923                 break;
2924         case 1152000 :
2925         case 4000000 :
2926                 fast_mode = IRCC_LCR_A_FAST;
2927                 break;
2928         }
2929         register_bank(fir_base, 0);
2930         outb((inb(fir_base + IRCC_LCR_A) & 0xbf) | fast_mode, fir_base + IRCC_LCR_A);
2931 }
2932
2933 /*
2934  * Function smsc_ircc_probe_transceiver_smsc_ircc_fast_pin_select(fir_base)
2935  *
2936  *    Probe transceiver
2937  *
2938  */
2939
2940 static int smsc_ircc_probe_transceiver_smsc_ircc_fast_pin_select(int fir_base)
2941 {
2942         return 0;
2943 }
2944
2945 /*
2946  * Function smsc_ircc_set_transceiver_toshiba_sat1800(fir_base, speed)
2947  *
2948  *    Set transceiver
2949  *
2950  */
2951
2952 static void smsc_ircc_set_transceiver_toshiba_sat1800(int fir_base, u32 speed)
2953 {
2954         u8 fast_mode;
2955
2956         switch (speed) {
2957         default:
2958         case 576000 :
2959                 fast_mode = 0;
2960                 break;
2961         case 1152000 :
2962         case 4000000 :
2963                 fast_mode = /*IRCC_LCR_A_FAST |*/ IRCC_LCR_A_GP_DATA;
2964                 break;
2965
2966         }
2967         /* This causes an interrupt */
2968         register_bank(fir_base, 0);
2969         outb((inb(fir_base + IRCC_LCR_A) &  0xbf) | fast_mode, fir_base + IRCC_LCR_A);
2970 }
2971
2972 /*
2973  * Function smsc_ircc_probe_transceiver_toshiba_sat1800(fir_base)
2974  *
2975  *    Probe transceiver
2976  *
2977  */
2978
2979 static int smsc_ircc_probe_transceiver_toshiba_sat1800(int fir_base)
2980 {
2981         return 0;
2982 }
2983
2984
2985 module_init(smsc_ircc_init);
2986 module_exit(smsc_ircc_cleanup);