git.oblomov.eu Git - linux-2.6/blob - arch/powerpc/boot/dts/gef_sbc610.dts

   1 /*
   2  * GE Fanuc SBC610 Device Tree Source
   3  *
   4  * Copyright 2008 GE Fanuc Intelligent Platforms Embedded Systems, Inc.
   5  *
   6  * This program is free software; you can redistribute  it and/or modify it
   7  * under  the terms of  the GNU General  Public License as published by the
   8  * Free Software Foundation;  either version 2 of the  License, or (at your
   9  * option) any later version.
  10  *
  11  * Based on: SBS CM6 Device Tree Source
  12  * Copyright 2007 SBS Technologies GmbH & Co. KG
  13  * And: mpc8641_hpcn.dts (MPC8641 HPCN Device Tree Source)
  14  * Copyright 2006 Freescale Semiconductor Inc.
  15  */
  16
  17 /*
  18  * Compiled with dtc -I dts -O dtb -o gef_sbc610.dtb gef_sbc610.dts
  19  */
  20
  21 /dts-v1/;
  22
  23 / {
  24         model = "GEF_SBC610";
  25         compatible = "gef,sbc610";
  26         #address-cells = <1>;
  27         #size-cells = <1>;
  28
  29         aliases {
  30                 ethernet0 = &enet0;
  31                 ethernet1 = &enet1;
  32                 serial0 = &serial0;
  33                 serial1 = &serial1;
  34                 pci0 = &pci0;
  35         };
  36
  37         cpus {
  38                 #address-cells = <1>;
  39                 #size-cells = <0>;
  40
  41                 PowerPC,8641@0 {
  42                         device_type = "cpu";
  43                         reg = <0>;
  44                         d-cache-line-size = <32>;       // 32 bytes
  45                         i-cache-line-size = <32>;       // 32 bytes
  46                         d-cache-size = <32768>;         // L1, 32K
  47                         i-cache-size = <32768>;         // L1, 32K
  48                         timebase-frequency = <0>;       // From uboot
  49                         bus-frequency = <0>;            // From uboot
  50                         clock-frequency = <0>;          // From uboot
  51                 };
  52                 PowerPC,8641@1 {
  53                         device_type = "cpu";
  54                         reg = <1>;
  55                         d-cache-line-size = <32>;       // 32 bytes
  56                         i-cache-line-size = <32>;       // 32 bytes
  57                         d-cache-size = <32768>;         // L1, 32K
  58                         i-cache-size = <32768>;         // L1, 32K
  59                         timebase-frequency = <0>;       // From uboot
  60                         bus-frequency = <0>;            // From uboot
  61                         clock-frequency = <0>;          // From uboot
  62                 };
  63         };
  64
  65         memory {
  66                 device_type = "memory";
  67                 reg = <0x0 0x40000000>; // set by uboot
  68         };
  69
  70         soc@fef00000 {
  71                 #address-cells = <1>;
  72                 #size-cells = <1>;
  73                 #interrupt-cells = <2>;
  74                 device_type = "soc";
  75                 compatible = "simple-bus";
  76                 ranges = <0x0 0xfef00000 0x00100000>;
  77                 reg = <0xfef00000 0x100000>;    // CCSRBAR 1M
  78                 bus-frequency = <0>;
  79
  80                 i2c1: i2c@3000 {
  81                         #address-cells = <1>;
  82                         #size-cells = <0>;
  83                         compatible = "fsl-i2c";
  84                         reg = <0x3000 0x100>;
  85                         interrupts = <0x2b 0x2>;
  86                         interrupt-parent = <&mpic>;
  87                         dfsrr;
  88
  89                         eti@6b {
  90                                 compatible = "dallas,ds1682";
  91                                 reg = <0x6b>;
  92                         };
  93                 };
  94
  95                 i2c2: i2c@3100 {
  96                         #address-cells = <1>;
  97                         #size-cells = <0>;
  98                         compatible = "fsl-i2c";
  99                         reg = <0x3100 0x100>;
 100                         interrupts = <0x2b 0x2>;
 101                         interrupt-parent = <&mpic>;
 102                         dfsrr;
 103                 };
 104
 105                 dma@21300 {
 106                         #address-cells = <1>;
 107                         #size-cells = <1>;
 108                         compatible = "fsl,mpc8641-dma", "fsl,eloplus-dma";
 109                         reg = <0x21300 0x4>;
 110                         ranges = <0x0 0x21100 0x200>;
 111                         cell-index = <0>;
 112                         dma-channel@0 {
 113                                 compatible = "fsl,mpc8641-dma-channel",
 114                                            "fsl,eloplus-dma-channel";
 115                                 reg = <0x0 0x80>;
 116                                 cell-index = <0>;
 117                                 interrupt-parent = <&mpic>;
 118                                 interrupts = <20 2>;
 119                         };
 120                         dma-channel@80 {
 121                                 compatible = "fsl,mpc8641-dma-channel",
 122                                            "fsl,eloplus-dma-channel";
 123                                 reg = <0x80 0x80>;
 124                                 cell-index = <1>;
 125                                 interrupt-parent = <&mpic>;
 126                                 interrupts = <21 2>;
 127                         };
 128                         dma-channel@100 {
 129                                 compatible = "fsl,mpc8641-dma-channel",
 130                                            "fsl,eloplus-dma-channel";
 131                                 reg = <0x100 0x80>;
 132                                 cell-index = <2>;
 133                                 interrupt-parent = <&mpic>;
 134                                 interrupts = <22 2>;
 135                         };
 136                         dma-channel@180 {
 137                                 compatible = "fsl,mpc8641-dma-channel",
 138                                            "fsl,eloplus-dma-channel";
 139                                 reg = <0x180 0x80>;
 140                                 cell-index = <3>;
 141                                 interrupt-parent = <&mpic>;
 142                                 interrupts = <23 2>;
 143                         };
 144                 };
 145
 146                 mdio@24520 {
 147                         #address-cells = <1>;
 148                         #size-cells = <0>;
 149                         compatible = "fsl,gianfar-mdio";
 150                         reg = <0x24520 0x20>;
 151
 152                         phy0: ethernet-phy@0 {
 153                                 interrupt-parent = <&mpic>;
 154                                 interrupts = <0x0 0x1>;
 155                                 reg = <1>;
 156                         };
 157                         phy2: ethernet-phy@2 {
 158                                 interrupt-parent = <&mpic>;
 159                                 interrupts = <0x0 0x1>;
 160                                 reg = <3>;
 161                         };
 162                 };
 163
 164                 enet0: ethernet@24000 {
 165                         device_type = "network";
 166                         model = "eTSEC";
 167                         compatible = "gianfar";
 168                         reg = <0x24000 0x1000>;
 169                         local-mac-address = [ 00 00 00 00 00 00 ];
 170                         interrupts = <0x1d 0x2 0x1e 0x2 0x22 0x2>;
 171                         interrupt-parent = <&mpic>;
 172                         phy-handle = <&phy0>;
 173                         phy-connection-type = "gmii";
 174                 };
 175
 176                 enet1: ethernet@26000 {
 177                         device_type = "network";
 178                         model = "eTSEC";
 179                         compatible = "gianfar";
 180                         reg = <0x26000 0x1000>;
 181                         local-mac-address = [ 00 00 00 00 00 00 ];
 182                         interrupts = <0x1f 0x2 0x20 0x2 0x21 0x2>;
 183                         interrupt-parent = <&mpic>;
 184                         phy-handle = <&phy2>;
 185                         phy-connection-type = "gmii";
 186                 };
 187
 188                 serial0: serial@4500 {
 189                         cell-index = <0>;
 190                         device_type = "serial";
 191                         compatible = "ns16550";
 192                         reg = <0x4500 0x100>;
 193                         clock-frequency = <0>;
 194                         interrupts = <0x2a 0x2>;
 195                         interrupt-parent = <&mpic>;
 196                 };
 197
 198                 serial1: serial@4600 {
 199                         cell-index = <1>;
 200                         device_type = "serial";
 201                         compatible = "ns16550";
 202                         reg = <0x4600 0x100>;
 203                         clock-frequency = <0>;
 204                         interrupts = <0x1c 0x2>;
 205                         interrupt-parent = <&mpic>;
 206                 };
 207
 208                 mpic: pic@40000 {
 209                         clock-frequency = <0>;
 210                         interrupt-controller;
 211                         #address-cells = <0>;
 212                         #interrupt-cells = <2>;
 213                         reg = <0x40000 0x40000>;
 214                         compatible = "chrp,open-pic";
 215                         device_type = "open-pic";
 216                 };
 217
 218                 global-utilities@e0000 {
 219                         compatible = "fsl,mpc8641-guts";
 220                         reg = <0xe0000 0x1000>;
 221                         fsl,has-rstcr;
 222                 };
 223         };
 224
 225         pci0: pcie@fef08000 {
 226                 compatible = "fsl,mpc8641-pcie";
 227                 device_type = "pci";
 228                 #interrupt-cells = <1>;
 229                 #size-cells = <2>;
 230                 #address-cells = <3>;
 231                 reg = <0xfef08000 0x1000>;
 232                 bus-range = <0x0 0xff>;
 233                 ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x40000000
 234                           0x01000000 0x0 0x00000000 0xfe000000 0x0 0x00400000>;
 235                 clock-frequency = <33333333>;
 236                 interrupt-parent = <&mpic>;
 237                 interrupts = <0x18 0x2>;
 238                 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
 239                 interrupt-map = <
 240                         0x0000 0x0 0x0 0x1 &mpic 0x0 0x1
 241                         0x0000 0x0 0x0 0x2 &mpic 0x1 0x1
 242                         0x0000 0x0 0x0 0x3 &mpic 0x2 0x1
 243                         0x0000 0x0 0x0 0x4 &mpic 0x3 0x1
 244                 >;
 245
 246                 pcie@0 {
 247                         reg = <0 0 0 0 0>;
 248                         #size-cells = <2>;
 249                         #address-cells = <3>;
 250                         device_type = "pci";
 251                         ranges = <0x02000000 0x0 0x80000000
 252                                   0x02000000 0x0 0x80000000
 253                                   0x0 0x40000000
 254
 255                                   0x01000000 0x0 0x00000000
 256                                   0x01000000 0x0 0x00000000
 257                                   0x0 0x00400000>;
 258                 };
 259         };
 260 };