git.oblomov.eu Git - linux-2.6/blob - drivers/net/ucc_geth.c

   1 /*
   2  * Copyright (C) Freescale Semicondutor, Inc. 2006. All rights reserved.
   3  *
   4  * Author: Shlomi Gridish <gridish@freescale.com>
   5  *         Li Yang <leoli@freescale.com>
   6  *
   7  * Description:
   8  * QE UCC Gigabit Ethernet Driver
   9  *
  10  * This program is free software; you can redistribute  it and/or modify it
  11  * under  the terms of  the GNU General  Public License as published by the
  12  * Free Software Foundation;  either version 2 of the  License, or (at your
  13  * option) any later version.
  14  */
  15 #include <linux/kernel.h>
  16 #include <linux/init.h>
  17 #include <linux/errno.h>
  18 #include <linux/slab.h>
  19 #include <linux/stddef.h>
  20 #include <linux/interrupt.h>
  21 #include <linux/netdevice.h>
  22 #include <linux/etherdevice.h>
  23 #include <linux/skbuff.h>
  24 #include <linux/spinlock.h>
  25 #include <linux/mm.h>
  26 #include <linux/ethtool.h>
  27 #include <linux/delay.h>
  28 #include <linux/dma-mapping.h>
  29 #include <linux/fsl_devices.h>
  30 #include <linux/ethtool.h>
  31 #include <linux/mii.h>
  32
  33 #include <asm/of_platform.h>
  34 #include <asm/uaccess.h>
  35 #include <asm/irq.h>
  36 #include <asm/io.h>
  37 #include <asm/immap_qe.h>
  38 #include <asm/qe.h>
  39 #include <asm/ucc.h>
  40 #include <asm/ucc_fast.h>
  41
  42 #include "ucc_geth.h"
  43 #include "ucc_geth_phy.h"
  44
  45 #undef DEBUG
  46
  47 #define DRV_DESC "QE UCC Gigabit Ethernet Controller version:Sept 11, 2006"
  48 #define DRV_NAME "ucc_geth"
  49
  50 #define ugeth_printk(level, format, arg...)  \
  51         printk(level format "\n", ## arg)
  52
  53 #define ugeth_dbg(format, arg...)            \
  54         ugeth_printk(KERN_DEBUG , format , ## arg)
  55 #define ugeth_err(format, arg...)            \
  56         ugeth_printk(KERN_ERR , format , ## arg)
  57 #define ugeth_info(format, arg...)           \
  58         ugeth_printk(KERN_INFO , format , ## arg)
  59 #define ugeth_warn(format, arg...)           \
  60         ugeth_printk(KERN_WARNING , format , ## arg)
  61
  62 #ifdef UGETH_VERBOSE_DEBUG
  63 #define ugeth_vdbg ugeth_dbg
  64 #else
  65 #define ugeth_vdbg(fmt, args...) do { } while (0)
  66 #endif                          /* UGETH_VERBOSE_DEBUG */
  67
  68 static DEFINE_SPINLOCK(ugeth_lock);
  69
  70 static struct ucc_geth_info ugeth_primary_info = {
  71         .uf_info = {
  72                     .bd_mem_part = MEM_PART_SYSTEM,
  73                     .rtsm = UCC_FAST_SEND_IDLES_BETWEEN_FRAMES,
  74                     .max_rx_buf_length = 1536,
  75 /* FIXME: should be changed in run time for 1G and 100M */
  76 #ifdef CONFIG_UGETH_HAS_GIGA
  77                     .urfs = UCC_GETH_URFS_GIGA_INIT,
  78                     .urfet = UCC_GETH_URFET_GIGA_INIT,
  79                     .urfset = UCC_GETH_URFSET_GIGA_INIT,
  80                     .utfs = UCC_GETH_UTFS_GIGA_INIT,
  81                     .utfet = UCC_GETH_UTFET_GIGA_INIT,
  82                     .utftt = UCC_GETH_UTFTT_GIGA_INIT,
  83 #else
  84                     .urfs = UCC_GETH_URFS_INIT,
  85                     .urfet = UCC_GETH_URFET_INIT,
  86                     .urfset = UCC_GETH_URFSET_INIT,
  87                     .utfs = UCC_GETH_UTFS_INIT,
  88                     .utfet = UCC_GETH_UTFET_INIT,
  89                     .utftt = UCC_GETH_UTFTT_INIT,
  90 #endif
  91                     .ufpt = 256,
  92                     .mode = UCC_FAST_PROTOCOL_MODE_ETHERNET,
  93                     .ttx_trx = UCC_FAST_GUMR_TRANSPARENT_TTX_TRX_NORMAL,
  94                     .tenc = UCC_FAST_TX_ENCODING_NRZ,
  95                     .renc = UCC_FAST_RX_ENCODING_NRZ,
  96                     .tcrc = UCC_FAST_16_BIT_CRC,
  97                     .synl = UCC_FAST_SYNC_LEN_NOT_USED,
  98                     },
  99         .numQueuesTx = 1,
 100         .numQueuesRx = 1,
 101         .extendedFilteringChainPointer = ((uint32_t) NULL),
 102         .typeorlen = 3072 /*1536 */ ,
 103         .nonBackToBackIfgPart1 = 0x40,
 104         .nonBackToBackIfgPart2 = 0x60,
 105         .miminumInterFrameGapEnforcement = 0x50,
 106         .backToBackInterFrameGap = 0x60,
 107         .mblinterval = 128,
 108         .nortsrbytetime = 5,
 109         .fracsiz = 1,
 110         .strictpriorityq = 0xff,
 111         .altBebTruncation = 0xa,
 112         .excessDefer = 1,
 113         .maxRetransmission = 0xf,
 114         .collisionWindow = 0x37,
 115         .receiveFlowControl = 1,
 116         .maxGroupAddrInHash = 4,
 117         .maxIndAddrInHash = 4,
 118         .prel = 7,
 119         .maxFrameLength = 1518,
 120         .minFrameLength = 64,
 121         .maxD1Length = 1520,
 122         .maxD2Length = 1520,
 123         .vlantype = 0x8100,
 124         .ecamptr = ((uint32_t) NULL),
 125         .eventRegMask = UCCE_OTHER,
 126         .pausePeriod = 0xf000,
 127         .interruptcoalescingmaxvalue = {1, 1, 1, 1, 1, 1, 1, 1},
 128         .bdRingLenTx = {
 129                         TX_BD_RING_LEN,
 130                         TX_BD_RING_LEN,
 131                         TX_BD_RING_LEN,
 132                         TX_BD_RING_LEN,
 133                         TX_BD_RING_LEN,
 134                         TX_BD_RING_LEN,
 135                         TX_BD_RING_LEN,
 136                         TX_BD_RING_LEN},
 137
 138         .bdRingLenRx = {
 139                         RX_BD_RING_LEN,
 140                         RX_BD_RING_LEN,
 141                         RX_BD_RING_LEN,
 142                         RX_BD_RING_LEN,
 143                         RX_BD_RING_LEN,
 144                         RX_BD_RING_LEN,
 145                         RX_BD_RING_LEN,
 146                         RX_BD_RING_LEN},
 147
 148         .numStationAddresses = UCC_GETH_NUM_OF_STATION_ADDRESSES_1,
 149         .largestexternallookupkeysize =
 150             QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_NONE,
 151         .statisticsMode = UCC_GETH_STATISTICS_GATHERING_MODE_NONE,
 152         .vlanOperationTagged = UCC_GETH_VLAN_OPERATION_TAGGED_NOP,
 153         .vlanOperationNonTagged = UCC_GETH_VLAN_OPERATION_NON_TAGGED_NOP,
 154         .rxQoSMode = UCC_GETH_QOS_MODE_DEFAULT,
 155         .aufc = UPSMR_AUTOMATIC_FLOW_CONTROL_MODE_NONE,
 156         .padAndCrc = MACCFG2_PAD_AND_CRC_MODE_PAD_AND_CRC,
 157         .numThreadsTx = UCC_GETH_NUM_OF_THREADS_4,
 158         .numThreadsRx = UCC_GETH_NUM_OF_THREADS_4,
 159         .riscTx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
 160         .riscRx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
 161 };
 162
 163 static struct ucc_geth_info ugeth_info[8];
 164
 165 #ifdef DEBUG
 166 static void mem_disp(u8 *addr, int size)
 167 {
 168         u8 *i;
 169         int size16Aling = (size >> 4) << 4;
 170         int size4Aling = (size >> 2) << 2;
 171         int notAlign = 0;
 172         if (size % 16)
 173                 notAlign = 1;
 174
 175         for (i = addr; (u32) i < (u32) addr + size16Aling; i += 16)
 176                 printk("0x%08x: %08x %08x %08x %08x\r\n",
 177                        (u32) i,
 178                        *((u32 *) (i)),
 179                        *((u32 *) (i + 4)),
 180                        *((u32 *) (i + 8)), *((u32 *) (i + 12)));
 181         if (notAlign == 1)
 182                 printk("0x%08x: ", (u32) i);
 183         for (; (u32) i < (u32) addr + size4Aling; i += 4)
 184                 printk("%08x ", *((u32 *) (i)));
 185         for (; (u32) i < (u32) addr + size; i++)
 186                 printk("%02x", *((u8 *) (i)));
 187         if (notAlign == 1)
 188                 printk("\r\n");
 189 }
 190 #endif /* DEBUG */
 191
 192 #ifdef CONFIG_UGETH_FILTERING
 193 static void enqueue(struct list_head *node, struct list_head *lh)
 194 {
 195         unsigned long flags;
 196
 197         spin_lock_irqsave(&ugeth_lock, flags);
 198         list_add_tail(node, lh);
 199         spin_unlock_irqrestore(&ugeth_lock, flags);
 200 }
 201 #endif /* CONFIG_UGETH_FILTERING */
 202
 203 static struct list_head *dequeue(struct list_head *lh)
 204 {
 205         unsigned long flags;
 206
 207         spin_lock_irqsave(&ugeth_lock, flags);
 208         if (!list_empty(lh)) {
 209                 struct list_head *node = lh->next;
 210                 list_del(node);
 211                 spin_unlock_irqrestore(&ugeth_lock, flags);
 212                 return node;
 213         } else {
 214                 spin_unlock_irqrestore(&ugeth_lock, flags);
 215                 return NULL;
 216         }
 217 }
 218
 219 static int get_interface_details(enum enet_interface enet_interface,
 220                                  enum enet_speed *speed,
 221                                  int *r10m,
 222                                  int *rmm,
 223                                  int *rpm,
 224                                  int *tbi, int *limited_to_full_duplex)
 225 {
 226         /* Analyze enet_interface according to Interface Mode
 227         Configuration table */
 228         switch (enet_interface) {
 229         case ENET_10_MII:
 230                 *speed = ENET_SPEED_10BT;
 231                 break;
 232         case ENET_10_RMII:
 233                 *speed = ENET_SPEED_10BT;
 234                 *r10m = 1;
 235                 *rmm = 1;
 236                 break;
 237         case ENET_10_RGMII:
 238                 *speed = ENET_SPEED_10BT;
 239                 *rpm = 1;
 240                 *r10m = 1;
 241                 *limited_to_full_duplex = 1;
 242                 break;
 243         case ENET_100_MII:
 244                 *speed = ENET_SPEED_100BT;
 245                 break;
 246         case ENET_100_RMII:
 247                 *speed = ENET_SPEED_100BT;
 248                 *rmm = 1;
 249                 break;
 250         case ENET_100_RGMII:
 251                 *speed = ENET_SPEED_100BT;
 252                 *rpm = 1;
 253                 *limited_to_full_duplex = 1;
 254                 break;
 255         case ENET_1000_GMII:
 256                 *speed = ENET_SPEED_1000BT;
 257                 *limited_to_full_duplex = 1;
 258                 break;
 259         case ENET_1000_RGMII:
 260                 *speed = ENET_SPEED_1000BT;
 261                 *rpm = 1;
 262                 *limited_to_full_duplex = 1;
 263                 break;
 264         case ENET_1000_TBI:
 265                 *speed = ENET_SPEED_1000BT;
 266                 *tbi = 1;
 267                 *limited_to_full_duplex = 1;
 268                 break;
 269         case ENET_1000_RTBI:
 270                 *speed = ENET_SPEED_1000BT;
 271                 *rpm = 1;
 272                 *tbi = 1;
 273                 *limited_to_full_duplex = 1;
 274                 break;
 275         default:
 276                 return -EINVAL;
 277                 break;
 278         }
 279
 280         return 0;
 281 }
 282
 283 static struct sk_buff *get_new_skb(struct ucc_geth_private *ugeth, u8 *bd)
 284 {
 285         struct sk_buff *skb = NULL;
 286
 287         skb = dev_alloc_skb(ugeth->ug_info->uf_info.max_rx_buf_length +
 288                                   UCC_GETH_RX_DATA_BUF_ALIGNMENT);
 289
 290         if (skb == NULL)
 291                 return NULL;
 292
 293         /* We need the data buffer to be aligned properly.  We will reserve
 294          * as many bytes as needed to align the data properly
 295          */
 296         skb_reserve(skb,
 297                     UCC_GETH_RX_DATA_BUF_ALIGNMENT -
 298                     (((unsigned)skb->data) & (UCC_GETH_RX_DATA_BUF_ALIGNMENT -
 299                                               1)));
 300
 301         skb->dev = ugeth->dev;
 302
 303         out_be32(&((struct qe_bd *)bd)->buf,
 304                       dma_map_single(NULL,
 305                                      skb->data,
 306                                      ugeth->ug_info->uf_info.max_rx_buf_length +
 307                                      UCC_GETH_RX_DATA_BUF_ALIGNMENT,
 308                                      DMA_FROM_DEVICE));
 309
 310         out_be32((u32 *)bd, (R_E | R_I | (in_be32((u32 *)bd) & R_W)));
 311
 312         return skb;
 313 }
 314
 315 static int rx_bd_buffer_set(struct ucc_geth_private *ugeth, u8 rxQ)
 316 {
 317         u8 *bd;
 318         u32 bd_status;
 319         struct sk_buff *skb;
 320         int i;
 321
 322         bd = ugeth->p_rx_bd_ring[rxQ];
 323         i = 0;
 324
 325         do {
 326                 bd_status = in_be32((u32*)bd);
 327                 skb = get_new_skb(ugeth, bd);
 328
 329                 if (!skb)       /* If can not allocate data buffer,
 330                                 abort. Cleanup will be elsewhere */
 331                         return -ENOMEM;
 332
 333                 ugeth->rx_skbuff[rxQ][i] = skb;
 334
 335                 /* advance the BD pointer */
 336                 bd += sizeof(struct qe_bd);
 337                 i++;
 338         } while (!(bd_status & R_W));
 339
 340         return 0;
 341 }
 342
 343 static int fill_init_enet_entries(struct ucc_geth_private *ugeth,
 344                                   volatile u32 *p_start,
 345                                   u8 num_entries,
 346                                   u32 thread_size,
 347                                   u32 thread_alignment,
 348                                   enum qe_risc_allocation risc,
 349                                   int skip_page_for_first_entry)
 350 {
 351         u32 init_enet_offset;
 352         u8 i;
 353         int snum;
 354
 355         for (i = 0; i < num_entries; i++) {
 356                 if ((snum = qe_get_snum()) < 0) {
 357                         ugeth_err("fill_init_enet_entries: Can not get SNUM.");
 358                         return snum;
 359                 }
 360                 if ((i == 0) && skip_page_for_first_entry)
 361                 /* First entry of Rx does not have page */
 362                         init_enet_offset = 0;
 363                 else {
 364                         init_enet_offset =
 365                             qe_muram_alloc(thread_size, thread_alignment);
 366                         if (IS_MURAM_ERR(init_enet_offset)) {
 367                                 ugeth_err
 368                 ("fill_init_enet_entries: Can not allocate DPRAM memory.");
 369                                 qe_put_snum((u8) snum);
 370                                 return -ENOMEM;
 371                         }
 372                 }
 373                 *(p_start++) =
 374                     ((u8) snum << ENET_INIT_PARAM_SNUM_SHIFT) | init_enet_offset
 375                     | risc;
 376         }
 377
 378         return 0;
 379 }
 380
 381 static int return_init_enet_entries(struct ucc_geth_private *ugeth,
 382                                     volatile u32 *p_start,
 383                                     u8 num_entries,
 384                                     enum qe_risc_allocation risc,
 385                                     int skip_page_for_first_entry)
 386 {
 387         u32 init_enet_offset;
 388         u8 i;
 389         int snum;
 390
 391         for (i = 0; i < num_entries; i++) {
 392                 /* Check that this entry was actually valid --
 393                 needed in case failed in allocations */
 394                 if ((*p_start & ENET_INIT_PARAM_RISC_MASK) == risc) {
 395                         snum =
 396                             (u32) (*p_start & ENET_INIT_PARAM_SNUM_MASK) >>
 397                             ENET_INIT_PARAM_SNUM_SHIFT;
 398                         qe_put_snum((u8) snum);
 399                         if (!((i == 0) && skip_page_for_first_entry)) {
 400                         /* First entry of Rx does not have page */
 401                                 init_enet_offset =
 402                                     (in_be32(p_start) &
 403                                      ENET_INIT_PARAM_PTR_MASK);
 404                                 qe_muram_free(init_enet_offset);
 405                         }
 406                         *(p_start++) = 0;       /* Just for cosmetics */
 407                 }
 408         }
 409
 410         return 0;
 411 }
 412
 413 #ifdef DEBUG
 414 static int dump_init_enet_entries(struct ucc_geth_private *ugeth,
 415                                   volatile u32 *p_start,
 416                                   u8 num_entries,
 417                                   u32 thread_size,
 418                                   enum qe_risc_allocation risc,
 419                                   int skip_page_for_first_entry)
 420 {
 421         u32 init_enet_offset;
 422         u8 i;
 423         int snum;
 424
 425         for (i = 0; i < num_entries; i++) {
 426                 /* Check that this entry was actually valid --
 427                 needed in case failed in allocations */
 428                 if ((*p_start & ENET_INIT_PARAM_RISC_MASK) == risc) {
 429                         snum =
 430                             (u32) (*p_start & ENET_INIT_PARAM_SNUM_MASK) >>
 431                             ENET_INIT_PARAM_SNUM_SHIFT;
 432                         qe_put_snum((u8) snum);
 433                         if (!((i == 0) && skip_page_for_first_entry)) {
 434                         /* First entry of Rx does not have page */
 435                                 init_enet_offset =
 436                                     (in_be32(p_start) &
 437                                      ENET_INIT_PARAM_PTR_MASK);
 438                                 ugeth_info("Init enet entry %d:", i);
 439                                 ugeth_info("Base address: 0x%08x",
 440                                            (u32)
 441                                            qe_muram_addr(init_enet_offset));
 442                                 mem_disp(qe_muram_addr(init_enet_offset),
 443                                          thread_size);
 444                         }
 445                         p_start++;
 446                 }
 447         }
 448
 449         return 0;
 450 }
 451 #endif
 452
 453 #ifdef CONFIG_UGETH_FILTERING
 454 static struct enet_addr_container *get_enet_addr_container(void)
 455 {
 456         struct enet_addr_container *enet_addr_cont;
 457
 458         /* allocate memory */
 459         enet_addr_cont = kmalloc(sizeof(struct enet_addr_container), GFP_KERNEL);
 460         if (!enet_addr_cont) {
 461                 ugeth_err("%s: No memory for enet_addr_container object.",
 462                           __FUNCTION__);
 463                 return NULL;
 464         }
 465
 466         return enet_addr_cont;
 467 }
 468 #endif /* CONFIG_UGETH_FILTERING */
 469
 470 static void put_enet_addr_container(struct enet_addr_container *enet_addr_cont)
 471 {
 472         kfree(enet_addr_cont);
 473 }
 474
 475 static int set_mac_addr(__be16 __iomem *reg, u8 *mac)
 476 {
 477         out_be16(&reg[0], ((u16)mac[5] << 8) | mac[4]);
 478         out_be16(&reg[1], ((u16)mac[3] << 8) | mac[2]);
 479         out_be16(&reg[2], ((u16)mac[1] << 8) | mac[0]);
 480 }
 481
 482 #ifdef CONFIG_UGETH_FILTERING
 483 static int hw_add_addr_in_paddr(struct ucc_geth_private *ugeth,
 484                                 u8 *p_enet_addr, u8 paddr_num)
 485 {
 486         struct ucc_geth_82xx_address_filtering_pram *p_82xx_addr_filt;
 487
 488         if (!(paddr_num < NUM_OF_PADDRS)) {
 489                 ugeth_warn("%s: Illegal paddr_num.", __FUNCTION__);
 490                 return -EINVAL;
 491         }
 492
 493         p_82xx_addr_filt =
 494             (struct ucc_geth_82xx_address_filtering_pram *) ugeth->p_rx_glbl_pram->
 495             addressfiltering;
 496
 497         /* Ethernet frames are defined in Little Endian mode,    */
 498         /* therefore to insert the address we reverse the bytes. */
 499         set_mac_addr(&p_82xx_addr_filt->paddr[paddr_num].h, p_enet_addr);
 500         return 0;
 501 }
 502 #endif /* CONFIG_UGETH_FILTERING */
 503
 504 static int hw_clear_addr_in_paddr(struct ucc_geth_private *ugeth, u8 paddr_num)
 505 {
 506         struct ucc_geth_82xx_address_filtering_pram *p_82xx_addr_filt;
 507
 508         if (!(paddr_num < NUM_OF_PADDRS)) {
 509                 ugeth_warn("%s: Illagel paddr_num.", __FUNCTION__);
 510                 return -EINVAL;
 511         }
 512
 513         p_82xx_addr_filt =
 514             (struct ucc_geth_82xx_address_filtering_pram *) ugeth->p_rx_glbl_pram->
 515             addressfiltering;
 516
 517         /* Writing address ff.ff.ff.ff.ff.ff disables address
 518         recognition for this register */
 519         out_be16(&p_82xx_addr_filt->paddr[paddr_num].h, 0xffff);
 520         out_be16(&p_82xx_addr_filt->paddr[paddr_num].m, 0xffff);
 521         out_be16(&p_82xx_addr_filt->paddr[paddr_num].l, 0xffff);
 522
 523         return 0;
 524 }
 525
 526 static void hw_add_addr_in_hash(struct ucc_geth_private *ugeth,
 527                                 u8 *p_enet_addr)
 528 {
 529         struct ucc_geth_82xx_address_filtering_pram *p_82xx_addr_filt;
 530         u32 cecr_subblock;
 531
 532         p_82xx_addr_filt =
 533             (struct ucc_geth_82xx_address_filtering_pram *) ugeth->p_rx_glbl_pram->
 534             addressfiltering;
 535
 536         cecr_subblock =
 537             ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.ucc_num);
 538
 539         /* Ethernet frames are defined in Little Endian mode,
 540         therefor to insert */
 541         /* the address to the hash (Big Endian mode), we reverse the bytes.*/
 542
 543         set_mac_addr(&p_82xx_addr_filt->taddr.h, p_enet_addr);
 544
 545         qe_issue_cmd(QE_SET_GROUP_ADDRESS, cecr_subblock,
 546                      QE_CR_PROTOCOL_ETHERNET, 0);
 547 }
 548
 549 #ifdef CONFIG_UGETH_MAGIC_PACKET
 550 static void magic_packet_detection_enable(struct ucc_geth_private *ugeth)
 551 {
 552         struct ucc_fast_private *uccf;
 553         struct ucc_geth *ug_regs;
 554         u32 maccfg2, uccm;
 555
 556         uccf = ugeth->uccf;
 557         ug_regs = ugeth->ug_regs;
 558
 559         /* Enable interrupts for magic packet detection */
 560         uccm = in_be32(uccf->p_uccm);
 561         uccm |= UCCE_MPD;
 562         out_be32(uccf->p_uccm, uccm);
 563
 564         /* Enable magic packet detection */
 565         maccfg2 = in_be32(&ug_regs->maccfg2);
 566         maccfg2 |= MACCFG2_MPE;
 567         out_be32(&ug_regs->maccfg2, maccfg2);
 568 }
 569
 570 static void magic_packet_detection_disable(struct ucc_geth_private *ugeth)
 571 {
 572         struct ucc_fast_private *uccf;
 573         struct ucc_geth *ug_regs;
 574         u32 maccfg2, uccm;
 575
 576         uccf = ugeth->uccf;
 577         ug_regs = ugeth->ug_regs;
 578
 579         /* Disable interrupts for magic packet detection */
 580         uccm = in_be32(uccf->p_uccm);
 581         uccm &= ~UCCE_MPD;
 582         out_be32(uccf->p_uccm, uccm);
 583
 584         /* Disable magic packet detection */
 585         maccfg2 = in_be32(&ug_regs->maccfg2);
 586         maccfg2 &= ~MACCFG2_MPE;
 587         out_be32(&ug_regs->maccfg2, maccfg2);
 588 }
 589 #endif /* MAGIC_PACKET */
 590
 591 static inline int compare_addr(u8 **addr1, u8 **addr2)
 592 {
 593         return memcmp(addr1, addr2, ENET_NUM_OCTETS_PER_ADDRESS);
 594 }
 595
 596 #ifdef DEBUG
 597 static void get_statistics(struct ucc_geth_private *ugeth,
 598                            struct ucc_geth_tx_firmware_statistics *
 599                            tx_firmware_statistics,
 600                            struct ucc_geth_rx_firmware_statistics *
 601                            rx_firmware_statistics,
 602                            struct ucc_geth_hardware_statistics *hardware_statistics)
 603 {
 604         struct ucc_fast *uf_regs;
 605         struct ucc_geth *ug_regs;
 606         struct ucc_geth_tx_firmware_statistics_pram *p_tx_fw_statistics_pram;
 607         struct ucc_geth_rx_firmware_statistics_pram *p_rx_fw_statistics_pram;
 608
 609         ug_regs = ugeth->ug_regs;
 610         uf_regs = (struct ucc_fast *) ug_regs;
 611         p_tx_fw_statistics_pram = ugeth->p_tx_fw_statistics_pram;
 612         p_rx_fw_statistics_pram = ugeth->p_rx_fw_statistics_pram;
 613
 614         /* Tx firmware only if user handed pointer and driver actually
 615         gathers Tx firmware statistics */
 616         if (tx_firmware_statistics && p_tx_fw_statistics_pram) {
 617                 tx_firmware_statistics->sicoltx =
 618                     in_be32(&p_tx_fw_statistics_pram->sicoltx);
 619                 tx_firmware_statistics->mulcoltx =
 620                     in_be32(&p_tx_fw_statistics_pram->mulcoltx);
 621                 tx_firmware_statistics->latecoltxfr =
 622                     in_be32(&p_tx_fw_statistics_pram->latecoltxfr);
 623                 tx_firmware_statistics->frabortduecol =
 624                     in_be32(&p_tx_fw_statistics_pram->frabortduecol);
 625                 tx_firmware_statistics->frlostinmactxer =
 626                     in_be32(&p_tx_fw_statistics_pram->frlostinmactxer);
 627                 tx_firmware_statistics->carriersenseertx =
 628                     in_be32(&p_tx_fw_statistics_pram->carriersenseertx);
 629                 tx_firmware_statistics->frtxok =
 630                     in_be32(&p_tx_fw_statistics_pram->frtxok);
 631                 tx_firmware_statistics->txfrexcessivedefer =
 632                     in_be32(&p_tx_fw_statistics_pram->txfrexcessivedefer);
 633                 tx_firmware_statistics->txpkts256 =
 634                     in_be32(&p_tx_fw_statistics_pram->txpkts256);
 635                 tx_firmware_statistics->txpkts512 =
 636                     in_be32(&p_tx_fw_statistics_pram->txpkts512);
 637                 tx_firmware_statistics->txpkts1024 =
 638                     in_be32(&p_tx_fw_statistics_pram->txpkts1024);
 639                 tx_firmware_statistics->txpktsjumbo =
 640                     in_be32(&p_tx_fw_statistics_pram->txpktsjumbo);
 641         }
 642
 643         /* Rx firmware only if user handed pointer and driver actually
 644          * gathers Rx firmware statistics */
 645         if (rx_firmware_statistics && p_rx_fw_statistics_pram) {
 646                 int i;
 647                 rx_firmware_statistics->frrxfcser =
 648                     in_be32(&p_rx_fw_statistics_pram->frrxfcser);
 649                 rx_firmware_statistics->fraligner =
 650                     in_be32(&p_rx_fw_statistics_pram->fraligner);
 651                 rx_firmware_statistics->inrangelenrxer =
 652                     in_be32(&p_rx_fw_statistics_pram->inrangelenrxer);
 653                 rx_firmware_statistics->outrangelenrxer =
 654                     in_be32(&p_rx_fw_statistics_pram->outrangelenrxer);
 655                 rx_firmware_statistics->frtoolong =
 656                     in_be32(&p_rx_fw_statistics_pram->frtoolong);
 657                 rx_firmware_statistics->runt =
 658                     in_be32(&p_rx_fw_statistics_pram->runt);
 659                 rx_firmware_statistics->verylongevent =
 660                     in_be32(&p_rx_fw_statistics_pram->verylongevent);
 661                 rx_firmware_statistics->symbolerror =
 662                     in_be32(&p_rx_fw_statistics_pram->symbolerror);
 663                 rx_firmware_statistics->dropbsy =
 664                     in_be32(&p_rx_fw_statistics_pram->dropbsy);
 665                 for (i = 0; i < 0x8; i++)
 666                         rx_firmware_statistics->res0[i] =
 667                             p_rx_fw_statistics_pram->res0[i];
 668                 rx_firmware_statistics->mismatchdrop =
 669                     in_be32(&p_rx_fw_statistics_pram->mismatchdrop);
 670                 rx_firmware_statistics->underpkts =
 671                     in_be32(&p_rx_fw_statistics_pram->underpkts);
 672                 rx_firmware_statistics->pkts256 =
 673                     in_be32(&p_rx_fw_statistics_pram->pkts256);
 674                 rx_firmware_statistics->pkts512 =
 675                     in_be32(&p_rx_fw_statistics_pram->pkts512);
 676                 rx_firmware_statistics->pkts1024 =
 677                     in_be32(&p_rx_fw_statistics_pram->pkts1024);
 678                 rx_firmware_statistics->pktsjumbo =
 679                     in_be32(&p_rx_fw_statistics_pram->pktsjumbo);
 680                 rx_firmware_statistics->frlossinmacer =
 681                     in_be32(&p_rx_fw_statistics_pram->frlossinmacer);
 682                 rx_firmware_statistics->pausefr =
 683                     in_be32(&p_rx_fw_statistics_pram->pausefr);
 684                 for (i = 0; i < 0x4; i++)
 685                         rx_firmware_statistics->res1[i] =
 686                             p_rx_fw_statistics_pram->res1[i];
 687                 rx_firmware_statistics->removevlan =
 688                     in_be32(&p_rx_fw_statistics_pram->removevlan);
 689                 rx_firmware_statistics->replacevlan =
 690                     in_be32(&p_rx_fw_statistics_pram->replacevlan);
 691                 rx_firmware_statistics->insertvlan =
 692                     in_be32(&p_rx_fw_statistics_pram->insertvlan);
 693         }
 694
 695         /* Hardware only if user handed pointer and driver actually
 696         gathers hardware statistics */
 697         if (hardware_statistics && (in_be32(&uf_regs->upsmr) & UPSMR_HSE)) {
 698                 hardware_statistics->tx64 = in_be32(&ug_regs->tx64);
 699                 hardware_statistics->tx127 = in_be32(&ug_regs->tx127);
 700                 hardware_statistics->tx255 = in_be32(&ug_regs->tx255);
 701                 hardware_statistics->rx64 = in_be32(&ug_regs->rx64);
 702                 hardware_statistics->rx127 = in_be32(&ug_regs->rx127);
 703                 hardware_statistics->rx255 = in_be32(&ug_regs->rx255);
 704                 hardware_statistics->txok = in_be32(&ug_regs->txok);
 705                 hardware_statistics->txcf = in_be16(&ug_regs->txcf);
 706                 hardware_statistics->tmca = in_be32(&ug_regs->tmca);
 707                 hardware_statistics->tbca = in_be32(&ug_regs->tbca);
 708                 hardware_statistics->rxfok = in_be32(&ug_regs->rxfok);
 709                 hardware_statistics->rxbok = in_be32(&ug_regs->rxbok);
 710                 hardware_statistics->rbyt = in_be32(&ug_regs->rbyt);
 711                 hardware_statistics->rmca = in_be32(&ug_regs->rmca);
 712                 hardware_statistics->rbca = in_be32(&ug_regs->rbca);
 713         }
 714 }
 715
 716 static void dump_bds(struct ucc_geth_private *ugeth)
 717 {
 718         int i;
 719         int length;
 720
 721         for (i = 0; i < ugeth->ug_info->numQueuesTx; i++) {
 722                 if (ugeth->p_tx_bd_ring[i]) {
 723                         length =
 724                             (ugeth->ug_info->bdRingLenTx[i] *
 725                              sizeof(struct qe_bd));
 726                         ugeth_info("TX BDs[%d]", i);
 727                         mem_disp(ugeth->p_tx_bd_ring[i], length);
 728                 }
 729         }
 730         for (i = 0; i < ugeth->ug_info->numQueuesRx; i++) {
 731                 if (ugeth->p_rx_bd_ring[i]) {
 732                         length =
 733                             (ugeth->ug_info->bdRingLenRx[i] *
 734                              sizeof(struct qe_bd));
 735                         ugeth_info("RX BDs[%d]", i);
 736                         mem_disp(ugeth->p_rx_bd_ring[i], length);
 737                 }
 738         }
 739 }
 740
 741 static void dump_regs(struct ucc_geth_private *ugeth)
 742 {
 743         int i;
 744
 745         ugeth_info("UCC%d Geth registers:", ugeth->ug_info->uf_info.ucc_num);
 746         ugeth_info("Base address: 0x%08x", (u32) ugeth->ug_regs);
 747
 748         ugeth_info("maccfg1    : addr - 0x%08x, val - 0x%08x",
 749                    (u32) & ugeth->ug_regs->maccfg1,
 750                    in_be32(&ugeth->ug_regs->maccfg1));
 751         ugeth_info("maccfg2    : addr - 0x%08x, val - 0x%08x",
 752                    (u32) & ugeth->ug_regs->maccfg2,
 753                    in_be32(&ugeth->ug_regs->maccfg2));
 754         ugeth_info("ipgifg     : addr - 0x%08x, val - 0x%08x",
 755                    (u32) & ugeth->ug_regs->ipgifg,
 756                    in_be32(&ugeth->ug_regs->ipgifg));
 757         ugeth_info("hafdup     : addr - 0x%08x, val - 0x%08x",
 758                    (u32) & ugeth->ug_regs->hafdup,
 759                    in_be32(&ugeth->ug_regs->hafdup));
 760         ugeth_info("miimcfg    : addr - 0x%08x, val - 0x%08x",
 761                    (u32) & ugeth->ug_regs->miimng.miimcfg,
 762                    in_be32(&ugeth->ug_regs->miimng.miimcfg));
 763         ugeth_info("miimcom    : addr - 0x%08x, val - 0x%08x",
 764                    (u32) & ugeth->ug_regs->miimng.miimcom,
 765                    in_be32(&ugeth->ug_regs->miimng.miimcom));
 766         ugeth_info("miimadd    : addr - 0x%08x, val - 0x%08x",
 767                    (u32) & ugeth->ug_regs->miimng.miimadd,
 768                    in_be32(&ugeth->ug_regs->miimng.miimadd));
 769         ugeth_info("miimcon    : addr - 0x%08x, val - 0x%08x",
 770                    (u32) & ugeth->ug_regs->miimng.miimcon,
 771                    in_be32(&ugeth->ug_regs->miimng.miimcon));
 772         ugeth_info("miimstat   : addr - 0x%08x, val - 0x%08x",
 773                    (u32) & ugeth->ug_regs->miimng.miimstat,
 774                    in_be32(&ugeth->ug_regs->miimng.miimstat));
 775         ugeth_info("miimmind   : addr - 0x%08x, val - 0x%08x",
 776                    (u32) & ugeth->ug_regs->miimng.miimind,
 777                    in_be32(&ugeth->ug_regs->miimng.miimind));
 778         ugeth_info("ifctl      : addr - 0x%08x, val - 0x%08x",
 779                    (u32) & ugeth->ug_regs->ifctl,
 780                    in_be32(&ugeth->ug_regs->ifctl));
 781         ugeth_info("ifstat     : addr - 0x%08x, val - 0x%08x",
 782                    (u32) & ugeth->ug_regs->ifstat,
 783                    in_be32(&ugeth->ug_regs->ifstat));
 784         ugeth_info("macstnaddr1: addr - 0x%08x, val - 0x%08x",
 785                    (u32) & ugeth->ug_regs->macstnaddr1,
 786                    in_be32(&ugeth->ug_regs->macstnaddr1));
 787         ugeth_info("macstnaddr2: addr - 0x%08x, val - 0x%08x",
 788                    (u32) & ugeth->ug_regs->macstnaddr2,
 789                    in_be32(&ugeth->ug_regs->macstnaddr2));
 790         ugeth_info("uempr      : addr - 0x%08x, val - 0x%08x",
 791                    (u32) & ugeth->ug_regs->uempr,
 792                    in_be32(&ugeth->ug_regs->uempr));
 793         ugeth_info("utbipar    : addr - 0x%08x, val - 0x%08x",
 794                    (u32) & ugeth->ug_regs->utbipar,
 795                    in_be32(&ugeth->ug_regs->utbipar));
 796         ugeth_info("uescr      : addr - 0x%08x, val - 0x%04x",
 797                    (u32) & ugeth->ug_regs->uescr,
 798                    in_be16(&ugeth->ug_regs->uescr));
 799         ugeth_info("tx64       : addr - 0x%08x, val - 0x%08x",
 800                    (u32) & ugeth->ug_regs->tx64,
 801                    in_be32(&ugeth->ug_regs->tx64));
 802         ugeth_info("tx127      : addr - 0x%08x, val - 0x%08x",
 803                    (u32) & ugeth->ug_regs->tx127,
 804                    in_be32(&ugeth->ug_regs->tx127));
 805         ugeth_info("tx255      : addr - 0x%08x, val - 0x%08x",
 806                    (u32) & ugeth->ug_regs->tx255,
 807                    in_be32(&ugeth->ug_regs->tx255));
 808         ugeth_info("rx64       : addr - 0x%08x, val - 0x%08x",
 809                    (u32) & ugeth->ug_regs->rx64,
 810                    in_be32(&ugeth->ug_regs->rx64));
 811         ugeth_info("rx127      : addr - 0x%08x, val - 0x%08x",
 812                    (u32) & ugeth->ug_regs->rx127,
 813                    in_be32(&ugeth->ug_regs->rx127));
 814         ugeth_info("rx255      : addr - 0x%08x, val - 0x%08x",
 815                    (u32) & ugeth->ug_regs->rx255,
 816                    in_be32(&ugeth->ug_regs->rx255));
 817         ugeth_info("txok       : addr - 0x%08x, val - 0x%08x",
 818                    (u32) & ugeth->ug_regs->txok,
 819                    in_be32(&ugeth->ug_regs->txok));
 820         ugeth_info("txcf       : addr - 0x%08x, val - 0x%04x",
 821                    (u32) & ugeth->ug_regs->txcf,
 822                    in_be16(&ugeth->ug_regs->txcf));
 823         ugeth_info("tmca       : addr - 0x%08x, val - 0x%08x",
 824                    (u32) & ugeth->ug_regs->tmca,
 825                    in_be32(&ugeth->ug_regs->tmca));
 826         ugeth_info("tbca       : addr - 0x%08x, val - 0x%08x",
 827                    (u32) & ugeth->ug_regs->tbca,
 828                    in_be32(&ugeth->ug_regs->tbca));
 829         ugeth_info("rxfok      : addr - 0x%08x, val - 0x%08x",
 830                    (u32) & ugeth->ug_regs->rxfok,
 831                    in_be32(&ugeth->ug_regs->rxfok));
 832         ugeth_info("rxbok      : addr - 0x%08x, val - 0x%08x",
 833                    (u32) & ugeth->ug_regs->rxbok,
 834                    in_be32(&ugeth->ug_regs->rxbok));
 835         ugeth_info("rbyt       : addr - 0x%08x, val - 0x%08x",
 836                    (u32) & ugeth->ug_regs->rbyt,
 837                    in_be32(&ugeth->ug_regs->rbyt));
 838         ugeth_info("rmca       : addr - 0x%08x, val - 0x%08x",
 839                    (u32) & ugeth->ug_regs->rmca,
 840                    in_be32(&ugeth->ug_regs->rmca));
 841         ugeth_info("rbca       : addr - 0x%08x, val - 0x%08x",
 842                    (u32) & ugeth->ug_regs->rbca,
 843                    in_be32(&ugeth->ug_regs->rbca));
 844         ugeth_info("scar       : addr - 0x%08x, val - 0x%08x",
 845                    (u32) & ugeth->ug_regs->scar,
 846                    in_be32(&ugeth->ug_regs->scar));
 847         ugeth_info("scam       : addr - 0x%08x, val - 0x%08x",
 848                    (u32) & ugeth->ug_regs->scam,
 849                    in_be32(&ugeth->ug_regs->scam));
 850
 851         if (ugeth->p_thread_data_tx) {
 852                 int numThreadsTxNumerical;
 853                 switch (ugeth->ug_info->numThreadsTx) {
 854                 case UCC_GETH_NUM_OF_THREADS_1:
 855                         numThreadsTxNumerical = 1;
 856                         break;
 857                 case UCC_GETH_NUM_OF_THREADS_2:
 858                         numThreadsTxNumerical = 2;
 859                         break;
 860                 case UCC_GETH_NUM_OF_THREADS_4:
 861                         numThreadsTxNumerical = 4;
 862                         break;
 863                 case UCC_GETH_NUM_OF_THREADS_6:
 864                         numThreadsTxNumerical = 6;
 865                         break;
 866                 case UCC_GETH_NUM_OF_THREADS_8:
 867                         numThreadsTxNumerical = 8;
 868                         break;
 869                 default:
 870                         numThreadsTxNumerical = 0;
 871                         break;
 872                 }
 873
 874                 ugeth_info("Thread data TXs:");
 875                 ugeth_info("Base address: 0x%08x",
 876                            (u32) ugeth->p_thread_data_tx);
 877                 for (i = 0; i < numThreadsTxNumerical; i++) {
 878                         ugeth_info("Thread data TX[%d]:", i);
 879                         ugeth_info("Base address: 0x%08x",
 880                                    (u32) & ugeth->p_thread_data_tx[i]);
 881                         mem_disp((u8 *) & ugeth->p_thread_data_tx[i],
 882                                  sizeof(struct ucc_geth_thread_data_tx));
 883                 }
 884         }
 885         if (ugeth->p_thread_data_rx) {
 886                 int numThreadsRxNumerical;
 887                 switch (ugeth->ug_info->numThreadsRx) {
 888                 case UCC_GETH_NUM_OF_THREADS_1:
 889                         numThreadsRxNumerical = 1;
 890                         break;
 891                 case UCC_GETH_NUM_OF_THREADS_2:
 892                         numThreadsRxNumerical = 2;
 893                         break;
 894                 case UCC_GETH_NUM_OF_THREADS_4:
 895                         numThreadsRxNumerical = 4;
 896                         break;
 897                 case UCC_GETH_NUM_OF_THREADS_6:
 898                         numThreadsRxNumerical = 6;
 899                         break;
 900                 case UCC_GETH_NUM_OF_THREADS_8:
 901                         numThreadsRxNumerical = 8;
 902                         break;
 903                 default:
 904                         numThreadsRxNumerical = 0;
 905                         break;
 906                 }
 907
 908                 ugeth_info("Thread data RX:");
 909                 ugeth_info("Base address: 0x%08x",
 910                            (u32) ugeth->p_thread_data_rx);
 911                 for (i = 0; i < numThreadsRxNumerical; i++) {
 912                         ugeth_info("Thread data RX[%d]:", i);
 913                         ugeth_info("Base address: 0x%08x",
 914                                    (u32) & ugeth->p_thread_data_rx[i]);
 915                         mem_disp((u8 *) & ugeth->p_thread_data_rx[i],
 916                                  sizeof(struct ucc_geth_thread_data_rx));
 917                 }
 918         }
 919         if (ugeth->p_exf_glbl_param) {
 920                 ugeth_info("EXF global param:");
 921                 ugeth_info("Base address: 0x%08x",
 922                            (u32) ugeth->p_exf_glbl_param);
 923                 mem_disp((u8 *) ugeth->p_exf_glbl_param,
 924                          sizeof(*ugeth->p_exf_glbl_param));
 925         }
 926         if (ugeth->p_tx_glbl_pram) {
 927                 ugeth_info("TX global param:");
 928                 ugeth_info("Base address: 0x%08x", (u32) ugeth->p_tx_glbl_pram);
 929                 ugeth_info("temoder      : addr - 0x%08x, val - 0x%04x",
 930                            (u32) & ugeth->p_tx_glbl_pram->temoder,
 931                            in_be16(&ugeth->p_tx_glbl_pram->temoder));
 932                 ugeth_info("sqptr        : addr - 0x%08x, val - 0x%08x",
 933                            (u32) & ugeth->p_tx_glbl_pram->sqptr,
 934                            in_be32(&ugeth->p_tx_glbl_pram->sqptr));
 935                 ugeth_info("schedulerbasepointer: addr - 0x%08x, val - 0x%08x",
 936                            (u32) & ugeth->p_tx_glbl_pram->schedulerbasepointer,
 937                            in_be32(&ugeth->p_tx_glbl_pram->
 938                                    schedulerbasepointer));
 939                 ugeth_info("txrmonbaseptr: addr - 0x%08x, val - 0x%08x",
 940                            (u32) & ugeth->p_tx_glbl_pram->txrmonbaseptr,
 941                            in_be32(&ugeth->p_tx_glbl_pram->txrmonbaseptr));
 942                 ugeth_info("tstate       : addr - 0x%08x, val - 0x%08x",
 943                            (u32) & ugeth->p_tx_glbl_pram->tstate,
 944                            in_be32(&ugeth->p_tx_glbl_pram->tstate));
 945                 ugeth_info("iphoffset[0] : addr - 0x%08x, val - 0x%02x",
 946                            (u32) & ugeth->p_tx_glbl_pram->iphoffset[0],
 947                            ugeth->p_tx_glbl_pram->iphoffset[0]);
 948                 ugeth_info("iphoffset[1] : addr - 0x%08x, val - 0x%02x",
 949                            (u32) & ugeth->p_tx_glbl_pram->iphoffset[1],
 950                            ugeth->p_tx_glbl_pram->iphoffset[1]);
 951                 ugeth_info("iphoffset[2] : addr - 0x%08x, val - 0x%02x",
 952                            (u32) & ugeth->p_tx_glbl_pram->iphoffset[2],
 953                            ugeth->p_tx_glbl_pram->iphoffset[2]);
 954                 ugeth_info("iphoffset[3] : addr - 0x%08x, val - 0x%02x",
 955                            (u32) & ugeth->p_tx_glbl_pram->iphoffset[3],
 956                            ugeth->p_tx_glbl_pram->iphoffset[3]);
 957                 ugeth_info("iphoffset[4] : addr - 0x%08x, val - 0x%02x",
 958                            (u32) & ugeth->p_tx_glbl_pram->iphoffset[4],
 959                            ugeth->p_tx_glbl_pram->iphoffset[4]);
 960                 ugeth_info("iphoffset[5] : addr - 0x%08x, val - 0x%02x",
 961                            (u32) & ugeth->p_tx_glbl_pram->iphoffset[5],
 962                            ugeth->p_tx_glbl_pram->iphoffset[5]);
 963                 ugeth_info("iphoffset[6] : addr - 0x%08x, val - 0x%02x",
 964                            (u32) & ugeth->p_tx_glbl_pram->iphoffset[6],
 965                            ugeth->p_tx_glbl_pram->iphoffset[6]);
 966                 ugeth_info("iphoffset[7] : addr - 0x%08x, val - 0x%02x",
 967                            (u32) & ugeth->p_tx_glbl_pram->iphoffset[7],
 968                            ugeth->p_tx_glbl_pram->iphoffset[7]);
 969                 ugeth_info("vtagtable[0] : addr - 0x%08x, val - 0x%08x",
 970                            (u32) & ugeth->p_tx_glbl_pram->vtagtable[0],
 971                            in_be32(&ugeth->p_tx_glbl_pram->vtagtable[0]));
 972                 ugeth_info("vtagtable[1] : addr - 0x%08x, val - 0x%08x",
 973                            (u32) & ugeth->p_tx_glbl_pram->vtagtable[1],
 974                            in_be32(&ugeth->p_tx_glbl_pram->vtagtable[1]));
 975                 ugeth_info("vtagtable[2] : addr - 0x%08x, val - 0x%08x",
 976                            (u32) & ugeth->p_tx_glbl_pram->vtagtable[2],
 977                            in_be32(&ugeth->p_tx_glbl_pram->vtagtable[2]));
 978                 ugeth_info("vtagtable[3] : addr - 0x%08x, val - 0x%08x",
 979                            (u32) & ugeth->p_tx_glbl_pram->vtagtable[3],
 980                            in_be32(&ugeth->p_tx_glbl_pram->vtagtable[3]));
 981                 ugeth_info("vtagtable[4] : addr - 0x%08x, val - 0x%08x",
 982                            (u32) & ugeth->p_tx_glbl_pram->vtagtable[4],
 983                            in_be32(&ugeth->p_tx_glbl_pram->vtagtable[4]));
 984                 ugeth_info("vtagtable[5] : addr - 0x%08x, val - 0x%08x",
 985                            (u32) & ugeth->p_tx_glbl_pram->vtagtable[5],
 986                            in_be32(&ugeth->p_tx_glbl_pram->vtagtable[5]));
 987                 ugeth_info("vtagtable[6] : addr - 0x%08x, val - 0x%08x",
 988                            (u32) & ugeth->p_tx_glbl_pram->vtagtable[6],
 989                            in_be32(&ugeth->p_tx_glbl_pram->vtagtable[6]));
 990                 ugeth_info("vtagtable[7] : addr - 0x%08x, val - 0x%08x",
 991                            (u32) & ugeth->p_tx_glbl_pram->vtagtable[7],
 992                            in_be32(&ugeth->p_tx_glbl_pram->vtagtable[7]));
 993                 ugeth_info("tqptr        : addr - 0x%08x, val - 0x%08x",
 994                            (u32) & ugeth->p_tx_glbl_pram->tqptr,
 995                            in_be32(&ugeth->p_tx_glbl_pram->tqptr));
 996         }
 997         if (ugeth->p_rx_glbl_pram) {
 998                 ugeth_info("RX global param:");
 999                 ugeth_info("Base address: 0x%08x", (u32) ugeth->p_rx_glbl_pram);
1000                 ugeth_info("remoder         : addr - 0x%08x, val - 0x%08x",
1001                            (u32) & ugeth->p_rx_glbl_pram->remoder,
1002                            in_be32(&ugeth->p_rx_glbl_pram->remoder));
1003                 ugeth_info("rqptr           : addr - 0x%08x, val - 0x%08x",
1004                            (u32) & ugeth->p_rx_glbl_pram->rqptr,
1005                            in_be32(&ugeth->p_rx_glbl_pram->rqptr));
1006                 ugeth_info("typeorlen       : addr - 0x%08x, val - 0x%04x",
1007                            (u32) & ugeth->p_rx_glbl_pram->typeorlen,
1008                            in_be16(&ugeth->p_rx_glbl_pram->typeorlen));
1009                 ugeth_info("rxgstpack       : addr - 0x%08x, val - 0x%02x",
1010                            (u32) & ugeth->p_rx_glbl_pram->rxgstpack,
1011                            ugeth->p_rx_glbl_pram->rxgstpack);
1012                 ugeth_info("rxrmonbaseptr   : addr - 0x%08x, val - 0x%08x",
1013                            (u32) & ugeth->p_rx_glbl_pram->rxrmonbaseptr,
1014                            in_be32(&ugeth->p_rx_glbl_pram->rxrmonbaseptr));
1015                 ugeth_info("intcoalescingptr: addr - 0x%08x, val - 0x%08x",
1016                            (u32) & ugeth->p_rx_glbl_pram->intcoalescingptr,
1017                            in_be32(&ugeth->p_rx_glbl_pram->intcoalescingptr));
1018                 ugeth_info("rstate          : addr - 0x%08x, val - 0x%02x",
1019                            (u32) & ugeth->p_rx_glbl_pram->rstate,
1020                            ugeth->p_rx_glbl_pram->rstate);
1021                 ugeth_info("mrblr           : addr - 0x%08x, val - 0x%04x",
1022                            (u32) & ugeth->p_rx_glbl_pram->mrblr,
1023                            in_be16(&ugeth->p_rx_glbl_pram->mrblr));
1024                 ugeth_info("rbdqptr         : addr - 0x%08x, val - 0x%08x",
1025                            (u32) & ugeth->p_rx_glbl_pram->rbdqptr,
1026                            in_be32(&ugeth->p_rx_glbl_pram->rbdqptr));
1027                 ugeth_info("mflr            : addr - 0x%08x, val - 0x%04x",
1028                            (u32) & ugeth->p_rx_glbl_pram->mflr,
1029                            in_be16(&ugeth->p_rx_glbl_pram->mflr));
1030                 ugeth_info("minflr          : addr - 0x%08x, val - 0x%04x",
1031                            (u32) & ugeth->p_rx_glbl_pram->minflr,
1032                            in_be16(&ugeth->p_rx_glbl_pram->minflr));
1033                 ugeth_info("maxd1           : addr - 0x%08x, val - 0x%04x",
1034                            (u32) & ugeth->p_rx_glbl_pram->maxd1,
1035                            in_be16(&ugeth->p_rx_glbl_pram->maxd1));
1036                 ugeth_info("maxd2           : addr - 0x%08x, val - 0x%04x",
1037                            (u32) & ugeth->p_rx_glbl_pram->maxd2,
1038                            in_be16(&ugeth->p_rx_glbl_pram->maxd2));
1039                 ugeth_info("ecamptr         : addr - 0x%08x, val - 0x%08x",
1040                            (u32) & ugeth->p_rx_glbl_pram->ecamptr,
1041                            in_be32(&ugeth->p_rx_glbl_pram->ecamptr));
1042                 ugeth_info("l2qt            : addr - 0x%08x, val - 0x%08x",
1043                            (u32) & ugeth->p_rx_glbl_pram->l2qt,
1044                            in_be32(&ugeth->p_rx_glbl_pram->l2qt));
1045                 ugeth_info("l3qt[0]         : addr - 0x%08x, val - 0x%08x",
1046                            (u32) & ugeth->p_rx_glbl_pram->l3qt[0],
1047                            in_be32(&ugeth->p_rx_glbl_pram->l3qt[0]));
1048                 ugeth_info("l3qt[1]         : addr - 0x%08x, val - 0x%08x",
1049                            (u32) & ugeth->p_rx_glbl_pram->l3qt[1],
1050                            in_be32(&ugeth->p_rx_glbl_pram->l3qt[1]));
1051                 ugeth_info("l3qt[2]         : addr - 0x%08x, val - 0x%08x",
1052                            (u32) & ugeth->p_rx_glbl_pram->l3qt[2],
1053                            in_be32(&ugeth->p_rx_glbl_pram->l3qt[2]));
1054                 ugeth_info("l3qt[3]         : addr - 0x%08x, val - 0x%08x",
1055                            (u32) & ugeth->p_rx_glbl_pram->l3qt[3],
1056                            in_be32(&ugeth->p_rx_glbl_pram->l3qt[3]));
1057                 ugeth_info("l3qt[4]         : addr - 0x%08x, val - 0x%08x",
1058                            (u32) & ugeth->p_rx_glbl_pram->l3qt[4],
1059                            in_be32(&ugeth->p_rx_glbl_pram->l3qt[4]));
1060                 ugeth_info("l3qt[5]         : addr - 0x%08x, val - 0x%08x",
1061                            (u32) & ugeth->p_rx_glbl_pram->l3qt[5],
1062                            in_be32(&ugeth->p_rx_glbl_pram->l3qt[5]));
1063                 ugeth_info("l3qt[6]         : addr - 0x%08x, val - 0x%08x",
1064                            (u32) & ugeth->p_rx_glbl_pram->l3qt[6],
1065                            in_be32(&ugeth->p_rx_glbl_pram->l3qt[6]));
1066                 ugeth_info("l3qt[7]         : addr - 0x%08x, val - 0x%08x",
1067                            (u32) & ugeth->p_rx_glbl_pram->l3qt[7],
1068                            in_be32(&ugeth->p_rx_glbl_pram->l3qt[7]));
1069                 ugeth_info("vlantype        : addr - 0x%08x, val - 0x%04x",
1070                            (u32) & ugeth->p_rx_glbl_pram->vlantype,
1071                            in_be16(&ugeth->p_rx_glbl_pram->vlantype));
1072                 ugeth_info("vlantci         : addr - 0x%08x, val - 0x%04x",
1073                            (u32) & ugeth->p_rx_glbl_pram->vlantci,
1074                            in_be16(&ugeth->p_rx_glbl_pram->vlantci));
1075                 for (i = 0; i < 64; i++)
1076                         ugeth_info
1077                     ("addressfiltering[%d]: addr - 0x%08x, val - 0x%02x",
1078                              i,
1079                              (u32) & ugeth->p_rx_glbl_pram->addressfiltering[i],
1080                              ugeth->p_rx_glbl_pram->addressfiltering[i]);
1081                 ugeth_info("exfGlobalParam  : addr - 0x%08x, val - 0x%08x",
1082                            (u32) & ugeth->p_rx_glbl_pram->exfGlobalParam,
1083                            in_be32(&ugeth->p_rx_glbl_pram->exfGlobalParam));
1084         }
1085         if (ugeth->p_send_q_mem_reg) {
1086                 ugeth_info("Send Q memory registers:");
1087                 ugeth_info("Base address: 0x%08x",
1088                            (u32) ugeth->p_send_q_mem_reg);
1089                 for (i = 0; i < ugeth->ug_info->numQueuesTx; i++) {
1090                         ugeth_info("SQQD[%d]:", i);
1091                         ugeth_info("Base address: 0x%08x",
1092                                    (u32) & ugeth->p_send_q_mem_reg->sqqd[i]);
1093                         mem_disp((u8 *) & ugeth->p_send_q_mem_reg->sqqd[i],
1094                                  sizeof(struct ucc_geth_send_queue_qd));
1095                 }
1096         }
1097         if (ugeth->p_scheduler) {
1098                 ugeth_info("Scheduler:");
1099                 ugeth_info("Base address: 0x%08x", (u32) ugeth->p_scheduler);
1100                 mem_disp((u8 *) ugeth->p_scheduler,
1101                          sizeof(*ugeth->p_scheduler));
1102         }
1103         if (ugeth->p_tx_fw_statistics_pram) {
1104                 ugeth_info("TX FW statistics pram:");
1105                 ugeth_info("Base address: 0x%08x",
1106                            (u32) ugeth->p_tx_fw_statistics_pram);
1107                 mem_disp((u8 *) ugeth->p_tx_fw_statistics_pram,
1108                          sizeof(*ugeth->p_tx_fw_statistics_pram));
1109         }
1110         if (ugeth->p_rx_fw_statistics_pram) {
1111                 ugeth_info("RX FW statistics pram:");
1112                 ugeth_info("Base address: 0x%08x",
1113                            (u32) ugeth->p_rx_fw_statistics_pram);
1114                 mem_disp((u8 *) ugeth->p_rx_fw_statistics_pram,
1115                          sizeof(*ugeth->p_rx_fw_statistics_pram));
1116         }
1117         if (ugeth->p_rx_irq_coalescing_tbl) {
1118                 ugeth_info("RX IRQ coalescing tables:");
1119                 ugeth_info("Base address: 0x%08x",
1120                            (u32) ugeth->p_rx_irq_coalescing_tbl);
1121                 for (i = 0; i < ugeth->ug_info->numQueuesRx; i++) {
1122                         ugeth_info("RX IRQ coalescing table entry[%d]:", i);
1123                         ugeth_info("Base address: 0x%08x",
1124                                    (u32) & ugeth->p_rx_irq_coalescing_tbl->
1125                                    coalescingentry[i]);
1126                         ugeth_info
1127                 ("interruptcoalescingmaxvalue: addr - 0x%08x, val - 0x%08x",
1128                              (u32) & ugeth->p_rx_irq_coalescing_tbl->
1129                              coalescingentry[i].interruptcoalescingmaxvalue,
1130                              in_be32(&ugeth->p_rx_irq_coalescing_tbl->
1131                                      coalescingentry[i].
1132                                      interruptcoalescingmaxvalue));
1133                         ugeth_info
1134                 ("interruptcoalescingcounter : addr - 0x%08x, val - 0x%08x",
1135                              (u32) & ugeth->p_rx_irq_coalescing_tbl->
1136                              coalescingentry[i].interruptcoalescingcounter,
1137                              in_be32(&ugeth->p_rx_irq_coalescing_tbl->
1138                                      coalescingentry[i].
1139                                      interruptcoalescingcounter));
1140                 }
1141         }
1142         if (ugeth->p_rx_bd_qs_tbl) {
1143                 ugeth_info("RX BD QS tables:");
1144                 ugeth_info("Base address: 0x%08x", (u32) ugeth->p_rx_bd_qs_tbl);
1145                 for (i = 0; i < ugeth->ug_info->numQueuesRx; i++) {
1146                         ugeth_info("RX BD QS table[%d]:", i);
1147                         ugeth_info("Base address: 0x%08x",
1148                                    (u32) & ugeth->p_rx_bd_qs_tbl[i]);
1149                         ugeth_info
1150                             ("bdbaseptr        : addr - 0x%08x, val - 0x%08x",
1151                              (u32) & ugeth->p_rx_bd_qs_tbl[i].bdbaseptr,
1152                              in_be32(&ugeth->p_rx_bd_qs_tbl[i].bdbaseptr));
1153                         ugeth_info
1154                             ("bdptr            : addr - 0x%08x, val - 0x%08x",
1155                              (u32) & ugeth->p_rx_bd_qs_tbl[i].bdptr,
1156                              in_be32(&ugeth->p_rx_bd_qs_tbl[i].bdptr));
1157                         ugeth_info
1158                             ("externalbdbaseptr: addr - 0x%08x, val - 0x%08x",
1159                              (u32) & ugeth->p_rx_bd_qs_tbl[i].externalbdbaseptr,
1160                              in_be32(&ugeth->p_rx_bd_qs_tbl[i].
1161                                      externalbdbaseptr));
1162                         ugeth_info
1163                             ("externalbdptr    : addr - 0x%08x, val - 0x%08x",
1164                              (u32) & ugeth->p_rx_bd_qs_tbl[i].externalbdptr,
1165                              in_be32(&ugeth->p_rx_bd_qs_tbl[i].externalbdptr));
1166                         ugeth_info("ucode RX Prefetched BDs:");
1167                         ugeth_info("Base address: 0x%08x",
1168                                    (u32)
1169                                    qe_muram_addr(in_be32
1170                                                  (&ugeth->p_rx_bd_qs_tbl[i].
1171                                                   bdbaseptr)));
1172                         mem_disp((u8 *)
1173                                  qe_muram_addr(in_be32
1174                                                (&ugeth->p_rx_bd_qs_tbl[i].
1175                                                 bdbaseptr)),
1176                                  sizeof(struct ucc_geth_rx_prefetched_bds));
1177                 }
1178         }
1179         if (ugeth->p_init_enet_param_shadow) {
1180                 int size;
1181                 ugeth_info("Init enet param shadow:");
1182                 ugeth_info("Base address: 0x%08x",
1183                            (u32) ugeth->p_init_enet_param_shadow);
1184                 mem_disp((u8 *) ugeth->p_init_enet_param_shadow,
1185                          sizeof(*ugeth->p_init_enet_param_shadow));
1186
1187                 size = sizeof(struct ucc_geth_thread_rx_pram);
1188                 if (ugeth->ug_info->rxExtendedFiltering) {
1189                         size +=
1190                             THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING;
1191                         if (ugeth->ug_info->largestexternallookupkeysize ==
1192                             QE_FLTR_TABLE_LOOKUP_KEY_SIZE_8_BYTES)
1193                                 size +=
1194                         THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING_8;
1195                         if (ugeth->ug_info->largestexternallookupkeysize ==
1196                             QE_FLTR_TABLE_LOOKUP_KEY_SIZE_16_BYTES)
1197                                 size +=
1198                         THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING_16;
1199                 }
1200
1201                 dump_init_enet_entries(ugeth,
1202                                        &(ugeth->p_init_enet_param_shadow->
1203                                          txthread[0]),
1204                                        ENET_INIT_PARAM_MAX_ENTRIES_TX,
1205                                        sizeof(struct ucc_geth_thread_tx_pram),
1206                                        ugeth->ug_info->riscTx, 0);
1207                 dump_init_enet_entries(ugeth,
1208                                        &(ugeth->p_init_enet_param_shadow->
1209                                          rxthread[0]),
1210                                        ENET_INIT_PARAM_MAX_ENTRIES_RX, size,
1211                                        ugeth->ug_info->riscRx, 1);
1212         }
1213 }
1214 #endif /* DEBUG */
1215
1216 static void init_default_reg_vals(volatile u32 *upsmr_register,
1217                                   volatile u32 *maccfg1_register,
1218                                   volatile u32 *maccfg2_register)
1219 {
1220         out_be32(upsmr_register, UCC_GETH_UPSMR_INIT);
1221         out_be32(maccfg1_register, UCC_GETH_MACCFG1_INIT);
1222         out_be32(maccfg2_register, UCC_GETH_MACCFG2_INIT);
1223 }
1224
1225 static int init_half_duplex_params(int alt_beb,
1226                                    int back_pressure_no_backoff,
1227                                    int no_backoff,
1228                                    int excess_defer,
1229                                    u8 alt_beb_truncation,
1230                                    u8 max_retransmissions,
1231                                    u8 collision_window,
1232                                    volatile u32 *hafdup_register)
1233 {
1234         u32 value = 0;
1235
1236         if ((alt_beb_truncation > HALFDUP_ALT_BEB_TRUNCATION_MAX) ||
1237             (max_retransmissions > HALFDUP_MAX_RETRANSMISSION_MAX) ||
1238             (collision_window > HALFDUP_COLLISION_WINDOW_MAX))
1239                 return -EINVAL;
1240
1241         value = (u32) (alt_beb_truncation << HALFDUP_ALT_BEB_TRUNCATION_SHIFT);
1242
1243         if (alt_beb)
1244                 value |= HALFDUP_ALT_BEB;
1245         if (back_pressure_no_backoff)
1246                 value |= HALFDUP_BACK_PRESSURE_NO_BACKOFF;
1247         if (no_backoff)
1248                 value |= HALFDUP_NO_BACKOFF;
1249         if (excess_defer)
1250                 value |= HALFDUP_EXCESSIVE_DEFER;
1251
1252         value |= (max_retransmissions << HALFDUP_MAX_RETRANSMISSION_SHIFT);
1253
1254         value |= collision_window;
1255
1256         out_be32(hafdup_register, value);
1257         return 0;
1258 }
1259
1260 static int init_inter_frame_gap_params(u8 non_btb_cs_ipg,
1261                                        u8 non_btb_ipg,
1262                                        u8 min_ifg,
1263                                        u8 btb_ipg,
1264                                        volatile u32 *ipgifg_register)
1265 {
1266         u32 value = 0;
1267
1268         /* Non-Back-to-back IPG part 1 should be <= Non-Back-to-back
1269         IPG part 2 */
1270         if (non_btb_cs_ipg > non_btb_ipg)
1271                 return -EINVAL;
1272
1273         if ((non_btb_cs_ipg > IPGIFG_NON_BACK_TO_BACK_IFG_PART1_MAX) ||
1274             (non_btb_ipg > IPGIFG_NON_BACK_TO_BACK_IFG_PART2_MAX) ||
1275             /*(min_ifg        > IPGIFG_MINIMUM_IFG_ENFORCEMENT_MAX) || */
1276             (btb_ipg > IPGIFG_BACK_TO_BACK_IFG_MAX))
1277                 return -EINVAL;
1278
1279         value |=
1280             ((non_btb_cs_ipg << IPGIFG_NON_BACK_TO_BACK_IFG_PART1_SHIFT) &
1281              IPGIFG_NBTB_CS_IPG_MASK);
1282         value |=
1283             ((non_btb_ipg << IPGIFG_NON_BACK_TO_BACK_IFG_PART2_SHIFT) &
1284              IPGIFG_NBTB_IPG_MASK);
1285         value |=
1286             ((min_ifg << IPGIFG_MINIMUM_IFG_ENFORCEMENT_SHIFT) &
1287              IPGIFG_MIN_IFG_MASK);
1288         value |= (btb_ipg & IPGIFG_BTB_IPG_MASK);
1289
1290         out_be32(ipgifg_register, value);
1291         return 0;
1292 }
1293
1294 static int init_flow_control_params(u32 automatic_flow_control_mode,
1295                                     int rx_flow_control_enable,
1296                                     int tx_flow_control_enable,
1297                                     u16 pause_period,
1298                                     u16 extension_field,
1299                                     volatile u32 *upsmr_register,
1300                                     volatile u32 *uempr_register,
1301                                     volatile u32 *maccfg1_register)
1302 {
1303         u32 value = 0;
1304
1305         /* Set UEMPR register */
1306         value = (u32) pause_period << UEMPR_PAUSE_TIME_VALUE_SHIFT;
1307         value |= (u32) extension_field << UEMPR_EXTENDED_PAUSE_TIME_VALUE_SHIFT;
1308         out_be32(uempr_register, value);
1309
1310         /* Set UPSMR register */
1311         value = in_be32(upsmr_register);
1312         value |= automatic_flow_control_mode;
1313         out_be32(upsmr_register, value);
1314
1315         value = in_be32(maccfg1_register);
1316         if (rx_flow_control_enable)
1317                 value |= MACCFG1_FLOW_RX;
1318         if (tx_flow_control_enable)
1319                 value |= MACCFG1_FLOW_TX;
1320         out_be32(maccfg1_register, value);
1321
1322         return 0;
1323 }
1324
1325 static int init_hw_statistics_gathering_mode(int enable_hardware_statistics,
1326                                              int auto_zero_hardware_statistics,
1327                                              volatile u32 *upsmr_register,
1328                                              volatile u16 *uescr_register)
1329 {
1330         u32 upsmr_value = 0;
1331         u16 uescr_value = 0;
1332         /* Enable hardware statistics gathering if requested */
1333         if (enable_hardware_statistics) {
1334                 upsmr_value = in_be32(upsmr_register);
1335                 upsmr_value |= UPSMR_HSE;
1336                 out_be32(upsmr_register, upsmr_value);
1337         }
1338
1339         /* Clear hardware statistics counters */
1340         uescr_value = in_be16(uescr_register);
1341         uescr_value |= UESCR_CLRCNT;
1342         /* Automatically zero hardware statistics counters on read,
1343         if requested */
1344         if (auto_zero_hardware_statistics)
1345                 uescr_value |= UESCR_AUTOZ;
1346         out_be16(uescr_register, uescr_value);
1347
1348         return 0;
1349 }
1350
1351 static int init_firmware_statistics_gathering_mode(int
1352                 enable_tx_firmware_statistics,
1353                 int enable_rx_firmware_statistics,
1354                 volatile u32 *tx_rmon_base_ptr,
1355                 u32 tx_firmware_statistics_structure_address,
1356                 volatile u32 *rx_rmon_base_ptr,
1357                 u32 rx_firmware_statistics_structure_address,
1358                 volatile u16 *temoder_register,
1359                 volatile u32 *remoder_register)
1360 {
1361         /* Note: this function does not check if */
1362         /* the parameters it receives are NULL   */
1363         u16 temoder_value;
1364         u32 remoder_value;
1365
1366         if (enable_tx_firmware_statistics) {
1367                 out_be32(tx_rmon_base_ptr,
1368                          tx_firmware_statistics_structure_address);
1369                 temoder_value = in_be16(temoder_register);
1370                 temoder_value |= TEMODER_TX_RMON_STATISTICS_ENABLE;
1371                 out_be16(temoder_register, temoder_value);
1372         }
1373
1374         if (enable_rx_firmware_statistics) {
1375                 out_be32(rx_rmon_base_ptr,
1376                          rx_firmware_statistics_structure_address);
1377                 remoder_value = in_be32(remoder_register);
1378                 remoder_value |= REMODER_RX_RMON_STATISTICS_ENABLE;
1379                 out_be32(remoder_register, remoder_value);
1380         }
1381
1382         return 0;
1383 }
1384
1385 static int init_mac_station_addr_regs(u8 address_byte_0,
1386                                       u8 address_byte_1,
1387                                       u8 address_byte_2,
1388                                       u8 address_byte_3,
1389                                       u8 address_byte_4,
1390                                       u8 address_byte_5,
1391                                       volatile u32 *macstnaddr1_register,
1392                                       volatile u32 *macstnaddr2_register)
1393 {
1394         u32 value = 0;
1395
1396         /* Example: for a station address of 0x12345678ABCD, */
1397         /* 0x12 is byte 0, 0x34 is byte 1 and so on and 0xCD is byte 5 */
1398
1399         /* MACSTNADDR1 Register: */
1400
1401         /* 0                      7   8                      15  */
1402         /* station address byte 5     station address byte 4     */
1403         /* 16                     23  24                     31  */
1404         /* station address byte 3     station address byte 2     */
1405         value |= (u32) ((address_byte_2 << 0) & 0x000000FF);
1406         value |= (u32) ((address_byte_3 << 8) & 0x0000FF00);
1407         value |= (u32) ((address_byte_4 << 16) & 0x00FF0000);
1408         value |= (u32) ((address_byte_5 << 24) & 0xFF000000);
1409
1410         out_be32(macstnaddr1_register, value);
1411
1412         /* MACSTNADDR2 Register: */
1413
1414         /* 0                      7   8                      15  */
1415         /* station address byte 1     station address byte 0     */
1416         /* 16                     23  24                     31  */
1417         /*         reserved                   reserved           */
1418         value = 0;
1419         value |= (u32) ((address_byte_0 << 16) & 0x00FF0000);
1420         value |= (u32) ((address_byte_1 << 24) & 0xFF000000);
1421
1422         out_be32(macstnaddr2_register, value);
1423
1424         return 0;
1425 }
1426
1427 static int init_mac_duplex_mode(int full_duplex,
1428                                 int limited_to_full_duplex,
1429                                 volatile u32 *maccfg2_register)
1430 {
1431         u32 value = 0;
1432
1433         /* some interfaces must work in full duplex mode */
1434         if ((full_duplex == 0) && (limited_to_full_duplex == 1))
1435                 return -EINVAL;
1436
1437         value = in_be32(maccfg2_register);
1438
1439         if (full_duplex)
1440                 value |= MACCFG2_FDX;
1441         else
1442                 value &= ~MACCFG2_FDX;
1443
1444         out_be32(maccfg2_register, value);
1445         return 0;
1446 }
1447
1448 static int init_check_frame_length_mode(int length_check,
1449                                         volatile u32 *maccfg2_register)
1450 {
1451         u32 value = 0;
1452
1453         value = in_be32(maccfg2_register);
1454
1455         if (length_check)
1456                 value |= MACCFG2_LC;
1457         else
1458                 value &= ~MACCFG2_LC;
1459
1460         out_be32(maccfg2_register, value);
1461         return 0;
1462 }
1463
1464 static int init_preamble_length(u8 preamble_length,
1465                                 volatile u32 *maccfg2_register)
1466 {
1467         u32 value = 0;
1468
1469         if ((preamble_length < 3) || (preamble_length > 7))
1470                 return -EINVAL;
1471
1472         value = in_be32(maccfg2_register);
1473         value &= ~MACCFG2_PREL_MASK;
1474         value |= (preamble_length << MACCFG2_PREL_SHIFT);
1475         out_be32(maccfg2_register, value);
1476         return 0;
1477 }
1478
1479 static int init_mii_management_configuration(int reset_mgmt,
1480                                              int preamble_supress,
1481                                              volatile u32 *miimcfg_register,
1482                                              volatile u32 *miimind_register)
1483 {
1484         unsigned int timeout = PHY_INIT_TIMEOUT;
1485         u32 value = 0;
1486
1487         value = in_be32(miimcfg_register);
1488         if (reset_mgmt) {
1489                 value |= MIIMCFG_RESET_MANAGEMENT;
1490                 out_be32(miimcfg_register, value);
1491         }
1492
1493         value = 0;
1494
1495         if (preamble_supress)
1496                 value |= MIIMCFG_NO_PREAMBLE;
1497
1498         value |= UCC_GETH_MIIMCFG_MNGMNT_CLC_DIV_INIT;
1499         out_be32(miimcfg_register, value);
1500
1501         /* Wait until the bus is free */
1502         while ((in_be32(miimind_register) & MIIMIND_BUSY) && timeout--)
1503                 cpu_relax();
1504
1505         if (timeout <= 0) {
1506                 ugeth_err("%s: The MII Bus is stuck!", __FUNCTION__);
1507                 return -ETIMEDOUT;
1508         }
1509
1510         return 0;
1511 }
1512
1513 static int init_rx_parameters(int reject_broadcast,
1514                               int receive_short_frames,
1515                               int promiscuous, volatile u32 *upsmr_register)
1516 {
1517         u32 value = 0;
1518
1519         value = in_be32(upsmr_register);
1520
1521         if (reject_broadcast)
1522                 value |= UPSMR_BRO;
1523         else
1524                 value &= ~UPSMR_BRO;
1525
1526         if (receive_short_frames)
1527                 value |= UPSMR_RSH;
1528         else
1529                 value &= ~UPSMR_RSH;
1530
1531         if (promiscuous)
1532                 value |= UPSMR_PRO;
1533         else
1534                 value &= ~UPSMR_PRO;
1535
1536         out_be32(upsmr_register, value);
1537
1538         return 0;
1539 }
1540
1541 static int init_max_rx_buff_len(u16 max_rx_buf_len,
1542                                 volatile u16 *mrblr_register)
1543 {
1544         /* max_rx_buf_len value must be a multiple of 128 */
1545         if ((max_rx_buf_len == 0)
1546             || (max_rx_buf_len % UCC_GETH_MRBLR_ALIGNMENT))
1547                 return -EINVAL;
1548
1549         out_be16(mrblr_register, max_rx_buf_len);
1550         return 0;
1551 }
1552
1553 static int init_min_frame_len(u16 min_frame_length,
1554                               volatile u16 *minflr_register,
1555                               volatile u16 *mrblr_register)
1556 {
1557         u16 mrblr_value = 0;
1558
1559         mrblr_value = in_be16(mrblr_register);
1560         if (min_frame_length >= (mrblr_value - 4))
1561                 return -EINVAL;
1562
1563         out_be16(minflr_register, min_frame_length);
1564         return 0;
1565 }
1566
1567 static int adjust_enet_interface(struct ucc_geth_private *ugeth)
1568 {
1569         struct ucc_geth_info *ug_info;
1570         struct ucc_geth *ug_regs;
1571         struct ucc_fast *uf_regs;
1572         enum enet_speed speed;
1573         int ret_val, rpm = 0, tbi = 0, r10m = 0, rmm =
1574             0, limited_to_full_duplex = 0;
1575         u32 upsmr, maccfg2, utbipar, tbiBaseAddress;
1576         u16 value;
1577
1578         ugeth_vdbg("%s: IN", __FUNCTION__);
1579
1580         ug_info = ugeth->ug_info;
1581         ug_regs = ugeth->ug_regs;
1582         uf_regs = ugeth->uccf->uf_regs;
1583
1584         /* Analyze enet_interface according to Interface Mode Configuration
1585         table */
1586         ret_val =
1587             get_interface_details(ug_info->enet_interface, &speed, &r10m, &rmm,
1588                                   &rpm, &tbi, &limited_to_full_duplex);
1589         if (ret_val != 0) {
1590                 ugeth_err
1591                   ("%s: half duplex not supported in requested configuration.",
1592                      __FUNCTION__);
1593                 return ret_val;
1594         }
1595
1596         /*                    Set MACCFG2                    */
1597         maccfg2 = in_be32(&ug_regs->maccfg2);
1598         maccfg2 &= ~MACCFG2_INTERFACE_MODE_MASK;
1599         if ((speed == ENET_SPEED_10BT) || (speed == ENET_SPEED_100BT))
1600                 maccfg2 |= MACCFG2_INTERFACE_MODE_NIBBLE;
1601         else if (speed == ENET_SPEED_1000BT)
1602                 maccfg2 |= MACCFG2_INTERFACE_MODE_BYTE;
1603         maccfg2 |= ug_info->padAndCrc;
1604         out_be32(&ug_regs->maccfg2, maccfg2);
1605
1606         /*                    Set UPSMR                      */
1607         upsmr = in_be32(&uf_regs->upsmr);
1608         upsmr &= ~(UPSMR_RPM | UPSMR_R10M | UPSMR_TBIM | UPSMR_RMM);
1609         if (rpm)
1610                 upsmr |= UPSMR_RPM;
1611         if (r10m)
1612                 upsmr |= UPSMR_R10M;
1613         if (tbi)
1614                 upsmr |= UPSMR_TBIM;
1615         if (rmm)
1616                 upsmr |= UPSMR_RMM;
1617         out_be32(&uf_regs->upsmr, upsmr);
1618
1619         /*                    Set UTBIPAR                    */
1620         utbipar = in_be32(&ug_regs->utbipar);
1621         utbipar &= ~UTBIPAR_PHY_ADDRESS_MASK;
1622         if (tbi)
1623                 utbipar |=
1624                     (ug_info->phy_address +
1625                      ugeth->ug_info->uf_info.
1626                      ucc_num) << UTBIPAR_PHY_ADDRESS_SHIFT;
1627         else
1628                 utbipar |=
1629                     (0x10 +
1630                      ugeth->ug_info->uf_info.
1631                      ucc_num) << UTBIPAR_PHY_ADDRESS_SHIFT;
1632         out_be32(&ug_regs->utbipar, utbipar);
1633
1634         /* Disable autonegotiation in tbi mode, because by default it
1635         comes up in autonegotiation mode. */
1636         /* Note that this depends on proper setting in utbipar register. */
1637         if (tbi) {
1638                 tbiBaseAddress = in_be32(&ug_regs->utbipar);
1639                 tbiBaseAddress &= UTBIPAR_PHY_ADDRESS_MASK;
1640                 tbiBaseAddress >>= UTBIPAR_PHY_ADDRESS_SHIFT;
1641                 value =
1642                     ugeth->mii_info->mdio_read(ugeth->dev, (u8) tbiBaseAddress,
1643                                                ENET_TBI_MII_CR);
1644                 value &= ~0x1000;       /* Turn off autonegotiation */
1645                 ugeth->mii_info->mdio_write(ugeth->dev, (u8) tbiBaseAddress,
1646                                             ENET_TBI_MII_CR, value);
1647         }
1648
1649         ret_val = init_mac_duplex_mode(1,
1650                                        limited_to_full_duplex,
1651                                        &ug_regs->maccfg2);
1652         if (ret_val != 0) {
1653                 ugeth_err
1654                 ("%s: half duplex not supported in requested configuration.",
1655                      __FUNCTION__);
1656                 return ret_val;
1657         }
1658
1659         init_check_frame_length_mode(ug_info->lengthCheckRx, &ug_regs->maccfg2);
1660
1661         ret_val = init_preamble_length(ug_info->prel, &ug_regs->maccfg2);
1662         if (ret_val != 0) {
1663                 ugeth_err
1664                     ("%s: Preamble length must be between 3 and 7 inclusive.",
1665                      __FUNCTION__);
1666                 return ret_val;
1667         }
1668
1669         return 0;
1670 }
1671
1672 /* Called every time the controller might need to be made
1673  * aware of new link state.  The PHY code conveys this
1674  * information through variables in the ugeth structure, and this
1675  * function converts those variables into the appropriate
1676  * register values, and can bring down the device if needed.
1677  */
1678 static void adjust_link(struct net_device *dev)
1679 {
1680         struct ucc_geth_private *ugeth = netdev_priv(dev);
1681         struct ucc_geth *ug_regs;
1682         u32 tempval;
1683         struct ugeth_mii_info *mii_info = ugeth->mii_info;
1684
1685         ug_regs = ugeth->ug_regs;
1686
1687         if (mii_info->link) {
1688                 /* Now we make sure that we can be in full duplex mode.
1689                  * If not, we operate in half-duplex mode. */
1690                 if (mii_info->duplex != ugeth->oldduplex) {
1691                         if (!(mii_info->duplex)) {
1692                                 tempval = in_be32(&ug_regs->maccfg2);
1693                                 tempval &= ~(MACCFG2_FDX);
1694                                 out_be32(&ug_regs->maccfg2, tempval);
1695
1696                                 ugeth_info("%s: Half Duplex", dev->name);
1697                         } else {
1698                                 tempval = in_be32(&ug_regs->maccfg2);
1699                                 tempval |= MACCFG2_FDX;
1700                                 out_be32(&ug_regs->maccfg2, tempval);
1701
1702                                 ugeth_info("%s: Full Duplex", dev->name);
1703                         }
1704
1705                         ugeth->oldduplex = mii_info->duplex;
1706                 }
1707
1708                 if (mii_info->speed != ugeth->oldspeed) {
1709                         switch (mii_info->speed) {
1710                         case 1000:
1711 #ifdef CONFIG_PPC_MPC836x
1712 /* FIXME: This code is for 100Mbs BUG fixing,
1713 remove this when it is fixed!!! */
1714                                 if (ugeth->ug_info->enet_interface ==
1715                                     ENET_1000_GMII)
1716                                 /* Run the commands which initialize the PHY */
1717                                 {
1718                                         tempval =
1719                                             (u32) mii_info->mdio_read(ugeth->
1720                                                 dev, mii_info->mii_id, 0x1b);
1721                                         tempval |= 0x000f;
1722                                         mii_info->mdio_write(ugeth->dev,
1723                                                 mii_info->mii_id, 0x1b,
1724                                                 (u16) tempval);
1725                                         tempval =
1726                                             (u32) mii_info->mdio_read(ugeth->
1727                                                 dev, mii_info->mii_id,
1728                                                 MII_BMCR);
1729                                         mii_info->mdio_write(ugeth->dev,
1730                                                 mii_info->mii_id, MII_BMCR,
1731                                                 (u16) (tempval | BMCR_RESET));
1732                                 } else if (ugeth->ug_info->enet_interface ==
1733                                            ENET_1000_RGMII)
1734                                 /* Run the commands which initialize the PHY */
1735                                 {
1736                                         tempval =
1737                                             (u32) mii_info->mdio_read(ugeth->
1738                                                 dev, mii_info->mii_id, 0x1b);
1739                                         tempval = (tempval & ~0x000f) | 0x000b;
1740                                         mii_info->mdio_write(ugeth->dev,
1741                                                 mii_info->mii_id, 0x1b,
1742                                                 (u16) tempval);
1743                                         tempval =
1744                                             (u32) mii_info->mdio_read(ugeth->
1745                                                 dev, mii_info->mii_id,
1746                                                 MII_BMCR);
1747                                         mii_info->mdio_write(ugeth->dev,
1748                                                 mii_info->mii_id, MII_BMCR,
1749                                                 (u16) (tempval | BMCR_RESET));
1750                                 }
1751                                 msleep(4000);
1752 #endif                          /* CONFIG_MPC8360 */
1753                                 adjust_enet_interface(ugeth);
1754                                 break;
1755                         case 100:
1756                         case 10:
1757 #ifdef CONFIG_PPC_MPC836x
1758 /* FIXME: This code is for 100Mbs BUG fixing,
1759 remove this lines when it will be fixed!!! */
1760                                 ugeth->ug_info->enet_interface = ENET_100_RGMII;
1761                                 tempval =
1762                                     (u32) mii_info->mdio_read(ugeth->dev,
1763                                                               mii_info->mii_id,
1764                                                               0x1b);
1765                                 tempval = (tempval & ~0x000f) | 0x000b;
1766                                 mii_info->mdio_write(ugeth->dev,
1767                                                      mii_info->mii_id, 0x1b,
1768                                                      (u16) tempval);
1769                                 tempval =
1770                                     (u32) mii_info->mdio_read(ugeth->dev,
1771                                                               mii_info->mii_id,
1772                                                               MII_BMCR);
1773                                 mii_info->mdio_write(ugeth->dev,
1774                                                      mii_info->mii_id, MII_BMCR,
1775                                                      (u16) (tempval |
1776                                                             BMCR_RESET));
1777                                 msleep(4000);
1778 #endif                          /* CONFIG_MPC8360 */
1779                                 adjust_enet_interface(ugeth);
1780                                 break;
1781                         default:
1782                                 ugeth_warn
1783                                     ("%s: Ack!  Speed (%d) is not 10/100/1000!",
1784                                      dev->name, mii_info->speed);
1785                                 break;
1786                         }
1787
1788                         ugeth_info("%s: Speed %dBT", dev->name,
1789                                    mii_info->speed);
1790
1791                         ugeth->oldspeed = mii_info->speed;
1792                 }
1793
1794                 if (!ugeth->oldlink) {
1795                         ugeth_info("%s: Link is up", dev->name);
1796                         ugeth->oldlink = 1;
1797                         netif_carrier_on(dev);
1798                         netif_schedule(dev);
1799                 }
1800         } else {
1801                 if (ugeth->oldlink) {
1802                         ugeth_info("%s: Link is down", dev->name);
1803                         ugeth->oldlink = 0;
1804                         ugeth->oldspeed = 0;
1805                         ugeth->oldduplex = -1;
1806                         netif_carrier_off(dev);
1807                 }
1808         }
1809 }
1810
1811 /* Configure the PHY for dev.
1812  * returns 0 if success.  -1 if failure
1813  */
1814 static int init_phy(struct net_device *dev)
1815 {
1816         struct ucc_geth_private *ugeth = netdev_priv(dev);
1817         struct phy_info *curphy;
1818         struct ucc_mii_mng *mii_regs;
1819         struct ugeth_mii_info *mii_info;
1820         int err;
1821
1822         mii_regs = &ugeth->ug_regs->miimng;
1823
1824         ugeth->oldlink = 0;
1825         ugeth->oldspeed = 0;
1826         ugeth->oldduplex = -1;
1827
1828         mii_info = kmalloc(sizeof(struct ugeth_mii_info), GFP_KERNEL);
1829
1830         if (NULL == mii_info) {
1831                 ugeth_err("%s: Could not allocate mii_info", dev->name);
1832                 return -ENOMEM;
1833         }
1834
1835         mii_info->mii_regs = mii_regs;
1836         mii_info->speed = SPEED_1000;
1837         mii_info->duplex = DUPLEX_FULL;
1838         mii_info->pause = 0;
1839         mii_info->link = 0;
1840
1841         mii_info->advertising = (ADVERTISED_10baseT_Half |
1842                                  ADVERTISED_10baseT_Full |
1843                                  ADVERTISED_100baseT_Half |
1844                                  ADVERTISED_100baseT_Full |
1845                                  ADVERTISED_1000baseT_Full);
1846         mii_info->autoneg = 1;
1847
1848         mii_info->mii_id = ugeth->ug_info->phy_address;
1849
1850         mii_info->dev = dev;
1851
1852         mii_info->mdio_read = &read_phy_reg;
1853         mii_info->mdio_write = &write_phy_reg;
1854
1855         spin_lock_init(&mii_info->mdio_lock);
1856
1857         ugeth->mii_info = mii_info;
1858
1859         spin_lock_irq(&ugeth->lock);
1860
1861         /* Set this UCC to be the master of the MII managment */
1862         ucc_set_qe_mux_mii_mng(ugeth->ug_info->uf_info.ucc_num);
1863
1864         if (init_mii_management_configuration(1,
1865                                               ugeth->ug_info->
1866                                               miiPreambleSupress,
1867                                               &mii_regs->miimcfg,
1868                                               &mii_regs->miimind)) {
1869                 ugeth_err("%s: The MII Bus is stuck!", dev->name);
1870                 err = -1;
1871                 goto bus_fail;
1872         }
1873
1874         spin_unlock_irq(&ugeth->lock);
1875
1876         /* get info for this PHY */
1877         curphy = get_phy_info(ugeth->mii_info);
1878
1879         if (curphy == NULL) {
1880                 ugeth_err("%s: No PHY found", dev->name);
1881                 err = -1;
1882                 goto no_phy;
1883         }
1884
1885         mii_info->phyinfo = curphy;
1886
1887         /* Run the commands which initialize the PHY */
1888         if (curphy->init) {
1889                 err = curphy->init(ugeth->mii_info);
1890                 if (err)
1891                         goto phy_init_fail;
1892         }
1893
1894         return 0;
1895
1896       phy_init_fail:
1897       no_phy:
1898       bus_fail:
1899         kfree(mii_info);
1900
1901         return err;
1902 }
1903
1904 #ifdef CONFIG_UGETH_TX_ON_DEMOND
1905 static int ugeth_transmit_on_demand(struct ucc_geth_private *ugeth)
1906 {
1907         struct ucc_fastransmit_on_demand(ugeth->uccf);
1908
1909         return 0;
1910 }
1911 #endif
1912
1913 static int ugeth_graceful_stop_tx(struct ucc_geth_private *ugeth)
1914 {
1915         struct ucc_fast_private *uccf;
1916         u32 cecr_subblock;
1917         u32 temp;
1918
1919         uccf = ugeth->uccf;
1920
1921         /* Mask GRACEFUL STOP TX interrupt bit and clear it */
1922         temp = in_be32(uccf->p_uccm);
1923         temp &= ~UCCE_GRA;
1924         out_be32(uccf->p_uccm, temp);
1925         out_be32(uccf->p_ucce, UCCE_GRA);       /* clear by writing 1 */
1926
1927         /* Issue host command */
1928         cecr_subblock =
1929             ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.ucc_num);
1930         qe_issue_cmd(QE_GRACEFUL_STOP_TX, cecr_subblock,
1931                      QE_CR_PROTOCOL_ETHERNET, 0);
1932
1933         /* Wait for command to complete */
1934         do {
1935                 temp = in_be32(uccf->p_ucce);
1936         } while (!(temp & UCCE_GRA));
1937
1938         uccf->stopped_tx = 1;
1939
1940         return 0;
1941 }
1942
1943 static int ugeth_graceful_stop_rx(struct ucc_geth_private * ugeth)
1944 {
1945         struct ucc_fast_private *uccf;
1946         u32 cecr_subblock;
1947         u8 temp;
1948
1949         uccf = ugeth->uccf;
1950
1951         /* Clear acknowledge bit */
1952         temp = ugeth->p_rx_glbl_pram->rxgstpack;
1953         temp &= ~GRACEFUL_STOP_ACKNOWLEDGE_RX;
1954         ugeth->p_rx_glbl_pram->rxgstpack = temp;
1955
1956         /* Keep issuing command and checking acknowledge bit until
1957         it is asserted, according to spec */
1958         do {
1959                 /* Issue host command */
1960                 cecr_subblock =
1961                     ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.
1962                                                 ucc_num);
1963                 qe_issue_cmd(QE_GRACEFUL_STOP_RX, cecr_subblock,
1964                              QE_CR_PROTOCOL_ETHERNET, 0);
1965
1966                 temp = ugeth->p_rx_glbl_pram->rxgstpack;
1967         } while (!(temp & GRACEFUL_STOP_ACKNOWLEDGE_RX));
1968
1969         uccf->stopped_rx = 1;
1970
1971         return 0;
1972 }
1973
1974 static int ugeth_restart_tx(struct ucc_geth_private *ugeth)
1975 {
1976         struct ucc_fast_private *uccf;
1977         u32 cecr_subblock;
1978
1979         uccf = ugeth->uccf;
1980
1981         cecr_subblock =
1982             ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.ucc_num);
1983         qe_issue_cmd(QE_RESTART_TX, cecr_subblock, QE_CR_PROTOCOL_ETHERNET, 0);
1984         uccf->stopped_tx = 0;
1985
1986         return 0;
1987 }
1988
1989 static int ugeth_restart_rx(struct ucc_geth_private *ugeth)
1990 {
1991         struct ucc_fast_private *uccf;
1992         u32 cecr_subblock;
1993
1994         uccf = ugeth->uccf;
1995
1996         cecr_subblock =
1997             ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.ucc_num);
1998         qe_issue_cmd(QE_RESTART_RX, cecr_subblock, QE_CR_PROTOCOL_ETHERNET,
1999                      0);
2000         uccf->stopped_rx = 0;
2001
2002         return 0;
2003 }
2004
2005 static int ugeth_enable(struct ucc_geth_private *ugeth, enum comm_dir mode)
2006 {
2007         struct ucc_fast_private *uccf;
2008         int enabled_tx, enabled_rx;
2009
2010         uccf = ugeth->uccf;
2011
2012         /* check if the UCC number is in range. */
2013         if (ugeth->ug_info->uf_info.ucc_num >= UCC_MAX_NUM) {
2014                 ugeth_err("%s: ucc_num out of range.", __FUNCTION__);
2015                 return -EINVAL;
2016         }
2017
2018         enabled_tx = uccf->enabled_tx;
2019         enabled_rx = uccf->enabled_rx;
2020
2021         /* Get Tx and Rx going again, in case this channel was actively
2022         disabled. */
2023         if ((mode & COMM_DIR_TX) && (!enabled_tx) && uccf->stopped_tx)
2024                 ugeth_restart_tx(ugeth);
2025         if ((mode & COMM_DIR_RX) && (!enabled_rx) && uccf->stopped_rx)
2026                 ugeth_restart_rx(ugeth);
2027
2028         ucc_fast_enable(uccf, mode);    /* OK to do even if not disabled */
2029
2030         return 0;
2031
2032 }
2033
2034 static int ugeth_disable(struct ucc_geth_private * ugeth, enum comm_dir mode)
2035 {
2036         struct ucc_fast_private *uccf;
2037
2038         uccf = ugeth->uccf;
2039
2040         /* check if the UCC number is in range. */
2041         if (ugeth->ug_info->uf_info.ucc_num >= UCC_MAX_NUM) {
2042                 ugeth_err("%s: ucc_num out of range.", __FUNCTION__);
2043                 return -EINVAL;
2044         }
2045
2046         /* Stop any transmissions */
2047         if ((mode & COMM_DIR_TX) && uccf->enabled_tx && !uccf->stopped_tx)
2048                 ugeth_graceful_stop_tx(ugeth);
2049
2050         /* Stop any receptions */
2051         if ((mode & COMM_DIR_RX) && uccf->enabled_rx && !uccf->stopped_rx)
2052                 ugeth_graceful_stop_rx(ugeth);
2053
2054         ucc_fast_disable(ugeth->uccf, mode); /* OK to do even if not enabled */
2055
2056         return 0;
2057 }
2058
2059 static void ugeth_dump_regs(struct ucc_geth_private *ugeth)
2060 {
2061 #ifdef DEBUG
2062         ucc_fast_dump_regs(ugeth->uccf);
2063         dump_regs(ugeth);
2064         dump_bds(ugeth);
2065 #endif
2066 }
2067
2068 #ifdef CONFIG_UGETH_FILTERING
2069 static int ugeth_ext_filtering_serialize_tad(struct ucc_geth_tad_params *
2070                                              p_UccGethTadParams,
2071                                              struct qe_fltr_tad *qe_fltr_tad)
2072 {
2073         u16 temp;
2074
2075         /* Zero serialized TAD */
2076         memset(qe_fltr_tad, 0, QE_FLTR_TAD_SIZE);
2077
2078         qe_fltr_tad->serialized[0] |= UCC_GETH_TAD_V;   /* Must have this */
2079         if (p_UccGethTadParams->rx_non_dynamic_extended_features_mode ||
2080             (p_UccGethTadParams->vtag_op != UCC_GETH_VLAN_OPERATION_TAGGED_NOP)
2081             || (p_UccGethTadParams->vnontag_op !=
2082                 UCC_GETH_VLAN_OPERATION_NON_TAGGED_NOP)
2083             )
2084                 qe_fltr_tad->serialized[0] |= UCC_GETH_TAD_EF;
2085         if (p_UccGethTadParams->reject_frame)
2086                 qe_fltr_tad->serialized[0] |= UCC_GETH_TAD_REJ;
2087         temp =
2088             (u16) (((u16) p_UccGethTadParams->
2089                     vtag_op) << UCC_GETH_TAD_VTAG_OP_SHIFT);
2090         qe_fltr_tad->serialized[0] |= (u8) (temp >> 8); /* upper bits */
2091
2092         qe_fltr_tad->serialized[1] |= (u8) (temp & 0x00ff);     /* lower bits */
2093         if (p_UccGethTadParams->vnontag_op ==
2094             UCC_GETH_VLAN_OPERATION_NON_TAGGED_Q_TAG_INSERT)
2095                 qe_fltr_tad->serialized[1] |= UCC_GETH_TAD_V_NON_VTAG_OP;
2096         qe_fltr_tad->serialized[1] |=
2097             p_UccGethTadParams->rqos << UCC_GETH_TAD_RQOS_SHIFT;
2098
2099         qe_fltr_tad->serialized[2] |=
2100             p_UccGethTadParams->vpri << UCC_GETH_TAD_V_PRIORITY_SHIFT;
2101         /* upper bits */
2102         qe_fltr_tad->serialized[2] |= (u8) (p_UccGethTadParams->vid >> 8);
2103         /* lower bits */
2104         qe_fltr_tad->serialized[3] |= (u8) (p_UccGethTadParams->vid & 0x00ff);
2105
2106         return 0;
2107 }
2108
2109 static struct enet_addr_container_t
2110     *ugeth_82xx_filtering_get_match_addr_in_hash(struct ucc_geth_private *ugeth,
2111                                                  struct enet_addr *p_enet_addr)
2112 {
2113         struct enet_addr_container *enet_addr_cont;
2114         struct list_head *p_lh;
2115         u16 i, num;
2116         int32_t j;
2117         u8 *p_counter;
2118
2119         if ((*p_enet_addr)[0] & ENET_GROUP_ADDR) {
2120                 p_lh = &ugeth->group_hash_q;
2121                 p_counter = &(ugeth->numGroupAddrInHash);
2122         } else {
2123                 p_lh = &ugeth->ind_hash_q;
2124                 p_counter = &(ugeth->numIndAddrInHash);
2125         }
2126
2127         if (!p_lh)
2128                 return NULL;
2129
2130         num = *p_counter;
2131
2132         for (i = 0; i < num; i++) {
2133                 enet_addr_cont =
2134                     (struct enet_addr_container *)
2135                     ENET_ADDR_CONT_ENTRY(dequeue(p_lh));
2136                 for (j = ENET_NUM_OCTETS_PER_ADDRESS - 1; j >= 0; j--) {
2137                         if ((*p_enet_addr)[j] != (enet_addr_cont->address)[j])
2138                                 break;
2139                         if (j == 0)
2140                                 return enet_addr_cont;  /* Found */
2141                 }
2142                 enqueue(p_lh, &enet_addr_cont->node);   /* Put it back */
2143         }
2144         return NULL;
2145 }
2146
2147 static int ugeth_82xx_filtering_add_addr_in_hash(struct ucc_geth_private *ugeth,
2148                                                  struct enet_addr *p_enet_addr)
2149 {
2150         enum ucc_geth_enet_address_recognition_location location;
2151         struct enet_addr_container *enet_addr_cont;
2152         struct list_head *p_lh;
2153         u8 i;
2154         u32 limit;
2155         u8 *p_counter;
2156
2157         if ((*p_enet_addr)[0] & ENET_GROUP_ADDR) {
2158                 p_lh = &ugeth->group_hash_q;
2159                 limit = ugeth->ug_info->maxGroupAddrInHash;
2160                 location =
2161                     UCC_GETH_ENET_ADDRESS_RECOGNITION_LOCATION_GROUP_HASH;
2162                 p_counter = &(ugeth->numGroupAddrInHash);
2163         } else {
2164                 p_lh = &ugeth->ind_hash_q;
2165                 limit = ugeth->ug_info->maxIndAddrInHash;
2166                 location =
2167                     UCC_GETH_ENET_ADDRESS_RECOGNITION_LOCATION_INDIVIDUAL_HASH;
2168                 p_counter = &(ugeth->numIndAddrInHash);
2169         }
2170
2171         if ((enet_addr_cont =
2172              ugeth_82xx_filtering_get_match_addr_in_hash(ugeth, p_enet_addr))) {
2173                 list_add(p_lh, &enet_addr_cont->node);  /* Put it back */
2174                 return 0;
2175         }
2176         if ((!p_lh) || (!(*p_counter < limit)))
2177                 return -EBUSY;
2178         if (!(enet_addr_cont = get_enet_addr_container()))
2179                 return -ENOMEM;
2180         for (i = 0; i < ENET_NUM_OCTETS_PER_ADDRESS; i++)
2181                 (enet_addr_cont->address)[i] = (*p_enet_addr)[i];
2182         enet_addr_cont->location = location;
2183         enqueue(p_lh, &enet_addr_cont->node);   /* Put it back */
2184         ++(*p_counter);
2185
2186         hw_add_addr_in_hash(ugeth, enet_addr_cont->address);
2187         return 0;
2188 }
2189
2190 static int ugeth_82xx_filtering_clear_addr_in_hash(struct ucc_geth_private *ugeth,
2191                                                    struct enet_addr *p_enet_addr)
2192 {
2193         struct ucc_geth_82xx_address_filtering_pram *p_82xx_addr_filt;
2194         struct enet_addr_container *enet_addr_cont;
2195         struct ucc_fast_private *uccf;
2196         enum comm_dir comm_dir;
2197         u16 i, num;
2198         struct list_head *p_lh;
2199         u32 *addr_h, *addr_l;
2200         u8 *p_counter;
2201
2202         uccf = ugeth->uccf;
2203
2204         p_82xx_addr_filt =
2205             (struct ucc_geth_82xx_address_filtering_pram *) ugeth->p_rx_glbl_pram->
2206             addressfiltering;
2207
2208         if (!
2209             (enet_addr_cont =
2210              ugeth_82xx_filtering_get_match_addr_in_hash(ugeth, p_enet_addr)))
2211                 return -ENOENT;
2212
2213         /* It's been found and removed from the CQ. */
2214         /* Now destroy its container */
2215         put_enet_addr_container(enet_addr_cont);
2216
2217         if ((*p_enet_addr)[0] & ENET_GROUP_ADDR) {
2218                 addr_h = &(p_82xx_addr_filt->gaddr_h);
2219                 addr_l = &(p_82xx_addr_filt->gaddr_l);
2220                 p_lh = &ugeth->group_hash_q;
2221                 p_counter = &(ugeth->numGroupAddrInHash);
2222         } else {
2223                 addr_h = &(p_82xx_addr_filt->iaddr_h);
2224                 addr_l = &(p_82xx_addr_filt->iaddr_l);
2225                 p_lh = &ugeth->ind_hash_q;
2226                 p_counter = &(ugeth->numIndAddrInHash);
2227         }
2228
2229         comm_dir = 0;
2230         if (uccf->enabled_tx)
2231                 comm_dir |= COMM_DIR_TX;
2232         if (uccf->enabled_rx)
2233                 comm_dir |= COMM_DIR_RX;
2234         if (comm_dir)
2235                 ugeth_disable(ugeth, comm_dir);
2236
2237         /* Clear the hash table. */
2238         out_be32(addr_h, 0x00000000);
2239         out_be32(addr_l, 0x00000000);
2240
2241         /* Add all remaining CQ elements back into hash */
2242         num = --(*p_counter);
2243         for (i = 0; i < num; i++) {
2244                 enet_addr_cont =
2245                     (struct enet_addr_container *)
2246                     ENET_ADDR_CONT_ENTRY(dequeue(p_lh));
2247                 hw_add_addr_in_hash(ugeth, enet_addr_cont->address);
2248                 enqueue(p_lh, &enet_addr_cont->node);   /* Put it back */
2249         }
2250
2251         if (comm_dir)
2252                 ugeth_enable(ugeth, comm_dir);
2253
2254         return 0;
2255 }
2256 #endif /* CONFIG_UGETH_FILTERING */
2257
2258 static int ugeth_82xx_filtering_clear_all_addr_in_hash(struct ucc_geth_private *
2259                                                        ugeth,
2260                                                        enum enet_addr_type
2261                                                        enet_addr_type)
2262 {
2263         struct ucc_geth_82xx_address_filtering_pram *p_82xx_addr_filt;
2264         struct ucc_fast_private *uccf;
2265         enum comm_dir comm_dir;
2266         struct list_head *p_lh;
2267         u16 i, num;
2268         u32 *addr_h, *addr_l;
2269         u8 *p_counter;
2270
2271         uccf = ugeth->uccf;
2272
2273         p_82xx_addr_filt =
2274             (struct ucc_geth_82xx_address_filtering_pram *) ugeth->p_rx_glbl_pram->
2275             addressfiltering;
2276
2277         if (enet_addr_type == ENET_ADDR_TYPE_GROUP) {
2278                 addr_h = &(p_82xx_addr_filt->gaddr_h);
2279                 addr_l = &(p_82xx_addr_filt->gaddr_l);
2280                 p_lh = &ugeth->group_hash_q;
2281                 p_counter = &(ugeth->numGroupAddrInHash);
2282         } else if (enet_addr_type == ENET_ADDR_TYPE_INDIVIDUAL) {
2283                 addr_h = &(p_82xx_addr_filt->iaddr_h);
2284                 addr_l = &(p_82xx_addr_filt->iaddr_l);
2285                 p_lh = &ugeth->ind_hash_q;
2286                 p_counter = &(ugeth->numIndAddrInHash);
2287         } else
2288                 return -EINVAL;
2289
2290         comm_dir = 0;
2291         if (uccf->enabled_tx)
2292                 comm_dir |= COMM_DIR_TX;
2293         if (uccf->enabled_rx)
2294                 comm_dir |= COMM_DIR_RX;
2295         if (comm_dir)
2296                 ugeth_disable(ugeth, comm_dir);
2297
2298         /* Clear the hash table. */
2299         out_be32(addr_h, 0x00000000);
2300         out_be32(addr_l, 0x00000000);
2301
2302         if (!p_lh)
2303                 return 0;
2304
2305         num = *p_counter;
2306
2307         /* Delete all remaining CQ elements */
2308         for (i = 0; i < num; i++)
2309                 put_enet_addr_container(ENET_ADDR_CONT_ENTRY(dequeue(p_lh)));
2310
2311         *p_counter = 0;
2312
2313         if (comm_dir)
2314                 ugeth_enable(ugeth, comm_dir);
2315
2316         return 0;
2317 }
2318
2319 #ifdef CONFIG_UGETH_FILTERING
2320 static int ugeth_82xx_filtering_add_addr_in_paddr(struct ucc_geth_private *ugeth,
2321                                                   struct enet_addr *p_enet_addr,
2322                                                   u8 paddr_num)
2323 {
2324         int i;
2325
2326         if ((*p_enet_addr)[0] & ENET_GROUP_ADDR)
2327                 ugeth_warn
2328                     ("%s: multicast address added to paddr will have no "
2329                      "effect - is this what you wanted?",
2330                      __FUNCTION__);
2331
2332         ugeth->indAddrRegUsed[paddr_num] = 1;   /* mark this paddr as used */
2333         /* store address in our database */
2334         for (i = 0; i < ENET_NUM_OCTETS_PER_ADDRESS; i++)
2335                 ugeth->paddr[paddr_num][i] = (*p_enet_addr)[i];
2336         /* put in hardware */
2337         return hw_add_addr_in_paddr(ugeth, p_enet_addr, paddr_num);
2338 }
2339 #endif /* CONFIG_UGETH_FILTERING */
2340
2341 static int ugeth_82xx_filtering_clear_addr_in_paddr(struct ucc_geth_private *ugeth,
2342                                                     u8 paddr_num)
2343 {
2344         ugeth->indAddrRegUsed[paddr_num] = 0; /* mark this paddr as not used */
2345         return hw_clear_addr_in_paddr(ugeth, paddr_num);/* clear in hardware */
2346 }
2347
2348 static void ucc_geth_memclean(struct ucc_geth_private *ugeth)
2349 {
2350         u16 i, j;
2351         u8 *bd;
2352
2353         if (!ugeth)
2354                 return;
2355
2356         if (ugeth->uccf)
2357                 ucc_fast_free(ugeth->uccf);
2358
2359         if (ugeth->p_thread_data_tx) {
2360                 qe_muram_free(ugeth->thread_dat_tx_offset);
2361                 ugeth->p_thread_data_tx = NULL;
2362         }
2363         if (ugeth->p_thread_data_rx) {
2364                 qe_muram_free(ugeth->thread_dat_rx_offset);
2365                 ugeth->p_thread_data_rx = NULL;
2366         }
2367         if (ugeth->p_exf_glbl_param) {
2368                 qe_muram_free(ugeth->exf_glbl_param_offset);
2369                 ugeth->p_exf_glbl_param = NULL;
2370         }
2371         if (ugeth->p_rx_glbl_pram) {
2372                 qe_muram_free(ugeth->rx_glbl_pram_offset);
2373                 ugeth->p_rx_glbl_pram = NULL;
2374         }
2375         if (ugeth->p_tx_glbl_pram) {
2376                 qe_muram_free(ugeth->tx_glbl_pram_offset);
2377                 ugeth->p_tx_glbl_pram = NULL;
2378         }
2379         if (ugeth->p_send_q_mem_reg) {
2380                 qe_muram_free(ugeth->send_q_mem_reg_offset);
2381                 ugeth->p_send_q_mem_reg = NULL;
2382         }
2383         if (ugeth->p_scheduler) {
2384                 qe_muram_free(ugeth->scheduler_offset);
2385                 ugeth->p_scheduler = NULL;
2386         }
2387         if (ugeth->p_tx_fw_statistics_pram) {
2388                 qe_muram_free(ugeth->tx_fw_statistics_pram_offset);
2389                 ugeth->p_tx_fw_statistics_pram = NULL;
2390         }
2391         if (ugeth->p_rx_fw_statistics_pram) {
2392                 qe_muram_free(ugeth->rx_fw_statistics_pram_offset);
2393                 ugeth->p_rx_fw_statistics_pram = NULL;
2394         }
2395         if (ugeth->p_rx_irq_coalescing_tbl) {
2396                 qe_muram_free(ugeth->rx_irq_coalescing_tbl_offset);
2397                 ugeth->p_rx_irq_coalescing_tbl = NULL;
2398         }
2399         if (ugeth->p_rx_bd_qs_tbl) {
2400                 qe_muram_free(ugeth->rx_bd_qs_tbl_offset);
2401                 ugeth->p_rx_bd_qs_tbl = NULL;
2402         }
2403         if (ugeth->p_init_enet_param_shadow) {
2404                 return_init_enet_entries(ugeth,
2405                                          &(ugeth->p_init_enet_param_shadow->
2406                                            rxthread[0]),
2407                                          ENET_INIT_PARAM_MAX_ENTRIES_RX,
2408                                          ugeth->ug_info->riscRx, 1);
2409                 return_init_enet_entries(ugeth,
2410                                          &(ugeth->p_init_enet_param_shadow->
2411                                            txthread[0]),
2412                                          ENET_INIT_PARAM_MAX_ENTRIES_TX,
2413                                          ugeth->ug_info->riscTx, 0);
2414                 kfree(ugeth->p_init_enet_param_shadow);
2415                 ugeth->p_init_enet_param_shadow = NULL;
2416         }
2417         for (i = 0; i < ugeth->ug_info->numQueuesTx; i++) {
2418                 bd = ugeth->p_tx_bd_ring[i];
2419                 for (j = 0; j < ugeth->ug_info->bdRingLenTx[i]; j++) {
2420                         if (ugeth->tx_skbuff[i][j]) {
2421                                 dma_unmap_single(NULL,
2422                                                  ((qe_bd_t *)bd)->buf,
2423                                                  (in_be32((u32 *)bd) &
2424                                                   BD_LENGTH_MASK),
2425                                                  DMA_TO_DEVICE);
2426                                 dev_kfree_skb_any(ugeth->tx_skbuff[i][j]);
2427                                 ugeth->tx_skbuff[i][j] = NULL;
2428                         }
2429                 }
2430
2431                 kfree(ugeth->tx_skbuff[i]);
2432
2433                 if (ugeth->p_tx_bd_ring[i]) {
2434                         if (ugeth->ug_info->uf_info.bd_mem_part ==
2435                             MEM_PART_SYSTEM)
2436                                 kfree((void *)ugeth->tx_bd_ring_offset[i]);
2437                         else if (ugeth->ug_info->uf_info.bd_mem_part ==
2438                                  MEM_PART_MURAM)
2439                                 qe_muram_free(ugeth->tx_bd_ring_offset[i]);
2440                         ugeth->p_tx_bd_ring[i] = NULL;
2441                 }
2442         }
2443         for (i = 0; i < ugeth->ug_info->numQueuesRx; i++) {
2444                 if (ugeth->p_rx_bd_ring[i]) {
2445                         /* Return existing data buffers in ring */
2446                         bd = ugeth->p_rx_bd_ring[i];
2447                         for (j = 0; j < ugeth->ug_info->bdRingLenRx[i]; j++) {
2448                                 if (ugeth->rx_skbuff[i][j]) {
2449                                         dma_unmap_single(NULL,
2450                                                 ((struct qe_bd *)bd)->buf,
2451                                                 ugeth->ug_info->
2452                                                 uf_info.max_rx_buf_length +
2453                                                 UCC_GETH_RX_DATA_BUF_ALIGNMENT,
2454                                                 DMA_FROM_DEVICE);
2455                                         dev_kfree_skb_any(
2456                                                 ugeth->rx_skbuff[i][j]);
2457                                         ugeth->rx_skbuff[i][j] = NULL;
2458                                 }
2459                                 bd += sizeof(struct qe_bd);
2460                         }
2461
2462                         kfree(ugeth->rx_skbuff[i]);
2463
2464                         if (ugeth->ug_info->uf_info.bd_mem_part ==
2465                             MEM_PART_SYSTEM)
2466                                 kfree((void *)ugeth->rx_bd_ring_offset[i]);
2467                         else if (ugeth->ug_info->uf_info.bd_mem_part ==
2468                                  MEM_PART_MURAM)
2469                                 qe_muram_free(ugeth->rx_bd_ring_offset[i]);
2470                         ugeth->p_rx_bd_ring[i] = NULL;
2471                 }
2472         }
2473         while (!list_empty(&ugeth->group_hash_q))
2474                 put_enet_addr_container(ENET_ADDR_CONT_ENTRY
2475                                         (dequeue(&ugeth->group_hash_q)));
2476         while (!list_empty(&ugeth->ind_hash_q))
2477                 put_enet_addr_container(ENET_ADDR_CONT_ENTRY
2478                                         (dequeue(&ugeth->ind_hash_q)));
2479
2480 }
2481
2482 static void ucc_geth_set_multi(struct net_device *dev)
2483 {
2484         struct ucc_geth_private *ugeth;
2485         struct dev_mc_list *dmi;
2486         struct ucc_fast *uf_regs;
2487         struct ucc_geth_82xx_address_filtering_pram *p_82xx_addr_filt;
2488         u8 tempaddr[6];
2489         u8 *mcptr, *tdptr;
2490         int i, j;
2491
2492         ugeth = netdev_priv(dev);
2493
2494         uf_regs = ugeth->uccf->uf_regs;
2495
2496         if (dev->flags & IFF_PROMISC) {
2497
2498                 uf_regs->upsmr |= UPSMR_PRO;
2499
2500         } else {
2501
2502                 uf_regs->upsmr &= ~UPSMR_PRO;
2503
2504                 p_82xx_addr_filt =
2505                     (struct ucc_geth_82xx_address_filtering_pram *) ugeth->
2506                     p_rx_glbl_pram->addressfiltering;
2507
2508                 if (dev->flags & IFF_ALLMULTI) {
2509                         /* Catch all multicast addresses, so set the
2510                          * filter to all 1's.
2511                          */
2512                         out_be32(&p_82xx_addr_filt->gaddr_h, 0xffffffff);
2513                         out_be32(&p_82xx_addr_filt->gaddr_l, 0xffffffff);
2514                 } else {
2515                         /* Clear filter and add the addresses in the list.
2516                          */
2517                         out_be32(&p_82xx_addr_filt->gaddr_h, 0x0);
2518                         out_be32(&p_82xx_addr_filt->gaddr_l, 0x0);
2519
2520                         dmi = dev->mc_list;
2521
2522                         for (i = 0; i < dev->mc_count; i++, dmi = dmi->next) {
2523
2524                                 /* Only support group multicast for now.
2525                                  */
2526                                 if (!(dmi->dmi_addr[0] & 1))
2527                                         continue;
2528
2529                                 /* The address in dmi_addr is LSB first,
2530                                  * and taddr is MSB first.  We have to
2531                                  * copy bytes MSB first from dmi_addr.
2532                                  */
2533                                 mcptr = (u8 *) dmi->dmi_addr + 5;
2534                                 tdptr = (u8 *) tempaddr;
2535                                 for (j = 0; j < 6; j++)
2536                                         *tdptr++ = *mcptr--;
2537
2538                                 /* Ask CPM to run CRC and set bit in
2539                                  * filter mask.
2540                                  */
2541                                 hw_add_addr_in_hash(ugeth, tempaddr);
2542                         }
2543                 }
2544         }
2545 }
2546
2547 static void ucc_geth_stop(struct ucc_geth_private *ugeth)
2548 {
2549         struct ucc_geth *ug_regs = ugeth->ug_regs;
2550         u32 tempval;
2551
2552         ugeth_vdbg("%s: IN", __FUNCTION__);
2553
2554         /* Disable the controller */
2555         ugeth_disable(ugeth, COMM_DIR_RX_AND_TX);
2556
2557         /* Tell the kernel the link is down */
2558         ugeth->mii_info->link = 0;
2559         adjust_link(ugeth->dev);
2560
2561         /* Mask all interrupts */
2562         out_be32(ugeth->uccf->p_ucce, 0x00000000);
2563
2564         /* Clear all interrupts */
2565         out_be32(ugeth->uccf->p_ucce, 0xffffffff);
2566
2567         /* Disable Rx and Tx */
2568         tempval = in_be32(&ug_regs->maccfg1);
2569         tempval &= ~(MACCFG1_ENABLE_RX | MACCFG1_ENABLE_TX);
2570         out_be32(&ug_regs->maccfg1, tempval);
2571
2572         if (ugeth->ug_info->board_flags & FSL_UGETH_BRD_HAS_PHY_INTR) {
2573                 /* Clear any pending interrupts */
2574                 mii_clear_phy_interrupt(ugeth->mii_info);
2575
2576                 /* Disable PHY Interrupts */
2577                 mii_configure_phy_interrupt(ugeth->mii_info,
2578                                             MII_INTERRUPT_DISABLED);
2579         }
2580
2581         free_irq(ugeth->ug_info->uf_info.irq, ugeth->dev);
2582
2583         if (ugeth->ug_info->board_flags & FSL_UGETH_BRD_HAS_PHY_INTR) {
2584                 free_irq(ugeth->ug_info->phy_interrupt, ugeth->dev);
2585         } else {
2586                 del_timer_sync(&ugeth->phy_info_timer);
2587         }
2588
2589         ucc_geth_memclean(ugeth);
2590 }
2591
2592 static int ucc_geth_startup(struct ucc_geth_private *ugeth)
2593 {
2594         struct ucc_geth_82xx_address_filtering_pram *p_82xx_addr_filt;
2595         struct ucc_geth_init_pram *p_init_enet_pram;
2596         struct ucc_fast_private *uccf;
2597         struct ucc_geth_info *ug_info;
2598         struct ucc_fast_info *uf_info;
2599         struct ucc_fast *uf_regs;
2600         struct ucc_geth *ug_regs;
2601         int ret_val = -EINVAL;
2602         u32 remoder = UCC_GETH_REMODER_INIT;
2603         u32 init_enet_pram_offset, cecr_subblock, command, maccfg1;
2604         u32 ifstat, i, j, size, l2qt, l3qt, length;
2605         u16 temoder = UCC_GETH_TEMODER_INIT;
2606         u16 test;
2607         u8 function_code = 0;
2608         u8 *bd, *endOfRing;
2609         u8 numThreadsRxNumerical, numThreadsTxNumerical;
2610
2611         ugeth_vdbg("%s: IN", __FUNCTION__);
2612
2613         ug_info = ugeth->ug_info;
2614         uf_info = &ug_info->uf_info;
2615
2616         if (!((uf_info->bd_mem_part == MEM_PART_SYSTEM) ||
2617               (uf_info->bd_mem_part == MEM_PART_MURAM))) {
2618                 ugeth_err("%s: Bad memory partition value.", __FUNCTION__);
2619                 return -EINVAL;
2620         }
2621
2622         /* Rx BD lengths */
2623         for (i = 0; i < ug_info->numQueuesRx; i++) {
2624                 if ((ug_info->bdRingLenRx[i] < UCC_GETH_RX_BD_RING_SIZE_MIN) ||
2625                     (ug_info->bdRingLenRx[i] %
2626                      UCC_GETH_RX_BD_RING_SIZE_ALIGNMENT)) {
2627                         ugeth_err
2628                             ("%s: Rx BD ring length must be multiple of 4,"
2629                                 " no smaller than 8.", __FUNCTION__);
2630                         return -EINVAL;
2631                 }
2632         }
2633
2634         /* Tx BD lengths */
2635         for (i = 0; i < ug_info->numQueuesTx; i++) {
2636                 if (ug_info->bdRingLenTx[i] < UCC_GETH_TX_BD_RING_SIZE_MIN) {
2637                         ugeth_err
2638                             ("%s: Tx BD ring length must be no smaller than 2.",
2639                              __FUNCTION__);
2640                         return -EINVAL;
2641                 }
2642         }
2643
2644         /* mrblr */
2645         if ((uf_info->max_rx_buf_length == 0) ||
2646             (uf_info->max_rx_buf_length % UCC_GETH_MRBLR_ALIGNMENT)) {
2647                 ugeth_err
2648                     ("%s: max_rx_buf_length must be non-zero multiple of 128.",
2649                      __FUNCTION__);
2650                 return -EINVAL;
2651         }
2652
2653         /* num Tx queues */
2654         if (ug_info->numQueuesTx > NUM_TX_QUEUES) {
2655                 ugeth_err("%s: number of tx queues too large.", __FUNCTION__);
2656                 return -EINVAL;
2657         }
2658
2659         /* num Rx queues */
2660         if (ug_info->numQueuesRx > NUM_RX_QUEUES) {
2661                 ugeth_err("%s: number of rx queues too large.", __FUNCTION__);
2662                 return -EINVAL;
2663         }
2664
2665         /* l2qt */
2666         for (i = 0; i < UCC_GETH_VLAN_PRIORITY_MAX; i++) {
2667                 if (ug_info->l2qt[i] >= ug_info->numQueuesRx) {
2668                         ugeth_err
2669                             ("%s: VLAN priority table entry must not be"
2670                                 " larger than number of Rx queues.",
2671                              __FUNCTION__);
2672                         return -EINVAL;
2673                 }
2674         }
2675
2676         /* l3qt */
2677         for (i = 0; i < UCC_GETH_IP_PRIORITY_MAX; i++) {
2678                 if (ug_info->l3qt[i] >= ug_info->numQueuesRx) {
2679                         ugeth_err
2680                             ("%s: IP priority table entry must not be"
2681                                 " larger than number of Rx queues.",
2682                              __FUNCTION__);
2683                         return -EINVAL;
2684                 }
2685         }
2686
2687         if (ug_info->cam && !ug_info->ecamptr) {
2688                 ugeth_err("%s: If cam mode is chosen, must supply cam ptr.",
2689                           __FUNCTION__);
2690                 return -EINVAL;
2691         }
2692
2693         if ((ug_info->numStationAddresses !=
2694              UCC_GETH_NUM_OF_STATION_ADDRESSES_1)
2695             && ug_info->rxExtendedFiltering) {
2696                 ugeth_err("%s: Number of station addresses greater than 1 "
2697                           "not allowed in extended parsing mode.",
2698                           __FUNCTION__);
2699                 return -EINVAL;
2700         }
2701
2702         /* Generate uccm_mask for receive */
2703         uf_info->uccm_mask = ug_info->eventRegMask & UCCE_OTHER;/* Errors */
2704         for (i = 0; i < ug_info->numQueuesRx; i++)
2705                 uf_info->uccm_mask |= (UCCE_RXBF_SINGLE_MASK << i);
2706
2707         for (i = 0; i < ug_info->numQueuesTx; i++)
2708                 uf_info->uccm_mask |= (UCCE_TXBF_SINGLE_MASK << i);
2709         /* Initialize the general fast UCC block. */
2710         if (ucc_fast_init(uf_info, &uccf)) {
2711                 ugeth_err("%s: Failed to init uccf.", __FUNCTION__);
2712                 ucc_geth_memclean(ugeth);
2713                 return -ENOMEM;
2714         }
2715         ugeth->uccf = uccf;
2716
2717         switch (ug_info->numThreadsRx) {
2718         case UCC_GETH_NUM_OF_THREADS_1:
2719                 numThreadsRxNumerical = 1;
2720                 break;
2721         case UCC_GETH_NUM_OF_THREADS_2:
2722                 numThreadsRxNumerical = 2;
2723                 break;
2724         case UCC_GETH_NUM_OF_THREADS_4:
2725                 numThreadsRxNumerical = 4;
2726                 break;
2727         case UCC_GETH_NUM_OF_THREADS_6:
2728                 numThreadsRxNumerical = 6;
2729                 break;
2730         case UCC_GETH_NUM_OF_THREADS_8:
2731                 numThreadsRxNumerical = 8;
2732                 break;
2733         default:
2734                 ugeth_err("%s: Bad number of Rx threads value.", __FUNCTION__);
2735                 ucc_geth_memclean(ugeth);
2736                 return -EINVAL;
2737                 break;
2738         }
2739
2740         switch (ug_info->numThreadsTx) {
2741         case UCC_GETH_NUM_OF_THREADS_1:
2742                 numThreadsTxNumerical = 1;
2743                 break;
2744         case UCC_GETH_NUM_OF_THREADS_2:
2745                 numThreadsTxNumerical = 2;
2746                 break;
2747         case UCC_GETH_NUM_OF_THREADS_4:
2748                 numThreadsTxNumerical = 4;
2749                 break;
2750         case UCC_GETH_NUM_OF_THREADS_6:
2751                 numThreadsTxNumerical = 6;
2752                 break;
2753         case UCC_GETH_NUM_OF_THREADS_8:
2754                 numThreadsTxNumerical = 8;
2755                 break;
2756         default:
2757                 ugeth_err("%s: Bad number of Tx threads value.", __FUNCTION__);
2758                 ucc_geth_memclean(ugeth);
2759                 return -EINVAL;
2760                 break;
2761         }
2762
2763         /* Calculate rx_extended_features */
2764         ugeth->rx_non_dynamic_extended_features = ug_info->ipCheckSumCheck ||
2765             ug_info->ipAddressAlignment ||
2766             (ug_info->numStationAddresses !=
2767              UCC_GETH_NUM_OF_STATION_ADDRESSES_1);
2768
2769         ugeth->rx_extended_features = ugeth->rx_non_dynamic_extended_features ||
2770             (ug_info->vlanOperationTagged != UCC_GETH_VLAN_OPERATION_TAGGED_NOP)
2771             || (ug_info->vlanOperationNonTagged !=
2772                 UCC_GETH_VLAN_OPERATION_NON_TAGGED_NOP);
2773
2774         uf_regs = uccf->uf_regs;
2775         ug_regs = (struct ucc_geth *) (uccf->uf_regs);
2776         ugeth->ug_regs = ug_regs;
2777
2778         init_default_reg_vals(&uf_regs->upsmr,
2779                               &ug_regs->maccfg1, &ug_regs->maccfg2);
2780
2781         /*                    Set UPSMR                      */
2782         /* For more details see the hardware spec.           */
2783         init_rx_parameters(ug_info->bro,
2784                            ug_info->rsh, ug_info->pro, &uf_regs->upsmr);
2785
2786         /* We're going to ignore other registers for now, */
2787         /* except as needed to get up and running         */
2788
2789         /*                    Set MACCFG1                    */
2790         /* For more details see the hardware spec.           */
2791         init_flow_control_params(ug_info->aufc,
2792                                  ug_info->receiveFlowControl,
2793                                  1,
2794                                  ug_info->pausePeriod,
2795                                  ug_info->extensionField,
2796                                  &uf_regs->upsmr,
2797                                  &ug_regs->uempr, &ug_regs->maccfg1);
2798
2799         maccfg1 = in_be32(&ug_regs->maccfg1);
2800         maccfg1 |= MACCFG1_ENABLE_RX;
2801         maccfg1 |= MACCFG1_ENABLE_TX;
2802         out_be32(&ug_regs->maccfg1, maccfg1);
2803
2804         /*                    Set IPGIFG                     */
2805         /* For more details see the hardware spec.           */
2806         ret_val = init_inter_frame_gap_params(ug_info->nonBackToBackIfgPart1,
2807                                               ug_info->nonBackToBackIfgPart2,
2808                                               ug_info->
2809                                               miminumInterFrameGapEnforcement,
2810                                               ug_info->backToBackInterFrameGap,
2811                                               &ug_regs->ipgifg);
2812         if (ret_val != 0) {
2813                 ugeth_err("%s: IPGIFG initialization parameter too large.",
2814                           __FUNCTION__);
2815                 ucc_geth_memclean(ugeth);
2816                 return ret_val;
2817         }
2818
2819         /*                    Set HAFDUP                     */
2820         /* For more details see the hardware spec.           */
2821         ret_val = init_half_duplex_params(ug_info->altBeb,
2822                                           ug_info->backPressureNoBackoff,
2823                                           ug_info->noBackoff,
2824                                           ug_info->excessDefer,
2825                                           ug_info->altBebTruncation,
2826                                           ug_info->maxRetransmission,
2827                                           ug_info->collisionWindow,
2828                                           &ug_regs->hafdup);
2829         if (ret_val != 0) {
2830                 ugeth_err("%s: Half Duplex initialization parameter too large.",
2831                           __FUNCTION__);
2832                 ucc_geth_memclean(ugeth);
2833                 return ret_val;
2834         }
2835
2836         /*                    Set IFSTAT                     */
2837         /* For more details see the hardware spec.           */
2838         /* Read only - resets upon read                      */
2839         ifstat = in_be32(&ug_regs->ifstat);
2840
2841         /*                    Clear UEMPR                    */
2842         /* For more details see the hardware spec.           */
2843         out_be32(&ug_regs->uempr, 0);
2844
2845         /*                    Set UESCR                      */
2846         /* For more details see the hardware spec.           */
2847         init_hw_statistics_gathering_mode((ug_info->statisticsMode &
2848                                 UCC_GETH_STATISTICS_GATHERING_MODE_HARDWARE),
2849                                 0, &uf_regs->upsmr, &ug_regs->uescr);
2850
2851         /* Allocate Tx bds */
2852         for (j = 0; j < ug_info->numQueuesTx; j++) {
2853                 /* Allocate in multiple of
2854                    UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT,
2855                    according to spec */
2856                 length = ((ug_info->bdRingLenTx[j] * sizeof(struct qe_bd))
2857                           / UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT)
2858                     * UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT;
2859                 if ((ug_info->bdRingLenTx[j] * sizeof(struct qe_bd)) %
2860                     UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT)
2861                         length += UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT;
2862                 if (uf_info->bd_mem_part == MEM_PART_SYSTEM) {
2863                         u32 align = 4;
2864                         if (UCC_GETH_TX_BD_RING_ALIGNMENT > 4)
2865                                 align = UCC_GETH_TX_BD_RING_ALIGNMENT;
2866                         ugeth->tx_bd_ring_offset[j] =
2867                                 (u32) (kmalloc((u32) (length + align),
2868                                 GFP_KERNEL));
2869                         if (ugeth->tx_bd_ring_offset[j] != 0)
2870                                 ugeth->p_tx_bd_ring[j] =
2871                                         (void*)((ugeth->tx_bd_ring_offset[j] +
2872                                         align) & ~(align - 1));
2873                 } else if (uf_info->bd_mem_part == MEM_PART_MURAM) {
2874                         ugeth->tx_bd_ring_offset[j] =
2875                             qe_muram_alloc(length,
2876                                            UCC_GETH_TX_BD_RING_ALIGNMENT);
2877                         if (!IS_MURAM_ERR(ugeth->tx_bd_ring_offset[j]))
2878                                 ugeth->p_tx_bd_ring[j] =
2879                                     (u8 *) qe_muram_addr(ugeth->
2880                                                          tx_bd_ring_offset[j]);
2881                 }
2882                 if (!ugeth->p_tx_bd_ring[j]) {
2883                         ugeth_err
2884                             ("%s: Can not allocate memory for Tx bd rings.",
2885                              __FUNCTION__);
2886                         ucc_geth_memclean(ugeth);
2887                         return -ENOMEM;
2888                 }
2889                 /* Zero unused end of bd ring, according to spec */
2890                 memset(ugeth->p_tx_bd_ring[j] +
2891                        ug_info->bdRingLenTx[j] * sizeof(struct qe_bd), 0,
2892                        length - ug_info->bdRingLenTx[j] * sizeof(struct qe_bd));
2893         }
2894
2895         /* Allocate Rx bds */
2896         for (j = 0; j < ug_info->numQueuesRx; j++) {
2897                 length = ug_info->bdRingLenRx[j] * sizeof(struct qe_bd);
2898                 if (uf_info->bd_mem_part == MEM_PART_SYSTEM) {
2899                         u32 align = 4;
2900                         if (UCC_GETH_RX_BD_RING_ALIGNMENT > 4)
2901                                 align = UCC_GETH_RX_BD_RING_ALIGNMENT;
2902                         ugeth->rx_bd_ring_offset[j] =
2903                             (u32) (kmalloc((u32) (length + align), GFP_KERNEL));
2904                         if (ugeth->rx_bd_ring_offset[j] != 0)
2905                                 ugeth->p_rx_bd_ring[j] =
2906                                         (void*)((ugeth->rx_bd_ring_offset[j] +
2907                                         align) & ~(align - 1));
2908                 } else if (uf_info->bd_mem_part == MEM_PART_MURAM) {
2909                         ugeth->rx_bd_ring_offset[j] =
2910                             qe_muram_alloc(length,
2911                                            UCC_GETH_RX_BD_RING_ALIGNMENT);
2912                         if (!IS_MURAM_ERR(ugeth->rx_bd_ring_offset[j]))
2913                                 ugeth->p_rx_bd_ring[j] =
2914                                     (u8 *) qe_muram_addr(ugeth->
2915                                                          rx_bd_ring_offset[j]);
2916                 }
2917                 if (!ugeth->p_rx_bd_ring[j]) {
2918                         ugeth_err
2919                             ("%s: Can not allocate memory for Rx bd rings.",
2920                              __FUNCTION__);
2921                         ucc_geth_memclean(ugeth);
2922                         return -ENOMEM;
2923                 }
2924         }
2925
2926         /* Init Tx bds */
2927         for (j = 0; j < ug_info->numQueuesTx; j++) {
2928                 /* Setup the skbuff rings */
2929                 ugeth->tx_skbuff[j] =
2930                     (struct sk_buff **)kmalloc(sizeof(struct sk_buff *) *
2931                                                ugeth->ug_info->bdRingLenTx[j],
2932                                                GFP_KERNEL);
2933
2934                 if (ugeth->tx_skbuff[j] == NULL) {
2935                         ugeth_err("%s: Could not allocate tx_skbuff",
2936                                   __FUNCTION__);
2937                         ucc_geth_memclean(ugeth);
2938                         return -ENOMEM;
2939                 }
2940
2941                 for (i = 0; i < ugeth->ug_info->bdRingLenTx[j]; i++)
2942                         ugeth->tx_skbuff[j][i] = NULL;
2943
2944                 ugeth->skb_curtx[j] = ugeth->skb_dirtytx[j] = 0;
2945                 bd = ugeth->confBd[j] = ugeth->txBd[j] = ugeth->p_tx_bd_ring[j];
2946                 for (i = 0; i < ug_info->bdRingLenTx[j]; i++) {
2947                         /* clear bd buffer */
2948                         out_be32(&((struct qe_bd *)bd)->buf, 0);
2949                         /* set bd status and length */
2950                         out_be32((u32 *)bd, 0);
2951                         bd += sizeof(struct qe_bd);
2952                 }
2953                 bd -= sizeof(struct qe_bd);
2954                 /* set bd status and length */
2955                 out_be32((u32 *)bd, T_W);       /* for last BD set Wrap bit */
2956         }
2957
2958         /* Init Rx bds */
2959         for (j = 0; j < ug_info->numQueuesRx; j++) {
2960                 /* Setup the skbuff rings */
2961                 ugeth->rx_skbuff[j] =
2962                     (struct sk_buff **)kmalloc(sizeof(struct sk_buff *) *
2963                                                ugeth->ug_info->bdRingLenRx[j],
2964                                                GFP_KERNEL);
2965
2966                 if (ugeth->rx_skbuff[j] == NULL) {
2967                         ugeth_err("%s: Could not allocate rx_skbuff",
2968                                   __FUNCTION__);
2969                         ucc_geth_memclean(ugeth);
2970                         return -ENOMEM;
2971                 }
2972
2973                 for (i = 0; i < ugeth->ug_info->bdRingLenRx[j]; i++)
2974                         ugeth->rx_skbuff[j][i] = NULL;
2975
2976                 ugeth->skb_currx[j] = 0;
2977                 bd = ugeth->rxBd[j] = ugeth->p_rx_bd_ring[j];
2978                 for (i = 0; i < ug_info->bdRingLenRx[j]; i++) {
2979                         /* set bd status and length */
2980                         out_be32((u32 *)bd, R_I);
2981                         /* clear bd buffer */
2982                         out_be32(&((struct qe_bd *)bd)->buf, 0);
2983                         bd += sizeof(struct qe_bd);
2984                 }
2985                 bd -= sizeof(struct qe_bd);
2986                 /* set bd status and length */
2987                 out_be32((u32 *)bd, R_W); /* for last BD set Wrap bit */
2988         }
2989
2990         /*
2991          * Global PRAM
2992          */
2993         /* Tx global PRAM */
2994         /* Allocate global tx parameter RAM page */
2995         ugeth->tx_glbl_pram_offset =
2996             qe_muram_alloc(sizeof(struct ucc_geth_tx_global_pram),
2997                            UCC_GETH_TX_GLOBAL_PRAM_ALIGNMENT);
2998         if (IS_MURAM_ERR(ugeth->tx_glbl_pram_offset)) {
2999                 ugeth_err
3000                     ("%s: Can not allocate DPRAM memory for p_tx_glbl_pram.",
3001                      __FUNCTION__);
3002                 ucc_geth_memclean(ugeth);
3003                 return -ENOMEM;
3004         }
3005         ugeth->p_tx_glbl_pram =
3006             (struct ucc_geth_tx_global_pram *) qe_muram_addr(ugeth->
3007                                                         tx_glbl_pram_offset);
3008         /* Zero out p_tx_glbl_pram */
3009         memset(ugeth->p_tx_glbl_pram, 0, sizeof(struct ucc_geth_tx_global_pram));
3010
3011         /* Fill global PRAM */
3012
3013         /* TQPTR */
3014         /* Size varies with number of Tx threads */
3015         ugeth->thread_dat_tx_offset =
3016             qe_muram_alloc(numThreadsTxNumerical *
3017                            sizeof(struct ucc_geth_thread_data_tx) +
3018                            32 * (numThreadsTxNumerical == 1),
3019                            UCC_GETH_THREAD_DATA_ALIGNMENT);
3020         if (IS_MURAM_ERR(ugeth->thread_dat_tx_offset)) {
3021                 ugeth_err
3022                     ("%s: Can not allocate DPRAM memory for p_thread_data_tx.",
3023                      __FUNCTION__);
3024                 ucc_geth_memclean(ugeth);
3025                 return -ENOMEM;
3026         }
3027
3028         ugeth->p_thread_data_tx =
3029             (struct ucc_geth_thread_data_tx *) qe_muram_addr(ugeth->
3030                                                         thread_dat_tx_offset);
3031         out_be32(&ugeth->p_tx_glbl_pram->tqptr, ugeth->thread_dat_tx_offset);
3032
3033         /* vtagtable */
3034         for (i = 0; i < UCC_GETH_TX_VTAG_TABLE_ENTRY_MAX; i++)
3035                 out_be32(&ugeth->p_tx_glbl_pram->vtagtable[i],
3036                          ug_info->vtagtable[i]);
3037
3038         /* iphoffset */
3039         for (i = 0; i < TX_IP_OFFSET_ENTRY_MAX; i++)
3040                 ugeth->p_tx_glbl_pram->iphoffset[i] = ug_info->iphoffset[i];
3041
3042         /* SQPTR */
3043         /* Size varies with number of Tx queues */
3044         ugeth->send_q_mem_reg_offset =
3045             qe_muram_alloc(ug_info->numQueuesTx *
3046                            sizeof(struct ucc_geth_send_queue_qd),
3047                            UCC_GETH_SEND_QUEUE_QUEUE_DESCRIPTOR_ALIGNMENT);
3048         if (IS_MURAM_ERR(ugeth->send_q_mem_reg_offset)) {
3049                 ugeth_err
3050                     ("%s: Can not allocate DPRAM memory for p_send_q_mem_reg.",
3051                      __FUNCTION__);
3052                 ucc_geth_memclean(ugeth);
3053                 return -ENOMEM;
3054         }
3055
3056         ugeth->p_send_q_mem_reg =
3057             (struct ucc_geth_send_queue_mem_region *) qe_muram_addr(ugeth->
3058                         send_q_mem_reg_offset);
3059         out_be32(&ugeth->p_tx_glbl_pram->sqptr, ugeth->send_q_mem_reg_offset);
3060
3061         /* Setup the table */
3062         /* Assume BD rings are already established */
3063         for (i = 0; i < ug_info->numQueuesTx; i++) {
3064                 endOfRing =
3065                     ugeth->p_tx_bd_ring[i] + (ug_info->bdRingLenTx[i] -
3066                                               1) * sizeof(struct qe_bd);
3067                 if (ugeth->ug_info->uf_info.bd_mem_part == MEM_PART_SYSTEM) {
3068                         out_be32(&ugeth->p_send_q_mem_reg->sqqd[i].bd_ring_base,
3069                                  (u32) virt_to_phys(ugeth->p_tx_bd_ring[i]));
3070                         out_be32(&ugeth->p_send_q_mem_reg->sqqd[i].
3071                                  last_bd_completed_address,
3072                                  (u32) virt_to_phys(endOfRing));
3073                 } else if (ugeth->ug_info->uf_info.bd_mem_part ==
3074                            MEM_PART_MURAM) {
3075                         out_be32(&ugeth->p_send_q_mem_reg->sqqd[i].bd_ring_base,
3076                                  (u32) immrbar_virt_to_phys(ugeth->
3077                                                             p_tx_bd_ring[i]));
3078                         out_be32(&ugeth->p_send_q_mem_reg->sqqd[i].
3079                                  last_bd_completed_address,
3080                                  (u32) immrbar_virt_to_phys(endOfRing));
3081                 }
3082         }
3083
3084         /* schedulerbasepointer */
3085
3086         if (ug_info->numQueuesTx > 1) {
3087         /* scheduler exists only if more than 1 tx queue */
3088                 ugeth->scheduler_offset =
3089                     qe_muram_alloc(sizeof(struct ucc_geth_scheduler),
3090                                    UCC_GETH_SCHEDULER_ALIGNMENT);
3091                 if (IS_MURAM_ERR(ugeth->scheduler_offset)) {
3092                         ugeth_err
3093                          ("%s: Can not allocate DPRAM memory for p_scheduler.",
3094                              __FUNCTION__);
3095                         ucc_geth_memclean(ugeth);
3096                         return -ENOMEM;
3097                 }
3098
3099                 ugeth->p_scheduler =
3100                     (struct ucc_geth_scheduler *) qe_muram_addr(ugeth->
3101                                                            scheduler_offset);
3102                 out_be32(&ugeth->p_tx_glbl_pram->schedulerbasepointer,
3103                          ugeth->scheduler_offset);
3104                 /* Zero out p_scheduler */
3105                 memset(ugeth->p_scheduler, 0, sizeof(struct ucc_geth_scheduler));
3106
3107                 /* Set values in scheduler */
3108                 out_be32(&ugeth->p_scheduler->mblinterval,
3109                          ug_info->mblinterval);
3110                 out_be16(&ugeth->p_scheduler->nortsrbytetime,
3111                          ug_info->nortsrbytetime);
3112                 ugeth->p_scheduler->fracsiz = ug_info->fracsiz;
3113                 ugeth->p_scheduler->strictpriorityq = ug_info->strictpriorityq;
3114                 ugeth->p_scheduler->txasap = ug_info->txasap;
3115                 ugeth->p_scheduler->extrabw = ug_info->extrabw;
3116                 for (i = 0; i < NUM_TX_QUEUES; i++)
3117                         ugeth->p_scheduler->weightfactor[i] =
3118                             ug_info->weightfactor[i];
3119
3120                 /* Set pointers to cpucount registers in scheduler */
3121                 ugeth->p_cpucount[0] = &(ugeth->p_scheduler->cpucount0);
3122                 ugeth->p_cpucount[1] = &(ugeth->p_scheduler->cpucount1);
3123                 ugeth->p_cpucount[2] = &(ugeth->p_scheduler->cpucount2);
3124                 ugeth->p_cpucount[3] = &(ugeth->p_scheduler->cpucount3);
3125                 ugeth->p_cpucount[4] = &(ugeth->p_scheduler->cpucount4);
3126                 ugeth->p_cpucount[5] = &(ugeth->p_scheduler->cpucount5);
3127                 ugeth->p_cpucount[6] = &(ugeth->p_scheduler->cpucount6);
3128                 ugeth->p_cpucount[7] = &(ugeth->p_scheduler->cpucount7);
3129         }
3130
3131         /* schedulerbasepointer */
3132         /* TxRMON_PTR (statistics) */
3133         if (ug_info->
3134             statisticsMode & UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_TX) {
3135                 ugeth->tx_fw_statistics_pram_offset =
3136                     qe_muram_alloc(sizeof
3137                                    (struct ucc_geth_tx_firmware_statistics_pram),
3138                                    UCC_GETH_TX_STATISTICS_ALIGNMENT);
3139                 if (IS_MURAM_ERR(ugeth->tx_fw_statistics_pram_offset)) {
3140                         ugeth_err
3141                             ("%s: Can not allocate DPRAM memory for"
3142                                 " p_tx_fw_statistics_pram.", __FUNCTION__);
3143                         ucc_geth_memclean(ugeth);
3144                         return -ENOMEM;
3145                 }
3146                 ugeth->p_tx_fw_statistics_pram =
3147                     (struct ucc_geth_tx_firmware_statistics_pram *)
3148                     qe_muram_addr(ugeth->tx_fw_statistics_pram_offset);
3149                 /* Zero out p_tx_fw_statistics_pram */
3150                 memset(ugeth->p_tx_fw_statistics_pram,
3151                        0, sizeof(struct ucc_geth_tx_firmware_statistics_pram));
3152         }
3153
3154         /* temoder */
3155         /* Already has speed set */
3156
3157         if (ug_info->numQueuesTx > 1)
3158                 temoder |= TEMODER_SCHEDULER_ENABLE;
3159         if (ug_info->ipCheckSumGenerate)
3160                 temoder |= TEMODER_IP_CHECKSUM_GENERATE;
3161         temoder |= ((ug_info->numQueuesTx - 1) << TEMODER_NUM_OF_QUEUES_SHIFT);
3162         out_be16(&ugeth->p_tx_glbl_pram->temoder, temoder);
3163
3164         test = in_be16(&ugeth->p_tx_glbl_pram->temoder);
3165
3166         /* Function code register value to be used later */
3167         function_code = QE_BMR_BYTE_ORDER_BO_MOT | UCC_FAST_FUNCTION_CODE_GBL;
3168         /* Required for QE */
3169
3170         /* function code register */
3171         out_be32(&ugeth->p_tx_glbl_pram->tstate, ((u32) function_code) << 24);
3172
3173         /* Rx global PRAM */
3174         /* Allocate global rx parameter RAM page */
3175         ugeth->rx_glbl_pram_offset =
3176             qe_muram_alloc(sizeof(struct ucc_geth_rx_global_pram),
3177                            UCC_GETH_RX_GLOBAL_PRAM_ALIGNMENT);
3178         if (IS_MURAM_ERR(ugeth->rx_glbl_pram_offset)) {
3179                 ugeth_err
3180                     ("%s: Can not allocate DPRAM memory for p_rx_glbl_pram.",
3181                      __FUNCTION__);
3182                 ucc_geth_memclean(ugeth);
3183                 return -ENOMEM;
3184         }
3185         ugeth->p_rx_glbl_pram =
3186             (struct ucc_geth_rx_global_pram *) qe_muram_addr(ugeth->
3187                                                         rx_glbl_pram_offset);
3188         /* Zero out p_rx_glbl_pram */
3189         memset(ugeth->p_rx_glbl_pram, 0, sizeof(struct ucc_geth_rx_global_pram));
3190
3191         /* Fill global PRAM */
3192
3193         /* RQPTR */
3194         /* Size varies with number of Rx threads */
3195         ugeth->thread_dat_rx_offset =
3196             qe_muram_alloc(numThreadsRxNumerical *
3197                            sizeof(struct ucc_geth_thread_data_rx),
3198                            UCC_GETH_THREAD_DATA_ALIGNMENT);
3199         if (IS_MURAM_ERR(ugeth->thread_dat_rx_offset)) {
3200                 ugeth_err
3201                     ("%s: Can not allocate DPRAM memory for p_thread_data_rx.",
3202                      __FUNCTION__);
3203                 ucc_geth_memclean(ugeth);
3204                 return -ENOMEM;
3205         }
3206
3207         ugeth->p_thread_data_rx =
3208             (struct ucc_geth_thread_data_rx *) qe_muram_addr(ugeth->
3209                                                         thread_dat_rx_offset);
3210         out_be32(&ugeth->p_rx_glbl_pram->rqptr, ugeth->thread_dat_rx_offset);
3211
3212         /* typeorlen */
3213         out_be16(&ugeth->p_rx_glbl_pram->typeorlen, ug_info->typeorlen);
3214
3215         /* rxrmonbaseptr (statistics) */
3216         if (ug_info->
3217             statisticsMode & UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_RX) {
3218                 ugeth->rx_fw_statistics_pram_offset =
3219                     qe_muram_alloc(sizeof
3220                                    (struct ucc_geth_rx_firmware_statistics_pram),
3221                                    UCC_GETH_RX_STATISTICS_ALIGNMENT);
3222                 if (IS_MURAM_ERR(ugeth->rx_fw_statistics_pram_offset)) {
3223                         ugeth_err
3224                                 ("%s: Can not allocate DPRAM memory for"
3225                                 " p_rx_fw_statistics_pram.", __FUNCTION__);
3226                         ucc_geth_memclean(ugeth);
3227                         return -ENOMEM;
3228                 }
3229                 ugeth->p_rx_fw_statistics_pram =
3230                     (struct ucc_geth_rx_firmware_statistics_pram *)
3231                     qe_muram_addr(ugeth->rx_fw_statistics_pram_offset);
3232                 /* Zero out p_rx_fw_statistics_pram */
3233                 memset(ugeth->p_rx_fw_statistics_pram, 0,
3234                        sizeof(struct ucc_geth_rx_firmware_statistics_pram));
3235         }
3236
3237         /* intCoalescingPtr */
3238
3239         /* Size varies with number of Rx queues */
3240         ugeth->rx_irq_coalescing_tbl_offset =
3241             qe_muram_alloc(ug_info->numQueuesRx *
3242                            sizeof(struct ucc_geth_rx_interrupt_coalescing_entry),
3243                            UCC_GETH_RX_INTERRUPT_COALESCING_ALIGNMENT);
3244         if (IS_MURAM_ERR(ugeth->rx_irq_coalescing_tbl_offset)) {
3245                 ugeth_err
3246                     ("%s: Can not allocate DPRAM memory for"
3247                         " p_rx_irq_coalescing_tbl.", __FUNCTION__);
3248                 ucc_geth_memclean(ugeth);
3249                 return -ENOMEM;
3250         }
3251
3252         ugeth->p_rx_irq_coalescing_tbl =
3253             (struct ucc_geth_rx_interrupt_coalescing_table *)
3254             qe_muram_addr(ugeth->rx_irq_coalescing_tbl_offset);
3255         out_be32(&ugeth->p_rx_glbl_pram->intcoalescingptr,
3256                  ugeth->rx_irq_coalescing_tbl_offset);
3257
3258         /* Fill interrupt coalescing table */
3259         for (i = 0; i < ug_info->numQueuesRx; i++) {
3260                 out_be32(&ugeth->p_rx_irq_coalescing_tbl->coalescingentry[i].
3261                          interruptcoalescingmaxvalue,
3262                          ug_info->interruptcoalescingmaxvalue[i]);
3263                 out_be32(&ugeth->p_rx_irq_coalescing_tbl->coalescingentry[i].
3264                          interruptcoalescingcounter,
3265                          ug_info->interruptcoalescingmaxvalue[i]);
3266         }
3267
3268         /* MRBLR */
3269         init_max_rx_buff_len(uf_info->max_rx_buf_length,
3270                              &ugeth->p_rx_glbl_pram->mrblr);
3271         /* MFLR */
3272         out_be16(&ugeth->p_rx_glbl_pram->mflr, ug_info->maxFrameLength);
3273         /* MINFLR */
3274         init_min_frame_len(ug_info->minFrameLength,
3275                            &ugeth->p_rx_glbl_pram->minflr,
3276                            &ugeth->p_rx_glbl_pram->mrblr);
3277         /* MAXD1 */
3278         out_be16(&ugeth->p_rx_glbl_pram->maxd1, ug_info->maxD1Length);
3279         /* MAXD2 */
3280         out_be16(&ugeth->p_rx_glbl_pram->maxd2, ug_info->maxD2Length);
3281
3282         /* l2qt */
3283         l2qt = 0;
3284         for (i = 0; i < UCC_GETH_VLAN_PRIORITY_MAX; i++)
3285                 l2qt |= (ug_info->l2qt[i] << (28 - 4 * i));
3286         out_be32(&ugeth->p_rx_glbl_pram->l2qt, l2qt);
3287
3288         /* l3qt */
3289         for (j = 0; j < UCC_GETH_IP_PRIORITY_MAX; j += 8) {
3290                 l3qt = 0;
3291                 for (i = 0; i < 8; i++)
3292                         l3qt |= (ug_info->l3qt[j + i] << (28 - 4 * i));
3293                 out_be32(&ugeth->p_rx_glbl_pram->l3qt[j/8], l3qt);
3294         }
3295
3296         /* vlantype */
3297         out_be16(&ugeth->p_rx_glbl_pram->vlantype, ug_info->vlantype);
3298
3299         /* vlantci */
3300         out_be16(&ugeth->p_rx_glbl_pram->vlantci, ug_info->vlantci);
3301
3302         /* ecamptr */
3303         out_be32(&ugeth->p_rx_glbl_pram->ecamptr, ug_info->ecamptr);
3304
3305         /* RBDQPTR */
3306         /* Size varies with number of Rx queues */
3307         ugeth->rx_bd_qs_tbl_offset =
3308             qe_muram_alloc(ug_info->numQueuesRx *
3309                            (sizeof(struct ucc_geth_rx_bd_queues_entry) +
3310                             sizeof(struct ucc_geth_rx_prefetched_bds)),
3311                            UCC_GETH_RX_BD_QUEUES_ALIGNMENT);
3312         if (IS_MURAM_ERR(ugeth->rx_bd_qs_tbl_offset)) {
3313                 ugeth_err
3314                     ("%s: Can not allocate DPRAM memory for p_rx_bd_qs_tbl.",
3315                      __FUNCTION__);
3316                 ucc_geth_memclean(ugeth);
3317                 return -ENOMEM;
3318         }
3319
3320         ugeth->p_rx_bd_qs_tbl =
3321             (struct ucc_geth_rx_bd_queues_entry *) qe_muram_addr(ugeth->
3322                                     rx_bd_qs_tbl_offset);
3323         out_be32(&ugeth->p_rx_glbl_pram->rbdqptr, ugeth->rx_bd_qs_tbl_offset);
3324         /* Zero out p_rx_bd_qs_tbl */
3325         memset(ugeth->p_rx_bd_qs_tbl,
3326                0,
3327                ug_info->numQueuesRx * (sizeof(struct ucc_geth_rx_bd_queues_entry) +
3328                                        sizeof(struct ucc_geth_rx_prefetched_bds)));
3329
3330         /* Setup the table */
3331         /* Assume BD rings are already established */
3332         for (i = 0; i < ug_info->numQueuesRx; i++) {
3333                 if (ugeth->ug_info->uf_info.bd_mem_part == MEM_PART_SYSTEM) {
3334                         out_be32(&ugeth->p_rx_bd_qs_tbl[i].externalbdbaseptr,
3335                                  (u32) virt_to_phys(ugeth->p_rx_bd_ring[i]));
3336                 } else if (ugeth->ug_info->uf_info.bd_mem_part ==
3337                            MEM_PART_MURAM) {
3338                         out_be32(&ugeth->p_rx_bd_qs_tbl[i].externalbdbaseptr,
3339                                  (u32) immrbar_virt_to_phys(ugeth->
3340                                                             p_rx_bd_ring[i]));
3341                 }
3342                 /* rest of fields handled by QE */
3343         }
3344
3345         /* remoder */
3346         /* Already has speed set */
3347
3348         if (ugeth->rx_extended_features)
3349                 remoder |= REMODER_RX_EXTENDED_FEATURES;
3350         if (ug_info->rxExtendedFiltering)
3351                 remoder |= REMODER_RX_EXTENDED_FILTERING;
3352         if (ug_info->dynamicMaxFrameLength)
3353                 remoder |= REMODER_DYNAMIC_MAX_FRAME_LENGTH;
3354         if (ug_info->dynamicMinFrameLength)
3355                 remoder |= REMODER_DYNAMIC_MIN_FRAME_LENGTH;
3356         remoder |=
3357             ug_info->vlanOperationTagged << REMODER_VLAN_OPERATION_TAGGED_SHIFT;
3358         remoder |=
3359             ug_info->
3360             vlanOperationNonTagged << REMODER_VLAN_OPERATION_NON_TAGGED_SHIFT;
3361         remoder |= ug_info->rxQoSMode << REMODER_RX_QOS_MODE_SHIFT;
3362         remoder |= ((ug_info->numQueuesRx - 1) << REMODER_NUM_OF_QUEUES_SHIFT);
3363         if (ug_info->ipCheckSumCheck)
3364                 remoder |= REMODER_IP_CHECKSUM_CHECK;
3365         if (ug_info->ipAddressAlignment)
3366                 remoder |= REMODER_IP_ADDRESS_ALIGNMENT;
3367         out_be32(&ugeth->p_rx_glbl_pram->remoder, remoder);
3368
3369         /* Note that this function must be called */
3370         /* ONLY AFTER p_tx_fw_statistics_pram */
3371         /* andp_UccGethRxFirmwareStatisticsPram are allocated ! */
3372         init_firmware_statistics_gathering_mode((ug_info->
3373                 statisticsMode &
3374                 UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_TX),
3375                 (ug_info->statisticsMode &
3376                 UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_RX),
3377                 &ugeth->p_tx_glbl_pram->txrmonbaseptr,
3378                 ugeth->tx_fw_statistics_pram_offset,
3379                 &ugeth->p_rx_glbl_pram->rxrmonbaseptr,
3380                 ugeth->rx_fw_statistics_pram_offset,
3381                 &ugeth->p_tx_glbl_pram->temoder,
3382                 &ugeth->p_rx_glbl_pram->remoder);
3383
3384         /* function code register */
3385         ugeth->p_rx_glbl_pram->rstate = function_code;
3386
3387         /* initialize extended filtering */
3388         if (ug_info->rxExtendedFiltering) {
3389                 if (!ug_info->extendedFilteringChainPointer) {
3390                         ugeth_err("%s: Null Extended Filtering Chain Pointer.",
3391                                   __FUNCTION__);
3392                         ucc_geth_memclean(ugeth);
3393                         return -EINVAL;
3394                 }
3395
3396                 /* Allocate memory for extended filtering Mode Global
3397                 Parameters */
3398                 ugeth->exf_glbl_param_offset =
3399                     qe_muram_alloc(sizeof(struct ucc_geth_exf_global_pram),
3400                 UCC_GETH_RX_EXTENDED_FILTERING_GLOBAL_PARAMETERS_ALIGNMENT);
3401                 if (IS_MURAM_ERR(ugeth->exf_glbl_param_offset)) {
3402                         ugeth_err
3403                                 ("%s: Can not allocate DPRAM memory for"
3404                                 " p_exf_glbl_param.", __FUNCTION__);
3405                         ucc_geth_memclean(ugeth);
3406                         return -ENOMEM;
3407                 }
3408
3409                 ugeth->p_exf_glbl_param =
3410                     (struct ucc_geth_exf_global_pram *) qe_muram_addr(ugeth->
3411                                  exf_glbl_param_offset);
3412                 out_be32(&ugeth->p_rx_glbl_pram->exfGlobalParam,
3413                          ugeth->exf_glbl_param_offset);
3414                 out_be32(&ugeth->p_exf_glbl_param->l2pcdptr,
3415                          (u32) ug_info->extendedFilteringChainPointer);
3416
3417         } else {                /* initialize 82xx style address filtering */
3418
3419                 /* Init individual address recognition registers to disabled */
3420
3421                 for (j = 0; j < NUM_OF_PADDRS; j++)
3422                         ugeth_82xx_filtering_clear_addr_in_paddr(ugeth, (u8) j);
3423
3424                 /* Create CQs for hash tables */
3425                 if (ug_info->maxGroupAddrInHash > 0) {
3426                         INIT_LIST_HEAD(&ugeth->group_hash_q);
3427                 }
3428                 if (ug_info->maxIndAddrInHash > 0) {
3429                         INIT_LIST_HEAD(&ugeth->ind_hash_q);
3430                 }
3431                 p_82xx_addr_filt =
3432                     (struct ucc_geth_82xx_address_filtering_pram *) ugeth->
3433                     p_rx_glbl_pram->addressfiltering;
3434
3435                 ugeth_82xx_filtering_clear_all_addr_in_hash(ugeth,
3436                         ENET_ADDR_TYPE_GROUP);
3437                 ugeth_82xx_filtering_clear_all_addr_in_hash(ugeth,
3438                         ENET_ADDR_TYPE_INDIVIDUAL);
3439         }
3440
3441         /*
3442          * Initialize UCC at QE level
3443          */
3444
3445         command = QE_INIT_TX_RX;
3446
3447         /* Allocate shadow InitEnet command parameter structure.
3448          * This is needed because after the InitEnet command is executed,
3449          * the structure in DPRAM is released, because DPRAM is a premium
3450          * resource.
3451          * This shadow structure keeps a copy of what was done so that the
3452          * allocated resources can be released when the channel is freed.
3453          */
3454         if (!(ugeth->p_init_enet_param_shadow =
3455              (struct ucc_geth_init_pram *) kmalloc(sizeof(struct ucc_geth_init_pram),
3456                                               GFP_KERNEL))) {
3457                 ugeth_err
3458                     ("%s: Can not allocate memory for"
3459                         " p_UccInitEnetParamShadows.", __FUNCTION__);
3460                 ucc_geth_memclean(ugeth);
3461                 return -ENOMEM;
3462         }
3463         /* Zero out *p_init_enet_param_shadow */
3464         memset((char *)ugeth->p_init_enet_param_shadow,
3465                0, sizeof(struct ucc_geth_init_pram));
3466
3467         /* Fill shadow InitEnet command parameter structure */
3468
3469         ugeth->p_init_enet_param_shadow->resinit1 =
3470             ENET_INIT_PARAM_MAGIC_RES_INIT1;
3471         ugeth->p_init_enet_param_shadow->resinit2 =
3472             ENET_INIT_PARAM_MAGIC_RES_INIT2;
3473         ugeth->p_init_enet_param_shadow->resinit3 =
3474             ENET_INIT_PARAM_MAGIC_RES_INIT3;
3475         ugeth->p_init_enet_param_shadow->resinit4 =
3476             ENET_INIT_PARAM_MAGIC_RES_INIT4;
3477         ugeth->p_init_enet_param_shadow->resinit5 =
3478             ENET_INIT_PARAM_MAGIC_RES_INIT5;
3479         ugeth->p_init_enet_param_shadow->rgftgfrxglobal |=
3480             ((u32) ug_info->numThreadsRx) << ENET_INIT_PARAM_RGF_SHIFT;
3481         ugeth->p_init_enet_param_shadow->rgftgfrxglobal |=
3482             ((u32) ug_info->numThreadsTx) << ENET_INIT_PARAM_TGF_SHIFT;
3483
3484         ugeth->p_init_enet_param_shadow->rgftgfrxglobal |=
3485             ugeth->rx_glbl_pram_offset | ug_info->riscRx;
3486         if ((ug_info->largestexternallookupkeysize !=
3487              QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_NONE)
3488             && (ug_info->largestexternallookupkeysize !=
3489                 QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_8_BYTES)
3490             && (ug_info->largestexternallookupkeysize !=
3491                 QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_16_BYTES)) {
3492                 ugeth_err("%s: Invalid largest External Lookup Key Size.",
3493                           __FUNCTION__);
3494                 ucc_geth_memclean(ugeth);
3495                 return -EINVAL;
3496         }
3497         ugeth->p_init_enet_param_shadow->largestexternallookupkeysize =
3498             ug_info->largestexternallookupkeysize;
3499         size = sizeof(struct ucc_geth_thread_rx_pram);
3500         if (ug_info->rxExtendedFiltering) {
3501                 size += THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING;
3502                 if (ug_info->largestexternallookupkeysize ==
3503                     QE_FLTR_TABLE_LOOKUP_KEY_SIZE_8_BYTES)
3504                         size +=
3505                             THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING_8;
3506                 if (ug_info->largestexternallookupkeysize ==
3507                     QE_FLTR_TABLE_LOOKUP_KEY_SIZE_16_BYTES)
3508                         size +=
3509                             THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING_16;
3510         }
3511
3512         if ((ret_val = fill_init_enet_entries(ugeth, &(ugeth->
3513                 p_init_enet_param_shadow->rxthread[0]),
3514                 (u8) (numThreadsRxNumerical + 1)
3515                 /* Rx needs one extra for terminator */
3516                 , size, UCC_GETH_THREAD_RX_PRAM_ALIGNMENT,
3517                 ug_info->riscRx, 1)) != 0) {
3518                         ugeth_err("%s: Can not fill p_init_enet_param_shadow.",
3519                                 __FUNCTION__);
3520                 ucc_geth_memclean(ugeth);
3521                 return ret_val;
3522         }
3523
3524         ugeth->p_init_enet_param_shadow->txglobal =
3525             ugeth->tx_glbl_pram_offset | ug_info->riscTx;
3526         if ((ret_val =
3527              fill_init_enet_entries(ugeth,
3528                                     &(ugeth->p_init_enet_param_shadow->
3529                                       txthread[0]), numThreadsTxNumerical,
3530                                     sizeof(struct ucc_geth_thread_tx_pram),
3531                                     UCC_GETH_THREAD_TX_PRAM_ALIGNMENT,
3532                                     ug_info->riscTx, 0)) != 0) {
3533                 ugeth_err("%s: Can not fill p_init_enet_param_shadow.",
3534                           __FUNCTION__);
3535                 ucc_geth_memclean(ugeth);
3536                 return ret_val;
3537         }
3538
3539         /* Load Rx bds with buffers */
3540         for (i = 0; i < ug_info->numQueuesRx; i++) {
3541                 if ((ret_val = rx_bd_buffer_set(ugeth, (u8) i)) != 0) {
3542                         ugeth_err("%s: Can not fill Rx bds with buffers.",
3543                                   __FUNCTION__);
3544                         ucc_geth_memclean(ugeth);
3545                         return ret_val;
3546                 }
3547         }
3548
3549         /* Allocate InitEnet command parameter structure */
3550         init_enet_pram_offset = qe_muram_alloc(sizeof(struct ucc_geth_init_pram), 4);
3551         if (IS_MURAM_ERR(init_enet_pram_offset)) {
3552                 ugeth_err
3553                     ("%s: Can not allocate DPRAM memory for p_init_enet_pram.",
3554                      __FUNCTION__);
3555                 ucc_geth_memclean(ugeth);
3556                 return -ENOMEM;
3557         }
3558         p_init_enet_pram =
3559             (struct ucc_geth_init_pram *) qe_muram_addr(init_enet_pram_offset);
3560
3561         /* Copy shadow InitEnet command parameter structure into PRAM */
3562         p_init_enet_pram->resinit1 = ugeth->p_init_enet_param_shadow->resinit1;
3563         p_init_enet_pram->resinit2 = ugeth->p_init_enet_param_shadow->resinit2;
3564         p_init_enet_pram->resinit3 = ugeth->p_init_enet_param_shadow->resinit3;
3565         p_init_enet_pram->resinit4 = ugeth->p_init_enet_param_shadow->resinit4;
3566         out_be16(&p_init_enet_pram->resinit5,
3567                  ugeth->p_init_enet_param_shadow->resinit5);
3568         p_init_enet_pram->largestexternallookupkeysize =
3569             ugeth->p_init_enet_param_shadow->largestexternallookupkeysize;
3570         out_be32(&p_init_enet_pram->rgftgfrxglobal,
3571                  ugeth->p_init_enet_param_shadow->rgftgfrxglobal);
3572         for (i = 0; i < ENET_INIT_PARAM_MAX_ENTRIES_RX; i++)
3573                 out_be32(&p_init_enet_pram->rxthread[i],
3574                          ugeth->p_init_enet_param_shadow->rxthread[i]);
3575         out_be32(&p_init_enet_pram->txglobal,
3576                  ugeth->p_init_enet_param_shadow->txglobal);
3577         for (i = 0; i < ENET_INIT_PARAM_MAX_ENTRIES_TX; i++)
3578                 out_be32(&p_init_enet_pram->txthread[i],
3579                          ugeth->p_init_enet_param_shadow->txthread[i]);
3580
3581         /* Issue QE command */
3582         cecr_subblock =
3583             ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.ucc_num);
3584         qe_issue_cmd(command, cecr_subblock, QE_CR_PROTOCOL_ETHERNET,
3585                      init_enet_pram_offset);
3586
3587         /* Free InitEnet command parameter */
3588         qe_muram_free(init_enet_pram_offset);
3589
3590         return 0;
3591 }
3592
3593 /* returns a net_device_stats structure pointer */
3594 static struct net_device_stats *ucc_geth_get_stats(struct net_device *dev)
3595 {
3596         struct ucc_geth_private *ugeth = netdev_priv(dev);
3597
3598         return &(ugeth->stats);
3599 }
3600
3601 /* ucc_geth_timeout gets called when a packet has not been
3602  * transmitted after a set amount of time.
3603  * For now, assume that clearing out all the structures, and
3604  * starting over will fix the problem. */
3605 static void ucc_geth_timeout(struct net_device *dev)
3606 {
3607         struct ucc_geth_private *ugeth = netdev_priv(dev);
3608
3609         ugeth_vdbg("%s: IN", __FUNCTION__);
3610
3611         ugeth->stats.tx_errors++;
3612
3613         ugeth_dump_regs(ugeth);
3614
3615         if (dev->flags & IFF_UP) {
3616                 ucc_geth_stop(ugeth);
3617                 ucc_geth_startup(ugeth);
3618         }
3619
3620         netif_schedule(dev);
3621 }
3622
3623 /* This is called by the kernel when a frame is ready for transmission. */
3624 /* It is pointed to by the dev->hard_start_xmit function pointer */
3625 static int ucc_geth_start_xmit(struct sk_buff *skb, struct net_device *dev)
3626 {
3627         struct ucc_geth_private *ugeth = netdev_priv(dev);
3628         u8 *bd;                 /* BD pointer */
3629         u32 bd_status;
3630         u8 txQ = 0;
3631
3632         ugeth_vdbg("%s: IN", __FUNCTION__);
3633
3634         spin_lock_irq(&ugeth->lock);
3635
3636         ugeth->stats.tx_bytes += skb->len;
3637
3638         /* Start from the next BD that should be filled */
3639         bd = ugeth->txBd[txQ];
3640         bd_status = in_be32((u32 *)bd);
3641         /* Save the skb pointer so we can free it later */
3642         ugeth->tx_skbuff[txQ][ugeth->skb_curtx[txQ]] = skb;
3643
3644         /* Update the current skb pointer (wrapping if this was the last) */
3645         ugeth->skb_curtx[txQ] =
3646             (ugeth->skb_curtx[txQ] +
3647              1) & TX_RING_MOD_MASK(ugeth->ug_info->bdRingLenTx[txQ]);
3648
3649         /* set up the buffer descriptor */
3650         out_be32(&((struct qe_bd *)bd)->buf,
3651                       dma_map_single(NULL, skb->data, skb->len, DMA_TO_DEVICE));
3652
3653         /* printk(KERN_DEBUG"skb->data is 0x%x\n",skb->data); */
3654
3655         bd_status = (bd_status & T_W) | T_R | T_I | T_L | skb->len;
3656
3657         /* set bd status and length */
3658         out_be32((u32 *)bd, bd_status);
3659
3660         dev->trans_start = jiffies;
3661
3662         /* Move to next BD in the ring */
3663         if (!(bd_status & T_W))
3664                 ugeth->txBd[txQ] = bd + sizeof(struct qe_bd);
3665         else
3666                 ugeth->txBd[txQ] = ugeth->p_tx_bd_ring[txQ];
3667
3668         /* If the next BD still needs to be cleaned up, then the bds
3669            are full.  We need to tell the kernel to stop sending us stuff. */
3670         if (bd == ugeth->confBd[txQ]) {
3671                 if (!netif_queue_stopped(dev))
3672                         netif_stop_queue(dev);
3673         }
3674
3675         if (ugeth->p_scheduler) {
3676                 ugeth->cpucount[txQ]++;
3677                 /* Indicate to QE that there are more Tx bds ready for
3678                 transmission */
3679                 /* This is done by writing a running counter of the bd
3680                 count to the scheduler PRAM. */
3681                 out_be16(ugeth->p_cpucount[txQ], ugeth->cpucount[txQ]);
3682         }
3683
3684         spin_unlock_irq(&ugeth->lock);
3685
3686         return 0;
3687 }
3688
3689 static int ucc_geth_rx(struct ucc_geth_private *ugeth, u8 rxQ, int rx_work_limit)
3690 {
3691         struct sk_buff *skb;
3692         u8 *bd;
3693         u16 length, howmany = 0;
3694         u32 bd_status;
3695         u8 *bdBuffer;
3696
3697         ugeth_vdbg("%s: IN", __FUNCTION__);
3698
3699         spin_lock(&ugeth->lock);
3700         /* collect received buffers */
3701         bd = ugeth->rxBd[rxQ];
3702
3703         bd_status = in_be32((u32 *)bd);
3704
3705         /* while there are received buffers and BD is full (~R_E) */
3706         while (!((bd_status & (R_E)) || (--rx_work_limit < 0))) {
3707                 bdBuffer = (u8 *) in_be32(&((struct qe_bd *)bd)->buf);
3708                 length = (u16) ((bd_status & BD_LENGTH_MASK) - 4);
3709                 skb = ugeth->rx_skbuff[rxQ][ugeth->skb_currx[rxQ]];
3710
3711                 /* determine whether buffer is first, last, first and last
3712                 (single buffer frame) or middle (not first and not last) */
3713                 if (!skb ||
3714                     (!(bd_status & (R_F | R_L))) ||
3715                     (bd_status & R_ERRORS_FATAL)) {
3716                         ugeth_vdbg("%s, %d: ERROR!!! skb - 0x%08x",
3717                                    __FUNCTION__, __LINE__, (u32) skb);
3718                         if (skb)
3719                                 dev_kfree_skb_any(skb);
3720
3721                         ugeth->rx_skbuff[rxQ][ugeth->skb_currx[rxQ]] = NULL;
3722                         ugeth->stats.rx_dropped++;
3723                 } else {
3724                         ugeth->stats.rx_packets++;
3725                         howmany++;
3726
3727                         /* Prep the skb for the packet */
3728                         skb_put(skb, length);
3729
3730                         /* Tell the skb what kind of packet this is */
3731                         skb->protocol = eth_type_trans(skb, ugeth->dev);
3732
3733                         ugeth->stats.rx_bytes += length;
3734                         /* Send the packet up the stack */
3735 #ifdef CONFIG_UGETH_NAPI
3736                         netif_receive_skb(skb);
3737 #else
3738                         netif_rx(skb);
3739 #endif                          /* CONFIG_UGETH_NAPI */
3740                 }
3741
3742                 ugeth->dev->last_rx = jiffies;
3743
3744                 skb = get_new_skb(ugeth, bd);
3745                 if (!skb) {
3746                         ugeth_warn("%s: No Rx Data Buffer", __FUNCTION__);
3747                         spin_unlock(&ugeth->lock);
3748                         ugeth->stats.rx_dropped++;
3749                         break;
3750                 }
3751
3752                 ugeth->rx_skbuff[rxQ][ugeth->skb_currx[rxQ]] = skb;
3753
3754                 /* update to point at the next skb */
3755                 ugeth->skb_currx[rxQ] =
3756                     (ugeth->skb_currx[rxQ] +
3757                      1) & RX_RING_MOD_MASK(ugeth->ug_info->bdRingLenRx[rxQ]);
3758
3759                 if (bd_status & R_W)
3760                         bd = ugeth->p_rx_bd_ring[rxQ];
3761                 else
3762                         bd += sizeof(struct qe_bd);
3763
3764                 bd_status = in_be32((u32 *)bd);
3765         }
3766
3767         ugeth->rxBd[rxQ] = bd;
3768         spin_unlock(&ugeth->lock);
3769         return howmany;
3770 }
3771
3772 static int ucc_geth_tx(struct net_device *dev, u8 txQ)
3773 {
3774         /* Start from the next BD that should be filled */
3775         struct ucc_geth_private *ugeth = netdev_priv(dev);
3776         u8 *bd;                 /* BD pointer */
3777         u32 bd_status;
3778
3779         bd = ugeth->confBd[txQ];
3780         bd_status = in_be32((u32 *)bd);
3781
3782         /* Normal processing. */
3783         while ((bd_status & T_R) == 0) {
3784                 /* BD contains already transmitted buffer.   */
3785                 /* Handle the transmitted buffer and release */
3786                 /* the BD to be used with the current frame  */
3787
3788                 if ((bd = ugeth->txBd[txQ]) && (netif_queue_stopped(dev) == 0))
3789                         break;
3790
3791                 ugeth->stats.tx_packets++;
3792
3793                 /* Free the sk buffer associated with this TxBD */
3794                 dev_kfree_skb_irq(ugeth->
3795                                   tx_skbuff[txQ][ugeth->skb_dirtytx[txQ]]);
3796                 ugeth->tx_skbuff[txQ][ugeth->skb_dirtytx[txQ]] = NULL;
3797                 ugeth->skb_dirtytx[txQ] =
3798                     (ugeth->skb_dirtytx[txQ] +
3799                      1) & TX_RING_MOD_MASK(ugeth->ug_info->bdRingLenTx[txQ]);
3800
3801                 /* We freed a buffer, so now we can restart transmission */
3802                 if (netif_queue_stopped(dev))
3803                         netif_wake_queue(dev);
3804
3805                 /* Advance the confirmation BD pointer */
3806                 if (!(bd_status & T_W))
3807                         ugeth->confBd[txQ] += sizeof(struct qe_bd);
3808                 else
3809                         ugeth->confBd[txQ] = ugeth->p_tx_bd_ring[txQ];
3810         }
3811         return 0;
3812 }
3813
3814 #ifdef CONFIG_UGETH_NAPI
3815 static int ucc_geth_poll(struct net_device *dev, int *budget)
3816 {
3817         struct ucc_geth_private *ugeth = netdev_priv(dev);
3818         int howmany;
3819         int rx_work_limit = *budget;
3820         u8 rxQ = 0;
3821
3822         if (rx_work_limit > dev->quota)
3823                 rx_work_limit = dev->quota;
3824
3825         howmany = ucc_geth_rx(ugeth, rxQ, rx_work_limit);
3826
3827         dev->quota -= howmany;
3828         rx_work_limit -= howmany;
3829         *budget -= howmany;
3830
3831         if (rx_work_limit >= 0)
3832                 netif_rx_complete(dev);
3833
3834         return (rx_work_limit < 0) ? 1 : 0;
3835 }
3836 #endif                          /* CONFIG_UGETH_NAPI */
3837
3838 static irqreturn_t ucc_geth_irq_handler(int irq, void *info)
3839 {
3840         struct net_device *dev = (struct net_device *)info;
3841         struct ucc_geth_private *ugeth = netdev_priv(dev);
3842         struct ucc_fast_private *uccf;
3843         struct ucc_geth_info *ug_info;
3844         register u32 ucce = 0;
3845         register u32 bit_mask = UCCE_RXBF_SINGLE_MASK;
3846         register u32 tx_mask = UCCE_TXBF_SINGLE_MASK;
3847         register u8 i;
3848
3849         ugeth_vdbg("%s: IN", __FUNCTION__);
3850
3851         if (!ugeth)
3852                 return IRQ_NONE;
3853
3854         uccf = ugeth->uccf;
3855         ug_info = ugeth->ug_info;
3856
3857         do {
3858                 ucce |= (u32) (in_be32(uccf->p_ucce) & in_be32(uccf->p_uccm));
3859
3860                 /* clear event bits for next time */
3861                 /* Side effect here is to mask ucce variable
3862                 for future processing below. */
3863                 out_be32(uccf->p_ucce, ucce);   /* Clear with ones,
3864                                                 but only bits in UCCM */
3865
3866                 /* We ignore Tx interrupts because Tx confirmation is
3867                 done inside Tx routine */
3868
3869                 for (i = 0; i < ug_info->numQueuesRx; i++) {
3870                         if (ucce & bit_mask)
3871                                 ucc_geth_rx(ugeth, i,
3872                                             (int)ugeth->ug_info->
3873                                             bdRingLenRx[i]);
3874                         ucce &= ~bit_mask;
3875                         bit_mask <<= 1;
3876                 }
3877
3878                 for (i = 0; i < ug_info->numQueuesTx; i++) {
3879                         if (ucce & tx_mask)
3880                                 ucc_geth_tx(dev, i);
3881                         ucce &= ~tx_mask;
3882                         tx_mask <<= 1;
3883                 }
3884
3885                 /* Exceptions */
3886                 if (ucce & UCCE_BSY) {
3887                         ugeth_vdbg("Got BUSY irq!!!!");
3888                         ugeth->stats.rx_errors++;
3889                         ucce &= ~UCCE_BSY;
3890                 }
3891                 if (ucce & UCCE_OTHER) {
3892                         ugeth_vdbg("Got frame with error (ucce - 0x%08x)!!!!",
3893                                    ucce);
3894                         ugeth->stats.rx_errors++;
3895                         ucce &= ~ucce;
3896                 }
3897         }
3898         while (ucce);
3899
3900         return IRQ_HANDLED;
3901 }
3902
3903 static irqreturn_t phy_interrupt(int irq, void *dev_id)
3904 {
3905         struct net_device *dev = (struct net_device *)dev_id;
3906         struct ucc_geth_private *ugeth = netdev_priv(dev);
3907
3908         ugeth_vdbg("%s: IN", __FUNCTION__);
3909
3910         /* Clear the interrupt */
3911         mii_clear_phy_interrupt(ugeth->mii_info);
3912
3913         /* Disable PHY interrupts */
3914         mii_configure_phy_interrupt(ugeth->mii_info, MII_INTERRUPT_DISABLED);
3915
3916         /* Schedule the phy change */
3917         schedule_work(&ugeth->tq);
3918
3919         return IRQ_HANDLED;
3920 }
3921
3922 /* Scheduled by the phy_interrupt/timer to handle PHY changes */
3923 static void ugeth_phy_change(void *data)
3924 {
3925         struct net_device *dev = (struct net_device *)data;
3926         struct ucc_geth_private *ugeth = netdev_priv(dev);
3927         struct ucc_geth *ug_regs;
3928         int result = 0;
3929
3930         ugeth_vdbg("%s: IN", __FUNCTION__);
3931
3932         ug_regs = ugeth->ug_regs;
3933
3934         /* Delay to give the PHY a chance to change the
3935          * register state */
3936         msleep(1);
3937
3938         /* Update the link, speed, duplex */
3939         result = ugeth->mii_info->phyinfo->read_status(ugeth->mii_info);
3940
3941         /* Adjust the known status as long as the link
3942          * isn't still coming up */
3943         if ((0 == result) || (ugeth->mii_info->link == 0))
3944                 adjust_link(dev);
3945
3946         /* Reenable interrupts, if needed */
3947         if (ugeth->ug_info->board_flags & FSL_UGETH_BRD_HAS_PHY_INTR)
3948                 mii_configure_phy_interrupt(ugeth->mii_info,
3949                                             MII_INTERRUPT_ENABLED);
3950 }
3951
3952 /* Called every so often on systems that don't interrupt
3953  * the core for PHY changes */
3954 static void ugeth_phy_timer(unsigned long data)
3955 {
3956         struct net_device *dev = (struct net_device *)data;
3957         struct ucc_geth_private *ugeth = netdev_priv(dev);
3958
3959         schedule_work(&ugeth->tq);
3960
3961         mod_timer(&ugeth->phy_info_timer, jiffies + PHY_CHANGE_TIME * HZ);
3962 }
3963
3964 /* Keep trying aneg for some time
3965  * If, after GFAR_AN_TIMEOUT seconds, it has not
3966  * finished, we switch to forced.
3967  * Either way, once the process has completed, we either
3968  * request the interrupt, or switch the timer over to
3969  * using ugeth_phy_timer to check status */
3970 static void ugeth_phy_startup_timer(unsigned long data)
3971 {
3972         struct ugeth_mii_info *mii_info = (struct ugeth_mii_info *)data;
3973         struct ucc_geth_private *ugeth = netdev_priv(mii_info->dev);
3974         static int secondary = UGETH_AN_TIMEOUT;
3975         int result;
3976
3977         /* Configure the Auto-negotiation */
3978         result = mii_info->phyinfo->config_aneg(mii_info);
3979
3980         /* If autonegotiation failed to start, and
3981          * we haven't timed out, reset the timer, and return */
3982         if (result && secondary--) {
3983                 mod_timer(&ugeth->phy_info_timer, jiffies + HZ);
3984                 return;
3985         } else if (result) {
3986                 /* Couldn't start autonegotiation.
3987                  * Try switching to forced */
3988                 mii_info->autoneg = 0;
3989                 result = mii_info->phyinfo->config_aneg(mii_info);
3990
3991                 /* Forcing failed!  Give up */
3992                 if (result) {
3993                         ugeth_err("%s: Forcing failed!", mii_info->dev->name);
3994                         return;
3995                 }
3996         }
3997
3998         /* Kill the timer so it can be restarted */
3999         del_timer_sync(&ugeth->phy_info_timer);
4000
4001         /* Grab the PHY interrupt, if necessary/possible */
4002         if (ugeth->ug_info->board_flags & FSL_UGETH_BRD_HAS_PHY_INTR) {
4003                 if (request_irq(ugeth->ug_info->phy_interrupt,
4004                                 phy_interrupt,
4005                                 SA_SHIRQ, "phy_interrupt", mii_info->dev) < 0) {
4006                         ugeth_err("%s: Can't get IRQ %d (PHY)",
4007                                   mii_info->dev->name,
4008                                   ugeth->ug_info->phy_interrupt);
4009                 } else {
4010                         mii_configure_phy_interrupt(ugeth->mii_info,
4011                                                     MII_INTERRUPT_ENABLED);
4012                         return;
4013                 }
4014         }
4015
4016         /* Start the timer again, this time in order to
4017          * handle a change in status */
4018         init_timer(&ugeth->phy_info_timer);
4019         ugeth->phy_info_timer.function = &ugeth_phy_timer;
4020         ugeth->phy_info_timer.data = (unsigned long)mii_info->dev;
4021         mod_timer(&ugeth->phy_info_timer, jiffies + PHY_CHANGE_TIME * HZ);
4022 }
4023
4024 /* Called when something needs to use the ethernet device */
4025 /* Returns 0 for success. */
4026 static int ucc_geth_open(struct net_device *dev)
4027 {
4028         struct ucc_geth_private *ugeth = netdev_priv(dev);
4029         int err;
4030
4031         ugeth_vdbg("%s: IN", __FUNCTION__);
4032
4033         /* Test station address */
4034         if (dev->dev_addr[0] & ENET_GROUP_ADDR) {
4035                 ugeth_err("%s: Multicast address used for station address"
4036                           " - is this what you wanted?", __FUNCTION__);
4037                 return -EINVAL;
4038         }
4039
4040         err = ucc_geth_startup(ugeth);
4041         if (err) {
4042                 ugeth_err("%s: Cannot configure net device, aborting.",
4043                           dev->name);
4044                 return err;
4045         }
4046
4047         err = adjust_enet_interface(ugeth);
4048         if (err) {
4049                 ugeth_err("%s: Cannot configure net device, aborting.",
4050                           dev->name);
4051                 return err;
4052         }
4053
4054         /*       Set MACSTNADDR1, MACSTNADDR2                */
4055         /* For more details see the hardware spec.           */
4056         init_mac_station_addr_regs(dev->dev_addr[0],
4057                                    dev->dev_addr[1],
4058                                    dev->dev_addr[2],
4059                                    dev->dev_addr[3],
4060                                    dev->dev_addr[4],
4061                                    dev->dev_addr[5],
4062                                    &ugeth->ug_regs->macstnaddr1,
4063                                    &ugeth->ug_regs->macstnaddr2);
4064
4065         err = init_phy(dev);
4066         if (err) {
4067                 ugeth_err("%s: Cannot initialzie PHY, aborting.", dev->name);
4068                 return err;
4069         }
4070 #ifndef CONFIG_UGETH_NAPI
4071         err =
4072             request_irq(ugeth->ug_info->uf_info.irq, ucc_geth_irq_handler, 0,
4073                         "UCC Geth", dev);
4074         if (err) {
4075                 ugeth_err("%s: Cannot get IRQ for net device, aborting.",
4076                           dev->name);
4077                 ucc_geth_stop(ugeth);
4078                 return err;
4079         }
4080 #endif                          /* CONFIG_UGETH_NAPI */
4081
4082         /* Set up the PHY change work queue */
4083         INIT_WORK(&ugeth->tq, ugeth_phy_change, dev);
4084
4085         init_timer(&ugeth->phy_info_timer);
4086         ugeth->phy_info_timer.function = &ugeth_phy_startup_timer;
4087         ugeth->phy_info_timer.data = (unsigned long)ugeth->mii_info;
4088         mod_timer(&ugeth->phy_info_timer, jiffies + HZ);
4089
4090         err = ugeth_enable(ugeth, COMM_DIR_RX_AND_TX);
4091         if (err) {
4092                 ugeth_err("%s: Cannot enable net device, aborting.", dev->name);
4093                 ucc_geth_stop(ugeth);
4094                 return err;
4095         }
4096
4097         netif_start_queue(dev);
4098
4099         return err;
4100 }
4101
4102 /* Stops the kernel queue, and halts the controller */
4103 static int ucc_geth_close(struct net_device *dev)
4104 {
4105         struct ucc_geth_private *ugeth = netdev_priv(dev);
4106
4107         ugeth_vdbg("%s: IN", __FUNCTION__);
4108
4109         ucc_geth_stop(ugeth);
4110
4111         /* Shutdown the PHY */
4112         if (ugeth->mii_info->phyinfo->close)
4113                 ugeth->mii_info->phyinfo->close(ugeth->mii_info);
4114
4115         kfree(ugeth->mii_info);
4116
4117         netif_stop_queue(dev);
4118
4119         return 0;
4120 }
4121
4122 const struct ethtool_ops ucc_geth_ethtool_ops = { };
4123
4124 static int ucc_geth_probe(struct of_device* ofdev, const struct of_device_id *match)
4125 {
4126         struct device *device = &ofdev->dev;
4127         struct device_node *np = ofdev->node;
4128         struct net_device *dev = NULL;
4129         struct ucc_geth_private *ugeth = NULL;
4130         struct ucc_geth_info *ug_info;
4131         struct resource res;
4132         struct device_node *phy;
4133         int err, ucc_num, phy_interface;
4134         static int mii_mng_configured = 0;
4135         const phandle *ph;
4136         const unsigned int *prop;
4137
4138         ugeth_vdbg("%s: IN", __FUNCTION__);
4139
4140         prop = get_property(np, "device-id", NULL);
4141         ucc_num = *prop - 1;
4142         if ((ucc_num < 0) || (ucc_num > 7))
4143                 return -ENODEV;
4144
4145         ug_info = &ugeth_info[ucc_num];
4146         ug_info->uf_info.ucc_num = ucc_num;
4147         prop = get_property(np, "rx-clock", NULL);
4148         ug_info->uf_info.rx_clock = *prop;
4149         prop = get_property(np, "tx-clock", NULL);
4150         ug_info->uf_info.tx_clock = *prop;
4151         err = of_address_to_resource(np, 0, &res);
4152         if (err)
4153                 return -EINVAL;
4154
4155         ug_info->uf_info.regs = res.start;
4156         ug_info->uf_info.irq = irq_of_parse_and_map(np, 0);
4157
4158         ph = get_property(np, "phy-handle", NULL);
4159         phy = of_find_node_by_phandle(*ph);
4160
4161         if (phy == NULL)
4162                 return -ENODEV;
4163
4164         prop = get_property(phy, "reg", NULL);
4165         ug_info->phy_address = *prop;
4166         prop = get_property(phy, "interface", NULL);
4167         ug_info->enet_interface = *prop;
4168         ug_info->phy_interrupt = irq_of_parse_and_map(phy, 0);
4169         ug_info->board_flags = (ug_info->phy_interrupt == NO_IRQ)?
4170                         0:FSL_UGETH_BRD_HAS_PHY_INTR;
4171
4172         printk(KERN_INFO "ucc_geth: UCC%1d at 0x%8x (irq = %d) \n",
4173                 ug_info->uf_info.ucc_num + 1, ug_info->uf_info.regs,
4174                 ug_info->uf_info.irq);
4175
4176         if (ug_info == NULL) {
4177                 ugeth_err("%s: [%d] Missing additional data!", __FUNCTION__,
4178                           ucc_num);
4179                 return -ENODEV;
4180         }
4181
4182         /* FIXME: Work around for early chip rev.               */
4183         /* There's a bug in initial chip rev(s) in the RGMII ac */
4184         /* timing.                                              */
4185         /* The following compensates by writing to the reserved */
4186         /* QE Port Output Hold Registers (CPOH1?).              */
4187         prop = get_property(phy, "interface", NULL);
4188         phy_interface = *prop;
4189         if ((phy_interface == ENET_1000_RGMII) ||
4190                         (phy_interface == ENET_100_RGMII) ||
4191                         (phy_interface == ENET_10_RGMII)) {
4192                 struct device_node *soc;
4193                 phys_addr_t immrbase = -1;
4194                 u32 *tmp_reg;
4195                 u32 tmp_val;
4196
4197                 soc = of_find_node_by_type(NULL, "soc");
4198                 if (soc) {
4199                         unsigned int size;
4200                         const void *prop = get_property(soc, "reg", &size);
4201                         immrbase = of_translate_address(soc, prop);
4202                         of_node_put(soc);
4203                 };
4204
4205                 tmp_reg = (u32 *) ioremap(immrbase + 0x14A8, 0x4);
4206                 tmp_val = in_be32(tmp_reg);
4207                 if (ucc_num == 1)
4208                         out_be32(tmp_reg, tmp_val | 0x00003000);
4209                 else if (ucc_num == 2)
4210                         out_be32(tmp_reg, tmp_val | 0x0c000000);
4211                 iounmap(tmp_reg);
4212         }
4213
4214         if (!mii_mng_configured) {
4215                 ucc_set_qe_mux_mii_mng(ucc_num);
4216                 mii_mng_configured = 1;
4217         }
4218
4219         /* Create an ethernet device instance */
4220         dev = alloc_etherdev(sizeof(*ugeth));
4221
4222         if (dev == NULL)
4223                 return -ENOMEM;
4224
4225         ugeth = netdev_priv(dev);
4226         spin_lock_init(&ugeth->lock);
4227
4228         dev_set_drvdata(device, dev);
4229
4230         /* Set the dev->base_addr to the gfar reg region */
4231         dev->base_addr = (unsigned long)(ug_info->uf_info.regs);
4232
4233         SET_MODULE_OWNER(dev);
4234         SET_NETDEV_DEV(dev, device);
4235
4236         /* Fill in the dev structure */
4237         dev->open = ucc_geth_open;
4238         dev->hard_start_xmit = ucc_geth_start_xmit;
4239         dev->tx_timeout = ucc_geth_timeout;
4240         dev->watchdog_timeo = TX_TIMEOUT;
4241 #ifdef CONFIG_UGETH_NAPI
4242         dev->poll = ucc_geth_poll;
4243         dev->weight = UCC_GETH_DEV_WEIGHT;
4244 #endif                          /* CONFIG_UGETH_NAPI */
4245         dev->stop = ucc_geth_close;
4246         dev->get_stats = ucc_geth_get_stats;
4247 //    dev->change_mtu = ucc_geth_change_mtu;
4248         dev->mtu = 1500;
4249         dev->set_multicast_list = ucc_geth_set_multi;
4250         dev->ethtool_ops = &ucc_geth_ethtool_ops;
4251
4252         err = register_netdev(dev);
4253         if (err) {
4254                 ugeth_err("%s: Cannot register net device, aborting.",
4255                           dev->name);
4256                 free_netdev(dev);
4257                 return err;
4258         }
4259
4260         ugeth->ug_info = ug_info;
4261         ugeth->dev = dev;
4262         memcpy(dev->dev_addr, get_property(np, "mac-address", NULL), 6);
4263
4264         return 0;
4265 }
4266
4267 static int ucc_geth_remove(struct of_device* ofdev)
4268 {
4269         struct device *device = &ofdev->dev;
4270         struct net_device *dev = dev_get_drvdata(device);
4271         struct ucc_geth_private *ugeth = netdev_priv(dev);
4272
4273         dev_set_drvdata(device, NULL);
4274         ucc_geth_memclean(ugeth);
4275         free_netdev(dev);
4276
4277         return 0;
4278 }
4279
4280 static struct of_device_id ucc_geth_match[] = {
4281         {
4282                 .type = "network",
4283                 .compatible = "ucc_geth",
4284         },
4285         {},
4286 };
4287
4288 MODULE_DEVICE_TABLE(of, ucc_geth_match);
4289
4290 static struct of_platform_driver ucc_geth_driver = {
4291         .name           = DRV_NAME,
4292         .match_table    = ucc_geth_match,
4293         .probe          = ucc_geth_probe,
4294         .remove         = ucc_geth_remove,
4295 };
4296
4297 static int __init ucc_geth_init(void)
4298 {
4299         int i;
4300
4301         printk(KERN_INFO "ucc_geth: " DRV_DESC "\n");
4302         for (i = 0; i < 8; i++)
4303                 memcpy(&(ugeth_info[i]), &ugeth_primary_info,
4304                        sizeof(ugeth_primary_info));
4305
4306         return of_register_platform_driver(&ucc_geth_driver);
4307 }
4308
4309 static void __exit ucc_geth_exit(void)
4310 {
4311         of_unregister_platform_driver(&ucc_geth_driver);
4312 }
4313
4314 module_init(ucc_geth_init);
4315 module_exit(ucc_geth_exit);
4316
4317 MODULE_AUTHOR("Freescale Semiconductor, Inc");
4318 MODULE_DESCRIPTION(DRV_DESC);
4319 MODULE_LICENSE("GPL");