2 * cirrus.h 1.4 1999/10/25 20:03:34
4 * The contents of this file are subject to the Mozilla Public License
5 * Version 1.1 (the "License"); you may not use this file except in
6 * compliance with the License. You may obtain a copy of the License
7 * at http://www.mozilla.org/MPL/
9 * Software distributed under the License is distributed on an "AS IS"
10 * basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See
11 * the License for the specific language governing rights and
12 * limitations under the License.
14 * The initial developer of the original code is David A. Hinds
15 * <dahinds@users.sourceforge.net>. Portions created by David A. Hinds
16 * are Copyright (C) 1999 David A. Hinds. All Rights Reserved.
18 * Alternatively, the contents of this file may be used under the
19 * terms of the GNU General Public License version 2 (the "GPL"), in which
20 * case the provisions of the GPL are applicable instead of the
21 * above. If you wish to allow the use of your version of this file
22 * only under the terms of the GPL and not to allow others to use
23 * your version of this file under the MPL, indicate your decision by
24 * deleting the provisions above and replace them with the notice and
25 * other provisions required by the GPL. If you do not delete the
26 * provisions above, a recipient may use your version of this file
27 * under either the MPL or the GPL.
30 #ifndef _LINUX_CIRRUS_H
31 #define _LINUX_CIRRUS_H
33 #ifndef PCI_VENDOR_ID_CIRRUS
34 #define PCI_VENDOR_ID_CIRRUS 0x1013
36 #ifndef PCI_DEVICE_ID_CIRRUS_6729
37 #define PCI_DEVICE_ID_CIRRUS_6729 0x1100
39 #ifndef PCI_DEVICE_ID_CIRRUS_6832
40 #define PCI_DEVICE_ID_CIRRUS_6832 0x1110
43 #define PD67_MISC_CTL_1 0x16 /* Misc control 1 */
44 #define PD67_FIFO_CTL 0x17 /* FIFO control */
45 #define PD67_MISC_CTL_2 0x1E /* Misc control 2 */
46 #define PD67_CHIP_INFO 0x1f /* Chip information */
47 #define PD67_ATA_CTL 0x026 /* 6730: ATA control */
48 #define PD67_EXT_INDEX 0x2e /* Extension index */
49 #define PD67_EXT_DATA 0x2f /* Extension data */
51 /* PD6722 extension registers -- indexed in PD67_EXT_INDEX */
52 #define PD67_DATA_MASK0 0x01 /* Data mask 0 */
53 #define PD67_DATA_MASK1 0x02 /* Data mask 1 */
54 #define PD67_DMA_CTL 0x03 /* DMA control */
56 /* PD6730 extension registers -- indexed in PD67_EXT_INDEX */
57 #define PD67_EXT_CTL_1 0x03 /* Extension control 1 */
58 #define PD67_MEM_PAGE(n) ((n)+5) /* PCI window bits 31:24 */
59 #define PD67_EXTERN_DATA 0x0a
60 #define PD67_MISC_CTL_3 0x25
61 #define PD67_SMB_PWR_CTL 0x26
63 /* I/O window address offset */
64 #define PD67_IO_OFF(w) (0x36+((w)<<1))
66 /* Timing register sets */
67 #define PD67_TIME_SETUP(n) (0x3a + 3*(n))
68 #define PD67_TIME_CMD(n) (0x3b + 3*(n))
69 #define PD67_TIME_RECOV(n) (0x3c + 3*(n))
71 /* Flags for PD67_MISC_CTL_1 */
72 #define PD67_MC1_5V_DET 0x01 /* 5v detect */
73 #define PD67_MC1_MEDIA_ENA 0x01 /* 6730: Multimedia enable */
74 #define PD67_MC1_VCC_3V 0x02 /* 3.3v Vcc */
75 #define PD67_MC1_PULSE_MGMT 0x04
76 #define PD67_MC1_PULSE_IRQ 0x08
77 #define PD67_MC1_SPKR_ENA 0x10
78 #define PD67_MC1_INPACK_ENA 0x80
80 /* Flags for PD67_FIFO_CTL */
81 #define PD67_FIFO_EMPTY 0x80
83 /* Flags for PD67_MISC_CTL_2 */
84 #define PD67_MC2_FREQ_BYPASS 0x01
85 #define PD67_MC2_DYNAMIC_MODE 0x02
86 #define PD67_MC2_SUSPEND 0x04
87 #define PD67_MC2_5V_CORE 0x08
88 #define PD67_MC2_LED_ENA 0x10 /* IRQ 12 is LED enable */
89 #define PD67_MC2_FAST_PCI 0x10 /* 6729: PCI bus > 25 MHz */
90 #define PD67_MC2_3STATE_BIT7 0x20 /* Floppy change bit */
91 #define PD67_MC2_DMA_MODE 0x40
92 #define PD67_MC2_IRQ15_RI 0x80 /* IRQ 15 is ring enable */
94 /* Flags for PD67_CHIP_INFO */
95 #define PD67_INFO_SLOTS 0x20 /* 0 = 1 slot, 1 = 2 slots */
96 #define PD67_INFO_CHIP_ID 0xc0
97 #define PD67_INFO_REV 0x1c
99 /* Fields in PD67_TIME_* registers */
100 #define PD67_TIME_SCALE 0xc0
101 #define PD67_TIME_SCALE_1 0x00
102 #define PD67_TIME_SCALE_16 0x40
103 #define PD67_TIME_SCALE_256 0x80
104 #define PD67_TIME_SCALE_4096 0xc0
105 #define PD67_TIME_MULT 0x3f
107 /* Fields in PD67_DMA_CTL */
108 #define PD67_DMA_MODE 0xc0
109 #define PD67_DMA_OFF 0x00
110 #define PD67_DMA_DREQ_INPACK 0x40
111 #define PD67_DMA_DREQ_WP 0x80
112 #define PD67_DMA_DREQ_BVD2 0xc0
113 #define PD67_DMA_PULLUP 0x20 /* Disable socket pullups? */
115 /* Fields in PD67_EXT_CTL_1 */
116 #define PD67_EC1_VCC_PWR_LOCK 0x01
117 #define PD67_EC1_AUTO_PWR_CLEAR 0x02
118 #define PD67_EC1_LED_ENA 0x04
119 #define PD67_EC1_INV_CARD_IRQ 0x08
120 #define PD67_EC1_INV_MGMT_IRQ 0x10
121 #define PD67_EC1_PULLUP_CTL 0x20
123 /* Fields in PD67_MISC_CTL_3 */
124 #define PD67_MC3_IRQ_MASK 0x03
125 #define PD67_MC3_IRQ_PCPCI 0x00
126 #define PD67_MC3_IRQ_EXTERN 0x01
127 #define PD67_MC3_IRQ_PCIWAY 0x02
128 #define PD67_MC3_IRQ_PCI 0x03
129 #define PD67_MC3_PWR_MASK 0x0c
130 #define PD67_MC3_PWR_SERIAL 0x00
131 #define PD67_MC3_PWR_TI2202 0x08
132 #define PD67_MC3_PWR_SMB 0x0c
134 /* Register definitions for Cirrus PD6832 PCI-to-CardBus bridge */
136 /* PD6832 extension registers -- indexed in PD67_EXT_INDEX */
137 #define PD68_EXT_CTL_2 0x0b
138 #define PD68_PCI_SPACE 0x22
139 #define PD68_PCCARD_SPACE 0x23
140 #define PD68_WINDOW_TYPE 0x24
141 #define PD68_EXT_CSC 0x2e
142 #define PD68_MISC_CTL_4 0x2f
143 #define PD68_MISC_CTL_5 0x30
144 #define PD68_MISC_CTL_6 0x31
146 /* Extra flags in PD67_MISC_CTL_3 */
147 #define PD68_MC3_HW_SUSP 0x10
148 #define PD68_MC3_MM_EXPAND 0x40
149 #define PD68_MC3_MM_ARM 0x80
151 /* Bridge Control Register */
152 #define PD6832_BCR_MGMT_IRQ_ENA 0x0800
154 /* Socket Number Register */
155 #define PD6832_SOCKET_NUMBER 0x004c /* 8 bit */
157 #endif /* _LINUX_CIRRUS_H */
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