2 * Copyright (C) 1994 Linus Torvalds
4 * Pentium III FXSR, SSE support
5 * General FPU state handling cleanups
6 * Gareth Hughes <gareth@valinux.com>, May 2000
7 * x86-64 work by Andi Kleen 2002
10 #ifndef _ASM_X86_I387_H
11 #define _ASM_X86_I387_H
13 #include <linux/sched.h>
14 #include <linux/kernel_stat.h>
15 #include <linux/regset.h>
17 #include <asm/processor.h>
18 #include <asm/sigcontext.h>
20 #include <asm/uaccess.h>
22 extern void fpu_init(void);
23 extern unsigned int mxcsr_feature_mask;
24 extern void mxcsr_feature_mask_init(void);
25 extern void init_fpu(struct task_struct *child);
26 extern asmlinkage void math_state_restore(void);
28 extern user_regset_active_fn fpregs_active, xfpregs_active;
29 extern user_regset_get_fn fpregs_get, xfpregs_get, fpregs_soft_get;
30 extern user_regset_set_fn fpregs_set, xfpregs_set, fpregs_soft_set;
32 #ifdef CONFIG_IA32_EMULATION
34 extern int save_i387_ia32(struct _fpstate_ia32 __user *buf);
35 extern int restore_i387_ia32(struct _fpstate_ia32 __user *buf);
40 /* Ignore delayed exceptions from user space */
41 static inline void tolerant_fwait(void)
43 asm volatile("1: fwait\n"
48 static inline int restore_fpu_checking(struct i387_fxsave_struct *fx)
52 asm volatile("1: rex64/fxrstor (%[fx])\n\t"
54 ".section .fixup,\"ax\"\n"
55 "3: movl $-1,%[err]\n"
60 #if 0 /* See comment in __save_init_fpu() below. */
61 : [fx] "r" (fx), "m" (*fx), "0" (0));
63 : [fx] "cdaSDb" (fx), "m" (*fx), "0" (0));
70 #define X87_FSW_ES (1 << 7) /* Exception Summary */
72 /* AMD CPUs don't save/restore FDP/FIP/FOP unless an exception
73 is pending. Clear the x87 state here by setting it to fixed
74 values. The kernel data segment can be sometimes 0 and sometimes
75 new user value. Both should be ok.
76 Use the PDA as safe address because it should be already in L1. */
77 static inline void clear_fpu_state(struct i387_fxsave_struct *fx)
79 if (unlikely(fx->swd & X87_FSW_ES))
80 asm volatile("fnclex");
81 alternative_input(ASM_NOP8 ASM_NOP2,
82 " emms\n" /* clear stack tags */
83 " fildl %%gs:0", /* load to clear state */
84 X86_FEATURE_FXSAVE_LEAK);
87 static inline int save_i387_checking(struct i387_fxsave_struct __user *fx)
91 asm volatile("1: rex64/fxsave (%[fx])\n\t"
93 ".section .fixup,\"ax\"\n"
94 "3: movl $-1,%[err]\n"
98 : [err] "=r" (err), "=m" (*fx)
99 #if 0 /* See comment in __fxsave_clear() below. */
100 : [fx] "r" (fx), "0" (0));
102 : [fx] "cdaSDb" (fx), "0" (0));
104 if (unlikely(err) && __clear_user(fx, sizeof(struct i387_fxsave_struct)))
106 /* No need to clear here because the caller clears USED_MATH */
110 static inline void __save_init_fpu(struct task_struct *tsk)
112 /* Using "rex64; fxsave %0" is broken because, if the memory operand
113 uses any extended registers for addressing, a second REX prefix
114 will be generated (to the assembler, rex64 followed by semicolon
115 is a separate instruction), and hence the 64-bitness is lost. */
117 /* Using "fxsaveq %0" would be the ideal choice, but is only supported
118 starting with gas 2.16. */
119 __asm__ __volatile__("fxsaveq %0"
120 : "=m" (tsk->thread.i387.fxsave));
122 /* Using, as a workaround, the properly prefixed form below isn't
123 accepted by any binutils version so far released, complaining that
124 the same type of prefix is used twice if an extended register is
125 needed for addressing (fix submitted to mainline 2005-11-21). */
126 __asm__ __volatile__("rex64/fxsave %0"
127 : "=m" (tsk->thread.i387.fxsave));
129 /* This, however, we can work around by forcing the compiler to select
130 an addressing mode that doesn't require extended registers. */
131 __asm__ __volatile__("rex64/fxsave %P2(%1)"
132 : "=m" (tsk->thread.i387.fxsave)
134 "i" (offsetof(__typeof__(*tsk),
135 thread.i387.fxsave)));
137 clear_fpu_state(&tsk->thread.i387.fxsave);
138 task_thread_info(tsk)->status &= ~TS_USEDFPU;
142 * Signal frame handlers.
145 static inline int save_i387(struct _fpstate __user *buf)
147 struct task_struct *tsk = current;
150 BUILD_BUG_ON(sizeof(struct user_i387_struct) !=
151 sizeof(tsk->thread.i387.fxsave));
153 if ((unsigned long)buf % 16)
154 printk("save_i387: bad fpstate %p\n", buf);
158 clear_used_math(); /* trigger finit */
159 if (task_thread_info(tsk)->status & TS_USEDFPU) {
160 err = save_i387_checking((struct i387_fxsave_struct __user *)buf);
162 task_thread_info(tsk)->status &= ~TS_USEDFPU;
165 if (__copy_to_user(buf, &tsk->thread.i387.fxsave,
166 sizeof(struct i387_fxsave_struct)))
173 * This restores directly out of user space. Exceptions are handled.
175 static inline int restore_i387(struct _fpstate __user *buf)
178 if (!(task_thread_info(current)->status & TS_USEDFPU)) {
180 task_thread_info(current)->status |= TS_USEDFPU;
182 return restore_fpu_checking((__force struct i387_fxsave_struct *)buf);
185 #else /* CONFIG_X86_32 */
187 static inline void tolerant_fwait(void)
189 asm volatile("fnclex ; fwait");
192 static inline void restore_fpu(struct task_struct *tsk)
195 * The "nop" is needed to make the instructions the same
202 "m" ((tsk)->thread.i387.fxsave));
205 /* We need a safe address that is cheap to find and that is already
206 in L1 during context switch. The best choices are unfortunately
207 different for UP and SMP */
209 #define safe_address (__per_cpu_offset[0])
211 #define safe_address (kstat_cpu(0).cpustat.user)
215 * These must be called with preempt disabled
217 static inline void __save_init_fpu(struct task_struct *tsk)
219 /* Use more nops than strictly needed in case the compiler
222 "fnsave %[fx] ;fwait;" GENERIC_NOP8 GENERIC_NOP4,
224 "bt $7,%[fsw] ; jnc 1f ; fnclex\n1:",
226 [fx] "m" (tsk->thread.i387.fxsave),
227 [fsw] "m" (tsk->thread.i387.fxsave.swd) : "memory");
228 /* AMD K7/K8 CPUs don't save/restore FDP/FIP/FOP unless an exception
229 is pending. Clear the x87 state here by setting it to fixed
230 values. safe_address is a random variable that should be in L1 */
232 GENERIC_NOP8 GENERIC_NOP2,
233 "emms\n\t" /* clear stack tags */
234 "fildl %[addr]", /* set F?P to defined value */
235 X86_FEATURE_FXSAVE_LEAK,
236 [addr] "m" (safe_address));
237 task_thread_info(tsk)->status &= ~TS_USEDFPU;
241 * Signal frame handlers...
243 extern int save_i387(struct _fpstate __user *buf);
244 extern int restore_i387(struct _fpstate __user *buf);
246 #endif /* CONFIG_X86_64 */
248 static inline void __unlazy_fpu(struct task_struct *tsk)
250 if (task_thread_info(tsk)->status & TS_USEDFPU) {
251 __save_init_fpu(tsk);
254 tsk->fpu_counter = 0;
257 static inline void __clear_fpu(struct task_struct *tsk)
259 if (task_thread_info(tsk)->status & TS_USEDFPU) {
261 task_thread_info(tsk)->status &= ~TS_USEDFPU;
266 static inline void kernel_fpu_begin(void)
268 struct thread_info *me = current_thread_info();
270 if (me->status & TS_USEDFPU)
271 __save_init_fpu(me->task);
276 static inline void kernel_fpu_end(void)
284 static inline void save_init_fpu(struct task_struct *tsk)
286 __save_init_fpu(tsk);
290 #define unlazy_fpu __unlazy_fpu
291 #define clear_fpu __clear_fpu
293 #else /* CONFIG_X86_32 */
296 * These disable preemption on their own and are safe
298 static inline void save_init_fpu(struct task_struct *tsk)
301 __save_init_fpu(tsk);
306 static inline void unlazy_fpu(struct task_struct *tsk)
313 static inline void clear_fpu(struct task_struct *tsk)
320 #endif /* CONFIG_X86_64 */
323 * i387 state interaction
325 static inline unsigned short get_fpu_cwd(struct task_struct *tsk)
328 return tsk->thread.i387.fxsave.cwd;
330 return (unsigned short)tsk->thread.i387.fsave.cwd;
334 static inline unsigned short get_fpu_swd(struct task_struct *tsk)
337 return tsk->thread.i387.fxsave.swd;
339 return (unsigned short)tsk->thread.i387.fsave.swd;
343 static inline unsigned short get_fpu_mxcsr(struct task_struct *tsk)
346 return tsk->thread.i387.fxsave.mxcsr;
348 return MXCSR_DEFAULT;
352 #endif /* _ASM_X86_I387_H */