git.oblomov.eu Git - linux-2.6/blob - arch/i386/kernel/io_apic.c

   1 /*
   2  *      Intel IO-APIC support for multi-Pentium hosts.
   3  *
   4  *      Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
   5  *
   6  *      Many thanks to Stig Venaas for trying out countless experimental
   7  *      patches and reporting/debugging problems patiently!
   8  *
   9  *      (c) 1999, Multiple IO-APIC support, developed by
  10  *      Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
  11  *      Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
  12  *      further tested and cleaned up by Zach Brown <zab@redhat.com>
  13  *      and Ingo Molnar <mingo@redhat.com>
  14  *
  15  *      Fixes
  16  *      Maciej W. Rozycki       :       Bits for genuine 82489DX APICs;
  17  *                                      thanks to Eric Gilmore
  18  *                                      and Rolf G. Tews
  19  *                                      for testing these extensively
  20  *      Paul Diefenbaugh        :       Added full ACPI support
  21  */
  22
  23 #include <linux/mm.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/init.h>
  26 #include <linux/delay.h>
  27 #include <linux/sched.h>
  28 #include <linux/smp_lock.h>
  29 #include <linux/mc146818rtc.h>
  30 #include <linux/compiler.h>
  31 #include <linux/acpi.h>
  32 #include <linux/module.h>
  33 #include <linux/sysdev.h>
  34 #include <linux/pci.h>
  35 #include <linux/msi.h>
  36 #include <linux/htirq.h>
  37 #include <linux/freezer.h>
  38
  39 #include <asm/io.h>
  40 #include <asm/smp.h>
  41 #include <asm/desc.h>
  42 #include <asm/timer.h>
  43 #include <asm/i8259.h>
  44 #include <asm/nmi.h>
  45 #include <asm/msidef.h>
  46 #include <asm/hypertransport.h>
  47
  48 #include <mach_apic.h>
  49 #include <mach_apicdef.h>
  50
  51 #include "io_ports.h"
  52
  53 int (*ioapic_renumber_irq)(int ioapic, int irq);
  54 atomic_t irq_mis_count;
  55
  56 /* Where if anywhere is the i8259 connect in external int mode */
  57 static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
  58
  59 static DEFINE_SPINLOCK(ioapic_lock);
  60 static DEFINE_SPINLOCK(vector_lock);
  61
  62 int timer_over_8254 __initdata = 1;
  63
  64 /*
  65  *      Is the SiS APIC rmw bug present ?
  66  *      -1 = don't know, 0 = no, 1 = yes
  67  */
  68 int sis_apic_bug = -1;
  69
  70 /*
  71  * # of IRQ routing registers
  72  */
  73 int nr_ioapic_registers[MAX_IO_APICS];
  74
  75 static int disable_timer_pin_1 __initdata;
  76
  77 /*
  78  * Rough estimation of how many shared IRQs there are, can
  79  * be changed anytime.
  80  */
  81 #define MAX_PLUS_SHARED_IRQS NR_IRQS
  82 #define PIN_MAP_SIZE (MAX_PLUS_SHARED_IRQS + NR_IRQS)
  83
  84 /*
  85  * This is performance-critical, we want to do it O(1)
  86  *
  87  * the indexing order of this array favors 1:1 mappings
  88  * between pins and IRQs.
  89  */
  90
  91 static struct irq_pin_list {
  92         int apic, pin, next;
  93 } irq_2_pin[PIN_MAP_SIZE];
  94
  95 struct io_apic {
  96         unsigned int index;
  97         unsigned int unused[3];
  98         unsigned int data;
  99 };
 100
 101 static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx)
 102 {
 103         return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx)
 104                 + (mp_ioapics[idx].mpc_apicaddr & ~PAGE_MASK);
 105 }
 106
 107 static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg)
 108 {
 109         struct io_apic __iomem *io_apic = io_apic_base(apic);
 110         writel(reg, &io_apic->index);
 111         return readl(&io_apic->data);
 112 }
 113
 114 static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value)
 115 {
 116         struct io_apic __iomem *io_apic = io_apic_base(apic);
 117         writel(reg, &io_apic->index);
 118         writel(value, &io_apic->data);
 119 }
 120
 121 /*
 122  * Re-write a value: to be used for read-modify-write
 123  * cycles where the read already set up the index register.
 124  *
 125  * Older SiS APIC requires we rewrite the index register
 126  */
 127 static inline void io_apic_modify(unsigned int apic, unsigned int reg, unsigned int value)
 128 {
 129         volatile struct io_apic __iomem *io_apic = io_apic_base(apic);
 130         if (sis_apic_bug)
 131                 writel(reg, &io_apic->index);
 132         writel(value, &io_apic->data);
 133 }
 134
 135 union entry_union {
 136         struct { u32 w1, w2; };
 137         struct IO_APIC_route_entry entry;
 138 };
 139
 140 static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin)
 141 {
 142         union entry_union eu;
 143         unsigned long flags;
 144         spin_lock_irqsave(&ioapic_lock, flags);
 145         eu.w1 = io_apic_read(apic, 0x10 + 2 * pin);
 146         eu.w2 = io_apic_read(apic, 0x11 + 2 * pin);
 147         spin_unlock_irqrestore(&ioapic_lock, flags);
 148         return eu.entry;
 149 }
 150
 151 /*
 152  * When we write a new IO APIC routing entry, we need to write the high
 153  * word first! If the mask bit in the low word is clear, we will enable
 154  * the interrupt, and we need to make sure the entry is fully populated
 155  * before that happens.
 156  */
 157 static void
 158 __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
 159 {
 160         union entry_union eu;
 161         eu.entry = e;
 162         io_apic_write(apic, 0x11 + 2*pin, eu.w2);
 163         io_apic_write(apic, 0x10 + 2*pin, eu.w1);
 164 }
 165
 166 static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
 167 {
 168         unsigned long flags;
 169         spin_lock_irqsave(&ioapic_lock, flags);
 170         __ioapic_write_entry(apic, pin, e);
 171         spin_unlock_irqrestore(&ioapic_lock, flags);
 172 }
 173
 174 /*
 175  * When we mask an IO APIC routing entry, we need to write the low
 176  * word first, in order to set the mask bit before we change the
 177  * high bits!
 178  */
 179 static void ioapic_mask_entry(int apic, int pin)
 180 {
 181         unsigned long flags;
 182         union entry_union eu = { .entry.mask = 1 };
 183
 184         spin_lock_irqsave(&ioapic_lock, flags);
 185         io_apic_write(apic, 0x10 + 2*pin, eu.w1);
 186         io_apic_write(apic, 0x11 + 2*pin, eu.w2);
 187         spin_unlock_irqrestore(&ioapic_lock, flags);
 188 }
 189
 190 /*
 191  * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
 192  * shared ISA-space IRQs, so we have to support them. We are super
 193  * fast in the common case, and fast for shared ISA-space IRQs.
 194  */
 195 static void add_pin_to_irq(unsigned int irq, int apic, int pin)
 196 {
 197         static int first_free_entry = NR_IRQS;
 198         struct irq_pin_list *entry = irq_2_pin + irq;
 199
 200         while (entry->next)
 201                 entry = irq_2_pin + entry->next;
 202
 203         if (entry->pin != -1) {
 204                 entry->next = first_free_entry;
 205                 entry = irq_2_pin + entry->next;
 206                 if (++first_free_entry >= PIN_MAP_SIZE)
 207                         panic("io_apic.c: whoops");
 208         }
 209         entry->apic = apic;
 210         entry->pin = pin;
 211 }
 212
 213 /*
 214  * Reroute an IRQ to a different pin.
 215  */
 216 static void __init replace_pin_at_irq(unsigned int irq,
 217                                       int oldapic, int oldpin,
 218                                       int newapic, int newpin)
 219 {
 220         struct irq_pin_list *entry = irq_2_pin + irq;
 221
 222         while (1) {
 223                 if (entry->apic == oldapic && entry->pin == oldpin) {
 224                         entry->apic = newapic;
 225                         entry->pin = newpin;
 226                 }
 227                 if (!entry->next)
 228                         break;
 229                 entry = irq_2_pin + entry->next;
 230         }
 231 }
 232
 233 static void __modify_IO_APIC_irq (unsigned int irq, unsigned long enable, unsigned long disable)
 234 {
 235         struct irq_pin_list *entry = irq_2_pin + irq;
 236         unsigned int pin, reg;
 237
 238         for (;;) {
 239                 pin = entry->pin;
 240                 if (pin == -1)
 241                         break;
 242                 reg = io_apic_read(entry->apic, 0x10 + pin*2);
 243                 reg &= ~disable;
 244                 reg |= enable;
 245                 io_apic_modify(entry->apic, 0x10 + pin*2, reg);
 246                 if (!entry->next)
 247                         break;
 248                 entry = irq_2_pin + entry->next;
 249         }
 250 }
 251
 252 /* mask = 1 */
 253 static void __mask_IO_APIC_irq (unsigned int irq)
 254 {
 255         __modify_IO_APIC_irq(irq, 0x00010000, 0);
 256 }
 257
 258 /* mask = 0 */
 259 static void __unmask_IO_APIC_irq (unsigned int irq)
 260 {
 261         __modify_IO_APIC_irq(irq, 0, 0x00010000);
 262 }
 263
 264 /* mask = 1, trigger = 0 */
 265 static void __mask_and_edge_IO_APIC_irq (unsigned int irq)
 266 {
 267         __modify_IO_APIC_irq(irq, 0x00010000, 0x00008000);
 268 }
 269
 270 /* mask = 0, trigger = 1 */
 271 static void __unmask_and_level_IO_APIC_irq (unsigned int irq)
 272 {
 273         __modify_IO_APIC_irq(irq, 0x00008000, 0x00010000);
 274 }
 275
 276 static void mask_IO_APIC_irq (unsigned int irq)
 277 {
 278         unsigned long flags;
 279
 280         spin_lock_irqsave(&ioapic_lock, flags);
 281         __mask_IO_APIC_irq(irq);
 282         spin_unlock_irqrestore(&ioapic_lock, flags);
 283 }
 284
 285 static void unmask_IO_APIC_irq (unsigned int irq)
 286 {
 287         unsigned long flags;
 288
 289         spin_lock_irqsave(&ioapic_lock, flags);
 290         __unmask_IO_APIC_irq(irq);
 291         spin_unlock_irqrestore(&ioapic_lock, flags);
 292 }
 293
 294 static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
 295 {
 296         struct IO_APIC_route_entry entry;
 297
 298         /* Check delivery_mode to be sure we're not clearing an SMI pin */
 299         entry = ioapic_read_entry(apic, pin);
 300         if (entry.delivery_mode == dest_SMI)
 301                 return;
 302
 303         /*
 304          * Disable it in the IO-APIC irq-routing table:
 305          */
 306         ioapic_mask_entry(apic, pin);
 307 }
 308
 309 static void clear_IO_APIC (void)
 310 {
 311         int apic, pin;
 312
 313         for (apic = 0; apic < nr_ioapics; apic++)
 314                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
 315                         clear_IO_APIC_pin(apic, pin);
 316 }
 317
 318 #ifdef CONFIG_SMP
 319 static void set_ioapic_affinity_irq(unsigned int irq, cpumask_t cpumask)
 320 {
 321         unsigned long flags;
 322         int pin;
 323         struct irq_pin_list *entry = irq_2_pin + irq;
 324         unsigned int apicid_value;
 325         cpumask_t tmp;
 326
 327         cpus_and(tmp, cpumask, cpu_online_map);
 328         if (cpus_empty(tmp))
 329                 tmp = TARGET_CPUS;
 330
 331         cpus_and(cpumask, tmp, CPU_MASK_ALL);
 332
 333         apicid_value = cpu_mask_to_apicid(cpumask);
 334         /* Prepare to do the io_apic_write */
 335         apicid_value = apicid_value << 24;
 336         spin_lock_irqsave(&ioapic_lock, flags);
 337         for (;;) {
 338                 pin = entry->pin;
 339                 if (pin == -1)
 340                         break;
 341                 io_apic_write(entry->apic, 0x10 + 1 + pin*2, apicid_value);
 342                 if (!entry->next)
 343                         break;
 344                 entry = irq_2_pin + entry->next;
 345         }
 346         irq_desc[irq].affinity = cpumask;
 347         spin_unlock_irqrestore(&ioapic_lock, flags);
 348 }
 349
 350 #if defined(CONFIG_IRQBALANCE)
 351 # include <asm/processor.h>     /* kernel_thread() */
 352 # include <linux/kernel_stat.h> /* kstat */
 353 # include <linux/slab.h>                /* kmalloc() */
 354 # include <linux/timer.h>       /* time_after() */
 355
 356 #ifdef CONFIG_BALANCED_IRQ_DEBUG
 357 #  define TDprintk(x...) do { printk("<%ld:%s:%d>: ", jiffies, __FILE__, __LINE__); printk(x); } while (0)
 358 #  define Dprintk(x...) do { TDprintk(x); } while (0)
 359 # else
 360 #  define TDprintk(x...)
 361 #  define Dprintk(x...)
 362 # endif
 363
 364 #define IRQBALANCE_CHECK_ARCH -999
 365 #define MAX_BALANCED_IRQ_INTERVAL       (5*HZ)
 366 #define MIN_BALANCED_IRQ_INTERVAL       (HZ/2)
 367 #define BALANCED_IRQ_MORE_DELTA         (HZ/10)
 368 #define BALANCED_IRQ_LESS_DELTA         (HZ)
 369
 370 static int irqbalance_disabled __read_mostly = IRQBALANCE_CHECK_ARCH;
 371 static int physical_balance __read_mostly;
 372 static long balanced_irq_interval __read_mostly = MAX_BALANCED_IRQ_INTERVAL;
 373
 374 static struct irq_cpu_info {
 375         unsigned long * last_irq;
 376         unsigned long * irq_delta;
 377         unsigned long irq;
 378 } irq_cpu_data[NR_CPUS];
 379
 380 #define CPU_IRQ(cpu)            (irq_cpu_data[cpu].irq)
 381 #define LAST_CPU_IRQ(cpu,irq)   (irq_cpu_data[cpu].last_irq[irq])
 382 #define IRQ_DELTA(cpu,irq)      (irq_cpu_data[cpu].irq_delta[irq])
 383
 384 #define IDLE_ENOUGH(cpu,now) \
 385         (idle_cpu(cpu) && ((now) - per_cpu(irq_stat, (cpu)).idle_timestamp > 1))
 386
 387 #define IRQ_ALLOWED(cpu, allowed_mask)  cpu_isset(cpu, allowed_mask)
 388
 389 #define CPU_TO_PACKAGEINDEX(i) (first_cpu(cpu_sibling_map[i]))
 390
 391 static cpumask_t balance_irq_affinity[NR_IRQS] = {
 392         [0 ... NR_IRQS-1] = CPU_MASK_ALL
 393 };
 394
 395 void set_balance_irq_affinity(unsigned int irq, cpumask_t mask)
 396 {
 397         balance_irq_affinity[irq] = mask;
 398 }
 399
 400 static unsigned long move(int curr_cpu, cpumask_t allowed_mask,
 401                         unsigned long now, int direction)
 402 {
 403         int search_idle = 1;
 404         int cpu = curr_cpu;
 405
 406         goto inside;
 407
 408         do {
 409                 if (unlikely(cpu == curr_cpu))
 410                         search_idle = 0;
 411 inside:
 412                 if (direction == 1) {
 413                         cpu++;
 414                         if (cpu >= NR_CPUS)
 415                                 cpu = 0;
 416                 } else {
 417                         cpu--;
 418                         if (cpu == -1)
 419                                 cpu = NR_CPUS-1;
 420                 }
 421         } while (!cpu_online(cpu) || !IRQ_ALLOWED(cpu,allowed_mask) ||
 422                         (search_idle && !IDLE_ENOUGH(cpu,now)));
 423
 424         return cpu;
 425 }
 426
 427 static inline void balance_irq(int cpu, int irq)
 428 {
 429         unsigned long now = jiffies;
 430         cpumask_t allowed_mask;
 431         unsigned int new_cpu;
 432
 433         if (irqbalance_disabled)
 434                 return;
 435
 436         cpus_and(allowed_mask, cpu_online_map, balance_irq_affinity[irq]);
 437         new_cpu = move(cpu, allowed_mask, now, 1);
 438         if (cpu != new_cpu) {
 439                 set_pending_irq(irq, cpumask_of_cpu(new_cpu));
 440         }
 441 }
 442
 443 static inline void rotate_irqs_among_cpus(unsigned long useful_load_threshold)
 444 {
 445         int i, j;
 446         Dprintk("Rotating IRQs among CPUs.\n");
 447         for_each_online_cpu(i) {
 448                 for (j = 0; j < NR_IRQS; j++) {
 449                         if (!irq_desc[j].action)
 450                                 continue;
 451                         /* Is it a significant load ?  */
 452                         if (IRQ_DELTA(CPU_TO_PACKAGEINDEX(i),j) <
 453                                                 useful_load_threshold)
 454                                 continue;
 455                         balance_irq(i, j);
 456                 }
 457         }
 458         balanced_irq_interval = max((long)MIN_BALANCED_IRQ_INTERVAL,
 459                 balanced_irq_interval - BALANCED_IRQ_LESS_DELTA);
 460         return;
 461 }
 462
 463 static void do_irq_balance(void)
 464 {
 465         int i, j;
 466         unsigned long max_cpu_irq = 0, min_cpu_irq = (~0);
 467         unsigned long move_this_load = 0;
 468         int max_loaded = 0, min_loaded = 0;
 469         int load;
 470         unsigned long useful_load_threshold = balanced_irq_interval + 10;
 471         int selected_irq;
 472         int tmp_loaded, first_attempt = 1;
 473         unsigned long tmp_cpu_irq;
 474         unsigned long imbalance = 0;
 475         cpumask_t allowed_mask, target_cpu_mask, tmp;
 476
 477         for_each_possible_cpu(i) {
 478                 int package_index;
 479                 CPU_IRQ(i) = 0;
 480                 if (!cpu_online(i))
 481                         continue;
 482                 package_index = CPU_TO_PACKAGEINDEX(i);
 483                 for (j = 0; j < NR_IRQS; j++) {
 484                         unsigned long value_now, delta;
 485                         /* Is this an active IRQ or balancing disabled ? */
 486                         if (!irq_desc[j].action || irq_balancing_disabled(j))
 487                                 continue;
 488                         if ( package_index == i )
 489                                 IRQ_DELTA(package_index,j) = 0;
 490                         /* Determine the total count per processor per IRQ */
 491                         value_now = (unsigned long) kstat_cpu(i).irqs[j];
 492
 493                         /* Determine the activity per processor per IRQ */
 494                         delta = value_now - LAST_CPU_IRQ(i,j);
 495
 496                         /* Update last_cpu_irq[][] for the next time */
 497                         LAST_CPU_IRQ(i,j) = value_now;
 498
 499                         /* Ignore IRQs whose rate is less than the clock */
 500                         if (delta < useful_load_threshold)
 501                                 continue;
 502                         /* update the load for the processor or package total */
 503                         IRQ_DELTA(package_index,j) += delta;
 504
 505                         /* Keep track of the higher numbered sibling as well */
 506                         if (i != package_index)
 507                                 CPU_IRQ(i) += delta;
 508                         /*
 509                          * We have sibling A and sibling B in the package
 510                          *
 511                          * cpu_irq[A] = load for cpu A + load for cpu B
 512                          * cpu_irq[B] = load for cpu B
 513                          */
 514                         CPU_IRQ(package_index) += delta;
 515                 }
 516         }
 517         /* Find the least loaded processor package */
 518         for_each_online_cpu(i) {
 519                 if (i != CPU_TO_PACKAGEINDEX(i))
 520                         continue;
 521                 if (min_cpu_irq > CPU_IRQ(i)) {
 522                         min_cpu_irq = CPU_IRQ(i);
 523                         min_loaded = i;
 524                 }
 525         }
 526         max_cpu_irq = ULONG_MAX;
 527
 528 tryanothercpu:
 529         /* Look for heaviest loaded processor.
 530          * We may come back to get the next heaviest loaded processor.
 531          * Skip processors with trivial loads.
 532          */
 533         tmp_cpu_irq = 0;
 534         tmp_loaded = -1;
 535         for_each_online_cpu(i) {
 536                 if (i != CPU_TO_PACKAGEINDEX(i))
 537                         continue;
 538                 if (max_cpu_irq <= CPU_IRQ(i))
 539                         continue;
 540                 if (tmp_cpu_irq < CPU_IRQ(i)) {
 541                         tmp_cpu_irq = CPU_IRQ(i);
 542                         tmp_loaded = i;
 543                 }
 544         }
 545
 546         if (tmp_loaded == -1) {
 547          /* In the case of small number of heavy interrupt sources,
 548           * loading some of the cpus too much. We use Ingo's original
 549           * approach to rotate them around.
 550           */
 551                 if (!first_attempt && imbalance >= useful_load_threshold) {
 552                         rotate_irqs_among_cpus(useful_load_threshold);
 553                         return;
 554                 }
 555                 goto not_worth_the_effort;
 556         }
 557
 558         first_attempt = 0;              /* heaviest search */
 559         max_cpu_irq = tmp_cpu_irq;      /* load */
 560         max_loaded = tmp_loaded;        /* processor */
 561         imbalance = (max_cpu_irq - min_cpu_irq) / 2;
 562
 563         Dprintk("max_loaded cpu = %d\n", max_loaded);
 564         Dprintk("min_loaded cpu = %d\n", min_loaded);
 565         Dprintk("max_cpu_irq load = %ld\n", max_cpu_irq);
 566         Dprintk("min_cpu_irq load = %ld\n", min_cpu_irq);
 567         Dprintk("load imbalance = %lu\n", imbalance);
 568
 569         /* if imbalance is less than approx 10% of max load, then
 570          * observe diminishing returns action. - quit
 571          */
 572         if (imbalance < (max_cpu_irq >> 3)) {
 573                 Dprintk("Imbalance too trivial\n");
 574                 goto not_worth_the_effort;
 575         }
 576
 577 tryanotherirq:
 578         /* if we select an IRQ to move that can't go where we want, then
 579          * see if there is another one to try.
 580          */
 581         move_this_load = 0;
 582         selected_irq = -1;
 583         for (j = 0; j < NR_IRQS; j++) {
 584                 /* Is this an active IRQ? */
 585                 if (!irq_desc[j].action)
 586                         continue;
 587                 if (imbalance <= IRQ_DELTA(max_loaded,j))
 588                         continue;
 589                 /* Try to find the IRQ that is closest to the imbalance
 590                  * without going over.
 591                  */
 592                 if (move_this_load < IRQ_DELTA(max_loaded,j)) {
 593                         move_this_load = IRQ_DELTA(max_loaded,j);
 594                         selected_irq = j;
 595                 }
 596         }
 597         if (selected_irq == -1) {
 598                 goto tryanothercpu;
 599         }
 600
 601         imbalance = move_this_load;
 602
 603         /* For physical_balance case, we accumlated both load
 604          * values in the one of the siblings cpu_irq[],
 605          * to use the same code for physical and logical processors
 606          * as much as possible.
 607          *
 608          * NOTE: the cpu_irq[] array holds the sum of the load for
 609          * sibling A and sibling B in the slot for the lowest numbered
 610          * sibling (A), _AND_ the load for sibling B in the slot for
 611          * the higher numbered sibling.
 612          *
 613          * We seek the least loaded sibling by making the comparison
 614          * (A+B)/2 vs B
 615          */
 616         load = CPU_IRQ(min_loaded) >> 1;
 617         for_each_cpu_mask(j, cpu_sibling_map[min_loaded]) {
 618                 if (load > CPU_IRQ(j)) {
 619                         /* This won't change cpu_sibling_map[min_loaded] */
 620                         load = CPU_IRQ(j);
 621                         min_loaded = j;
 622                 }
 623         }
 624
 625         cpus_and(allowed_mask,
 626                 cpu_online_map,
 627                 balance_irq_affinity[selected_irq]);
 628         target_cpu_mask = cpumask_of_cpu(min_loaded);
 629         cpus_and(tmp, target_cpu_mask, allowed_mask);
 630
 631         if (!cpus_empty(tmp)) {
 632
 633                 Dprintk("irq = %d moved to cpu = %d\n",
 634                                 selected_irq, min_loaded);
 635                 /* mark for change destination */
 636                 set_pending_irq(selected_irq, cpumask_of_cpu(min_loaded));
 637
 638                 /* Since we made a change, come back sooner to
 639                  * check for more variation.
 640                  */
 641                 balanced_irq_interval = max((long)MIN_BALANCED_IRQ_INTERVAL,
 642                         balanced_irq_interval - BALANCED_IRQ_LESS_DELTA);
 643                 return;
 644         }
 645         goto tryanotherirq;
 646
 647 not_worth_the_effort:
 648         /*
 649          * if we did not find an IRQ to move, then adjust the time interval
 650          * upward
 651          */
 652         balanced_irq_interval = min((long)MAX_BALANCED_IRQ_INTERVAL,
 653                 balanced_irq_interval + BALANCED_IRQ_MORE_DELTA);
 654         Dprintk("IRQ worth rotating not found\n");
 655         return;
 656 }
 657
 658 static int balanced_irq(void *unused)
 659 {
 660         int i;
 661         unsigned long prev_balance_time = jiffies;
 662         long time_remaining = balanced_irq_interval;
 663
 664         daemonize("kirqd");
 665
 666         /* push everything to CPU 0 to give us a starting point.  */
 667         for (i = 0 ; i < NR_IRQS ; i++) {
 668                 irq_desc[i].pending_mask = cpumask_of_cpu(0);
 669                 set_pending_irq(i, cpumask_of_cpu(0));
 670         }
 671
 672         for ( ; ; ) {
 673                 time_remaining = schedule_timeout_interruptible(time_remaining);
 674                 try_to_freeze();
 675                 if (time_after(jiffies,
 676                                 prev_balance_time+balanced_irq_interval)) {
 677                         preempt_disable();
 678                         do_irq_balance();
 679                         prev_balance_time = jiffies;
 680                         time_remaining = balanced_irq_interval;
 681                         preempt_enable();
 682                 }
 683         }
 684         return 0;
 685 }
 686
 687 static int __init balanced_irq_init(void)
 688 {
 689         int i;
 690         struct cpuinfo_x86 *c;
 691         cpumask_t tmp;
 692
 693         cpus_shift_right(tmp, cpu_online_map, 2);
 694         c = &boot_cpu_data;
 695         /* When not overwritten by the command line ask subarchitecture. */
 696         if (irqbalance_disabled == IRQBALANCE_CHECK_ARCH)
 697                 irqbalance_disabled = NO_BALANCE_IRQ;
 698         if (irqbalance_disabled)
 699                 return 0;
 700
 701          /* disable irqbalance completely if there is only one processor online */
 702         if (num_online_cpus() < 2) {
 703                 irqbalance_disabled = 1;
 704                 return 0;
 705         }
 706         /*
 707          * Enable physical balance only if more than 1 physical processor
 708          * is present
 709          */
 710         if (smp_num_siblings > 1 && !cpus_empty(tmp))
 711                 physical_balance = 1;
 712
 713         for_each_online_cpu(i) {
 714                 irq_cpu_data[i].irq_delta = kmalloc(sizeof(unsigned long) * NR_IRQS, GFP_KERNEL);
 715                 irq_cpu_data[i].last_irq = kmalloc(sizeof(unsigned long) * NR_IRQS, GFP_KERNEL);
 716                 if (irq_cpu_data[i].irq_delta == NULL || irq_cpu_data[i].last_irq == NULL) {
 717                         printk(KERN_ERR "balanced_irq_init: out of memory");
 718                         goto failed;
 719                 }
 720                 memset(irq_cpu_data[i].irq_delta,0,sizeof(unsigned long) * NR_IRQS);
 721                 memset(irq_cpu_data[i].last_irq,0,sizeof(unsigned long) * NR_IRQS);
 722         }
 723
 724         printk(KERN_INFO "Starting balanced_irq\n");
 725         if (kernel_thread(balanced_irq, NULL, CLONE_KERNEL) >= 0)
 726                 return 0;
 727         else
 728                 printk(KERN_ERR "balanced_irq_init: failed to spawn balanced_irq");
 729 failed:
 730         for_each_possible_cpu(i) {
 731                 kfree(irq_cpu_data[i].irq_delta);
 732                 irq_cpu_data[i].irq_delta = NULL;
 733                 kfree(irq_cpu_data[i].last_irq);
 734                 irq_cpu_data[i].last_irq = NULL;
 735         }
 736         return 0;
 737 }
 738
 739 int __init irqbalance_disable(char *str)
 740 {
 741         irqbalance_disabled = 1;
 742         return 1;
 743 }
 744
 745 __setup("noirqbalance", irqbalance_disable);
 746
 747 late_initcall(balanced_irq_init);
 748 #endif /* CONFIG_IRQBALANCE */
 749 #endif /* CONFIG_SMP */
 750
 751 #ifndef CONFIG_SMP
 752 void fastcall send_IPI_self(int vector)
 753 {
 754         unsigned int cfg;
 755
 756         /*
 757          * Wait for idle.
 758          */
 759         apic_wait_icr_idle();
 760         cfg = APIC_DM_FIXED | APIC_DEST_SELF | vector | APIC_DEST_LOGICAL;
 761         /*
 762          * Send the IPI. The write to APIC_ICR fires this off.
 763          */
 764         apic_write_around(APIC_ICR, cfg);
 765 }
 766 #endif /* !CONFIG_SMP */
 767
 768
 769 /*
 770  * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
 771  * specific CPU-side IRQs.
 772  */
 773
 774 #define MAX_PIRQS 8
 775 static int pirq_entries [MAX_PIRQS];
 776 static int pirqs_enabled;
 777 int skip_ioapic_setup;
 778
 779 static int __init ioapic_setup(char *str)
 780 {
 781         skip_ioapic_setup = 1;
 782         return 1;
 783 }
 784
 785 __setup("noapic", ioapic_setup);
 786
 787 static int __init ioapic_pirq_setup(char *str)
 788 {
 789         int i, max;
 790         int ints[MAX_PIRQS+1];
 791
 792         get_options(str, ARRAY_SIZE(ints), ints);
 793
 794         for (i = 0; i < MAX_PIRQS; i++)
 795                 pirq_entries[i] = -1;
 796
 797         pirqs_enabled = 1;
 798         apic_printk(APIC_VERBOSE, KERN_INFO
 799                         "PIRQ redirection, working around broken MP-BIOS.\n");
 800         max = MAX_PIRQS;
 801         if (ints[0] < MAX_PIRQS)
 802                 max = ints[0];
 803
 804         for (i = 0; i < max; i++) {
 805                 apic_printk(APIC_VERBOSE, KERN_DEBUG
 806                                 "... PIRQ%d -> IRQ %d\n", i, ints[i+1]);
 807                 /*
 808                  * PIRQs are mapped upside down, usually.
 809                  */
 810                 pirq_entries[MAX_PIRQS-i-1] = ints[i+1];
 811         }
 812         return 1;
 813 }
 814
 815 __setup("pirq=", ioapic_pirq_setup);
 816
 817 /*
 818  * Find the IRQ entry number of a certain pin.
 819  */
 820 static int find_irq_entry(int apic, int pin, int type)
 821 {
 822         int i;
 823
 824         for (i = 0; i < mp_irq_entries; i++)
 825                 if (mp_irqs[i].mpc_irqtype == type &&
 826                     (mp_irqs[i].mpc_dstapic == mp_ioapics[apic].mpc_apicid ||
 827                      mp_irqs[i].mpc_dstapic == MP_APIC_ALL) &&
 828                     mp_irqs[i].mpc_dstirq == pin)
 829                         return i;
 830
 831         return -1;
 832 }
 833
 834 /*
 835  * Find the pin to which IRQ[irq] (ISA) is connected
 836  */
 837 static int __init find_isa_irq_pin(int irq, int type)
 838 {
 839         int i;
 840
 841         for (i = 0; i < mp_irq_entries; i++) {
 842                 int lbus = mp_irqs[i].mpc_srcbus;
 843
 844                 if ((mp_bus_id_to_type[lbus] == MP_BUS_ISA ||
 845                      mp_bus_id_to_type[lbus] == MP_BUS_EISA ||
 846                      mp_bus_id_to_type[lbus] == MP_BUS_MCA
 847                     ) &&
 848                     (mp_irqs[i].mpc_irqtype == type) &&
 849                     (mp_irqs[i].mpc_srcbusirq == irq))
 850
 851                         return mp_irqs[i].mpc_dstirq;
 852         }
 853         return -1;
 854 }
 855
 856 static int __init find_isa_irq_apic(int irq, int type)
 857 {
 858         int i;
 859
 860         for (i = 0; i < mp_irq_entries; i++) {
 861                 int lbus = mp_irqs[i].mpc_srcbus;
 862
 863                 if ((mp_bus_id_to_type[lbus] == MP_BUS_ISA ||
 864                      mp_bus_id_to_type[lbus] == MP_BUS_EISA ||
 865                      mp_bus_id_to_type[lbus] == MP_BUS_MCA
 866                     ) &&
 867                     (mp_irqs[i].mpc_irqtype == type) &&
 868                     (mp_irqs[i].mpc_srcbusirq == irq))
 869                         break;
 870         }
 871         if (i < mp_irq_entries) {
 872                 int apic;
 873                 for(apic = 0; apic < nr_ioapics; apic++) {
 874                         if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic)
 875                                 return apic;
 876                 }
 877         }
 878
 879         return -1;
 880 }
 881
 882 /*
 883  * Find a specific PCI IRQ entry.
 884  * Not an __init, possibly needed by modules
 885  */
 886 static int pin_2_irq(int idx, int apic, int pin);
 887
 888 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
 889 {
 890         int apic, i, best_guess = -1;
 891
 892         apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, "
 893                 "slot:%d, pin:%d.\n", bus, slot, pin);
 894         if (mp_bus_id_to_pci_bus[bus] == -1) {
 895                 printk(KERN_WARNING "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
 896                 return -1;
 897         }
 898         for (i = 0; i < mp_irq_entries; i++) {
 899                 int lbus = mp_irqs[i].mpc_srcbus;
 900
 901                 for (apic = 0; apic < nr_ioapics; apic++)
 902                         if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic ||
 903                             mp_irqs[i].mpc_dstapic == MP_APIC_ALL)
 904                                 break;
 905
 906                 if ((mp_bus_id_to_type[lbus] == MP_BUS_PCI) &&
 907                     !mp_irqs[i].mpc_irqtype &&
 908                     (bus == lbus) &&
 909                     (slot == ((mp_irqs[i].mpc_srcbusirq >> 2) & 0x1f))) {
 910                         int irq = pin_2_irq(i,apic,mp_irqs[i].mpc_dstirq);
 911
 912                         if (!(apic || IO_APIC_IRQ(irq)))
 913                                 continue;
 914
 915                         if (pin == (mp_irqs[i].mpc_srcbusirq & 3))
 916                                 return irq;
 917                         /*
 918                          * Use the first all-but-pin matching entry as a
 919                          * best-guess fuzzy result for broken mptables.
 920                          */
 921                         if (best_guess < 0)
 922                                 best_guess = irq;
 923                 }
 924         }
 925         return best_guess;
 926 }
 927 EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector);
 928
 929 /*
 930  * This function currently is only a helper for the i386 smp boot process where
 931  * we need to reprogram the ioredtbls to cater for the cpus which have come online
 932  * so mask in all cases should simply be TARGET_CPUS
 933  */
 934 #ifdef CONFIG_SMP
 935 void __init setup_ioapic_dest(void)
 936 {
 937         int pin, ioapic, irq, irq_entry;
 938
 939         if (skip_ioapic_setup == 1)
 940                 return;
 941
 942         for (ioapic = 0; ioapic < nr_ioapics; ioapic++) {
 943                 for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
 944                         irq_entry = find_irq_entry(ioapic, pin, mp_INT);
 945                         if (irq_entry == -1)
 946                                 continue;
 947                         irq = pin_2_irq(irq_entry, ioapic, pin);
 948                         set_ioapic_affinity_irq(irq, TARGET_CPUS);
 949                 }
 950
 951         }
 952 }
 953 #endif
 954
 955 /*
 956  * EISA Edge/Level control register, ELCR
 957  */
 958 static int EISA_ELCR(unsigned int irq)
 959 {
 960         if (irq < 16) {
 961                 unsigned int port = 0x4d0 + (irq >> 3);
 962                 return (inb(port) >> (irq & 7)) & 1;
 963         }
 964         apic_printk(APIC_VERBOSE, KERN_INFO
 965                         "Broken MPtable reports ISA irq %d\n", irq);
 966         return 0;
 967 }
 968
 969 /* EISA interrupts are always polarity zero and can be edge or level
 970  * trigger depending on the ELCR value.  If an interrupt is listed as
 971  * EISA conforming in the MP table, that means its trigger type must
 972  * be read in from the ELCR */
 973
 974 #define default_EISA_trigger(idx)       (EISA_ELCR(mp_irqs[idx].mpc_srcbusirq))
 975 #define default_EISA_polarity(idx)      (0)
 976
 977 /* ISA interrupts are always polarity zero edge triggered,
 978  * when listed as conforming in the MP table. */
 979
 980 #define default_ISA_trigger(idx)        (0)
 981 #define default_ISA_polarity(idx)       (0)
 982
 983 /* PCI interrupts are always polarity one level triggered,
 984  * when listed as conforming in the MP table. */
 985
 986 #define default_PCI_trigger(idx)        (1)
 987 #define default_PCI_polarity(idx)       (1)
 988
 989 /* MCA interrupts are always polarity zero level triggered,
 990  * when listed as conforming in the MP table. */
 991
 992 #define default_MCA_trigger(idx)        (1)
 993 #define default_MCA_polarity(idx)       (0)
 994
 995 static int __init MPBIOS_polarity(int idx)
 996 {
 997         int bus = mp_irqs[idx].mpc_srcbus;
 998         int polarity;
 999
1000         /*
1001          * Determine IRQ line polarity (high active or low active):
1002          */
1003         switch (mp_irqs[idx].mpc_irqflag & 3)
1004         {
1005                 case 0: /* conforms, ie. bus-type dependent polarity */
1006                 {
1007                         switch (mp_bus_id_to_type[bus])
1008                         {
1009                                 case MP_BUS_ISA: /* ISA pin */
1010                                 {
1011                                         polarity = default_ISA_polarity(idx);
1012                                         break;
1013                                 }
1014                                 case MP_BUS_EISA: /* EISA pin */
1015                                 {
1016                                         polarity = default_EISA_polarity(idx);
1017                                         break;
1018                                 }
1019                                 case MP_BUS_PCI: /* PCI pin */
1020                                 {
1021                                         polarity = default_PCI_polarity(idx);
1022                                         break;
1023                                 }
1024                                 case MP_BUS_MCA: /* MCA pin */
1025                                 {
1026                                         polarity = default_MCA_polarity(idx);
1027                                         break;
1028                                 }
1029                                 default:
1030                                 {
1031                                         printk(KERN_WARNING "broken BIOS!!\n");
1032                                         polarity = 1;
1033                                         break;
1034                                 }
1035                         }
1036                         break;
1037                 }
1038                 case 1: /* high active */
1039                 {
1040                         polarity = 0;
1041                         break;
1042                 }
1043                 case 2: /* reserved */
1044                 {
1045                         printk(KERN_WARNING "broken BIOS!!\n");
1046                         polarity = 1;
1047                         break;
1048                 }
1049                 case 3: /* low active */
1050                 {
1051                         polarity = 1;
1052                         break;
1053                 }
1054                 default: /* invalid */
1055                 {
1056                         printk(KERN_WARNING "broken BIOS!!\n");
1057                         polarity = 1;
1058                         break;
1059                 }
1060         }
1061         return polarity;
1062 }
1063
1064 static int MPBIOS_trigger(int idx)
1065 {
1066         int bus = mp_irqs[idx].mpc_srcbus;
1067         int trigger;
1068
1069         /*
1070          * Determine IRQ trigger mode (edge or level sensitive):
1071          */
1072         switch ((mp_irqs[idx].mpc_irqflag>>2) & 3)
1073         {
1074                 case 0: /* conforms, ie. bus-type dependent */
1075                 {
1076                         switch (mp_bus_id_to_type[bus])
1077                         {
1078                                 case MP_BUS_ISA: /* ISA pin */
1079                                 {
1080                                         trigger = default_ISA_trigger(idx);
1081                                         break;
1082                                 }
1083                                 case MP_BUS_EISA: /* EISA pin */
1084                                 {
1085                                         trigger = default_EISA_trigger(idx);
1086                                         break;
1087                                 }
1088                                 case MP_BUS_PCI: /* PCI pin */
1089                                 {
1090                                         trigger = default_PCI_trigger(idx);
1091                                         break;
1092                                 }
1093                                 case MP_BUS_MCA: /* MCA pin */
1094                                 {
1095                                         trigger = default_MCA_trigger(idx);
1096                                         break;
1097                                 }
1098                                 default:
1099                                 {
1100                                         printk(KERN_WARNING "broken BIOS!!\n");
1101                                         trigger = 1;
1102                                         break;
1103                                 }
1104                         }
1105                         break;
1106                 }
1107                 case 1: /* edge */
1108                 {
1109                         trigger = 0;
1110                         break;
1111                 }
1112                 case 2: /* reserved */
1113                 {
1114                         printk(KERN_WARNING "broken BIOS!!\n");
1115                         trigger = 1;
1116                         break;
1117                 }
1118                 case 3: /* level */
1119                 {
1120                         trigger = 1;
1121                         break;
1122                 }
1123                 default: /* invalid */
1124                 {
1125                         printk(KERN_WARNING "broken BIOS!!\n");
1126                         trigger = 0;
1127                         break;
1128                 }
1129         }
1130         return trigger;
1131 }
1132
1133 static inline int irq_polarity(int idx)
1134 {
1135         return MPBIOS_polarity(idx);
1136 }
1137
1138 static inline int irq_trigger(int idx)
1139 {
1140         return MPBIOS_trigger(idx);
1141 }
1142
1143 static int pin_2_irq(int idx, int apic, int pin)
1144 {
1145         int irq, i;
1146         int bus = mp_irqs[idx].mpc_srcbus;
1147
1148         /*
1149          * Debugging check, we are in big trouble if this message pops up!
1150          */
1151         if (mp_irqs[idx].mpc_dstirq != pin)
1152                 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
1153
1154         switch (mp_bus_id_to_type[bus])
1155         {
1156                 case MP_BUS_ISA: /* ISA pin */
1157                 case MP_BUS_EISA:
1158                 case MP_BUS_MCA:
1159                 {
1160                         irq = mp_irqs[idx].mpc_srcbusirq;
1161                         break;
1162                 }
1163                 case MP_BUS_PCI: /* PCI pin */
1164                 {
1165                         /*
1166                          * PCI IRQs are mapped in order
1167                          */
1168                         i = irq = 0;
1169                         while (i < apic)
1170                                 irq += nr_ioapic_registers[i++];
1171                         irq += pin;
1172
1173                         /*
1174                          * For MPS mode, so far only needed by ES7000 platform
1175                          */
1176                         if (ioapic_renumber_irq)
1177                                 irq = ioapic_renumber_irq(apic, irq);
1178
1179                         break;
1180                 }
1181                 default:
1182                 {
1183                         printk(KERN_ERR "unknown bus type %d.\n",bus);
1184                         irq = 0;
1185                         break;
1186                 }
1187         }
1188
1189         /*
1190          * PCI IRQ command line redirection. Yes, limits are hardcoded.
1191          */
1192         if ((pin >= 16) && (pin <= 23)) {
1193                 if (pirq_entries[pin-16] != -1) {
1194                         if (!pirq_entries[pin-16]) {
1195                                 apic_printk(APIC_VERBOSE, KERN_DEBUG
1196                                                 "disabling PIRQ%d\n", pin-16);
1197                         } else {
1198                                 irq = pirq_entries[pin-16];
1199                                 apic_printk(APIC_VERBOSE, KERN_DEBUG
1200                                                 "using PIRQ%d -> IRQ %d\n",
1201                                                 pin-16, irq);
1202                         }
1203                 }
1204         }
1205         return irq;
1206 }
1207
1208 static inline int IO_APIC_irq_trigger(int irq)
1209 {
1210         int apic, idx, pin;
1211
1212         for (apic = 0; apic < nr_ioapics; apic++) {
1213                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1214                         idx = find_irq_entry(apic,pin,mp_INT);
1215                         if ((idx != -1) && (irq == pin_2_irq(idx,apic,pin)))
1216                                 return irq_trigger(idx);
1217                 }
1218         }
1219         /*
1220          * nonexistent IRQs are edge default
1221          */
1222         return 0;
1223 }
1224
1225 /* irq_vectors is indexed by the sum of all RTEs in all I/O APICs. */
1226 static u8 irq_vector[NR_IRQ_VECTORS] __read_mostly = { FIRST_DEVICE_VECTOR , 0 };
1227
1228 static int __assign_irq_vector(int irq)
1229 {
1230         static int current_vector = FIRST_DEVICE_VECTOR, current_offset = 0;
1231         int vector, offset, i;
1232
1233         BUG_ON((unsigned)irq >= NR_IRQ_VECTORS);
1234
1235         if (irq_vector[irq] > 0)
1236                 return irq_vector[irq];
1237
1238         vector = current_vector;
1239         offset = current_offset;
1240 next:
1241         vector += 8;
1242         if (vector >= FIRST_SYSTEM_VECTOR) {
1243                 offset = (offset + 1) % 8;
1244                 vector = FIRST_DEVICE_VECTOR + offset;
1245         }
1246         if (vector == current_vector)
1247                 return -ENOSPC;
1248         if (vector == SYSCALL_VECTOR)
1249                 goto next;
1250         for (i = 0; i < NR_IRQ_VECTORS; i++)
1251                 if (irq_vector[i] == vector)
1252                         goto next;
1253
1254         current_vector = vector;
1255         current_offset = offset;
1256         irq_vector[irq] = vector;
1257
1258         return vector;
1259 }
1260
1261 static int assign_irq_vector(int irq)
1262 {
1263         unsigned long flags;
1264         int vector;
1265
1266         spin_lock_irqsave(&vector_lock, flags);
1267         vector = __assign_irq_vector(irq);
1268         spin_unlock_irqrestore(&vector_lock, flags);
1269
1270         return vector;
1271 }
1272 static struct irq_chip ioapic_chip;
1273
1274 #define IOAPIC_AUTO     -1
1275 #define IOAPIC_EDGE     0
1276 #define IOAPIC_LEVEL    1
1277
1278 static void ioapic_register_intr(int irq, int vector, unsigned long trigger)
1279 {
1280         if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1281                         trigger == IOAPIC_LEVEL)
1282                 set_irq_chip_and_handler_name(irq, &ioapic_chip,
1283                                          handle_fasteoi_irq, "fasteoi");
1284         else
1285                 set_irq_chip_and_handler_name(irq, &ioapic_chip,
1286                                          handle_edge_irq, "edge");
1287         set_intr_gate(vector, interrupt[irq]);
1288 }
1289
1290 static void __init setup_IO_APIC_irqs(void)
1291 {
1292         struct IO_APIC_route_entry entry;
1293         int apic, pin, idx, irq, first_notcon = 1, vector;
1294         unsigned long flags;
1295
1296         apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
1297
1298         for (apic = 0; apic < nr_ioapics; apic++) {
1299         for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1300
1301                 /*
1302                  * add it to the IO-APIC irq-routing table:
1303                  */
1304                 memset(&entry,0,sizeof(entry));
1305
1306                 entry.delivery_mode = INT_DELIVERY_MODE;
1307                 entry.dest_mode = INT_DEST_MODE;
1308                 entry.mask = 0;                         /* enable IRQ */
1309                 entry.dest.logical.logical_dest =
1310                                         cpu_mask_to_apicid(TARGET_CPUS);
1311
1312                 idx = find_irq_entry(apic,pin,mp_INT);
1313                 if (idx == -1) {
1314                         if (first_notcon) {
1315                                 apic_printk(APIC_VERBOSE, KERN_DEBUG
1316                                                 " IO-APIC (apicid-pin) %d-%d",
1317                                                 mp_ioapics[apic].mpc_apicid,
1318                                                 pin);
1319                                 first_notcon = 0;
1320                         } else
1321                                 apic_printk(APIC_VERBOSE, ", %d-%d",
1322                                         mp_ioapics[apic].mpc_apicid, pin);
1323                         continue;
1324                 }
1325
1326                 entry.trigger = irq_trigger(idx);
1327                 entry.polarity = irq_polarity(idx);
1328
1329                 if (irq_trigger(idx)) {
1330                         entry.trigger = 1;
1331                         entry.mask = 1;
1332                 }
1333
1334                 irq = pin_2_irq(idx, apic, pin);
1335                 /*
1336                  * skip adding the timer int on secondary nodes, which causes
1337                  * a small but painful rift in the time-space continuum
1338                  */
1339                 if (multi_timer_check(apic, irq))
1340                         continue;
1341                 else
1342                         add_pin_to_irq(irq, apic, pin);
1343
1344                 if (!apic && !IO_APIC_IRQ(irq))
1345                         continue;
1346
1347                 if (IO_APIC_IRQ(irq)) {
1348                         vector = assign_irq_vector(irq);
1349                         entry.vector = vector;
1350                         ioapic_register_intr(irq, vector, IOAPIC_AUTO);
1351
1352                         if (!apic && (irq < 16))
1353                                 disable_8259A_irq(irq);
1354                 }
1355                 spin_lock_irqsave(&ioapic_lock, flags);
1356                 __ioapic_write_entry(apic, pin, entry);
1357                 irq_desc[irq].affinity = TARGET_CPUS;
1358                 spin_unlock_irqrestore(&ioapic_lock, flags);
1359         }
1360         }
1361
1362         if (!first_notcon)
1363                 apic_printk(APIC_VERBOSE, " not connected.\n");
1364 }
1365
1366 /*
1367  * Set up the 8259A-master output pin:
1368  */
1369 static void __init setup_ExtINT_IRQ0_pin(unsigned int apic, unsigned int pin, int vector)
1370 {
1371         struct IO_APIC_route_entry entry;
1372
1373         memset(&entry,0,sizeof(entry));
1374
1375         disable_8259A_irq(0);
1376
1377         /* mask LVT0 */
1378         apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
1379
1380         /*
1381          * We use logical delivery to get the timer IRQ
1382          * to the first CPU.
1383          */
1384         entry.dest_mode = INT_DEST_MODE;
1385         entry.mask = 0;                                 /* unmask IRQ now */
1386         entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
1387         entry.delivery_mode = INT_DELIVERY_MODE;
1388         entry.polarity = 0;
1389         entry.trigger = 0;
1390         entry.vector = vector;
1391
1392         /*
1393          * The timer IRQ doesn't have to know that behind the
1394          * scene we have a 8259A-master in AEOI mode ...
1395          */
1396         irq_desc[0].chip = &ioapic_chip;
1397         set_irq_handler(0, handle_edge_irq);
1398
1399         /*
1400          * Add it to the IO-APIC irq-routing table:
1401          */
1402         ioapic_write_entry(apic, pin, entry);
1403
1404         enable_8259A_irq(0);
1405 }
1406
1407 static inline void UNEXPECTED_IO_APIC(void)
1408 {
1409 }
1410
1411 void __init print_IO_APIC(void)
1412 {
1413         int apic, i;
1414         union IO_APIC_reg_00 reg_00;
1415         union IO_APIC_reg_01 reg_01;
1416         union IO_APIC_reg_02 reg_02;
1417         union IO_APIC_reg_03 reg_03;
1418         unsigned long flags;
1419
1420         if (apic_verbosity == APIC_QUIET)
1421                 return;
1422
1423         printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
1424         for (i = 0; i < nr_ioapics; i++)
1425                 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
1426                        mp_ioapics[i].mpc_apicid, nr_ioapic_registers[i]);
1427
1428         /*
1429          * We are a bit conservative about what we expect.  We have to
1430          * know about every hardware change ASAP.
1431          */
1432         printk(KERN_INFO "testing the IO APIC.......................\n");
1433
1434         for (apic = 0; apic < nr_ioapics; apic++) {
1435
1436         spin_lock_irqsave(&ioapic_lock, flags);
1437         reg_00.raw = io_apic_read(apic, 0);
1438         reg_01.raw = io_apic_read(apic, 1);
1439         if (reg_01.bits.version >= 0x10)
1440                 reg_02.raw = io_apic_read(apic, 2);
1441         if (reg_01.bits.version >= 0x20)
1442                 reg_03.raw = io_apic_read(apic, 3);
1443         spin_unlock_irqrestore(&ioapic_lock, flags);
1444
1445         printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mpc_apicid);
1446         printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
1447         printk(KERN_DEBUG ".......    : physical APIC id: %02X\n", reg_00.bits.ID);
1448         printk(KERN_DEBUG ".......    : Delivery Type: %X\n", reg_00.bits.delivery_type);
1449         printk(KERN_DEBUG ".......    : LTS          : %X\n", reg_00.bits.LTS);
1450         if (reg_00.bits.ID >= get_physical_broadcast())
1451                 UNEXPECTED_IO_APIC();
1452         if (reg_00.bits.__reserved_1 || reg_00.bits.__reserved_2)
1453                 UNEXPECTED_IO_APIC();
1454
1455         printk(KERN_DEBUG ".... register #01: %08X\n", reg_01.raw);
1456         printk(KERN_DEBUG ".......     : max redirection entries: %04X\n", reg_01.bits.entries);
1457         if (    (reg_01.bits.entries != 0x0f) && /* older (Neptune) boards */
1458                 (reg_01.bits.entries != 0x17) && /* typical ISA+PCI boards */
1459                 (reg_01.bits.entries != 0x1b) && /* Compaq Proliant boards */
1460                 (reg_01.bits.entries != 0x1f) && /* dual Xeon boards */
1461                 (reg_01.bits.entries != 0x22) && /* bigger Xeon boards */
1462                 (reg_01.bits.entries != 0x2E) &&
1463                 (reg_01.bits.entries != 0x3F)
1464         )
1465                 UNEXPECTED_IO_APIC();
1466
1467         printk(KERN_DEBUG ".......     : PRQ implemented: %X\n", reg_01.bits.PRQ);
1468         printk(KERN_DEBUG ".......     : IO APIC version: %04X\n", reg_01.bits.version);
1469         if (    (reg_01.bits.version != 0x01) && /* 82489DX IO-APICs */
1470                 (reg_01.bits.version != 0x10) && /* oldest IO-APICs */
1471                 (reg_01.bits.version != 0x11) && /* Pentium/Pro IO-APICs */
1472                 (reg_01.bits.version != 0x13) && /* Xeon IO-APICs */
1473                 (reg_01.bits.version != 0x20)    /* Intel P64H (82806 AA) */
1474         )
1475                 UNEXPECTED_IO_APIC();
1476         if (reg_01.bits.__reserved_1 || reg_01.bits.__reserved_2)
1477                 UNEXPECTED_IO_APIC();
1478
1479         /*
1480          * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
1481          * but the value of reg_02 is read as the previous read register
1482          * value, so ignore it if reg_02 == reg_01.
1483          */
1484         if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) {
1485                 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
1486                 printk(KERN_DEBUG ".......     : arbitration: %02X\n", reg_02.bits.arbitration);
1487                 if (reg_02.bits.__reserved_1 || reg_02.bits.__reserved_2)
1488                         UNEXPECTED_IO_APIC();
1489         }
1490
1491         /*
1492          * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
1493          * or reg_03, but the value of reg_0[23] is read as the previous read
1494          * register value, so ignore it if reg_03 == reg_0[12].
1495          */
1496         if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw &&
1497             reg_03.raw != reg_01.raw) {
1498                 printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw);
1499                 printk(KERN_DEBUG ".......     : Boot DT    : %X\n", reg_03.bits.boot_DT);
1500                 if (reg_03.bits.__reserved_1)
1501                         UNEXPECTED_IO_APIC();
1502         }
1503
1504         printk(KERN_DEBUG ".... IRQ redirection table:\n");
1505
1506         printk(KERN_DEBUG " NR Log Phy Mask Trig IRR Pol"
1507                           " Stat Dest Deli Vect:   \n");
1508
1509         for (i = 0; i <= reg_01.bits.entries; i++) {
1510                 struct IO_APIC_route_entry entry;
1511
1512                 entry = ioapic_read_entry(apic, i);
1513
1514                 printk(KERN_DEBUG " %02x %03X %02X  ",
1515                         i,
1516                         entry.dest.logical.logical_dest,
1517                         entry.dest.physical.physical_dest
1518                 );
1519
1520                 printk("%1d    %1d    %1d   %1d   %1d    %1d    %1d    %02X\n",
1521                         entry.mask,
1522                         entry.trigger,
1523                         entry.irr,
1524                         entry.polarity,
1525                         entry.delivery_status,
1526                         entry.dest_mode,
1527                         entry.delivery_mode,
1528                         entry.vector
1529                 );
1530         }
1531         }
1532         printk(KERN_DEBUG "IRQ to pin mappings:\n");
1533         for (i = 0; i < NR_IRQS; i++) {
1534                 struct irq_pin_list *entry = irq_2_pin + i;
1535                 if (entry->pin < 0)
1536                         continue;
1537                 printk(KERN_DEBUG "IRQ%d ", i);
1538                 for (;;) {
1539                         printk("-> %d:%d", entry->apic, entry->pin);
1540                         if (!entry->next)
1541                                 break;
1542                         entry = irq_2_pin + entry->next;
1543                 }
1544                 printk("\n");
1545         }
1546
1547         printk(KERN_INFO ".................................... done.\n");
1548
1549         return;
1550 }
1551
1552 #if 0
1553
1554 static void print_APIC_bitfield (int base)
1555 {
1556         unsigned int v;
1557         int i, j;
1558
1559         if (apic_verbosity == APIC_QUIET)
1560                 return;
1561
1562         printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG);
1563         for (i = 0; i < 8; i++) {
1564                 v = apic_read(base + i*0x10);
1565                 for (j = 0; j < 32; j++) {
1566                         if (v & (1<<j))
1567                                 printk("1");
1568                         else
1569                                 printk("0");
1570                 }
1571                 printk("\n");
1572         }
1573 }
1574
1575 void /*__init*/ print_local_APIC(void * dummy)
1576 {
1577         unsigned int v, ver, maxlvt;
1578
1579         if (apic_verbosity == APIC_QUIET)
1580                 return;
1581
1582         printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
1583                 smp_processor_id(), hard_smp_processor_id());
1584         v = apic_read(APIC_ID);
1585         printk(KERN_INFO "... APIC ID:      %08x (%01x)\n", v, GET_APIC_ID(v));
1586         v = apic_read(APIC_LVR);
1587         printk(KERN_INFO "... APIC VERSION: %08x\n", v);
1588         ver = GET_APIC_VERSION(v);
1589         maxlvt = lapic_get_maxlvt();
1590
1591         v = apic_read(APIC_TASKPRI);
1592         printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
1593
1594         if (APIC_INTEGRATED(ver)) {                     /* !82489DX */
1595                 v = apic_read(APIC_ARBPRI);
1596                 printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
1597                         v & APIC_ARBPRI_MASK);
1598                 v = apic_read(APIC_PROCPRI);
1599                 printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
1600         }
1601
1602         v = apic_read(APIC_EOI);
1603         printk(KERN_DEBUG "... APIC EOI: %08x\n", v);
1604         v = apic_read(APIC_RRR);
1605         printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1606         v = apic_read(APIC_LDR);
1607         printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
1608         v = apic_read(APIC_DFR);
1609         printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1610         v = apic_read(APIC_SPIV);
1611         printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1612
1613         printk(KERN_DEBUG "... APIC ISR field:\n");
1614         print_APIC_bitfield(APIC_ISR);
1615         printk(KERN_DEBUG "... APIC TMR field:\n");
1616         print_APIC_bitfield(APIC_TMR);
1617         printk(KERN_DEBUG "... APIC IRR field:\n");
1618         print_APIC_bitfield(APIC_IRR);
1619
1620         if (APIC_INTEGRATED(ver)) {             /* !82489DX */
1621                 if (maxlvt > 3)         /* Due to the Pentium erratum 3AP. */
1622                         apic_write(APIC_ESR, 0);
1623                 v = apic_read(APIC_ESR);
1624                 printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1625         }
1626
1627         v = apic_read(APIC_ICR);
1628         printk(KERN_DEBUG "... APIC ICR: %08x\n", v);
1629         v = apic_read(APIC_ICR2);
1630         printk(KERN_DEBUG "... APIC ICR2: %08x\n", v);
1631
1632         v = apic_read(APIC_LVTT);
1633         printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1634
1635         if (maxlvt > 3) {                       /* PC is LVT#4. */
1636                 v = apic_read(APIC_LVTPC);
1637                 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1638         }
1639         v = apic_read(APIC_LVT0);
1640         printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1641         v = apic_read(APIC_LVT1);
1642         printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1643
1644         if (maxlvt > 2) {                       /* ERR is LVT#3. */
1645                 v = apic_read(APIC_LVTERR);
1646                 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1647         }
1648
1649         v = apic_read(APIC_TMICT);
1650         printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1651         v = apic_read(APIC_TMCCT);
1652         printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1653         v = apic_read(APIC_TDCR);
1654         printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1655         printk("\n");
1656 }
1657
1658 void print_all_local_APICs (void)
1659 {
1660         on_each_cpu(print_local_APIC, NULL, 1, 1);
1661 }
1662
1663 void /*__init*/ print_PIC(void)
1664 {
1665         unsigned int v;
1666         unsigned long flags;
1667
1668         if (apic_verbosity == APIC_QUIET)
1669                 return;
1670
1671         printk(KERN_DEBUG "\nprinting PIC contents\n");
1672
1673         spin_lock_irqsave(&i8259A_lock, flags);
1674
1675         v = inb(0xa1) << 8 | inb(0x21);
1676         printk(KERN_DEBUG "... PIC  IMR: %04x\n", v);
1677
1678         v = inb(0xa0) << 8 | inb(0x20);
1679         printk(KERN_DEBUG "... PIC  IRR: %04x\n", v);
1680
1681         outb(0x0b,0xa0);
1682         outb(0x0b,0x20);
1683         v = inb(0xa0) << 8 | inb(0x20);
1684         outb(0x0a,0xa0);
1685         outb(0x0a,0x20);
1686
1687         spin_unlock_irqrestore(&i8259A_lock, flags);
1688
1689         printk(KERN_DEBUG "... PIC  ISR: %04x\n", v);
1690
1691         v = inb(0x4d1) << 8 | inb(0x4d0);
1692         printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1693 }
1694
1695 #endif  /*  0  */
1696
1697 static void __init enable_IO_APIC(void)
1698 {
1699         union IO_APIC_reg_01 reg_01;
1700         int i8259_apic, i8259_pin;
1701         int i, apic;
1702         unsigned long flags;
1703
1704         for (i = 0; i < PIN_MAP_SIZE; i++) {
1705                 irq_2_pin[i].pin = -1;
1706                 irq_2_pin[i].next = 0;
1707         }
1708         if (!pirqs_enabled)
1709                 for (i = 0; i < MAX_PIRQS; i++)
1710                         pirq_entries[i] = -1;
1711
1712         /*
1713          * The number of IO-APIC IRQ registers (== #pins):
1714          */
1715         for (apic = 0; apic < nr_ioapics; apic++) {
1716                 spin_lock_irqsave(&ioapic_lock, flags);
1717                 reg_01.raw = io_apic_read(apic, 1);
1718                 spin_unlock_irqrestore(&ioapic_lock, flags);
1719                 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
1720         }
1721         for(apic = 0; apic < nr_ioapics; apic++) {
1722                 int pin;
1723                 /* See if any of the pins is in ExtINT mode */
1724                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1725                         struct IO_APIC_route_entry entry;
1726                         entry = ioapic_read_entry(apic, pin);
1727
1728
1729                         /* If the interrupt line is enabled and in ExtInt mode
1730                          * I have found the pin where the i8259 is connected.
1731                          */
1732                         if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
1733                                 ioapic_i8259.apic = apic;
1734                                 ioapic_i8259.pin  = pin;
1735                                 goto found_i8259;
1736                         }
1737                 }
1738         }
1739  found_i8259:
1740         /* Look to see what if the MP table has reported the ExtINT */
1741         /* If we could not find the appropriate pin by looking at the ioapic
1742          * the i8259 probably is not connected the ioapic but give the
1743          * mptable a chance anyway.
1744          */
1745         i8259_pin  = find_isa_irq_pin(0, mp_ExtINT);
1746         i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
1747         /* Trust the MP table if nothing is setup in the hardware */
1748         if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
1749                 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
1750                 ioapic_i8259.pin  = i8259_pin;
1751                 ioapic_i8259.apic = i8259_apic;
1752         }
1753         /* Complain if the MP table and the hardware disagree */
1754         if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
1755                 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
1756         {
1757                 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
1758         }
1759
1760         /*
1761          * Do not trust the IO-APIC being empty at bootup
1762          */
1763         clear_IO_APIC();
1764 }
1765
1766 /*
1767  * Not an __init, needed by the reboot code
1768  */
1769 void disable_IO_APIC(void)
1770 {
1771         /*
1772          * Clear the IO-APIC before rebooting:
1773          */
1774         clear_IO_APIC();
1775
1776         /*
1777          * If the i8259 is routed through an IOAPIC
1778          * Put that IOAPIC in virtual wire mode
1779          * so legacy interrupts can be delivered.
1780          */
1781         if (ioapic_i8259.pin != -1) {
1782                 struct IO_APIC_route_entry entry;
1783
1784                 memset(&entry, 0, sizeof(entry));
1785                 entry.mask            = 0; /* Enabled */
1786                 entry.trigger         = 0; /* Edge */
1787                 entry.irr             = 0;
1788                 entry.polarity        = 0; /* High */
1789                 entry.delivery_status = 0;
1790                 entry.dest_mode       = 0; /* Physical */
1791                 entry.delivery_mode   = dest_ExtINT; /* ExtInt */
1792                 entry.vector          = 0;
1793                 entry.dest.physical.physical_dest =
1794                                         GET_APIC_ID(apic_read(APIC_ID));
1795
1796                 /*
1797                  * Add it to the IO-APIC irq-routing table:
1798                  */
1799                 ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry);
1800         }
1801         disconnect_bsp_APIC(ioapic_i8259.pin != -1);
1802 }
1803
1804 /*
1805  * function to set the IO-APIC physical IDs based on the
1806  * values stored in the MPC table.
1807  *
1808  * by Matt Domsch <Matt_Domsch@dell.com>  Tue Dec 21 12:25:05 CST 1999
1809  */
1810
1811 #ifndef CONFIG_X86_NUMAQ
1812 static void __init setup_ioapic_ids_from_mpc(void)
1813 {
1814         union IO_APIC_reg_00 reg_00;
1815         physid_mask_t phys_id_present_map;
1816         int apic;
1817         int i;
1818         unsigned char old_id;
1819         unsigned long flags;
1820
1821         /*
1822          * Don't check I/O APIC IDs for xAPIC systems.  They have
1823          * no meaning without the serial APIC bus.
1824          */
1825         if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
1826                 || APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
1827                 return;
1828         /*
1829          * This is broken; anything with a real cpu count has to
1830          * circumvent this idiocy regardless.
1831          */
1832         phys_id_present_map = ioapic_phys_id_map(phys_cpu_present_map);
1833
1834         /*
1835          * Set the IOAPIC ID to the value stored in the MPC table.
1836          */
1837         for (apic = 0; apic < nr_ioapics; apic++) {
1838
1839                 /* Read the register 0 value */
1840                 spin_lock_irqsave(&ioapic_lock, flags);
1841                 reg_00.raw = io_apic_read(apic, 0);
1842                 spin_unlock_irqrestore(&ioapic_lock, flags);
1843
1844                 old_id = mp_ioapics[apic].mpc_apicid;
1845
1846                 if (mp_ioapics[apic].mpc_apicid >= get_physical_broadcast()) {
1847                         printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
1848                                 apic, mp_ioapics[apic].mpc_apicid);
1849                         printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1850                                 reg_00.bits.ID);
1851                         mp_ioapics[apic].mpc_apicid = reg_00.bits.ID;
1852                 }
1853
1854                 /*
1855                  * Sanity check, is the ID really free? Every APIC in a
1856                  * system must have a unique ID or we get lots of nice
1857                  * 'stuck on smp_invalidate_needed IPI wait' messages.
1858                  */
1859                 if (check_apicid_used(phys_id_present_map,
1860                                         mp_ioapics[apic].mpc_apicid)) {
1861                         printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n",
1862                                 apic, mp_ioapics[apic].mpc_apicid);
1863                         for (i = 0; i < get_physical_broadcast(); i++)
1864                                 if (!physid_isset(i, phys_id_present_map))
1865                                         break;
1866                         if (i >= get_physical_broadcast())
1867                                 panic("Max APIC ID exceeded!\n");
1868                         printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1869                                 i);
1870                         physid_set(i, phys_id_present_map);
1871                         mp_ioapics[apic].mpc_apicid = i;
1872                 } else {
1873                         physid_mask_t tmp;
1874                         tmp = apicid_to_cpu_present(mp_ioapics[apic].mpc_apicid);
1875                         apic_printk(APIC_VERBOSE, "Setting %d in the "
1876                                         "phys_id_present_map\n",
1877                                         mp_ioapics[apic].mpc_apicid);
1878                         physids_or(phys_id_present_map, phys_id_present_map, tmp);
1879                 }
1880
1881
1882                 /*
1883                  * We need to adjust the IRQ routing table
1884                  * if the ID changed.
1885                  */
1886                 if (old_id != mp_ioapics[apic].mpc_apicid)
1887                         for (i = 0; i < mp_irq_entries; i++)
1888                                 if (mp_irqs[i].mpc_dstapic == old_id)
1889                                         mp_irqs[i].mpc_dstapic
1890                                                 = mp_ioapics[apic].mpc_apicid;
1891
1892                 /*
1893                  * Read the right value from the MPC table and
1894                  * write it into the ID register.
1895                  */
1896                 apic_printk(APIC_VERBOSE, KERN_INFO
1897                         "...changing IO-APIC physical APIC ID to %d ...",
1898                         mp_ioapics[apic].mpc_apicid);
1899
1900                 reg_00.bits.ID = mp_ioapics[apic].mpc_apicid;
1901                 spin_lock_irqsave(&ioapic_lock, flags);
1902                 io_apic_write(apic, 0, reg_00.raw);
1903                 spin_unlock_irqrestore(&ioapic_lock, flags);
1904
1905                 /*
1906                  * Sanity check
1907                  */
1908                 spin_lock_irqsave(&ioapic_lock, flags);
1909                 reg_00.raw = io_apic_read(apic, 0);
1910                 spin_unlock_irqrestore(&ioapic_lock, flags);
1911                 if (reg_00.bits.ID != mp_ioapics[apic].mpc_apicid)
1912                         printk("could not set ID!\n");
1913                 else
1914                         apic_printk(APIC_VERBOSE, " ok.\n");
1915         }
1916 }
1917 #else
1918 static void __init setup_ioapic_ids_from_mpc(void) { }
1919 #endif
1920
1921 int no_timer_check __initdata;
1922
1923 static int __init notimercheck(char *s)
1924 {
1925         no_timer_check = 1;
1926         return 1;
1927 }
1928 __setup("no_timer_check", notimercheck);
1929
1930 /*
1931  * There is a nasty bug in some older SMP boards, their mptable lies
1932  * about the timer IRQ. We do the following to work around the situation:
1933  *
1934  *      - timer IRQ defaults to IO-APIC IRQ
1935  *      - if this function detects that timer IRQs are defunct, then we fall
1936  *        back to ISA timer IRQs
1937  */
1938 int __init timer_irq_works(void)
1939 {
1940         unsigned long t1 = jiffies;
1941
1942         if (no_timer_check)
1943                 return 1;
1944
1945         local_irq_enable();
1946         /* Let ten ticks pass... */
1947         mdelay((10 * 1000) / HZ);
1948
1949         /*
1950          * Expect a few ticks at least, to be sure some possible
1951          * glue logic does not lock up after one or two first
1952          * ticks in a non-ExtINT mode.  Also the local APIC
1953          * might have cached one ExtINT interrupt.  Finally, at
1954          * least one tick may be lost due to delays.
1955          */
1956         if (jiffies - t1 > 4)
1957                 return 1;
1958
1959         return 0;
1960 }
1961
1962 /*
1963  * In the SMP+IOAPIC case it might happen that there are an unspecified
1964  * number of pending IRQ events unhandled. These cases are very rare,
1965  * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1966  * better to do it this way as thus we do not have to be aware of
1967  * 'pending' interrupts in the IRQ path, except at this point.
1968  */
1969 /*
1970  * Edge triggered needs to resend any interrupt
1971  * that was delayed but this is now handled in the device
1972  * independent code.
1973  */
1974
1975 /*
1976  * Startup quirk:
1977  *
1978  * Starting up a edge-triggered IO-APIC interrupt is
1979  * nasty - we need to make sure that we get the edge.
1980  * If it is already asserted for some reason, we need
1981  * return 1 to indicate that is was pending.
1982  *
1983  * This is not complete - we should be able to fake
1984  * an edge even if it isn't on the 8259A...
1985  *
1986  * (We do this for level-triggered IRQs too - it cannot hurt.)
1987  */
1988 static unsigned int startup_ioapic_irq(unsigned int irq)
1989 {
1990         int was_pending = 0;
1991         unsigned long flags;
1992
1993         spin_lock_irqsave(&ioapic_lock, flags);
1994         if (irq < 16) {
1995                 disable_8259A_irq(irq);
1996                 if (i8259A_irq_pending(irq))
1997                         was_pending = 1;
1998         }
1999         __unmask_IO_APIC_irq(irq);
2000         spin_unlock_irqrestore(&ioapic_lock, flags);
2001
2002         return was_pending;
2003 }
2004
2005 static void ack_ioapic_irq(unsigned int irq)
2006 {
2007         move_native_irq(irq);
2008         ack_APIC_irq();
2009 }
2010
2011 static void ack_ioapic_quirk_irq(unsigned int irq)
2012 {
2013         unsigned long v;
2014         int i;
2015
2016         move_native_irq(irq);
2017 /*
2018  * It appears there is an erratum which affects at least version 0x11
2019  * of I/O APIC (that's the 82093AA and cores integrated into various
2020  * chipsets).  Under certain conditions a level-triggered interrupt is
2021  * erroneously delivered as edge-triggered one but the respective IRR
2022  * bit gets set nevertheless.  As a result the I/O unit expects an EOI
2023  * message but it will never arrive and further interrupts are blocked
2024  * from the source.  The exact reason is so far unknown, but the
2025  * phenomenon was observed when two consecutive interrupt requests
2026  * from a given source get delivered to the same CPU and the source is
2027  * temporarily disabled in between.
2028  *
2029  * A workaround is to simulate an EOI message manually.  We achieve it
2030  * by setting the trigger mode to edge and then to level when the edge
2031  * trigger mode gets detected in the TMR of a local APIC for a
2032  * level-triggered interrupt.  We mask the source for the time of the
2033  * operation to prevent an edge-triggered interrupt escaping meanwhile.
2034  * The idea is from Manfred Spraul.  --macro
2035  */
2036         i = irq_vector[irq];
2037
2038         v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1));
2039
2040         ack_APIC_irq();
2041
2042         if (!(v & (1 << (i & 0x1f)))) {
2043                 atomic_inc(&irq_mis_count);
2044                 spin_lock(&ioapic_lock);
2045                 __mask_and_edge_IO_APIC_irq(irq);
2046                 __unmask_and_level_IO_APIC_irq(irq);
2047                 spin_unlock(&ioapic_lock);
2048         }
2049 }
2050
2051 static int ioapic_retrigger_irq(unsigned int irq)
2052 {
2053         send_IPI_self(irq_vector[irq]);
2054
2055         return 1;
2056 }
2057
2058 static struct irq_chip ioapic_chip __read_mostly = {
2059         .name           = "IO-APIC",
2060         .startup        = startup_ioapic_irq,
2061         .mask           = mask_IO_APIC_irq,
2062         .unmask         = unmask_IO_APIC_irq,
2063         .ack            = ack_ioapic_irq,
2064         .eoi            = ack_ioapic_quirk_irq,
2065 #ifdef CONFIG_SMP
2066         .set_affinity   = set_ioapic_affinity_irq,
2067 #endif
2068         .retrigger      = ioapic_retrigger_irq,
2069 };
2070
2071
2072 static inline void init_IO_APIC_traps(void)
2073 {
2074         int irq;
2075
2076         /*
2077          * NOTE! The local APIC isn't very good at handling
2078          * multiple interrupts at the same interrupt level.
2079          * As the interrupt level is determined by taking the
2080          * vector number and shifting that right by 4, we
2081          * want to spread these out a bit so that they don't
2082          * all fall in the same interrupt level.
2083          *
2084          * Also, we've got to be careful not to trash gate
2085          * 0x80, because int 0x80 is hm, kind of importantish. ;)
2086          */
2087         for (irq = 0; irq < NR_IRQS ; irq++) {
2088                 int tmp = irq;
2089                 if (IO_APIC_IRQ(tmp) && !irq_vector[tmp]) {
2090                         /*
2091                          * Hmm.. We don't have an entry for this,
2092                          * so default to an old-fashioned 8259
2093                          * interrupt if we can..
2094                          */
2095                         if (irq < 16)
2096                                 make_8259A_irq(irq);
2097                         else
2098                                 /* Strange. Oh, well.. */
2099                                 irq_desc[irq].chip = &no_irq_chip;
2100                 }
2101         }
2102 }
2103
2104 /*
2105  * The local APIC irq-chip implementation:
2106  */
2107
2108 static void ack_apic(unsigned int irq)
2109 {
2110         ack_APIC_irq();
2111 }
2112
2113 static void mask_lapic_irq (unsigned int irq)
2114 {
2115         unsigned long v;
2116
2117         v = apic_read(APIC_LVT0);
2118         apic_write_around(APIC_LVT0, v | APIC_LVT_MASKED);
2119 }
2120
2121 static void unmask_lapic_irq (unsigned int irq)
2122 {
2123         unsigned long v;
2124
2125         v = apic_read(APIC_LVT0);
2126         apic_write_around(APIC_LVT0, v & ~APIC_LVT_MASKED);
2127 }
2128
2129 static struct irq_chip lapic_chip __read_mostly = {
2130         .name           = "local-APIC-edge",
2131         .mask           = mask_lapic_irq,
2132         .unmask         = unmask_lapic_irq,
2133         .eoi            = ack_apic,
2134 };
2135
2136 static void setup_nmi (void)
2137 {
2138         /*
2139          * Dirty trick to enable the NMI watchdog ...
2140          * We put the 8259A master into AEOI mode and
2141          * unmask on all local APICs LVT0 as NMI.
2142          *
2143          * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
2144          * is from Maciej W. Rozycki - so we do not have to EOI from
2145          * the NMI handler or the timer interrupt.
2146          */
2147         apic_printk(APIC_VERBOSE, KERN_INFO "activating NMI Watchdog ...");
2148
2149         on_each_cpu(enable_NMI_through_LVT0, NULL, 1, 1);
2150
2151         apic_printk(APIC_VERBOSE, " done.\n");
2152 }
2153
2154 /*
2155  * This looks a bit hackish but it's about the only one way of sending
2156  * a few INTA cycles to 8259As and any associated glue logic.  ICR does
2157  * not support the ExtINT mode, unfortunately.  We need to send these
2158  * cycles as some i82489DX-based boards have glue logic that keeps the
2159  * 8259A interrupt line asserted until INTA.  --macro
2160  */
2161 static inline void unlock_ExtINT_logic(void)
2162 {
2163         int apic, pin, i;
2164         struct IO_APIC_route_entry entry0, entry1;
2165         unsigned char save_control, save_freq_select;
2166
2167         pin  = find_isa_irq_pin(8, mp_INT);
2168         if (pin == -1) {
2169                 WARN_ON_ONCE(1);
2170                 return;
2171         }
2172         apic = find_isa_irq_apic(8, mp_INT);
2173         if (apic == -1) {
2174                 WARN_ON_ONCE(1);
2175                 return;
2176         }
2177
2178         entry0 = ioapic_read_entry(apic, pin);
2179         clear_IO_APIC_pin(apic, pin);
2180
2181         memset(&entry1, 0, sizeof(entry1));
2182
2183         entry1.dest_mode = 0;                   /* physical delivery */
2184         entry1.mask = 0;                        /* unmask IRQ now */
2185         entry1.dest.physical.physical_dest = hard_smp_processor_id();
2186         entry1.delivery_mode = dest_ExtINT;
2187         entry1.polarity = entry0.polarity;
2188         entry1.trigger = 0;
2189         entry1.vector = 0;
2190
2191         ioapic_write_entry(apic, pin, entry1);
2192
2193         save_control = CMOS_READ(RTC_CONTROL);
2194         save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
2195         CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
2196                    RTC_FREQ_SELECT);
2197         CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
2198
2199         i = 100;
2200         while (i-- > 0) {
2201                 mdelay(10);
2202                 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
2203                         i -= 10;
2204         }
2205
2206         CMOS_WRITE(save_control, RTC_CONTROL);
2207         CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
2208         clear_IO_APIC_pin(apic, pin);
2209
2210         ioapic_write_entry(apic, pin, entry0);
2211 }
2212
2213 int timer_uses_ioapic_pin_0;
2214
2215 /*
2216  * This code may look a bit paranoid, but it's supposed to cooperate with
2217  * a wide range of boards and BIOS bugs.  Fortunately only the timer IRQ
2218  * is so screwy.  Thanks to Brian Perkins for testing/hacking this beast
2219  * fanatically on his truly buggy board.
2220  */
2221 static inline void __init check_timer(void)
2222 {
2223         int apic1, pin1, apic2, pin2;
2224         int vector;
2225
2226         /*
2227          * get/set the timer IRQ vector:
2228          */
2229         disable_8259A_irq(0);
2230         vector = assign_irq_vector(0);
2231         set_intr_gate(vector, interrupt[0]);
2232
2233         /*
2234          * Subtle, code in do_timer_interrupt() expects an AEOI
2235          * mode for the 8259A whenever interrupts are routed
2236          * through I/O APICs.  Also IRQ0 has to be enabled in
2237          * the 8259A which implies the virtual wire has to be
2238          * disabled in the local APIC.
2239          */
2240         apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
2241         init_8259A(1);
2242         timer_ack = 1;
2243         if (timer_over_8254 > 0)
2244                 enable_8259A_irq(0);
2245
2246         pin1  = find_isa_irq_pin(0, mp_INT);
2247         apic1 = find_isa_irq_apic(0, mp_INT);
2248         pin2  = ioapic_i8259.pin;
2249         apic2 = ioapic_i8259.apic;
2250
2251         if (pin1 == 0)
2252                 timer_uses_ioapic_pin_0 = 1;
2253
2254         printk(KERN_INFO "..TIMER: vector=0x%02X apic1=%d pin1=%d apic2=%d pin2=%d\n",
2255                 vector, apic1, pin1, apic2, pin2);
2256
2257         if (pin1 != -1) {
2258                 /*
2259                  * Ok, does IRQ0 through the IOAPIC work?
2260                  */
2261                 unmask_IO_APIC_irq(0);
2262                 if (timer_irq_works()) {
2263                         if (nmi_watchdog == NMI_IO_APIC) {
2264                                 disable_8259A_irq(0);
2265                                 setup_nmi();
2266                                 enable_8259A_irq(0);
2267                         }
2268                         if (disable_timer_pin_1 > 0)
2269                                 clear_IO_APIC_pin(0, pin1);
2270                         return;
2271                 }
2272                 clear_IO_APIC_pin(apic1, pin1);
2273                 printk(KERN_ERR "..MP-BIOS bug: 8254 timer not connected to "
2274                                 "IO-APIC\n");
2275         }
2276
2277         printk(KERN_INFO "...trying to set up timer (IRQ0) through the 8259A ... ");
2278         if (pin2 != -1) {
2279                 printk("\n..... (found pin %d) ...", pin2);
2280                 /*
2281                  * legacy devices should be connected to IO APIC #0
2282                  */
2283                 setup_ExtINT_IRQ0_pin(apic2, pin2, vector);
2284                 if (timer_irq_works()) {
2285                         printk("works.\n");
2286                         if (pin1 != -1)
2287                                 replace_pin_at_irq(0, apic1, pin1, apic2, pin2);
2288                         else
2289                                 add_pin_to_irq(0, apic2, pin2);
2290                         if (nmi_watchdog == NMI_IO_APIC) {
2291                                 setup_nmi();
2292                         }
2293                         return;
2294                 }
2295                 /*
2296                  * Cleanup, just in case ...
2297                  */
2298                 clear_IO_APIC_pin(apic2, pin2);
2299         }
2300         printk(" failed.\n");
2301
2302         if (nmi_watchdog == NMI_IO_APIC) {
2303                 printk(KERN_WARNING "timer doesn't work through the IO-APIC - disabling NMI Watchdog!\n");
2304                 nmi_watchdog = 0;
2305         }
2306
2307         printk(KERN_INFO "...trying to set up timer as Virtual Wire IRQ...");
2308
2309         disable_8259A_irq(0);
2310         set_irq_chip_and_handler_name(0, &lapic_chip, handle_fasteoi_irq,
2311                                       "fasteoi");
2312         apic_write_around(APIC_LVT0, APIC_DM_FIXED | vector);   /* Fixed mode */
2313         enable_8259A_irq(0);
2314
2315         if (timer_irq_works()) {
2316                 printk(" works.\n");
2317                 return;
2318         }
2319         apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | vector);
2320         printk(" failed.\n");
2321
2322         printk(KERN_INFO "...trying to set up timer as ExtINT IRQ...");
2323
2324         timer_ack = 0;
2325         init_8259A(0);
2326         make_8259A_irq(0);
2327         apic_write_around(APIC_LVT0, APIC_DM_EXTINT);
2328
2329         unlock_ExtINT_logic();
2330
2331         if (timer_irq_works()) {
2332                 printk(" works.\n");
2333                 return;
2334         }
2335         printk(" failed :(.\n");
2336         panic("IO-APIC + timer doesn't work!  Boot with apic=debug and send a "
2337                 "report.  Then try booting with the 'noapic' option");
2338 }
2339
2340 /*
2341  *
2342  * IRQ's that are handled by the PIC in the MPS IOAPIC case.
2343  * - IRQ2 is the cascade IRQ, and cannot be a io-apic IRQ.
2344  *   Linux doesn't really care, as it's not actually used
2345  *   for any interrupt handling anyway.
2346  */
2347 #define PIC_IRQS        (1 << PIC_CASCADE_IR)
2348
2349 void __init setup_IO_APIC(void)
2350 {
2351         enable_IO_APIC();
2352
2353         if (acpi_ioapic)
2354                 io_apic_irqs = ~0;      /* all IRQs go through IOAPIC */
2355         else
2356                 io_apic_irqs = ~PIC_IRQS;
2357
2358         printk("ENABLING IO-APIC IRQs\n");
2359
2360         /*
2361          * Set up IO-APIC IRQ routing.
2362          */
2363         if (!acpi_ioapic)
2364                 setup_ioapic_ids_from_mpc();
2365         sync_Arb_IDs();
2366         setup_IO_APIC_irqs();
2367         init_IO_APIC_traps();
2368         check_timer();
2369         if (!acpi_ioapic)
2370                 print_IO_APIC();
2371 }
2372
2373 static int __init setup_disable_8254_timer(char *s)
2374 {
2375         timer_over_8254 = -1;
2376         return 1;
2377 }
2378 static int __init setup_enable_8254_timer(char *s)
2379 {
2380         timer_over_8254 = 2;
2381         return 1;
2382 }
2383
2384 __setup("disable_8254_timer", setup_disable_8254_timer);
2385 __setup("enable_8254_timer", setup_enable_8254_timer);
2386
2387 /*
2388  *      Called after all the initialization is done. If we didnt find any
2389  *      APIC bugs then we can allow the modify fast path
2390  */
2391
2392 static int __init io_apic_bug_finalize(void)
2393 {
2394         if(sis_apic_bug == -1)
2395                 sis_apic_bug = 0;
2396         return 0;
2397 }
2398
2399 late_initcall(io_apic_bug_finalize);
2400
2401 struct sysfs_ioapic_data {
2402         struct sys_device dev;
2403         struct IO_APIC_route_entry entry[0];
2404 };
2405 static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS];
2406
2407 static int ioapic_suspend(struct sys_device *dev, pm_message_t state)
2408 {
2409         struct IO_APIC_route_entry *entry;
2410         struct sysfs_ioapic_data *data;
2411         int i;
2412
2413         data = container_of(dev, struct sysfs_ioapic_data, dev);
2414         entry = data->entry;
2415         for (i = 0; i < nr_ioapic_registers[dev->id]; i ++)
2416                 entry[i] = ioapic_read_entry(dev->id, i);
2417
2418         return 0;
2419 }
2420
2421 static int ioapic_resume(struct sys_device *dev)
2422 {
2423         struct IO_APIC_route_entry *entry;
2424         struct sysfs_ioapic_data *data;
2425         unsigned long flags;
2426         union IO_APIC_reg_00 reg_00;
2427         int i;
2428
2429         data = container_of(dev, struct sysfs_ioapic_data, dev);
2430         entry = data->entry;
2431
2432         spin_lock_irqsave(&ioapic_lock, flags);
2433         reg_00.raw = io_apic_read(dev->id, 0);
2434         if (reg_00.bits.ID != mp_ioapics[dev->id].mpc_apicid) {
2435                 reg_00.bits.ID = mp_ioapics[dev->id].mpc_apicid;
2436                 io_apic_write(dev->id, 0, reg_00.raw);
2437         }
2438         spin_unlock_irqrestore(&ioapic_lock, flags);
2439         for (i = 0; i < nr_ioapic_registers[dev->id]; i ++)
2440                 ioapic_write_entry(dev->id, i, entry[i]);
2441
2442         return 0;
2443 }
2444
2445 static struct sysdev_class ioapic_sysdev_class = {
2446         set_kset_name("ioapic"),
2447         .suspend = ioapic_suspend,
2448         .resume = ioapic_resume,
2449 };
2450
2451 static int __init ioapic_init_sysfs(void)
2452 {
2453         struct sys_device * dev;
2454         int i, size, error = 0;
2455
2456         error = sysdev_class_register(&ioapic_sysdev_class);
2457         if (error)
2458                 return error;
2459
2460         for (i = 0; i < nr_ioapics; i++ ) {
2461                 size = sizeof(struct sys_device) + nr_ioapic_registers[i]
2462                         * sizeof(struct IO_APIC_route_entry);
2463                 mp_ioapic_data[i] = kmalloc(size, GFP_KERNEL);
2464                 if (!mp_ioapic_data[i]) {
2465                         printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
2466                         continue;
2467                 }
2468                 memset(mp_ioapic_data[i], 0, size);
2469                 dev = &mp_ioapic_data[i]->dev;
2470                 dev->id = i;
2471                 dev->cls = &ioapic_sysdev_class;
2472                 error = sysdev_register(dev);
2473                 if (error) {
2474                         kfree(mp_ioapic_data[i]);
2475                         mp_ioapic_data[i] = NULL;
2476                         printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
2477                         continue;
2478                 }
2479         }
2480
2481         return 0;
2482 }
2483
2484 device_initcall(ioapic_init_sysfs);
2485
2486 /*
2487  * Dynamic irq allocate and deallocation
2488  */
2489 int create_irq(void)
2490 {
2491         /* Allocate an unused irq */
2492         int irq, new, vector = 0;
2493         unsigned long flags;
2494
2495         irq = -ENOSPC;
2496         spin_lock_irqsave(&vector_lock, flags);
2497         for (new = (NR_IRQS - 1); new >= 0; new--) {
2498                 if (platform_legacy_irq(new))
2499                         continue;
2500                 if (irq_vector[new] != 0)
2501                         continue;
2502                 vector = __assign_irq_vector(new);
2503                 if (likely(vector > 0))
2504                         irq = new;
2505                 break;
2506         }
2507         spin_unlock_irqrestore(&vector_lock, flags);
2508
2509         if (irq >= 0) {
2510                 set_intr_gate(vector, interrupt[irq]);
2511                 dynamic_irq_init(irq);
2512         }
2513         return irq;
2514 }
2515
2516 void destroy_irq(unsigned int irq)
2517 {
2518         unsigned long flags;
2519
2520         dynamic_irq_cleanup(irq);
2521
2522         spin_lock_irqsave(&vector_lock, flags);
2523         irq_vector[irq] = 0;
2524         spin_unlock_irqrestore(&vector_lock, flags);
2525 }
2526
2527 /*
2528  * MSI mesage composition
2529  */
2530 #ifdef CONFIG_PCI_MSI
2531 static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, struct msi_msg *msg)
2532 {
2533         int vector;
2534         unsigned dest;
2535
2536         vector = assign_irq_vector(irq);
2537         if (vector >= 0) {
2538                 dest = cpu_mask_to_apicid(TARGET_CPUS);
2539
2540                 msg->address_hi = MSI_ADDR_BASE_HI;
2541                 msg->address_lo =
2542                         MSI_ADDR_BASE_LO |
2543                         ((INT_DEST_MODE == 0) ?
2544                                 MSI_ADDR_DEST_MODE_PHYSICAL:
2545                                 MSI_ADDR_DEST_MODE_LOGICAL) |
2546                         ((INT_DELIVERY_MODE != dest_LowestPrio) ?
2547                                 MSI_ADDR_REDIRECTION_CPU:
2548                                 MSI_ADDR_REDIRECTION_LOWPRI) |
2549                         MSI_ADDR_DEST_ID(dest);
2550
2551                 msg->data =
2552                         MSI_DATA_TRIGGER_EDGE |
2553                         MSI_DATA_LEVEL_ASSERT |
2554                         ((INT_DELIVERY_MODE != dest_LowestPrio) ?
2555                                 MSI_DATA_DELIVERY_FIXED:
2556                                 MSI_DATA_DELIVERY_LOWPRI) |
2557                         MSI_DATA_VECTOR(vector);
2558         }
2559         return vector;
2560 }
2561
2562 #ifdef CONFIG_SMP
2563 static void set_msi_irq_affinity(unsigned int irq, cpumask_t mask)
2564 {
2565         struct msi_msg msg;
2566         unsigned int dest;
2567         cpumask_t tmp;
2568         int vector;
2569
2570         cpus_and(tmp, mask, cpu_online_map);
2571         if (cpus_empty(tmp))
2572                 tmp = TARGET_CPUS;
2573
2574         vector = assign_irq_vector(irq);
2575         if (vector < 0)
2576                 return;
2577
2578         dest = cpu_mask_to_apicid(mask);
2579
2580         read_msi_msg(irq, &msg);
2581
2582         msg.data &= ~MSI_DATA_VECTOR_MASK;
2583         msg.data |= MSI_DATA_VECTOR(vector);
2584         msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
2585         msg.address_lo |= MSI_ADDR_DEST_ID(dest);
2586
2587         write_msi_msg(irq, &msg);
2588         irq_desc[irq].affinity = mask;
2589 }
2590 #endif /* CONFIG_SMP */
2591
2592 /*
2593  * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
2594  * which implement the MSI or MSI-X Capability Structure.
2595  */
2596 static struct irq_chip msi_chip = {
2597         .name           = "PCI-MSI",
2598         .unmask         = unmask_msi_irq,
2599         .mask           = mask_msi_irq,
2600         .ack            = ack_ioapic_irq,
2601 #ifdef CONFIG_SMP
2602         .set_affinity   = set_msi_irq_affinity,
2603 #endif
2604         .retrigger      = ioapic_retrigger_irq,
2605 };
2606
2607 int arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc)
2608 {
2609         struct msi_msg msg;
2610         int irq, ret;
2611         irq = create_irq();
2612         if (irq < 0)
2613                 return irq;
2614
2615         set_irq_msi(irq, desc);
2616         ret = msi_compose_msg(dev, irq, &msg);
2617         if (ret < 0) {
2618                 destroy_irq(irq);
2619                 return ret;
2620         }
2621
2622         write_msi_msg(irq, &msg);
2623
2624         set_irq_chip_and_handler_name(irq, &msi_chip, handle_edge_irq,
2625                                       "edge");
2626
2627         return irq;
2628 }
2629
2630 void arch_teardown_msi_irq(unsigned int irq)
2631 {
2632         destroy_irq(irq);
2633 }
2634
2635 #endif /* CONFIG_PCI_MSI */
2636
2637 /*
2638  * Hypertransport interrupt support
2639  */
2640 #ifdef CONFIG_HT_IRQ
2641
2642 #ifdef CONFIG_SMP
2643
2644 static void target_ht_irq(unsigned int irq, unsigned int dest)
2645 {
2646         struct ht_irq_msg msg;
2647         fetch_ht_irq_msg(irq, &msg);
2648
2649         msg.address_lo &= ~(HT_IRQ_LOW_DEST_ID_MASK);
2650         msg.address_hi &= ~(HT_IRQ_HIGH_DEST_ID_MASK);
2651
2652         msg.address_lo |= HT_IRQ_LOW_DEST_ID(dest);
2653         msg.address_hi |= HT_IRQ_HIGH_DEST_ID(dest);
2654
2655         write_ht_irq_msg(irq, &msg);
2656 }
2657
2658 static void set_ht_irq_affinity(unsigned int irq, cpumask_t mask)
2659 {
2660         unsigned int dest;
2661         cpumask_t tmp;
2662
2663         cpus_and(tmp, mask, cpu_online_map);
2664         if (cpus_empty(tmp))
2665                 tmp = TARGET_CPUS;
2666
2667         cpus_and(mask, tmp, CPU_MASK_ALL);
2668
2669         dest = cpu_mask_to_apicid(mask);
2670
2671         target_ht_irq(irq, dest);
2672         irq_desc[irq].affinity = mask;
2673 }
2674 #endif
2675
2676 static struct irq_chip ht_irq_chip = {
2677         .name           = "PCI-HT",
2678         .mask           = mask_ht_irq,
2679         .unmask         = unmask_ht_irq,
2680         .ack            = ack_ioapic_irq,
2681 #ifdef CONFIG_SMP
2682         .set_affinity   = set_ht_irq_affinity,
2683 #endif
2684         .retrigger      = ioapic_retrigger_irq,
2685 };
2686
2687 int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev)
2688 {
2689         int vector;
2690
2691         vector = assign_irq_vector(irq);
2692         if (vector >= 0) {
2693                 struct ht_irq_msg msg;
2694                 unsigned dest;
2695                 cpumask_t tmp;
2696
2697                 cpus_clear(tmp);
2698                 cpu_set(vector >> 8, tmp);
2699                 dest = cpu_mask_to_apicid(tmp);
2700
2701                 msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest);
2702
2703                 msg.address_lo =
2704                         HT_IRQ_LOW_BASE |
2705                         HT_IRQ_LOW_DEST_ID(dest) |
2706                         HT_IRQ_LOW_VECTOR(vector) |
2707                         ((INT_DEST_MODE == 0) ?
2708                                 HT_IRQ_LOW_DM_PHYSICAL :
2709                                 HT_IRQ_LOW_DM_LOGICAL) |
2710                         HT_IRQ_LOW_RQEOI_EDGE |
2711                         ((INT_DELIVERY_MODE != dest_LowestPrio) ?
2712                                 HT_IRQ_LOW_MT_FIXED :
2713                                 HT_IRQ_LOW_MT_ARBITRATED) |
2714                         HT_IRQ_LOW_IRQ_MASKED;
2715
2716                 write_ht_irq_msg(irq, &msg);
2717
2718                 set_irq_chip_and_handler_name(irq, &ht_irq_chip,
2719                                               handle_edge_irq, "edge");
2720         }
2721         return vector;
2722 }
2723 #endif /* CONFIG_HT_IRQ */
2724
2725 /* --------------------------------------------------------------------------
2726                           ACPI-based IOAPIC Configuration
2727    -------------------------------------------------------------------------- */
2728
2729 #ifdef CONFIG_ACPI
2730
2731 int __init io_apic_get_unique_id (int ioapic, int apic_id)
2732 {
2733         union IO_APIC_reg_00 reg_00;
2734         static physid_mask_t apic_id_map = PHYSID_MASK_NONE;
2735         physid_mask_t tmp;
2736         unsigned long flags;
2737         int i = 0;
2738
2739         /*
2740          * The P4 platform supports up to 256 APIC IDs on two separate APIC
2741          * buses (one for LAPICs, one for IOAPICs), where predecessors only
2742          * supports up to 16 on one shared APIC bus.
2743          *
2744          * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
2745          *      advantage of new APIC bus architecture.
2746          */
2747
2748         if (physids_empty(apic_id_map))
2749                 apic_id_map = ioapic_phys_id_map(phys_cpu_present_map);
2750
2751         spin_lock_irqsave(&ioapic_lock, flags);
2752         reg_00.raw = io_apic_read(ioapic, 0);
2753         spin_unlock_irqrestore(&ioapic_lock, flags);
2754
2755         if (apic_id >= get_physical_broadcast()) {
2756                 printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying "
2757                         "%d\n", ioapic, apic_id, reg_00.bits.ID);
2758                 apic_id = reg_00.bits.ID;
2759         }
2760
2761         /*
2762          * Every APIC in a system must have a unique ID or we get lots of nice
2763          * 'stuck on smp_invalidate_needed IPI wait' messages.
2764          */
2765         if (check_apicid_used(apic_id_map, apic_id)) {
2766
2767                 for (i = 0; i < get_physical_broadcast(); i++) {
2768                         if (!check_apicid_used(apic_id_map, i))
2769                                 break;
2770                 }
2771
2772                 if (i == get_physical_broadcast())
2773                         panic("Max apic_id exceeded!\n");
2774
2775                 printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, "
2776                         "trying %d\n", ioapic, apic_id, i);
2777
2778                 apic_id = i;
2779         }
2780
2781         tmp = apicid_to_cpu_present(apic_id);
2782         physids_or(apic_id_map, apic_id_map, tmp);
2783
2784         if (reg_00.bits.ID != apic_id) {
2785                 reg_00.bits.ID = apic_id;
2786
2787                 spin_lock_irqsave(&ioapic_lock, flags);
2788                 io_apic_write(ioapic, 0, reg_00.raw);
2789                 reg_00.raw = io_apic_read(ioapic, 0);
2790                 spin_unlock_irqrestore(&ioapic_lock, flags);
2791
2792                 /* Sanity check */
2793                 if (reg_00.bits.ID != apic_id) {
2794                         printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic);
2795                         return -1;
2796                 }
2797         }
2798
2799         apic_printk(APIC_VERBOSE, KERN_INFO
2800                         "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id);
2801
2802         return apic_id;
2803 }
2804
2805
2806 int __init io_apic_get_version (int ioapic)
2807 {
2808         union IO_APIC_reg_01    reg_01;
2809         unsigned long flags;
2810
2811         spin_lock_irqsave(&ioapic_lock, flags);
2812         reg_01.raw = io_apic_read(ioapic, 1);
2813         spin_unlock_irqrestore(&ioapic_lock, flags);
2814
2815         return reg_01.bits.version;
2816 }
2817
2818
2819 int __init io_apic_get_redir_entries (int ioapic)
2820 {
2821         union IO_APIC_reg_01    reg_01;
2822         unsigned long flags;
2823
2824         spin_lock_irqsave(&ioapic_lock, flags);
2825         reg_01.raw = io_apic_read(ioapic, 1);
2826         spin_unlock_irqrestore(&ioapic_lock, flags);
2827
2828         return reg_01.bits.entries;
2829 }
2830
2831
2832 int io_apic_set_pci_routing (int ioapic, int pin, int irq, int edge_level, int active_high_low)
2833 {
2834         struct IO_APIC_route_entry entry;
2835         unsigned long flags;
2836
2837         if (!IO_APIC_IRQ(irq)) {
2838                 printk(KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
2839                         ioapic);
2840                 return -EINVAL;
2841         }
2842
2843         /*
2844          * Generate a PCI IRQ routing entry and program the IOAPIC accordingly.
2845          * Note that we mask (disable) IRQs now -- these get enabled when the
2846          * corresponding device driver registers for this IRQ.
2847          */
2848
2849         memset(&entry,0,sizeof(entry));
2850
2851         entry.delivery_mode = INT_DELIVERY_MODE;
2852         entry.dest_mode = INT_DEST_MODE;
2853         entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
2854         entry.trigger = edge_level;
2855         entry.polarity = active_high_low;
2856         entry.mask  = 1;
2857
2858         /*
2859          * IRQs < 16 are already in the irq_2_pin[] map
2860          */
2861         if (irq >= 16)
2862                 add_pin_to_irq(irq, ioapic, pin);
2863
2864         entry.vector = assign_irq_vector(irq);
2865
2866         apic_printk(APIC_DEBUG, KERN_DEBUG "IOAPIC[%d]: Set PCI routing entry "
2867                 "(%d-%d -> 0x%x -> IRQ %d Mode:%i Active:%i)\n", ioapic,
2868                 mp_ioapics[ioapic].mpc_apicid, pin, entry.vector, irq,
2869                 edge_level, active_high_low);
2870
2871         ioapic_register_intr(irq, entry.vector, edge_level);
2872
2873         if (!ioapic && (irq < 16))
2874                 disable_8259A_irq(irq);
2875
2876         spin_lock_irqsave(&ioapic_lock, flags);
2877         __ioapic_write_entry(ioapic, pin, entry);
2878         irq_desc[irq].affinity = TARGET_CPUS;
2879         spin_unlock_irqrestore(&ioapic_lock, flags);
2880
2881         return 0;
2882 }
2883
2884 #endif /* CONFIG_ACPI */
2885
2886 static int __init parse_disable_timer_pin_1(char *arg)
2887 {
2888         disable_timer_pin_1 = 1;
2889         return 0;
2890 }
2891 early_param("disable_timer_pin_1", parse_disable_timer_pin_1);
2892
2893 static int __init parse_enable_timer_pin_1(char *arg)
2894 {
2895         disable_timer_pin_1 = -1;
2896         return 0;
2897 }
2898 early_param("enable_timer_pin_1", parse_enable_timer_pin_1);
2899
2900 static int __init parse_noapic(char *arg)
2901 {
2902         /* disable IO-APIC */
2903         disable_ioapic_setup();
2904         return 0;
2905 }
2906 early_param("noapic", parse_noapic);