2 * MPC8610 HPCD board specific routines
4 * Initial author: Xianghua Xiao <x.xiao@freescale.com>
5 * Recode: Jason Jin <jason.jin@freescale.com>
6 * York Sun <yorksun@freescale.com>
8 * Rewrite the interrupt routing. remove the 8259PIC support,
9 * All the integrated device in ULI use sideband interrupt.
11 * Copyright 2008 Freescale Semiconductor Inc.
13 * This program is free software; you can redistribute it and/or modify it
14 * under the terms of the GNU General Public License as published by the
15 * Free Software Foundation; either version 2 of the License, or (at your
16 * option) any later version.
19 #include <linux/stddef.h>
20 #include <linux/kernel.h>
21 #include <linux/pci.h>
22 #include <linux/kdev_t.h>
23 #include <linux/delay.h>
24 #include <linux/seq_file.h>
27 #include <asm/system.h>
29 #include <asm/machdep.h>
30 #include <asm/pci-bridge.h>
31 #include <asm/mpc86xx.h>
33 #include <mm/mmu_decl.h>
38 #include <linux/of_platform.h>
39 #include <sysdev/fsl_pci.h>
40 #include <sysdev/fsl_soc.h>
44 static unsigned char *pixis_bdcfg0, *pixis_arch;
46 static struct of_device_id __initdata mpc8610_ids[] = {
47 { .compatible = "fsl,mpc8610-immr", },
48 { .compatible = "simple-bus", },
52 static int __init mpc8610_declare_of_platform_devices(void)
54 /* Without this call, the SSI device driver won't get probed. */
55 of_platform_bus_probe(NULL, mpc8610_ids, NULL);
59 machine_device_initcall(mpc86xx_hpcd, mpc8610_declare_of_platform_devices);
62 static void __devinit quirk_uli1575(struct pci_dev *dev)
67 pci_read_config_dword(dev, 0x48, &temp32);
68 pci_write_config_dword(dev, 0x48, (temp32 | 1<<26));
70 /* Enable sideband interrupt */
71 pci_read_config_dword(dev, 0x90, &temp32);
72 pci_write_config_dword(dev, 0x90, (temp32 | 1<<22));
75 static void __devinit quirk_uli5288(struct pci_dev *dev)
80 /* Interrupt Disable, Needed when SATA disabled */
81 pci_read_config_word(dev, PCI_COMMAND, &temp);
83 pci_write_config_word(dev, PCI_COMMAND, temp);
85 pci_read_config_byte(dev, 0x83, &c);
87 pci_write_config_byte(dev, 0x83, c);
89 pci_write_config_byte(dev, PCI_CLASS_PROG, 0x01);
90 pci_write_config_byte(dev, PCI_CLASS_DEVICE, 0x06);
92 pci_read_config_byte(dev, 0x83, &c);
94 pci_write_config_byte(dev, 0x83, c);
98 * Since 8259PIC was disabled on the board, the IDE device can not
99 * use the legacy IRQ, we need to let the IDE device work under
100 * native mode and use the interrupt line like other PCI devices.
101 * IRQ14 is a sideband interrupt from IDE device to CPU and we use this
102 * as the interrupt for IDE device.
104 static void __devinit quirk_uli5229(struct pci_dev *dev)
108 pci_read_config_byte(dev, 0x4b, &c);
110 pci_write_config_byte(dev, 0x4b, c);
114 * SATA interrupt pin bug fix
115 * There's a chip bug for 5288, The interrupt pin should be 2,
116 * not the read only value 1, So it use INTB#, not INTA# which
117 * actually used by the IDE device 5229.
118 * As of this bug, during the PCI initialization, 5288 read the
119 * irq of IDE device from the device tree, this function fix this
120 * bug by re-assigning a correct irq to 5288.
123 static void __devinit final_uli5288(struct pci_dev *dev)
125 struct pci_controller *hose = pci_bus_to_host(dev->bus);
126 struct device_node *hosenode = hose ? hose->dn : NULL;
134 laddr[0] = (hose->first_busno << 16) | (PCI_DEVFN(31, 0) << 8);
135 laddr[1] = laddr[2] = 0;
136 of_irq_map_raw(hosenode, &pin, 1, laddr, &oirq);
137 virq = irq_create_of_mapping(oirq.controller, oirq.specifier,
142 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, 0x1575, quirk_uli1575);
143 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, 0x5288, quirk_uli5288);
144 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, 0x5229, quirk_uli5229);
145 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, 0x5288, final_uli5288);
146 #endif /* CONFIG_PCI */
148 #if defined(CONFIG_FB_FSL_DIU) || defined(CONFIG_FB_FSL_DIU_MODULE)
150 static u32 get_busfreq(void)
152 struct device_node *node;
155 node = of_find_node_by_type(NULL, "cpu");
158 const unsigned int *prop =
159 of_get_property(node, "bus-frequency", &size);
167 unsigned int mpc8610hpcd_get_pixel_format(unsigned int bits_per_pixel,
170 static const unsigned long pixelformat[][3] = {
171 {0x88882317, 0x88083218, 0x65052119},
172 {0x88883316, 0x88082219, 0x65053118},
174 unsigned int pix_fmt, arch_monitor;
176 arch_monitor = ((*pixis_arch == 0x01) && (monitor_port == 0))? 0 : 1;
177 /* DVI port for board version 0x01 */
179 if (bits_per_pixel == 32)
180 pix_fmt = pixelformat[arch_monitor][0];
181 else if (bits_per_pixel == 24)
182 pix_fmt = pixelformat[arch_monitor][1];
183 else if (bits_per_pixel == 16)
184 pix_fmt = pixelformat[arch_monitor][2];
186 pix_fmt = pixelformat[1][0];
191 void mpc8610hpcd_set_gamma_table(int monitor_port, char *gamma_table_base)
194 if (monitor_port == 2) { /* dual link LVDS */
195 for (i = 0; i < 256*3; i++)
196 gamma_table_base[i] = (gamma_table_base[i] << 2) |
197 ((gamma_table_base[i] >> 6) & 0x03);
201 #define PX_BRDCFG0_DVISEL (1 << 3)
202 #define PX_BRDCFG0_DLINK (1 << 4)
203 #define PX_BRDCFG0_DIU_MASK (PX_BRDCFG0_DVISEL | PX_BRDCFG0_DLINK)
205 void mpc8610hpcd_set_monitor_port(int monitor_port)
207 static const u8 bdcfg[] = {
208 PX_BRDCFG0_DVISEL | PX_BRDCFG0_DLINK,
213 if (monitor_port < 3)
214 clrsetbits_8(pixis_bdcfg0, PX_BRDCFG0_DIU_MASK,
215 bdcfg[monitor_port]);
218 void mpc8610hpcd_set_pixel_clock(unsigned int pixclock)
220 u32 __iomem *clkdvdr;
222 /* variables for pixel clock calcs */
223 ulong bestval, bestfreq, speed_ccb, minpixclock, maxpixclock;
228 clkdvdr = ioremap(get_immrbase() + 0xe0800, sizeof(u32));
230 printk(KERN_ERR "Err: can't map clock divider register!\n");
234 /* Pixel Clock configuration */
235 pr_debug("DIU: Bus Frequency = %d\n", get_busfreq());
236 speed_ccb = get_busfreq();
238 /* Calculate the pixel clock with the smallest error */
239 /* calculate the following in steps to avoid overflow */
240 pr_debug("DIU pixclock in ps - %d\n", pixclock);
241 temp = 1000000000/pixclock;
244 pr_debug("DIU pixclock freq - %u\n", pixclock);
246 temp = pixclock * 5 / 100;
247 pr_debug("deviation = %d\n", temp);
248 minpixclock = pixclock - temp;
249 maxpixclock = pixclock + temp;
250 pr_debug("DIU minpixclock - %lu\n", minpixclock);
251 pr_debug("DIU maxpixclock - %lu\n", maxpixclock);
252 pixval = speed_ccb/pixclock;
253 pr_debug("DIU pixval = %lu\n", pixval);
257 pr_debug("DIU bestval = %lu\n", bestval);
260 for (i = -1; i <= 1; i++) {
261 temp = speed_ccb / ((pixval+i) + 1);
262 pr_debug("DIU test pixval i= %d, pixval=%lu, temp freq. = %u\n",
264 if ((temp < minpixclock) || (temp > maxpixclock))
265 pr_debug("DIU exceeds monitor range (%lu to %lu)\n",
266 minpixclock, maxpixclock);
267 else if (abs(temp - pixclock) < err) {
268 pr_debug("Entered the else if block %d\n", i);
269 err = abs(temp - pixclock);
275 pr_debug("DIU chose = %lx\n", bestval);
276 pr_debug("DIU error = %ld\n NomPixClk ", err);
277 pr_debug("DIU: Best Freq = %lx\n", bestfreq);
278 /* Modify PXCLK in GUTS CLKDVDR */
279 pr_debug("DIU: Current value of CLKDVDR = 0x%08x\n", (*clkdvdr));
280 temp = (*clkdvdr) & 0x2000FFFF;
281 *clkdvdr = temp; /* turn off clock */
282 *clkdvdr = temp | 0x80000000 | (((bestval) & 0x1F) << 16);
283 pr_debug("DIU: Modified value of CLKDVDR = 0x%08x\n", (*clkdvdr));
287 ssize_t mpc8610hpcd_show_monitor_port(int monitor_port, char *buf)
289 return snprintf(buf, PAGE_SIZE,
291 "%c1 - Single link LVDS\n"
292 "%c2 - Dual link LVDS\n",
293 monitor_port == 0 ? '*' : ' ',
294 monitor_port == 1 ? '*' : ' ',
295 monitor_port == 2 ? '*' : ' ');
298 int mpc8610hpcd_set_sysfs_monitor_port(int val)
300 return val < 3 ? val : 0;
305 static void __init mpc86xx_hpcd_setup_arch(void)
308 struct device_node *np;
309 unsigned char *pixis;
312 ppc_md.progress("mpc86xx_hpcd_setup_arch()", 0);
315 for_each_node_by_type(np, "pci") {
316 if (of_device_is_compatible(np, "fsl,mpc8610-pci")
317 || of_device_is_compatible(np, "fsl,mpc8641-pcie")) {
318 struct resource rsrc;
319 of_address_to_resource(np, 0, &rsrc);
320 if ((rsrc.start & 0xfffff) == 0xa000)
321 fsl_add_bridge(np, 1);
323 fsl_add_bridge(np, 0);
327 #if defined(CONFIG_FB_FSL_DIU) || defined(CONFIG_FB_FSL_DIU_MODULE)
328 preallocate_diu_videomemory();
329 diu_ops.get_pixel_format = mpc8610hpcd_get_pixel_format;
330 diu_ops.set_gamma_table = mpc8610hpcd_set_gamma_table;
331 diu_ops.set_monitor_port = mpc8610hpcd_set_monitor_port;
332 diu_ops.set_pixel_clock = mpc8610hpcd_set_pixel_clock;
333 diu_ops.show_monitor_port = mpc8610hpcd_show_monitor_port;
334 diu_ops.set_sysfs_monitor_port = mpc8610hpcd_set_sysfs_monitor_port;
337 np = of_find_compatible_node(NULL, NULL, "fsl,fpga-pixis");
339 of_address_to_resource(np, 0, &r);
341 pixis = ioremap(r.start, 32);
343 printk(KERN_ERR "Err: can't map FPGA cfg register!\n");
346 pixis_bdcfg0 = pixis + 8;
347 pixis_arch = pixis + 1;
349 printk(KERN_ERR "Err: "
350 "can't find device node 'fsl,fpga-pixis'\n");
352 printk("MPC86xx HPCD board from Freescale Semiconductor\n");
356 * Called very early, device-tree isn't unflattened
358 static int __init mpc86xx_hpcd_probe(void)
360 unsigned long root = of_get_flat_dt_root();
362 if (of_flat_dt_is_compatible(root, "fsl,MPC8610HPCD"))
363 return 1; /* Looks good */
368 static long __init mpc86xx_time_init(void)
372 /* Set the time base to zero */
376 temp = mfspr(SPRN_HID0);
378 mtspr(SPRN_HID0, temp);
379 asm volatile("isync");
384 define_machine(mpc86xx_hpcd) {
385 .name = "MPC86xx HPCD",
386 .probe = mpc86xx_hpcd_probe,
387 .setup_arch = mpc86xx_hpcd_setup_arch,
388 .init_IRQ = mpc86xx_init_irq,
389 .get_irq = mpic_get_irq,
390 .restart = fsl_rstcr_restart,
391 .time_init = mpc86xx_time_init,
392 .calibrate_decr = generic_calibrate_decr,
393 .progress = udbg_progress,
394 .pcibios_fixup_bus = fsl_pcibios_fixup_bus,