Merge branch 'for-linus' of master.kernel.org:/home/rmk/linux-2.6-arm
[linux-2.6] / arch / sparc64 / kernel / pci_fire.c
1 /* pci_fire.c: Sun4u platform PCI-E controller support.
2  *
3  * Copyright (C) 2007 David S. Miller (davem@davemloft.net)
4  */
5 #include <linux/kernel.h>
6 #include <linux/pci.h>
7 #include <linux/slab.h>
8 #include <linux/init.h>
9
10 #include <asm/oplib.h>
11 #include <asm/prom.h>
12
13 #include "pci_impl.h"
14
15 #define fire_read(__reg) \
16 ({      u64 __ret; \
17         __asm__ __volatile__("ldxa [%1] %2, %0" \
18                              : "=r" (__ret) \
19                              : "r" (__reg), "i" (ASI_PHYS_BYPASS_EC_E) \
20                              : "memory"); \
21         __ret; \
22 })
23 #define fire_write(__reg, __val) \
24         __asm__ __volatile__("stxa %0, [%1] %2" \
25                              : /* no outputs */ \
26                              : "r" (__val), "r" (__reg), \
27                                "i" (ASI_PHYS_BYPASS_EC_E) \
28                              : "memory")
29
30 /* Fire config space address format is nearly identical to
31  * that of SCHIZO and PSYCHO, except that in order to accomodate
32  * PCI-E extended config space the encoding can handle 12 bits
33  * of register address:
34  *
35  *  32     28 27 20 19    15 14      12 11  2  1 0
36  * -------------------------------------------------
37  * |0 0 0 0 0| bus | device | function | reg | 0 0 |
38  * -------------------------------------------------
39  */
40 #define FIRE_CONFIG_BASE(PBM)   ((PBM)->config_space)
41 #define FIRE_CONFIG_ENCODE(BUS, DEVFN, REG)     \
42         (((unsigned long)(BUS)   << 20) |       \
43          ((unsigned long)(DEVFN) << 12)  |      \
44          ((unsigned long)(REG)))
45
46 static void *fire_pci_config_mkaddr(struct pci_pbm_info *pbm,
47                                       unsigned char bus,
48                                       unsigned int devfn,
49                                       int where)
50 {
51         if (!pbm)
52                 return NULL;
53         return (void *)
54                 (FIRE_CONFIG_BASE(pbm) |
55                  FIRE_CONFIG_ENCODE(bus, devfn, where));
56 }
57
58 /* FIRE PCI configuration space accessors. */
59
60 static int fire_read_pci_cfg(struct pci_bus *bus_dev, unsigned int devfn,
61                              int where, int size, u32 *value)
62 {
63         struct pci_pbm_info *pbm = bus_dev->sysdata;
64         unsigned char bus = bus_dev->number;
65         u32 *addr;
66         u16 tmp16;
67         u8 tmp8;
68
69         if (bus_dev == pbm->pci_bus && devfn == 0x00)
70                 return pci_host_bridge_read_pci_cfg(bus_dev, devfn, where,
71                                                     size, value);
72         switch (size) {
73         case 1:
74                 *value = 0xff;
75                 break;
76         case 2:
77                 *value = 0xffff;
78                 break;
79         case 4:
80                 *value = 0xffffffff;
81                 break;
82         }
83
84         addr = fire_pci_config_mkaddr(pbm, bus, devfn, where);
85         if (!addr)
86                 return PCIBIOS_SUCCESSFUL;
87
88         switch (size) {
89         case 1:
90                 pci_config_read8((u8 *)addr, &tmp8);
91                 *value = tmp8;
92                 break;
93
94         case 2:
95                 if (where & 0x01) {
96                         printk("pci_read_config_word: misaligned reg [%x]\n",
97                                where);
98                         return PCIBIOS_SUCCESSFUL;
99                 }
100                 pci_config_read16((u16 *)addr, &tmp16);
101                 *value = tmp16;
102                 break;
103
104         case 4:
105                 if (where & 0x03) {
106                         printk("pci_read_config_dword: misaligned reg [%x]\n",
107                                where);
108                         return PCIBIOS_SUCCESSFUL;
109                 }
110
111                 pci_config_read32(addr, value);
112                 break;
113         }
114         return PCIBIOS_SUCCESSFUL;
115 }
116
117 static int fire_write_pci_cfg(struct pci_bus *bus_dev, unsigned int devfn,
118                               int where, int size, u32 value)
119 {
120         struct pci_pbm_info *pbm = bus_dev->sysdata;
121         unsigned char bus = bus_dev->number;
122         u32 *addr;
123
124         if (bus_dev == pbm->pci_bus && devfn == 0x00)
125                 return pci_host_bridge_write_pci_cfg(bus_dev, devfn, where,
126                                                      size, value);
127         addr = fire_pci_config_mkaddr(pbm, bus, devfn, where);
128         if (!addr)
129                 return PCIBIOS_SUCCESSFUL;
130
131         switch (size) {
132         case 1:
133                 pci_config_write8((u8 *)addr, value);
134                 break;
135
136         case 2:
137                 if (where & 0x01) {
138                         printk("pci_write_config_word: misaligned reg [%x]\n",
139                                where);
140                         return PCIBIOS_SUCCESSFUL;
141                 }
142                 pci_config_write16((u16 *)addr, value);
143                 break;
144
145         case 4:
146                 if (where & 0x03) {
147                         printk("pci_write_config_dword: misaligned reg [%x]\n",
148                                where);
149                         return PCIBIOS_SUCCESSFUL;
150                 }
151
152                 pci_config_write32(addr, value);
153         }
154         return PCIBIOS_SUCCESSFUL;
155 }
156
157 static struct pci_ops pci_fire_ops = {
158         .read   =       fire_read_pci_cfg,
159         .write  =       fire_write_pci_cfg,
160 };
161
162 static void pci_fire_scan_bus(struct pci_pbm_info *pbm)
163 {
164         pbm->pci_bus = pci_scan_one_pbm(pbm);
165
166         /* XXX register error interrupt handlers XXX */
167 }
168
169 #define FIRE_IOMMU_CONTROL      0x40000UL
170 #define FIRE_IOMMU_TSBBASE      0x40008UL
171 #define FIRE_IOMMU_FLUSH        0x40100UL
172 #define FIRE_IOMMU_FLUSHINV     0x40100UL
173
174 static void pci_fire_pbm_iommu_init(struct pci_pbm_info *pbm)
175 {
176         struct iommu *iommu = pbm->iommu;
177         u32 vdma[2], dma_mask;
178         u64 control;
179         int tsbsize;
180
181         /* No virtual-dma property on these guys, use largest size.  */
182         vdma[0] = 0xc0000000; /* base */
183         vdma[1] = 0x40000000; /* size */
184         dma_mask = 0xffffffff;
185         tsbsize = 128;
186
187         /* Register addresses. */
188         iommu->iommu_control  = pbm->pbm_regs + FIRE_IOMMU_CONTROL;
189         iommu->iommu_tsbbase  = pbm->pbm_regs + FIRE_IOMMU_TSBBASE;
190         iommu->iommu_flush    = pbm->pbm_regs + FIRE_IOMMU_FLUSH;
191         iommu->iommu_flushinv = pbm->pbm_regs + FIRE_IOMMU_FLUSHINV;
192
193         /* We use the main control/status register of FIRE as the write
194          * completion register.
195          */
196         iommu->write_complete_reg = pbm->controller_regs + 0x410000UL;
197
198         /*
199          * Invalidate TLB Entries.
200          */
201         fire_write(iommu->iommu_flushinv, ~(u64)0);
202
203         pci_iommu_table_init(iommu, tsbsize * 8 * 1024, vdma[0], dma_mask);
204
205         fire_write(iommu->iommu_tsbbase, __pa(iommu->page_table) | 0x7UL);
206
207         control = fire_read(iommu->iommu_control);
208         control |= (0x00000400 /* TSB cache snoop enable */     |
209                     0x00000300 /* Cache mode */                 |
210                     0x00000002 /* Bypass enable */              |
211                     0x00000001 /* Translation enable */);
212         fire_write(iommu->iommu_control, control);
213 }
214
215 /* Based at pbm->controller_regs */
216 #define FIRE_PARITY_CONTROL     0x470010UL
217 #define  FIRE_PARITY_ENAB       0x8000000000000000UL
218 #define FIRE_FATAL_RESET_CTL    0x471028UL
219 #define  FIRE_FATAL_RESET_SPARE 0x0000000004000000UL
220 #define  FIRE_FATAL_RESET_MB    0x0000000002000000UL
221 #define  FIRE_FATAL_RESET_CPE   0x0000000000008000UL
222 #define  FIRE_FATAL_RESET_APE   0x0000000000004000UL
223 #define  FIRE_FATAL_RESET_PIO   0x0000000000000040UL
224 #define  FIRE_FATAL_RESET_JW    0x0000000000000004UL
225 #define  FIRE_FATAL_RESET_JI    0x0000000000000002UL
226 #define  FIRE_FATAL_RESET_JR    0x0000000000000001UL
227 #define FIRE_CORE_INTR_ENABLE   0x471800UL
228
229 /* Based at pbm->pbm_regs */
230 #define FIRE_TLU_CTRL           0x80000UL
231 #define  FIRE_TLU_CTRL_TIM      0x00000000da000000UL
232 #define  FIRE_TLU_CTRL_QDET     0x0000000000000100UL
233 #define  FIRE_TLU_CTRL_CFG      0x0000000000000001UL
234 #define FIRE_TLU_DEV_CTRL       0x90008UL
235 #define FIRE_TLU_LINK_CTRL      0x90020UL
236 #define FIRE_TLU_LINK_CTRL_CLK  0x0000000000000040UL
237 #define FIRE_LPU_RESET          0xe2008UL
238 #define FIRE_LPU_LLCFG          0xe2200UL
239 #define  FIRE_LPU_LLCFG_VC0     0x0000000000000100UL
240 #define FIRE_LPU_FCTRL_UCTRL    0xe2240UL
241 #define  FIRE_LPU_FCTRL_UCTRL_N 0x0000000000000002UL
242 #define  FIRE_LPU_FCTRL_UCTRL_P 0x0000000000000001UL
243 #define FIRE_LPU_TXL_FIFOP      0xe2430UL
244 #define FIRE_LPU_LTSSM_CFG2     0xe2788UL
245 #define FIRE_LPU_LTSSM_CFG3     0xe2790UL
246 #define FIRE_LPU_LTSSM_CFG4     0xe2798UL
247 #define FIRE_LPU_LTSSM_CFG5     0xe27a0UL
248 #define FIRE_DMC_IENAB          0x31800UL
249 #define FIRE_DMC_DBG_SEL_A      0x53000UL
250 #define FIRE_DMC_DBG_SEL_B      0x53008UL
251 #define FIRE_PEC_IENAB          0x51800UL
252
253 static void pci_fire_hw_init(struct pci_pbm_info *pbm)
254 {
255         u64 val;
256
257         fire_write(pbm->controller_regs + FIRE_PARITY_CONTROL,
258                    FIRE_PARITY_ENAB);
259
260         fire_write(pbm->controller_regs + FIRE_FATAL_RESET_CTL,
261                    (FIRE_FATAL_RESET_SPARE |
262                     FIRE_FATAL_RESET_MB |
263                     FIRE_FATAL_RESET_CPE |
264                     FIRE_FATAL_RESET_APE |
265                     FIRE_FATAL_RESET_PIO |
266                     FIRE_FATAL_RESET_JW |
267                     FIRE_FATAL_RESET_JI |
268                     FIRE_FATAL_RESET_JR));
269
270         fire_write(pbm->controller_regs + FIRE_CORE_INTR_ENABLE, ~(u64)0);
271
272         val = fire_read(pbm->pbm_regs + FIRE_TLU_CTRL);
273         val |= (FIRE_TLU_CTRL_TIM |
274                 FIRE_TLU_CTRL_QDET |
275                 FIRE_TLU_CTRL_CFG);
276         fire_write(pbm->pbm_regs + FIRE_TLU_CTRL, val);
277         fire_write(pbm->pbm_regs + FIRE_TLU_DEV_CTRL, 0);
278         fire_write(pbm->pbm_regs + FIRE_TLU_LINK_CTRL,
279                    FIRE_TLU_LINK_CTRL_CLK);
280
281         fire_write(pbm->pbm_regs + FIRE_LPU_RESET, 0);
282         fire_write(pbm->pbm_regs + FIRE_LPU_LLCFG,
283                    FIRE_LPU_LLCFG_VC0);
284         fire_write(pbm->pbm_regs + FIRE_LPU_FCTRL_UCTRL,
285                    (FIRE_LPU_FCTRL_UCTRL_N |
286                     FIRE_LPU_FCTRL_UCTRL_P));
287         fire_write(pbm->pbm_regs + FIRE_LPU_TXL_FIFOP,
288                    ((0xffff << 16) | (0x0000 << 0)));
289         fire_write(pbm->pbm_regs + FIRE_LPU_LTSSM_CFG2, 3000000);
290         fire_write(pbm->pbm_regs + FIRE_LPU_LTSSM_CFG3, 500000);
291         fire_write(pbm->pbm_regs + FIRE_LPU_LTSSM_CFG4,
292                    (2 << 16) | (140 << 8));
293         fire_write(pbm->pbm_regs + FIRE_LPU_LTSSM_CFG5, 0);
294
295         fire_write(pbm->pbm_regs + FIRE_DMC_IENAB, ~(u64)0);
296         fire_write(pbm->pbm_regs + FIRE_DMC_DBG_SEL_A, 0);
297         fire_write(pbm->pbm_regs + FIRE_DMC_DBG_SEL_B, 0);
298
299         fire_write(pbm->pbm_regs + FIRE_PEC_IENAB, ~(u64)0);
300 }
301
302 static void pci_fire_pbm_init(struct pci_controller_info *p,
303                               struct device_node *dp, u32 portid)
304 {
305         const struct linux_prom64_registers *regs;
306         struct pci_pbm_info *pbm;
307
308         if ((portid & 1) == 0)
309                 pbm = &p->pbm_A;
310         else
311                 pbm = &p->pbm_B;
312
313         pbm->next = pci_pbm_root;
314         pci_pbm_root = pbm;
315
316         pbm->scan_bus = pci_fire_scan_bus;
317         pbm->pci_ops = &pci_fire_ops;
318
319         pbm->index = pci_num_pbms++;
320
321         pbm->portid = portid;
322         pbm->parent = p;
323         pbm->prom_node = dp;
324         pbm->name = dp->full_name;
325
326         regs = of_get_property(dp, "reg", NULL);
327         pbm->pbm_regs = regs[0].phys_addr;
328         pbm->controller_regs = regs[1].phys_addr - 0x410000UL;
329
330         printk("%s: SUN4U PCIE Bus Module\n", pbm->name);
331
332         pci_determine_mem_io_space(pbm);
333
334         pci_get_pbm_props(pbm);
335
336         pci_fire_hw_init(pbm);
337         pci_fire_pbm_iommu_init(pbm);
338 }
339
340 static inline int portid_compare(u32 x, u32 y)
341 {
342         if (x == (y ^ 1))
343                 return 1;
344         return 0;
345 }
346
347 void fire_pci_init(struct device_node *dp, const char *model_name)
348 {
349         struct pci_controller_info *p;
350         u32 portid = of_getintprop_default(dp, "portid", 0xff);
351         struct iommu *iommu;
352         struct pci_pbm_info *pbm;
353
354         for (pbm = pci_pbm_root; pbm; pbm = pbm->next) {
355                 if (portid_compare(pbm->portid, portid)) {
356                         pci_fire_pbm_init(pbm->parent, dp, portid);
357                         return;
358                 }
359         }
360
361         p = kzalloc(sizeof(struct pci_controller_info), GFP_ATOMIC);
362         if (!p)
363                 goto fatal_memory_error;
364
365         iommu = kzalloc(sizeof(struct iommu), GFP_ATOMIC);
366         if (!iommu)
367                 goto fatal_memory_error;
368
369         p->pbm_A.iommu = iommu;
370
371         iommu = kzalloc(sizeof(struct iommu), GFP_ATOMIC);
372         if (!iommu)
373                 goto fatal_memory_error;
374
375         p->pbm_B.iommu = iommu;
376
377         /* XXX MSI support XXX */
378
379         /* Like PSYCHO and SCHIZO we have a 2GB aligned area
380          * for memory space.
381          */
382         pci_memspace_mask = 0x7fffffffUL;
383
384         pci_fire_pbm_init(p, dp, portid);
385         return;
386
387 fatal_memory_error:
388         prom_printf("PCI_FIRE: Fatal memory allocation error.\n");
389         prom_halt();
390 }