2 * linux/drivers/video/amba-clcd.c
4 * Copyright (C) 2001 ARM Limited, by David A Rusling
5 * Updated to 2.5, Deep Blue Solutions Ltd.
7 * This file is subject to the terms and conditions of the GNU General Public
8 * License. See the file COPYING in the main directory of this archive
11 * ARM PrimeCell PL110 Color LCD Controller
13 #include <linux/module.h>
14 #include <linux/kernel.h>
15 #include <linux/errno.h>
16 #include <linux/string.h>
17 #include <linux/slab.h>
18 #include <linux/delay.h>
21 #include <linux/init.h>
22 #include <linux/ioport.h>
23 #include <linux/list.h>
25 #include <asm/sizes.h>
26 #include <asm/hardware/amba.h>
27 #include <asm/hardware/clock.h>
29 #include <asm/hardware/amba_clcd.h>
31 #define to_clcd(info) container_of(info, struct clcd_fb, fb)
33 /* This is limited to 16 characters when displayed by X startup */
34 static const char *clcd_name = "CLCD FB";
37 * Unfortunately, the enable/disable functions may be called either from
38 * process or IRQ context, and we _need_ to delay. This is _not_ good.
40 static inline void clcdfb_sleep(unsigned int ms)
49 static inline void clcdfb_set_start(struct clcd_fb *fb)
51 unsigned long ustart = fb->fb.fix.smem_start;
54 ustart += fb->fb.var.yoffset * fb->fb.fix.line_length;
55 lstart = ustart + fb->fb.var.yres * fb->fb.fix.line_length / 2;
57 writel(ustart, fb->regs + CLCD_UBAS);
58 writel(lstart, fb->regs + CLCD_LBAS);
61 static void clcdfb_disable(struct clcd_fb *fb)
65 if (fb->board->disable)
66 fb->board->disable(fb);
68 val = readl(fb->regs + CLCD_CNTL);
69 if (val & CNTL_LCDPWR) {
71 writel(val, fb->regs + CLCD_CNTL);
75 if (val & CNTL_LCDEN) {
77 writel(val, fb->regs + CLCD_CNTL);
81 * Disable CLCD clock source.
86 static void clcdfb_enable(struct clcd_fb *fb, u32 cntl)
89 * Enable the CLCD clock source.
94 * Bring up by first enabling..
97 writel(cntl, fb->regs + CLCD_CNTL);
102 * and now apply power.
105 writel(cntl, fb->regs + CLCD_CNTL);
108 * finally, enable the interface.
110 if (fb->board->enable)
111 fb->board->enable(fb);
115 clcdfb_set_bitfields(struct clcd_fb *fb, struct fb_var_screeninfo *var)
119 memset(&var->transp, 0, sizeof(var->transp));
120 memset(&var->red, 0, sizeof(var->red));
121 memset(&var->green, 0, sizeof(var->green));
122 memset(&var->blue, 0, sizeof(var->blue));
124 switch (var->bits_per_pixel) {
129 var->red.length = var->bits_per_pixel;
131 var->green.length = var->bits_per_pixel;
132 var->green.offset = 0;
133 var->blue.length = var->bits_per_pixel;
134 var->blue.offset = 0;
138 var->green.length = 6;
139 var->blue.length = 5;
140 if (fb->panel->cntl & CNTL_BGR) {
141 var->red.offset = 11;
142 var->green.offset = 5;
143 var->blue.offset = 0;
146 var->green.offset = 5;
147 var->blue.offset = 11;
151 if (fb->panel->cntl & CNTL_LCDTFT) {
153 var->green.length = 8;
154 var->blue.length = 8;
156 if (fb->panel->cntl & CNTL_BGR) {
157 var->red.offset = 16;
158 var->green.offset = 8;
159 var->blue.offset = 0;
162 var->green.offset = 8;
163 var->blue.offset = 16;
175 static int clcdfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
177 struct clcd_fb *fb = to_clcd(info);
180 if (fb->board->check)
181 ret = fb->board->check(fb, var);
184 var->xres_virtual * var->bits_per_pixel / 8 *
185 var->yres_virtual > fb->fb.fix.smem_len)
189 ret = clcdfb_set_bitfields(fb, var);
194 static int clcdfb_set_par(struct fb_info *info)
196 struct clcd_fb *fb = to_clcd(info);
197 struct clcd_regs regs;
199 fb->fb.fix.line_length = fb->fb.var.xres_virtual *
200 fb->fb.var.bits_per_pixel / 8;
202 if (fb->fb.var.bits_per_pixel <= 8)
203 fb->fb.fix.visual = FB_VISUAL_PSEUDOCOLOR;
205 fb->fb.fix.visual = FB_VISUAL_TRUECOLOR;
207 fb->board->decode(fb, ®s);
211 writel(regs.tim0, fb->regs + CLCD_TIM0);
212 writel(regs.tim1, fb->regs + CLCD_TIM1);
213 writel(regs.tim2, fb->regs + CLCD_TIM2);
214 writel(regs.tim3, fb->regs + CLCD_TIM3);
216 clcdfb_set_start(fb);
218 clk_set_rate(fb->clk, (1000000000 / regs.pixclock) * 1000);
220 fb->clcd_cntl = regs.cntl;
222 clcdfb_enable(fb, regs.cntl);
225 printk(KERN_INFO "CLCD: Registers set to\n"
226 KERN_INFO " %08x %08x %08x %08x\n"
227 KERN_INFO " %08x %08x %08x %08x\n",
228 readl(fb->regs + CLCD_TIM0), readl(fb->regs + CLCD_TIM1),
229 readl(fb->regs + CLCD_TIM2), readl(fb->regs + CLCD_TIM3),
230 readl(fb->regs + CLCD_UBAS), readl(fb->regs + CLCD_LBAS),
231 readl(fb->regs + CLCD_IENB), readl(fb->regs + CLCD_CNTL));
237 static inline u32 convert_bitfield(int val, struct fb_bitfield *bf)
239 unsigned int mask = (1 << bf->length) - 1;
241 return (val >> (16 - bf->length) & mask) << bf->offset;
245 * Set a single color register. The values supplied have a 16 bit
246 * magnitude. Return != 0 for invalid regno.
249 clcdfb_setcolreg(unsigned int regno, unsigned int red, unsigned int green,
250 unsigned int blue, unsigned int transp, struct fb_info *info)
252 struct clcd_fb *fb = to_clcd(info);
255 fb->cmap[regno] = convert_bitfield(transp, &fb->fb.var.transp) |
256 convert_bitfield(blue, &fb->fb.var.blue) |
257 convert_bitfield(green, &fb->fb.var.green) |
258 convert_bitfield(red, &fb->fb.var.red);
260 if (fb->fb.fix.visual == FB_VISUAL_PSEUDOCOLOR && regno < 256) {
261 int hw_reg = CLCD_PALETTE + ((regno * 2) & ~3);
262 u32 val, mask, newval;
264 newval = (red >> 11) & 0x001f;
265 newval |= (green >> 6) & 0x03e0;
266 newval |= (blue >> 1) & 0x7c00;
269 * 3.2.11: if we're configured for big endian
270 * byte order, the palette entries are swapped.
272 if (fb->clcd_cntl & CNTL_BEBO)
282 val = readl(fb->regs + hw_reg) & mask;
283 writel(val | newval, fb->regs + hw_reg);
290 * Blank the screen if blank_mode != 0, else unblank. If blank == NULL
291 * then the caller blanks by setting the CLUT (Color Look Up Table) to all
292 * black. Return 0 if blanking succeeded, != 0 if un-/blanking failed due
293 * to e.g. a video mode which doesn't support it. Implements VESA suspend
294 * and powerdown modes on hardware that supports disabling hsync/vsync:
295 * blank_mode == 2: suspend vsync
296 * blank_mode == 3: suspend hsync
297 * blank_mode == 4: powerdown
299 static int clcdfb_blank(int blank_mode, struct fb_info *info)
301 struct clcd_fb *fb = to_clcd(info);
303 if (blank_mode != 0) {
306 clcdfb_enable(fb, fb->clcd_cntl);
311 static int clcdfb_mmap(struct fb_info *info, struct file *file,
312 struct vm_area_struct *vma)
314 struct clcd_fb *fb = to_clcd(info);
315 unsigned long len, off = vma->vm_pgoff << PAGE_SHIFT;
318 len = info->fix.smem_len;
320 if (off <= len && vma->vm_end - vma->vm_start <= len - off &&
322 ret = fb->board->mmap(fb, vma);
327 static struct fb_ops clcdfb_ops = {
328 .owner = THIS_MODULE,
329 .fb_check_var = clcdfb_check_var,
330 .fb_set_par = clcdfb_set_par,
331 .fb_setcolreg = clcdfb_setcolreg,
332 .fb_blank = clcdfb_blank,
333 .fb_fillrect = cfb_fillrect,
334 .fb_copyarea = cfb_copyarea,
335 .fb_imageblit = cfb_imageblit,
336 .fb_cursor = soft_cursor,
337 .fb_mmap = clcdfb_mmap,
340 static int clcdfb_register(struct clcd_fb *fb)
344 fb->clk = clk_get(&fb->dev->dev, "CLCDCLK");
345 if (IS_ERR(fb->clk)) {
346 ret = PTR_ERR(fb->clk);
350 ret = clk_use(fb->clk);
354 fb->fb.fix.mmio_start = fb->dev->res.start;
355 fb->fb.fix.mmio_len = SZ_4K;
357 fb->regs = ioremap(fb->fb.fix.mmio_start, fb->fb.fix.mmio_len);
359 printk(KERN_ERR "CLCD: unable to remap registers\n");
364 fb->fb.fbops = &clcdfb_ops;
365 fb->fb.flags = FBINFO_FLAG_DEFAULT;
366 fb->fb.pseudo_palette = fb->cmap;
368 strncpy(fb->fb.fix.id, clcd_name, sizeof(fb->fb.fix.id));
369 fb->fb.fix.type = FB_TYPE_PACKED_PIXELS;
370 fb->fb.fix.type_aux = 0;
371 fb->fb.fix.xpanstep = 0;
372 fb->fb.fix.ypanstep = 0;
373 fb->fb.fix.ywrapstep = 0;
374 fb->fb.fix.accel = FB_ACCEL_NONE;
376 fb->fb.var.xres = fb->panel->mode.xres;
377 fb->fb.var.yres = fb->panel->mode.yres;
378 fb->fb.var.xres_virtual = fb->panel->mode.xres;
379 fb->fb.var.yres_virtual = fb->panel->mode.yres;
380 fb->fb.var.bits_per_pixel = fb->panel->bpp;
381 fb->fb.var.grayscale = fb->panel->grayscale;
382 fb->fb.var.pixclock = fb->panel->mode.pixclock;
383 fb->fb.var.left_margin = fb->panel->mode.left_margin;
384 fb->fb.var.right_margin = fb->panel->mode.right_margin;
385 fb->fb.var.upper_margin = fb->panel->mode.upper_margin;
386 fb->fb.var.lower_margin = fb->panel->mode.lower_margin;
387 fb->fb.var.hsync_len = fb->panel->mode.hsync_len;
388 fb->fb.var.vsync_len = fb->panel->mode.vsync_len;
389 fb->fb.var.sync = fb->panel->mode.sync;
390 fb->fb.var.vmode = fb->panel->mode.vmode;
391 fb->fb.var.activate = FB_ACTIVATE_NOW;
392 fb->fb.var.nonstd = 0;
393 fb->fb.var.height = fb->panel->height;
394 fb->fb.var.width = fb->panel->width;
395 fb->fb.var.accel_flags = 0;
397 fb->fb.monspecs.hfmin = 0;
398 fb->fb.monspecs.hfmax = 100000;
399 fb->fb.monspecs.vfmin = 0;
400 fb->fb.monspecs.vfmax = 400;
401 fb->fb.monspecs.dclkmin = 1000000;
402 fb->fb.monspecs.dclkmax = 100000000;
405 * Make sure that the bitfields are set appropriately.
407 clcdfb_set_bitfields(fb, &fb->fb.var);
410 * Allocate colourmap.
412 fb_alloc_cmap(&fb->fb.cmap, 256, 0);
415 * Ensure interrupts are disabled.
417 writel(0, fb->regs + CLCD_IENB);
419 fb_set_var(&fb->fb, &fb->fb.var);
421 printk(KERN_INFO "CLCD: %s hardware, %s display\n",
422 fb->board->name, fb->panel->mode.name);
424 ret = register_framebuffer(&fb->fb);
428 printk(KERN_ERR "CLCD: cannot register framebuffer (%d)\n", ret);
439 static int clcdfb_probe(struct amba_device *dev, void *id)
441 struct clcd_board *board = dev->dev.platform_data;
448 ret = amba_request_regions(dev, NULL);
450 printk(KERN_ERR "CLCD: unable to reserve regs region\n");
454 fb = (struct clcd_fb *) kmalloc(sizeof(struct clcd_fb), GFP_KERNEL);
456 printk(KERN_INFO "CLCD: could not allocate new clcd_fb struct\n");
460 memset(fb, 0, sizeof(struct clcd_fb));
465 ret = fb->board->setup(fb);
469 ret = clcdfb_register(fb);
471 amba_set_drvdata(dev, fb);
475 fb->board->remove(fb);
479 amba_release_regions(dev);
484 static int clcdfb_remove(struct amba_device *dev)
486 struct clcd_fb *fb = amba_get_drvdata(dev);
488 amba_set_drvdata(dev, NULL);
491 unregister_framebuffer(&fb->fb);
496 fb->board->remove(fb);
500 amba_release_regions(dev);
505 static struct amba_id clcdfb_id_table[] = {
513 static struct amba_driver clcd_driver = {
515 .name = "clcd-pl110",
517 .probe = clcdfb_probe,
518 .remove = clcdfb_remove,
519 .id_table = clcdfb_id_table,
522 int __init amba_clcdfb_init(void)
524 if (fb_get_options("ambafb", NULL))
527 return amba_driver_register(&clcd_driver);
530 module_init(amba_clcdfb_init);
532 static void __exit amba_clcdfb_exit(void)
534 amba_driver_unregister(&clcd_driver);
537 module_exit(amba_clcdfb_exit);
539 MODULE_DESCRIPTION("ARM PrimeCell PL110 CLCD core driver");
540 MODULE_LICENSE("GPL");