git.oblomov.eu Git - linux-2.6/blob - drivers/scsi/qla2xxx/qla_sup.c

   1 /*
   2  * QLogic Fibre Channel HBA Driver
   3  * Copyright (c)  2003-2008 QLogic Corporation
   4  *
   5  * See LICENSE.qla2xxx for copyright and licensing details.
   6  */
   7 #include "qla_def.h"
   8
   9 #include <linux/delay.h>
  10 #include <linux/vmalloc.h>
  11 #include <asm/uaccess.h>
  12
  13 static uint16_t qla2x00_nvram_request(scsi_qla_host_t *, uint32_t);
  14 static void qla2x00_nv_deselect(scsi_qla_host_t *);
  15 static void qla2x00_nv_write(scsi_qla_host_t *, uint16_t);
  16
  17 /*
  18  * NVRAM support routines
  19  */
  20
  21 /**
  22  * qla2x00_lock_nvram_access() -
  23  * @ha: HA context
  24  */
  25 static void
  26 qla2x00_lock_nvram_access(scsi_qla_host_t *ha)
  27 {
  28         uint16_t data;
  29         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
  30
  31         if (!IS_QLA2100(ha) && !IS_QLA2200(ha) && !IS_QLA2300(ha)) {
  32                 data = RD_REG_WORD(&reg->nvram);
  33                 while (data & NVR_BUSY) {
  34                         udelay(100);
  35                         data = RD_REG_WORD(&reg->nvram);
  36                 }
  37
  38                 /* Lock resource */
  39                 WRT_REG_WORD(&reg->u.isp2300.host_semaphore, 0x1);
  40                 RD_REG_WORD(&reg->u.isp2300.host_semaphore);
  41                 udelay(5);
  42                 data = RD_REG_WORD(&reg->u.isp2300.host_semaphore);
  43                 while ((data & BIT_0) == 0) {
  44                         /* Lock failed */
  45                         udelay(100);
  46                         WRT_REG_WORD(&reg->u.isp2300.host_semaphore, 0x1);
  47                         RD_REG_WORD(&reg->u.isp2300.host_semaphore);
  48                         udelay(5);
  49                         data = RD_REG_WORD(&reg->u.isp2300.host_semaphore);
  50                 }
  51         }
  52 }
  53
  54 /**
  55  * qla2x00_unlock_nvram_access() -
  56  * @ha: HA context
  57  */
  58 static void
  59 qla2x00_unlock_nvram_access(scsi_qla_host_t *ha)
  60 {
  61         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
  62
  63         if (!IS_QLA2100(ha) && !IS_QLA2200(ha) && !IS_QLA2300(ha)) {
  64                 WRT_REG_WORD(&reg->u.isp2300.host_semaphore, 0);
  65                 RD_REG_WORD(&reg->u.isp2300.host_semaphore);
  66         }
  67 }
  68
  69 /**
  70  * qla2x00_get_nvram_word() - Calculates word position in NVRAM and calls the
  71  *      request routine to get the word from NVRAM.
  72  * @ha: HA context
  73  * @addr: Address in NVRAM to read
  74  *
  75  * Returns the word read from nvram @addr.
  76  */
  77 static uint16_t
  78 qla2x00_get_nvram_word(scsi_qla_host_t *ha, uint32_t addr)
  79 {
  80         uint16_t        data;
  81         uint32_t        nv_cmd;
  82
  83         nv_cmd = addr << 16;
  84         nv_cmd |= NV_READ_OP;
  85         data = qla2x00_nvram_request(ha, nv_cmd);
  86
  87         return (data);
  88 }
  89
  90 /**
  91  * qla2x00_write_nvram_word() - Write NVRAM data.
  92  * @ha: HA context
  93  * @addr: Address in NVRAM to write
  94  * @data: word to program
  95  */
  96 static void
  97 qla2x00_write_nvram_word(scsi_qla_host_t *ha, uint32_t addr, uint16_t data)
  98 {
  99         int count;
 100         uint16_t word;
 101         uint32_t nv_cmd, wait_cnt;
 102         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
 103
 104         qla2x00_nv_write(ha, NVR_DATA_OUT);
 105         qla2x00_nv_write(ha, 0);
 106         qla2x00_nv_write(ha, 0);
 107
 108         for (word = 0; word < 8; word++)
 109                 qla2x00_nv_write(ha, NVR_DATA_OUT);
 110
 111         qla2x00_nv_deselect(ha);
 112
 113         /* Write data */
 114         nv_cmd = (addr << 16) | NV_WRITE_OP;
 115         nv_cmd |= data;
 116         nv_cmd <<= 5;
 117         for (count = 0; count < 27; count++) {
 118                 if (nv_cmd & BIT_31)
 119                         qla2x00_nv_write(ha, NVR_DATA_OUT);
 120                 else
 121                         qla2x00_nv_write(ha, 0);
 122
 123                 nv_cmd <<= 1;
 124         }
 125
 126         qla2x00_nv_deselect(ha);
 127
 128         /* Wait for NVRAM to become ready */
 129         WRT_REG_WORD(&reg->nvram, NVR_SELECT);
 130         RD_REG_WORD(&reg->nvram);               /* PCI Posting. */
 131         wait_cnt = NVR_WAIT_CNT;
 132         do {
 133                 if (!--wait_cnt) {
 134                         DEBUG9_10(printk("%s(%ld): NVRAM didn't go ready...\n",
 135                             __func__, ha->host_no));
 136                         break;
 137                 }
 138                 NVRAM_DELAY();
 139                 word = RD_REG_WORD(&reg->nvram);
 140         } while ((word & NVR_DATA_IN) == 0);
 141
 142         qla2x00_nv_deselect(ha);
 143
 144         /* Disable writes */
 145         qla2x00_nv_write(ha, NVR_DATA_OUT);
 146         for (count = 0; count < 10; count++)
 147                 qla2x00_nv_write(ha, 0);
 148
 149         qla2x00_nv_deselect(ha);
 150 }
 151
 152 static int
 153 qla2x00_write_nvram_word_tmo(scsi_qla_host_t *ha, uint32_t addr, uint16_t data,
 154     uint32_t tmo)
 155 {
 156         int ret, count;
 157         uint16_t word;
 158         uint32_t nv_cmd;
 159         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
 160
 161         ret = QLA_SUCCESS;
 162
 163         qla2x00_nv_write(ha, NVR_DATA_OUT);
 164         qla2x00_nv_write(ha, 0);
 165         qla2x00_nv_write(ha, 0);
 166
 167         for (word = 0; word < 8; word++)
 168                 qla2x00_nv_write(ha, NVR_DATA_OUT);
 169
 170         qla2x00_nv_deselect(ha);
 171
 172         /* Write data */
 173         nv_cmd = (addr << 16) | NV_WRITE_OP;
 174         nv_cmd |= data;
 175         nv_cmd <<= 5;
 176         for (count = 0; count < 27; count++) {
 177                 if (nv_cmd & BIT_31)
 178                         qla2x00_nv_write(ha, NVR_DATA_OUT);
 179                 else
 180                         qla2x00_nv_write(ha, 0);
 181
 182                 nv_cmd <<= 1;
 183         }
 184
 185         qla2x00_nv_deselect(ha);
 186
 187         /* Wait for NVRAM to become ready */
 188         WRT_REG_WORD(&reg->nvram, NVR_SELECT);
 189         RD_REG_WORD(&reg->nvram);               /* PCI Posting. */
 190         do {
 191                 NVRAM_DELAY();
 192                 word = RD_REG_WORD(&reg->nvram);
 193                 if (!--tmo) {
 194                         ret = QLA_FUNCTION_FAILED;
 195                         break;
 196                 }
 197         } while ((word & NVR_DATA_IN) == 0);
 198
 199         qla2x00_nv_deselect(ha);
 200
 201         /* Disable writes */
 202         qla2x00_nv_write(ha, NVR_DATA_OUT);
 203         for (count = 0; count < 10; count++)
 204                 qla2x00_nv_write(ha, 0);
 205
 206         qla2x00_nv_deselect(ha);
 207
 208         return ret;
 209 }
 210
 211 /**
 212  * qla2x00_nvram_request() - Sends read command to NVRAM and gets data from
 213  *      NVRAM.
 214  * @ha: HA context
 215  * @nv_cmd: NVRAM command
 216  *
 217  * Bit definitions for NVRAM command:
 218  *
 219  *      Bit 26     = start bit
 220  *      Bit 25, 24 = opcode
 221  *      Bit 23-16  = address
 222  *      Bit 15-0   = write data
 223  *
 224  * Returns the word read from nvram @addr.
 225  */
 226 static uint16_t
 227 qla2x00_nvram_request(scsi_qla_host_t *ha, uint32_t nv_cmd)
 228 {
 229         uint8_t         cnt;
 230         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
 231         uint16_t        data = 0;
 232         uint16_t        reg_data;
 233
 234         /* Send command to NVRAM. */
 235         nv_cmd <<= 5;
 236         for (cnt = 0; cnt < 11; cnt++) {
 237                 if (nv_cmd & BIT_31)
 238                         qla2x00_nv_write(ha, NVR_DATA_OUT);
 239                 else
 240                         qla2x00_nv_write(ha, 0);
 241                 nv_cmd <<= 1;
 242         }
 243
 244         /* Read data from NVRAM. */
 245         for (cnt = 0; cnt < 16; cnt++) {
 246                 WRT_REG_WORD(&reg->nvram, NVR_SELECT | NVR_CLOCK);
 247                 RD_REG_WORD(&reg->nvram);       /* PCI Posting. */
 248                 NVRAM_DELAY();
 249                 data <<= 1;
 250                 reg_data = RD_REG_WORD(&reg->nvram);
 251                 if (reg_data & NVR_DATA_IN)
 252                         data |= BIT_0;
 253                 WRT_REG_WORD(&reg->nvram, NVR_SELECT);
 254                 RD_REG_WORD(&reg->nvram);       /* PCI Posting. */
 255                 NVRAM_DELAY();
 256         }
 257
 258         /* Deselect chip. */
 259         WRT_REG_WORD(&reg->nvram, NVR_DESELECT);
 260         RD_REG_WORD(&reg->nvram);               /* PCI Posting. */
 261         NVRAM_DELAY();
 262
 263         return (data);
 264 }
 265
 266 /**
 267  * qla2x00_nv_write() - Clean NVRAM operations.
 268  * @ha: HA context
 269  */
 270 static void
 271 qla2x00_nv_deselect(scsi_qla_host_t *ha)
 272 {
 273         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
 274
 275         WRT_REG_WORD(&reg->nvram, NVR_DESELECT);
 276         RD_REG_WORD(&reg->nvram);               /* PCI Posting. */
 277         NVRAM_DELAY();
 278 }
 279
 280 /**
 281  * qla2x00_nv_write() - Prepare for NVRAM read/write operation.
 282  * @ha: HA context
 283  * @data: Serial interface selector
 284  */
 285 static void
 286 qla2x00_nv_write(scsi_qla_host_t *ha, uint16_t data)
 287 {
 288         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
 289
 290         WRT_REG_WORD(&reg->nvram, data | NVR_SELECT | NVR_WRT_ENABLE);
 291         RD_REG_WORD(&reg->nvram);               /* PCI Posting. */
 292         NVRAM_DELAY();
 293         WRT_REG_WORD(&reg->nvram, data | NVR_SELECT| NVR_CLOCK |
 294             NVR_WRT_ENABLE);
 295         RD_REG_WORD(&reg->nvram);               /* PCI Posting. */
 296         NVRAM_DELAY();
 297         WRT_REG_WORD(&reg->nvram, data | NVR_SELECT | NVR_WRT_ENABLE);
 298         RD_REG_WORD(&reg->nvram);               /* PCI Posting. */
 299         NVRAM_DELAY();
 300 }
 301
 302 /**
 303  * qla2x00_clear_nvram_protection() -
 304  * @ha: HA context
 305  */
 306 static int
 307 qla2x00_clear_nvram_protection(scsi_qla_host_t *ha)
 308 {
 309         int ret, stat;
 310         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
 311         uint32_t word, wait_cnt;
 312         uint16_t wprot, wprot_old;
 313
 314         /* Clear NVRAM write protection. */
 315         ret = QLA_FUNCTION_FAILED;
 316
 317         wprot_old = cpu_to_le16(qla2x00_get_nvram_word(ha, ha->nvram_base));
 318         stat = qla2x00_write_nvram_word_tmo(ha, ha->nvram_base,
 319             __constant_cpu_to_le16(0x1234), 100000);
 320         wprot = cpu_to_le16(qla2x00_get_nvram_word(ha, ha->nvram_base));
 321         if (stat != QLA_SUCCESS || wprot != 0x1234) {
 322                 /* Write enable. */
 323                 qla2x00_nv_write(ha, NVR_DATA_OUT);
 324                 qla2x00_nv_write(ha, 0);
 325                 qla2x00_nv_write(ha, 0);
 326                 for (word = 0; word < 8; word++)
 327                         qla2x00_nv_write(ha, NVR_DATA_OUT);
 328
 329                 qla2x00_nv_deselect(ha);
 330
 331                 /* Enable protection register. */
 332                 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
 333                 qla2x00_nv_write(ha, NVR_PR_ENABLE);
 334                 qla2x00_nv_write(ha, NVR_PR_ENABLE);
 335                 for (word = 0; word < 8; word++)
 336                         qla2x00_nv_write(ha, NVR_DATA_OUT | NVR_PR_ENABLE);
 337
 338                 qla2x00_nv_deselect(ha);
 339
 340                 /* Clear protection register (ffff is cleared). */
 341                 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
 342                 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
 343                 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
 344                 for (word = 0; word < 8; word++)
 345                         qla2x00_nv_write(ha, NVR_DATA_OUT | NVR_PR_ENABLE);
 346
 347                 qla2x00_nv_deselect(ha);
 348
 349                 /* Wait for NVRAM to become ready. */
 350                 WRT_REG_WORD(&reg->nvram, NVR_SELECT);
 351                 RD_REG_WORD(&reg->nvram);       /* PCI Posting. */
 352                 wait_cnt = NVR_WAIT_CNT;
 353                 do {
 354                         if (!--wait_cnt) {
 355                                 DEBUG9_10(printk("%s(%ld): NVRAM didn't go "
 356                                     "ready...\n", __func__,
 357                                     ha->host_no));
 358                                 break;
 359                         }
 360                         NVRAM_DELAY();
 361                         word = RD_REG_WORD(&reg->nvram);
 362                 } while ((word & NVR_DATA_IN) == 0);
 363
 364                 if (wait_cnt)
 365                         ret = QLA_SUCCESS;
 366         } else
 367                 qla2x00_write_nvram_word(ha, ha->nvram_base, wprot_old);
 368
 369         return ret;
 370 }
 371
 372 static void
 373 qla2x00_set_nvram_protection(scsi_qla_host_t *ha, int stat)
 374 {
 375         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
 376         uint32_t word, wait_cnt;
 377
 378         if (stat != QLA_SUCCESS)
 379                 return;
 380
 381         /* Set NVRAM write protection. */
 382         /* Write enable. */
 383         qla2x00_nv_write(ha, NVR_DATA_OUT);
 384         qla2x00_nv_write(ha, 0);
 385         qla2x00_nv_write(ha, 0);
 386         for (word = 0; word < 8; word++)
 387                 qla2x00_nv_write(ha, NVR_DATA_OUT);
 388
 389         qla2x00_nv_deselect(ha);
 390
 391         /* Enable protection register. */
 392         qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
 393         qla2x00_nv_write(ha, NVR_PR_ENABLE);
 394         qla2x00_nv_write(ha, NVR_PR_ENABLE);
 395         for (word = 0; word < 8; word++)
 396                 qla2x00_nv_write(ha, NVR_DATA_OUT | NVR_PR_ENABLE);
 397
 398         qla2x00_nv_deselect(ha);
 399
 400         /* Enable protection register. */
 401         qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
 402         qla2x00_nv_write(ha, NVR_PR_ENABLE);
 403         qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
 404         for (word = 0; word < 8; word++)
 405                 qla2x00_nv_write(ha, NVR_PR_ENABLE);
 406
 407         qla2x00_nv_deselect(ha);
 408
 409         /* Wait for NVRAM to become ready. */
 410         WRT_REG_WORD(&reg->nvram, NVR_SELECT);
 411         RD_REG_WORD(&reg->nvram);               /* PCI Posting. */
 412         wait_cnt = NVR_WAIT_CNT;
 413         do {
 414                 if (!--wait_cnt) {
 415                         DEBUG9_10(printk("%s(%ld): NVRAM didn't go ready...\n",
 416                             __func__, ha->host_no));
 417                         break;
 418                 }
 419                 NVRAM_DELAY();
 420                 word = RD_REG_WORD(&reg->nvram);
 421         } while ((word & NVR_DATA_IN) == 0);
 422 }
 423
 424
 425 /*****************************************************************************/
 426 /* Flash Manipulation Routines                                               */
 427 /*****************************************************************************/
 428
 429 #define OPTROM_BURST_SIZE       0x1000
 430 #define OPTROM_BURST_DWORDS     (OPTROM_BURST_SIZE / 4)
 431
 432 static inline uint32_t
 433 flash_conf_to_access_addr(uint32_t faddr)
 434 {
 435         return FARX_ACCESS_FLASH_CONF | faddr;
 436 }
 437
 438 static inline uint32_t
 439 flash_data_to_access_addr(uint32_t faddr)
 440 {
 441         return FARX_ACCESS_FLASH_DATA | faddr;
 442 }
 443
 444 static inline uint32_t
 445 nvram_conf_to_access_addr(uint32_t naddr)
 446 {
 447         return FARX_ACCESS_NVRAM_CONF | naddr;
 448 }
 449
 450 static inline uint32_t
 451 nvram_data_to_access_addr(uint32_t naddr)
 452 {
 453         return FARX_ACCESS_NVRAM_DATA | naddr;
 454 }
 455
 456 static uint32_t
 457 qla24xx_read_flash_dword(scsi_qla_host_t *ha, uint32_t addr)
 458 {
 459         int rval;
 460         uint32_t cnt, data;
 461         struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
 462
 463         WRT_REG_DWORD(&reg->flash_addr, addr & ~FARX_DATA_FLAG);
 464         /* Wait for READ cycle to complete. */
 465         rval = QLA_SUCCESS;
 466         for (cnt = 3000;
 467             (RD_REG_DWORD(&reg->flash_addr) & FARX_DATA_FLAG) == 0 &&
 468             rval == QLA_SUCCESS; cnt--) {
 469                 if (cnt)
 470                         udelay(10);
 471                 else
 472                         rval = QLA_FUNCTION_TIMEOUT;
 473                 cond_resched();
 474         }
 475
 476         /* TODO: What happens if we time out? */
 477         data = 0xDEADDEAD;
 478         if (rval == QLA_SUCCESS)
 479                 data = RD_REG_DWORD(&reg->flash_data);
 480
 481         return data;
 482 }
 483
 484 uint32_t *
 485 qla24xx_read_flash_data(scsi_qla_host_t *ha, uint32_t *dwptr, uint32_t faddr,
 486     uint32_t dwords)
 487 {
 488         uint32_t i;
 489
 490         /* Dword reads to flash. */
 491         for (i = 0; i < dwords; i++, faddr++)
 492                 dwptr[i] = cpu_to_le32(qla24xx_read_flash_dword(ha,
 493                     flash_data_to_access_addr(faddr)));
 494
 495         return dwptr;
 496 }
 497
 498 static int
 499 qla24xx_write_flash_dword(scsi_qla_host_t *ha, uint32_t addr, uint32_t data)
 500 {
 501         int rval;
 502         uint32_t cnt;
 503         struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
 504
 505         WRT_REG_DWORD(&reg->flash_data, data);
 506         RD_REG_DWORD(&reg->flash_data);         /* PCI Posting. */
 507         WRT_REG_DWORD(&reg->flash_addr, addr | FARX_DATA_FLAG);
 508         /* Wait for Write cycle to complete. */
 509         rval = QLA_SUCCESS;
 510         for (cnt = 500000; (RD_REG_DWORD(&reg->flash_addr) & FARX_DATA_FLAG) &&
 511             rval == QLA_SUCCESS; cnt--) {
 512                 if (cnt)
 513                         udelay(10);
 514                 else
 515                         rval = QLA_FUNCTION_TIMEOUT;
 516                 cond_resched();
 517         }
 518         return rval;
 519 }
 520
 521 static void
 522 qla24xx_get_flash_manufacturer(scsi_qla_host_t *ha, uint8_t *man_id,
 523     uint8_t *flash_id)
 524 {
 525         uint32_t ids;
 526
 527         ids = qla24xx_read_flash_dword(ha, flash_data_to_access_addr(0xd03ab));
 528         *man_id = LSB(ids);
 529         *flash_id = MSB(ids);
 530
 531         /* Check if man_id and flash_id are valid. */
 532         if (ids != 0xDEADDEAD && (*man_id == 0 || *flash_id == 0)) {
 533                 /* Read information using 0x9f opcode
 534                  * Device ID, Mfg ID would be read in the format:
 535                  *   <Ext Dev Info><Device ID Part2><Device ID Part 1><Mfg ID>
 536                  * Example: ATMEL 0x00 01 45 1F
 537                  * Extract MFG and Dev ID from last two bytes.
 538                  */
 539                 ids = qla24xx_read_flash_dword(ha,
 540                     flash_data_to_access_addr(0xd009f));
 541                 *man_id = LSB(ids);
 542                 *flash_id = MSB(ids);
 543         }
 544 }
 545
 546 void
 547 qla2xxx_get_flash_info(scsi_qla_host_t *ha)
 548 {
 549 #define FLASH_BLK_SIZE_32K      0x8000
 550 #define FLASH_BLK_SIZE_64K      0x10000
 551         uint16_t cnt, chksum;
 552         uint16_t *wptr;
 553         struct qla_fdt_layout *fdt;
 554         uint8_t man_id, flash_id;
 555
 556         if (!IS_QLA24XX_TYPE(ha) && !IS_QLA25XX(ha))
 557                 return;
 558
 559         wptr = (uint16_t *)ha->request_ring;
 560         fdt = (struct qla_fdt_layout *)ha->request_ring;
 561         ha->isp_ops->read_optrom(ha, (uint8_t *)ha->request_ring,
 562             FA_FLASH_DESCR_ADDR << 2, OPTROM_BURST_SIZE);
 563         if (*wptr == __constant_cpu_to_le16(0xffff))
 564                 goto no_flash_data;
 565         if (fdt->sig[0] != 'Q' || fdt->sig[1] != 'L' || fdt->sig[2] != 'I' ||
 566             fdt->sig[3] != 'D')
 567                 goto no_flash_data;
 568
 569         for (cnt = 0, chksum = 0; cnt < sizeof(struct qla_fdt_layout) >> 1;
 570             cnt++)
 571                 chksum += le16_to_cpu(*wptr++);
 572         if (chksum) {
 573                 DEBUG2(qla_printk(KERN_INFO, ha, "Inconsistent FDT detected: "
 574                     "checksum=0x%x id=%c version=0x%x.\n", chksum, fdt->sig[0],
 575                     le16_to_cpu(fdt->version)));
 576                 DEBUG9(qla2x00_dump_buffer((uint8_t *)fdt, sizeof(*fdt)));
 577                 goto no_flash_data;
 578         }
 579
 580         ha->fdt_odd_index = le16_to_cpu(fdt->man_id) == 0x1f;
 581         ha->fdt_wrt_disable = fdt->wrt_disable_bits;
 582         ha->fdt_erase_cmd = flash_conf_to_access_addr(0x0300 | fdt->erase_cmd);
 583         ha->fdt_block_size = le32_to_cpu(fdt->block_size);
 584         if (fdt->unprotect_sec_cmd) {
 585                 ha->fdt_unprotect_sec_cmd = flash_conf_to_access_addr(0x0300 |
 586                     fdt->unprotect_sec_cmd);
 587                 ha->fdt_protect_sec_cmd = fdt->protect_sec_cmd ?
 588                     flash_conf_to_access_addr(0x0300 | fdt->protect_sec_cmd):
 589                     flash_conf_to_access_addr(0x0336);
 590         }
 591
 592         DEBUG2(qla_printk(KERN_DEBUG, ha, "Flash[FDT]: (0x%x/0x%x) erase=0x%x "
 593             "pro=%x upro=%x idx=%d wrtd=0x%x blk=0x%x.\n",
 594             le16_to_cpu(fdt->man_id), le16_to_cpu(fdt->id), ha->fdt_erase_cmd,
 595             ha->fdt_protect_sec_cmd, ha->fdt_unprotect_sec_cmd,
 596             ha->fdt_odd_index, ha->fdt_wrt_disable, ha->fdt_block_size));
 597         return;
 598
 599 no_flash_data:
 600         qla24xx_get_flash_manufacturer(ha, &man_id, &flash_id);
 601         ha->fdt_wrt_disable = 0x9c;
 602         ha->fdt_erase_cmd = flash_conf_to_access_addr(0x03d8);
 603         switch (man_id) {
 604         case 0xbf: /* STT flash. */
 605                 if (flash_id == 0x8e)
 606                         ha->fdt_block_size = FLASH_BLK_SIZE_64K;
 607                 else
 608                         ha->fdt_block_size = FLASH_BLK_SIZE_32K;
 609
 610                 if (flash_id == 0x80)
 611                         ha->fdt_erase_cmd = flash_conf_to_access_addr(0x0352);
 612                 break;
 613         case 0x13: /* ST M25P80. */
 614                 ha->fdt_block_size = FLASH_BLK_SIZE_64K;
 615                 break;
 616         case 0x1f: /* Atmel 26DF081A. */
 617                 ha->fdt_odd_index = 1;
 618                 ha->fdt_block_size = FLASH_BLK_SIZE_64K;
 619                 ha->fdt_erase_cmd = flash_conf_to_access_addr(0x0320);
 620                 ha->fdt_unprotect_sec_cmd = flash_conf_to_access_addr(0x0339);
 621                 ha->fdt_protect_sec_cmd = flash_conf_to_access_addr(0x0336);
 622                 break;
 623         default:
 624                 /* Default to 64 kb sector size. */
 625                 ha->fdt_block_size = FLASH_BLK_SIZE_64K;
 626                 break;
 627         }
 628
 629         DEBUG2(qla_printk(KERN_DEBUG, ha, "Flash[MID]: (0x%x/0x%x) erase=0x%x "
 630             "pro=%x upro=%x idx=%d wrtd=0x%x blk=0x%x.\n", man_id, flash_id,
 631             ha->fdt_erase_cmd, ha->fdt_protect_sec_cmd,
 632             ha->fdt_unprotect_sec_cmd, ha->fdt_odd_index, ha->fdt_wrt_disable,
 633             ha->fdt_block_size));
 634 }
 635
 636 static void
 637 qla24xx_unprotect_flash(scsi_qla_host_t *ha)
 638 {
 639         struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
 640
 641         /* Enable flash write. */
 642         WRT_REG_DWORD(&reg->ctrl_status,
 643             RD_REG_DWORD(&reg->ctrl_status) | CSRX_FLASH_ENABLE);
 644         RD_REG_DWORD(&reg->ctrl_status);        /* PCI Posting. */
 645
 646         if (!ha->fdt_wrt_disable)
 647                 return;
 648
 649         /* Disable flash write-protection. */
 650         qla24xx_write_flash_dword(ha, flash_conf_to_access_addr(0x101), 0);
 651         /* Some flash parts need an additional zero-write to clear bits.*/
 652         qla24xx_write_flash_dword(ha, flash_conf_to_access_addr(0x101), 0);
 653 }
 654
 655 static void
 656 qla24xx_protect_flash(scsi_qla_host_t *ha)
 657 {
 658         uint32_t cnt;
 659         struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
 660
 661         if (!ha->fdt_wrt_disable)
 662                 goto skip_wrt_protect;
 663
 664         /* Enable flash write-protection and wait for completion. */
 665         qla24xx_write_flash_dword(ha, flash_conf_to_access_addr(0x101),
 666             ha->fdt_wrt_disable);
 667         for (cnt = 300; cnt &&
 668             qla24xx_read_flash_dword(ha,
 669                     flash_conf_to_access_addr(0x005)) & BIT_0;
 670             cnt--) {
 671                 udelay(10);
 672         }
 673
 674 skip_wrt_protect:
 675         /* Disable flash write. */
 676         WRT_REG_DWORD(&reg->ctrl_status,
 677             RD_REG_DWORD(&reg->ctrl_status) & ~CSRX_FLASH_ENABLE);
 678         RD_REG_DWORD(&reg->ctrl_status);        /* PCI Posting. */
 679 }
 680
 681 static int
 682 qla24xx_write_flash_data(scsi_qla_host_t *ha, uint32_t *dwptr, uint32_t faddr,
 683     uint32_t dwords)
 684 {
 685         int ret;
 686         uint32_t liter, miter;
 687         uint32_t sec_mask, rest_addr;
 688         uint32_t fdata, findex;
 689         dma_addr_t optrom_dma;
 690         void *optrom = NULL;
 691         uint32_t *s, *d;
 692
 693         ret = QLA_SUCCESS;
 694
 695         /* Prepare burst-capable write on supported ISPs. */
 696         if (IS_QLA25XX(ha) && !(faddr & 0xfff) &&
 697             dwords > OPTROM_BURST_DWORDS) {
 698                 optrom = dma_alloc_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE,
 699                     &optrom_dma, GFP_KERNEL);
 700                 if (!optrom) {
 701                         qla_printk(KERN_DEBUG, ha,
 702                             "Unable to allocate memory for optrom burst write "
 703                             "(%x KB).\n", OPTROM_BURST_SIZE / 1024);
 704                 }
 705         }
 706
 707         rest_addr = (ha->fdt_block_size >> 2) - 1;
 708         sec_mask = 0x80000 - (ha->fdt_block_size >> 2);
 709
 710         qla24xx_unprotect_flash(ha);
 711
 712         for (liter = 0; liter < dwords; liter++, faddr++, dwptr++) {
 713                 if (ha->fdt_odd_index) {
 714                         findex = faddr << 2;
 715                         fdata = findex & sec_mask;
 716                 } else {
 717                         findex = faddr;
 718                         fdata = (findex & sec_mask) << 2;
 719                 }
 720
 721                 /* Are we at the beginning of a sector? */
 722                 if ((findex & rest_addr) == 0) {
 723                         /* Do sector unprotect. */
 724                         if (ha->fdt_unprotect_sec_cmd)
 725                                 qla24xx_write_flash_dword(ha,
 726                                     ha->fdt_unprotect_sec_cmd,
 727                                     (fdata & 0xff00) | ((fdata << 16) &
 728                                     0xff0000) | ((fdata >> 16) & 0xff));
 729                         ret = qla24xx_write_flash_dword(ha, ha->fdt_erase_cmd,
 730                             (fdata & 0xff00) |((fdata << 16) &
 731                             0xff0000) | ((fdata >> 16) & 0xff));
 732                         if (ret != QLA_SUCCESS) {
 733                                 DEBUG9(printk("%s(%ld) Unable to flash "
 734                                     "sector: address=%x.\n", __func__,
 735                                     ha->host_no, faddr));
 736                                 break;
 737                         }
 738                 }
 739
 740                 /* Go with burst-write. */
 741                 if (optrom && (liter + OPTROM_BURST_DWORDS) <= dwords) {
 742                         /* Copy data to DMA'ble buffer. */
 743                         for (miter = 0, s = optrom, d = dwptr;
 744                             miter < OPTROM_BURST_DWORDS; miter++, s++, d++)
 745                                 *s = cpu_to_le32(*d);
 746
 747                         ret = qla2x00_load_ram(ha, optrom_dma,
 748                             flash_data_to_access_addr(faddr),
 749                             OPTROM_BURST_DWORDS);
 750                         if (ret != QLA_SUCCESS) {
 751                                 qla_printk(KERN_WARNING, ha,
 752                                     "Unable to burst-write optrom segment "
 753                                     "(%x/%x/%llx).\n", ret,
 754                                     flash_data_to_access_addr(faddr),
 755                                     (unsigned long long)optrom_dma);
 756                                 qla_printk(KERN_WARNING, ha,
 757                                     "Reverting to slow-write.\n");
 758
 759                                 dma_free_coherent(&ha->pdev->dev,
 760                                     OPTROM_BURST_SIZE, optrom, optrom_dma);
 761                                 optrom = NULL;
 762                         } else {
 763                                 liter += OPTROM_BURST_DWORDS - 1;
 764                                 faddr += OPTROM_BURST_DWORDS - 1;
 765                                 dwptr += OPTROM_BURST_DWORDS - 1;
 766                                 continue;
 767                         }
 768                 }
 769
 770                 ret = qla24xx_write_flash_dword(ha,
 771                     flash_data_to_access_addr(faddr), cpu_to_le32(*dwptr));
 772                 if (ret != QLA_SUCCESS) {
 773                         DEBUG9(printk("%s(%ld) Unable to program flash "
 774                             "address=%x data=%x.\n", __func__,
 775                             ha->host_no, faddr, *dwptr));
 776                         break;
 777                 }
 778
 779                 /* Do sector protect. */
 780                 if (ha->fdt_unprotect_sec_cmd &&
 781                     ((faddr & rest_addr) == rest_addr))
 782                         qla24xx_write_flash_dword(ha,
 783                             ha->fdt_protect_sec_cmd,
 784                             (fdata & 0xff00) | ((fdata << 16) &
 785                             0xff0000) | ((fdata >> 16) & 0xff));
 786         }
 787
 788         qla24xx_protect_flash(ha);
 789
 790         if (optrom)
 791                 dma_free_coherent(&ha->pdev->dev,
 792                     OPTROM_BURST_SIZE, optrom, optrom_dma);
 793
 794         return ret;
 795 }
 796
 797 uint8_t *
 798 qla2x00_read_nvram_data(scsi_qla_host_t *ha, uint8_t *buf, uint32_t naddr,
 799     uint32_t bytes)
 800 {
 801         uint32_t i;
 802         uint16_t *wptr;
 803
 804         /* Word reads to NVRAM via registers. */
 805         wptr = (uint16_t *)buf;
 806         qla2x00_lock_nvram_access(ha);
 807         for (i = 0; i < bytes >> 1; i++, naddr++)
 808                 wptr[i] = cpu_to_le16(qla2x00_get_nvram_word(ha,
 809                     naddr));
 810         qla2x00_unlock_nvram_access(ha);
 811
 812         return buf;
 813 }
 814
 815 uint8_t *
 816 qla24xx_read_nvram_data(scsi_qla_host_t *ha, uint8_t *buf, uint32_t naddr,
 817     uint32_t bytes)
 818 {
 819         uint32_t i;
 820         uint32_t *dwptr;
 821
 822         /* Dword reads to flash. */
 823         dwptr = (uint32_t *)buf;
 824         for (i = 0; i < bytes >> 2; i++, naddr++)
 825                 dwptr[i] = cpu_to_le32(qla24xx_read_flash_dword(ha,
 826                     nvram_data_to_access_addr(naddr)));
 827
 828         return buf;
 829 }
 830
 831 int
 832 qla2x00_write_nvram_data(scsi_qla_host_t *ha, uint8_t *buf, uint32_t naddr,
 833     uint32_t bytes)
 834 {
 835         int ret, stat;
 836         uint32_t i;
 837         uint16_t *wptr;
 838         unsigned long flags;
 839
 840         ret = QLA_SUCCESS;
 841
 842         spin_lock_irqsave(&ha->hardware_lock, flags);
 843         qla2x00_lock_nvram_access(ha);
 844
 845         /* Disable NVRAM write-protection. */
 846         stat = qla2x00_clear_nvram_protection(ha);
 847
 848         wptr = (uint16_t *)buf;
 849         for (i = 0; i < bytes >> 1; i++, naddr++) {
 850                 qla2x00_write_nvram_word(ha, naddr,
 851                     cpu_to_le16(*wptr));
 852                 wptr++;
 853         }
 854
 855         /* Enable NVRAM write-protection. */
 856         qla2x00_set_nvram_protection(ha, stat);
 857
 858         qla2x00_unlock_nvram_access(ha);
 859         spin_unlock_irqrestore(&ha->hardware_lock, flags);
 860
 861         return ret;
 862 }
 863
 864 int
 865 qla24xx_write_nvram_data(scsi_qla_host_t *ha, uint8_t *buf, uint32_t naddr,
 866     uint32_t bytes)
 867 {
 868         int ret;
 869         uint32_t i;
 870         uint32_t *dwptr;
 871         struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
 872
 873         ret = QLA_SUCCESS;
 874
 875         /* Enable flash write. */
 876         WRT_REG_DWORD(&reg->ctrl_status,
 877             RD_REG_DWORD(&reg->ctrl_status) | CSRX_FLASH_ENABLE);
 878         RD_REG_DWORD(&reg->ctrl_status);        /* PCI Posting. */
 879
 880         /* Disable NVRAM write-protection. */
 881         qla24xx_write_flash_dword(ha, nvram_conf_to_access_addr(0x101),
 882             0);
 883         qla24xx_write_flash_dword(ha, nvram_conf_to_access_addr(0x101),
 884             0);
 885
 886         /* Dword writes to flash. */
 887         dwptr = (uint32_t *)buf;
 888         for (i = 0; i < bytes >> 2; i++, naddr++, dwptr++) {
 889                 ret = qla24xx_write_flash_dword(ha,
 890                     nvram_data_to_access_addr(naddr),
 891                     cpu_to_le32(*dwptr));
 892                 if (ret != QLA_SUCCESS) {
 893                         DEBUG9(printk("%s(%ld) Unable to program "
 894                             "nvram address=%x data=%x.\n", __func__,
 895                             ha->host_no, naddr, *dwptr));
 896                         break;
 897                 }
 898         }
 899
 900         /* Enable NVRAM write-protection. */
 901         qla24xx_write_flash_dword(ha, nvram_conf_to_access_addr(0x101),
 902             0x8c);
 903
 904         /* Disable flash write. */
 905         WRT_REG_DWORD(&reg->ctrl_status,
 906             RD_REG_DWORD(&reg->ctrl_status) & ~CSRX_FLASH_ENABLE);
 907         RD_REG_DWORD(&reg->ctrl_status);        /* PCI Posting. */
 908
 909         return ret;
 910 }
 911
 912 uint8_t *
 913 qla25xx_read_nvram_data(scsi_qla_host_t *ha, uint8_t *buf, uint32_t naddr,
 914     uint32_t bytes)
 915 {
 916         uint32_t i;
 917         uint32_t *dwptr;
 918
 919         /* Dword reads to flash. */
 920         dwptr = (uint32_t *)buf;
 921         for (i = 0; i < bytes >> 2; i++, naddr++)
 922                 dwptr[i] = cpu_to_le32(qla24xx_read_flash_dword(ha,
 923                     flash_data_to_access_addr(FA_VPD_NVRAM_ADDR | naddr)));
 924
 925         return buf;
 926 }
 927
 928 int
 929 qla25xx_write_nvram_data(scsi_qla_host_t *ha, uint8_t *buf, uint32_t naddr,
 930     uint32_t bytes)
 931 {
 932 #define RMW_BUFFER_SIZE (64 * 1024)
 933         uint8_t *dbuf;
 934
 935         dbuf = vmalloc(RMW_BUFFER_SIZE);
 936         if (!dbuf)
 937                 return QLA_MEMORY_ALLOC_FAILED;
 938         ha->isp_ops->read_optrom(ha, dbuf, FA_VPD_NVRAM_ADDR << 2,
 939             RMW_BUFFER_SIZE);
 940         memcpy(dbuf + (naddr << 2), buf, bytes);
 941         ha->isp_ops->write_optrom(ha, dbuf, FA_VPD_NVRAM_ADDR << 2,
 942             RMW_BUFFER_SIZE);
 943         vfree(dbuf);
 944
 945         return QLA_SUCCESS;
 946 }
 947
 948 static inline void
 949 qla2x00_flip_colors(scsi_qla_host_t *ha, uint16_t *pflags)
 950 {
 951         if (IS_QLA2322(ha)) {
 952                 /* Flip all colors. */
 953                 if (ha->beacon_color_state == QLA_LED_ALL_ON) {
 954                         /* Turn off. */
 955                         ha->beacon_color_state = 0;
 956                         *pflags = GPIO_LED_ALL_OFF;
 957                 } else {
 958                         /* Turn on. */
 959                         ha->beacon_color_state = QLA_LED_ALL_ON;
 960                         *pflags = GPIO_LED_RGA_ON;
 961                 }
 962         } else {
 963                 /* Flip green led only. */
 964                 if (ha->beacon_color_state == QLA_LED_GRN_ON) {
 965                         /* Turn off. */
 966                         ha->beacon_color_state = 0;
 967                         *pflags = GPIO_LED_GREEN_OFF_AMBER_OFF;
 968                 } else {
 969                         /* Turn on. */
 970                         ha->beacon_color_state = QLA_LED_GRN_ON;
 971                         *pflags = GPIO_LED_GREEN_ON_AMBER_OFF;
 972                 }
 973         }
 974 }
 975
 976 #define PIO_REG(h, r) ((h)->pio_address + offsetof(struct device_reg_2xxx, r))
 977
 978 void
 979 qla2x00_beacon_blink(struct scsi_qla_host *ha)
 980 {
 981         uint16_t gpio_enable;
 982         uint16_t gpio_data;
 983         uint16_t led_color = 0;
 984         unsigned long flags;
 985         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
 986
 987         spin_lock_irqsave(&ha->hardware_lock, flags);
 988
 989         /* Save the Original GPIOE. */
 990         if (ha->pio_address) {
 991                 gpio_enable = RD_REG_WORD_PIO(PIO_REG(ha, gpioe));
 992                 gpio_data = RD_REG_WORD_PIO(PIO_REG(ha, gpiod));
 993         } else {
 994                 gpio_enable = RD_REG_WORD(&reg->gpioe);
 995                 gpio_data = RD_REG_WORD(&reg->gpiod);
 996         }
 997
 998         /* Set the modified gpio_enable values */
 999         gpio_enable |= GPIO_LED_MASK;
1000
1001         if (ha->pio_address) {
1002                 WRT_REG_WORD_PIO(PIO_REG(ha, gpioe), gpio_enable);
1003         } else {
1004                 WRT_REG_WORD(&reg->gpioe, gpio_enable);
1005                 RD_REG_WORD(&reg->gpioe);
1006         }
1007
1008         qla2x00_flip_colors(ha, &led_color);
1009
1010         /* Clear out any previously set LED color. */
1011         gpio_data &= ~GPIO_LED_MASK;
1012
1013         /* Set the new input LED color to GPIOD. */
1014         gpio_data |= led_color;
1015
1016         /* Set the modified gpio_data values */
1017         if (ha->pio_address) {
1018                 WRT_REG_WORD_PIO(PIO_REG(ha, gpiod), gpio_data);
1019         } else {
1020                 WRT_REG_WORD(&reg->gpiod, gpio_data);
1021                 RD_REG_WORD(&reg->gpiod);
1022         }
1023
1024         spin_unlock_irqrestore(&ha->hardware_lock, flags);
1025 }
1026
1027 int
1028 qla2x00_beacon_on(struct scsi_qla_host *ha)
1029 {
1030         uint16_t gpio_enable;
1031         uint16_t gpio_data;
1032         unsigned long flags;
1033         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1034
1035         ha->fw_options[1] &= ~FO1_SET_EMPHASIS_SWING;
1036         ha->fw_options[1] |= FO1_DISABLE_GPIO6_7;
1037
1038         if (qla2x00_set_fw_options(ha, ha->fw_options) != QLA_SUCCESS) {
1039                 qla_printk(KERN_WARNING, ha,
1040                     "Unable to update fw options (beacon on).\n");
1041                 return QLA_FUNCTION_FAILED;
1042         }
1043
1044         /* Turn off LEDs. */
1045         spin_lock_irqsave(&ha->hardware_lock, flags);
1046         if (ha->pio_address) {
1047                 gpio_enable = RD_REG_WORD_PIO(PIO_REG(ha, gpioe));
1048                 gpio_data = RD_REG_WORD_PIO(PIO_REG(ha, gpiod));
1049         } else {
1050                 gpio_enable = RD_REG_WORD(&reg->gpioe);
1051                 gpio_data = RD_REG_WORD(&reg->gpiod);
1052         }
1053         gpio_enable |= GPIO_LED_MASK;
1054
1055         /* Set the modified gpio_enable values. */
1056         if (ha->pio_address) {
1057                 WRT_REG_WORD_PIO(PIO_REG(ha, gpioe), gpio_enable);
1058         } else {
1059                 WRT_REG_WORD(&reg->gpioe, gpio_enable);
1060                 RD_REG_WORD(&reg->gpioe);
1061         }
1062
1063         /* Clear out previously set LED colour. */
1064         gpio_data &= ~GPIO_LED_MASK;
1065         if (ha->pio_address) {
1066                 WRT_REG_WORD_PIO(PIO_REG(ha, gpiod), gpio_data);
1067         } else {
1068                 WRT_REG_WORD(&reg->gpiod, gpio_data);
1069                 RD_REG_WORD(&reg->gpiod);
1070         }
1071         spin_unlock_irqrestore(&ha->hardware_lock, flags);
1072
1073         /*
1074          * Let the per HBA timer kick off the blinking process based on
1075          * the following flags. No need to do anything else now.
1076          */
1077         ha->beacon_blink_led = 1;
1078         ha->beacon_color_state = 0;
1079
1080         return QLA_SUCCESS;
1081 }
1082
1083 int
1084 qla2x00_beacon_off(struct scsi_qla_host *ha)
1085 {
1086         int rval = QLA_SUCCESS;
1087
1088         ha->beacon_blink_led = 0;
1089
1090         /* Set the on flag so when it gets flipped it will be off. */
1091         if (IS_QLA2322(ha))
1092                 ha->beacon_color_state = QLA_LED_ALL_ON;
1093         else
1094                 ha->beacon_color_state = QLA_LED_GRN_ON;
1095
1096         ha->isp_ops->beacon_blink(ha);  /* This turns green LED off */
1097
1098         ha->fw_options[1] &= ~FO1_SET_EMPHASIS_SWING;
1099         ha->fw_options[1] &= ~FO1_DISABLE_GPIO6_7;
1100
1101         rval = qla2x00_set_fw_options(ha, ha->fw_options);
1102         if (rval != QLA_SUCCESS)
1103                 qla_printk(KERN_WARNING, ha,
1104                     "Unable to update fw options (beacon off).\n");
1105         return rval;
1106 }
1107
1108
1109 static inline void
1110 qla24xx_flip_colors(scsi_qla_host_t *ha, uint16_t *pflags)
1111 {
1112         /* Flip all colors. */
1113         if (ha->beacon_color_state == QLA_LED_ALL_ON) {
1114                 /* Turn off. */
1115                 ha->beacon_color_state = 0;
1116                 *pflags = 0;
1117         } else {
1118                 /* Turn on. */
1119                 ha->beacon_color_state = QLA_LED_ALL_ON;
1120                 *pflags = GPDX_LED_YELLOW_ON | GPDX_LED_AMBER_ON;
1121         }
1122 }
1123
1124 void
1125 qla24xx_beacon_blink(struct scsi_qla_host *ha)
1126 {
1127         uint16_t led_color = 0;
1128         uint32_t gpio_data;
1129         unsigned long flags;
1130         struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1131
1132         /* Save the Original GPIOD. */
1133         spin_lock_irqsave(&ha->hardware_lock, flags);
1134         gpio_data = RD_REG_DWORD(&reg->gpiod);
1135
1136         /* Enable the gpio_data reg for update. */
1137         gpio_data |= GPDX_LED_UPDATE_MASK;
1138
1139         WRT_REG_DWORD(&reg->gpiod, gpio_data);
1140         gpio_data = RD_REG_DWORD(&reg->gpiod);
1141
1142         /* Set the color bits. */
1143         qla24xx_flip_colors(ha, &led_color);
1144
1145         /* Clear out any previously set LED color. */
1146         gpio_data &= ~GPDX_LED_COLOR_MASK;
1147
1148         /* Set the new input LED color to GPIOD. */
1149         gpio_data |= led_color;
1150
1151         /* Set the modified gpio_data values. */
1152         WRT_REG_DWORD(&reg->gpiod, gpio_data);
1153         gpio_data = RD_REG_DWORD(&reg->gpiod);
1154         spin_unlock_irqrestore(&ha->hardware_lock, flags);
1155 }
1156
1157 int
1158 qla24xx_beacon_on(struct scsi_qla_host *ha)
1159 {
1160         uint32_t gpio_data;
1161         unsigned long flags;
1162         struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1163
1164         if (ha->beacon_blink_led == 0) {
1165                 /* Enable firmware for update */
1166                 ha->fw_options[1] |= ADD_FO1_DISABLE_GPIO_LED_CTRL;
1167
1168                 if (qla2x00_set_fw_options(ha, ha->fw_options) != QLA_SUCCESS)
1169                         return QLA_FUNCTION_FAILED;
1170
1171                 if (qla2x00_get_fw_options(ha, ha->fw_options) !=
1172                     QLA_SUCCESS) {
1173                         qla_printk(KERN_WARNING, ha,
1174                             "Unable to update fw options (beacon on).\n");
1175                         return QLA_FUNCTION_FAILED;
1176                 }
1177
1178                 spin_lock_irqsave(&ha->hardware_lock, flags);
1179                 gpio_data = RD_REG_DWORD(&reg->gpiod);
1180
1181                 /* Enable the gpio_data reg for update. */
1182                 gpio_data |= GPDX_LED_UPDATE_MASK;
1183                 WRT_REG_DWORD(&reg->gpiod, gpio_data);
1184                 RD_REG_DWORD(&reg->gpiod);
1185
1186                 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1187         }
1188
1189         /* So all colors blink together. */
1190         ha->beacon_color_state = 0;
1191
1192         /* Let the per HBA timer kick off the blinking process. */
1193         ha->beacon_blink_led = 1;
1194
1195         return QLA_SUCCESS;
1196 }
1197
1198 int
1199 qla24xx_beacon_off(struct scsi_qla_host *ha)
1200 {
1201         uint32_t gpio_data;
1202         unsigned long flags;
1203         struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1204
1205         ha->beacon_blink_led = 0;
1206         ha->beacon_color_state = QLA_LED_ALL_ON;
1207
1208         ha->isp_ops->beacon_blink(ha);  /* Will flip to all off. */
1209
1210         /* Give control back to firmware. */
1211         spin_lock_irqsave(&ha->hardware_lock, flags);
1212         gpio_data = RD_REG_DWORD(&reg->gpiod);
1213
1214         /* Disable the gpio_data reg for update. */
1215         gpio_data &= ~GPDX_LED_UPDATE_MASK;
1216         WRT_REG_DWORD(&reg->gpiod, gpio_data);
1217         RD_REG_DWORD(&reg->gpiod);
1218         spin_unlock_irqrestore(&ha->hardware_lock, flags);
1219
1220         ha->fw_options[1] &= ~ADD_FO1_DISABLE_GPIO_LED_CTRL;
1221
1222         if (qla2x00_set_fw_options(ha, ha->fw_options) != QLA_SUCCESS) {
1223                 qla_printk(KERN_WARNING, ha,
1224                     "Unable to update fw options (beacon off).\n");
1225                 return QLA_FUNCTION_FAILED;
1226         }
1227
1228         if (qla2x00_get_fw_options(ha, ha->fw_options) != QLA_SUCCESS) {
1229                 qla_printk(KERN_WARNING, ha,
1230                     "Unable to get fw options (beacon off).\n");
1231                 return QLA_FUNCTION_FAILED;
1232         }
1233
1234         return QLA_SUCCESS;
1235 }
1236
1237
1238 /*
1239  * Flash support routines
1240  */
1241
1242 /**
1243  * qla2x00_flash_enable() - Setup flash for reading and writing.
1244  * @ha: HA context
1245  */
1246 static void
1247 qla2x00_flash_enable(scsi_qla_host_t *ha)
1248 {
1249         uint16_t data;
1250         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1251
1252         data = RD_REG_WORD(&reg->ctrl_status);
1253         data |= CSR_FLASH_ENABLE;
1254         WRT_REG_WORD(&reg->ctrl_status, data);
1255         RD_REG_WORD(&reg->ctrl_status);         /* PCI Posting. */
1256 }
1257
1258 /**
1259  * qla2x00_flash_disable() - Disable flash and allow RISC to run.
1260  * @ha: HA context
1261  */
1262 static void
1263 qla2x00_flash_disable(scsi_qla_host_t *ha)
1264 {
1265         uint16_t data;
1266         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1267
1268         data = RD_REG_WORD(&reg->ctrl_status);
1269         data &= ~(CSR_FLASH_ENABLE);
1270         WRT_REG_WORD(&reg->ctrl_status, data);
1271         RD_REG_WORD(&reg->ctrl_status);         /* PCI Posting. */
1272 }
1273
1274 /**
1275  * qla2x00_read_flash_byte() - Reads a byte from flash
1276  * @ha: HA context
1277  * @addr: Address in flash to read
1278  *
1279  * A word is read from the chip, but, only the lower byte is valid.
1280  *
1281  * Returns the byte read from flash @addr.
1282  */
1283 static uint8_t
1284 qla2x00_read_flash_byte(scsi_qla_host_t *ha, uint32_t addr)
1285 {
1286         uint16_t data;
1287         uint16_t bank_select;
1288         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1289
1290         bank_select = RD_REG_WORD(&reg->ctrl_status);
1291
1292         if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
1293                 /* Specify 64K address range: */
1294                 /*  clear out Module Select and Flash Address bits [19:16]. */
1295                 bank_select &= ~0xf8;
1296                 bank_select |= addr >> 12 & 0xf0;
1297                 bank_select |= CSR_FLASH_64K_BANK;
1298                 WRT_REG_WORD(&reg->ctrl_status, bank_select);
1299                 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1300
1301                 WRT_REG_WORD(&reg->flash_address, (uint16_t)addr);
1302                 data = RD_REG_WORD(&reg->flash_data);
1303
1304                 return (uint8_t)data;
1305         }
1306
1307         /* Setup bit 16 of flash address. */
1308         if ((addr & BIT_16) && ((bank_select & CSR_FLASH_64K_BANK) == 0)) {
1309                 bank_select |= CSR_FLASH_64K_BANK;
1310                 WRT_REG_WORD(&reg->ctrl_status, bank_select);
1311                 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1312         } else if (((addr & BIT_16) == 0) &&
1313             (bank_select & CSR_FLASH_64K_BANK)) {
1314                 bank_select &= ~(CSR_FLASH_64K_BANK);
1315                 WRT_REG_WORD(&reg->ctrl_status, bank_select);
1316                 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1317         }
1318
1319         /* Always perform IO mapped accesses to the FLASH registers. */
1320         if (ha->pio_address) {
1321                 uint16_t data2;
1322
1323                 WRT_REG_WORD_PIO(PIO_REG(ha, flash_address), (uint16_t)addr);
1324                 do {
1325                         data = RD_REG_WORD_PIO(PIO_REG(ha, flash_data));
1326                         barrier();
1327                         cpu_relax();
1328                         data2 = RD_REG_WORD_PIO(PIO_REG(ha, flash_data));
1329                 } while (data != data2);
1330         } else {
1331                 WRT_REG_WORD(&reg->flash_address, (uint16_t)addr);
1332                 data = qla2x00_debounce_register(&reg->flash_data);
1333         }
1334
1335         return (uint8_t)data;
1336 }
1337
1338 /**
1339  * qla2x00_write_flash_byte() - Write a byte to flash
1340  * @ha: HA context
1341  * @addr: Address in flash to write
1342  * @data: Data to write
1343  */
1344 static void
1345 qla2x00_write_flash_byte(scsi_qla_host_t *ha, uint32_t addr, uint8_t data)
1346 {
1347         uint16_t bank_select;
1348         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1349
1350         bank_select = RD_REG_WORD(&reg->ctrl_status);
1351         if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
1352                 /* Specify 64K address range: */
1353                 /*  clear out Module Select and Flash Address bits [19:16]. */
1354                 bank_select &= ~0xf8;
1355                 bank_select |= addr >> 12 & 0xf0;
1356                 bank_select |= CSR_FLASH_64K_BANK;
1357                 WRT_REG_WORD(&reg->ctrl_status, bank_select);
1358                 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1359
1360                 WRT_REG_WORD(&reg->flash_address, (uint16_t)addr);
1361                 RD_REG_WORD(&reg->ctrl_status);         /* PCI Posting. */
1362                 WRT_REG_WORD(&reg->flash_data, (uint16_t)data);
1363                 RD_REG_WORD(&reg->ctrl_status);         /* PCI Posting. */
1364
1365                 return;
1366         }
1367
1368         /* Setup bit 16 of flash address. */
1369         if ((addr & BIT_16) && ((bank_select & CSR_FLASH_64K_BANK) == 0)) {
1370                 bank_select |= CSR_FLASH_64K_BANK;
1371                 WRT_REG_WORD(&reg->ctrl_status, bank_select);
1372                 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1373         } else if (((addr & BIT_16) == 0) &&
1374             (bank_select & CSR_FLASH_64K_BANK)) {
1375                 bank_select &= ~(CSR_FLASH_64K_BANK);
1376                 WRT_REG_WORD(&reg->ctrl_status, bank_select);
1377                 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1378         }
1379
1380         /* Always perform IO mapped accesses to the FLASH registers. */
1381         if (ha->pio_address) {
1382                 WRT_REG_WORD_PIO(PIO_REG(ha, flash_address), (uint16_t)addr);
1383                 WRT_REG_WORD_PIO(PIO_REG(ha, flash_data), (uint16_t)data);
1384         } else {
1385                 WRT_REG_WORD(&reg->flash_address, (uint16_t)addr);
1386                 RD_REG_WORD(&reg->ctrl_status);         /* PCI Posting. */
1387                 WRT_REG_WORD(&reg->flash_data, (uint16_t)data);
1388                 RD_REG_WORD(&reg->ctrl_status);         /* PCI Posting. */
1389         }
1390 }
1391
1392 /**
1393  * qla2x00_poll_flash() - Polls flash for completion.
1394  * @ha: HA context
1395  * @addr: Address in flash to poll
1396  * @poll_data: Data to be polled
1397  * @man_id: Flash manufacturer ID
1398  * @flash_id: Flash ID
1399  *
1400  * This function polls the device until bit 7 of what is read matches data
1401  * bit 7 or until data bit 5 becomes a 1.  If that hapens, the flash ROM timed
1402  * out (a fatal error).  The flash book recommeds reading bit 7 again after
1403  * reading bit 5 as a 1.
1404  *
1405  * Returns 0 on success, else non-zero.
1406  */
1407 static int
1408 qla2x00_poll_flash(scsi_qla_host_t *ha, uint32_t addr, uint8_t poll_data,
1409     uint8_t man_id, uint8_t flash_id)
1410 {
1411         int status;
1412         uint8_t flash_data;
1413         uint32_t cnt;
1414
1415         status = 1;
1416
1417         /* Wait for 30 seconds for command to finish. */
1418         poll_data &= BIT_7;
1419         for (cnt = 3000000; cnt; cnt--) {
1420                 flash_data = qla2x00_read_flash_byte(ha, addr);
1421                 if ((flash_data & BIT_7) == poll_data) {
1422                         status = 0;
1423                         break;
1424                 }
1425
1426                 if (man_id != 0x40 && man_id != 0xda) {
1427                         if ((flash_data & BIT_5) && cnt > 2)
1428                                 cnt = 2;
1429                 }
1430                 udelay(10);
1431                 barrier();
1432                 cond_resched();
1433         }
1434         return status;
1435 }
1436
1437 /**
1438  * qla2x00_program_flash_address() - Programs a flash address
1439  * @ha: HA context
1440  * @addr: Address in flash to program
1441  * @data: Data to be written in flash
1442  * @man_id: Flash manufacturer ID
1443  * @flash_id: Flash ID
1444  *
1445  * Returns 0 on success, else non-zero.
1446  */
1447 static int
1448 qla2x00_program_flash_address(scsi_qla_host_t *ha, uint32_t addr, uint8_t data,
1449     uint8_t man_id, uint8_t flash_id)
1450 {
1451         /* Write Program Command Sequence. */
1452         if (IS_OEM_001(ha)) {
1453                 qla2x00_write_flash_byte(ha, 0xaaa, 0xaa);
1454                 qla2x00_write_flash_byte(ha, 0x555, 0x55);
1455                 qla2x00_write_flash_byte(ha, 0xaaa, 0xa0);
1456                 qla2x00_write_flash_byte(ha, addr, data);
1457         } else {
1458                 if (man_id == 0xda && flash_id == 0xc1) {
1459                         qla2x00_write_flash_byte(ha, addr, data);
1460                         if (addr & 0x7e)
1461                                 return 0;
1462                 } else {
1463                         qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
1464                         qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
1465                         qla2x00_write_flash_byte(ha, 0x5555, 0xa0);
1466                         qla2x00_write_flash_byte(ha, addr, data);
1467                 }
1468         }
1469
1470         udelay(150);
1471
1472         /* Wait for write to complete. */
1473         return qla2x00_poll_flash(ha, addr, data, man_id, flash_id);
1474 }
1475
1476 /**
1477  * qla2x00_erase_flash() - Erase the flash.
1478  * @ha: HA context
1479  * @man_id: Flash manufacturer ID
1480  * @flash_id: Flash ID
1481  *
1482  * Returns 0 on success, else non-zero.
1483  */
1484 static int
1485 qla2x00_erase_flash(scsi_qla_host_t *ha, uint8_t man_id, uint8_t flash_id)
1486 {
1487         /* Individual Sector Erase Command Sequence */
1488         if (IS_OEM_001(ha)) {
1489                 qla2x00_write_flash_byte(ha, 0xaaa, 0xaa);
1490                 qla2x00_write_flash_byte(ha, 0x555, 0x55);
1491                 qla2x00_write_flash_byte(ha, 0xaaa, 0x80);
1492                 qla2x00_write_flash_byte(ha, 0xaaa, 0xaa);
1493                 qla2x00_write_flash_byte(ha, 0x555, 0x55);
1494                 qla2x00_write_flash_byte(ha, 0xaaa, 0x10);
1495         } else {
1496                 qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
1497                 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
1498                 qla2x00_write_flash_byte(ha, 0x5555, 0x80);
1499                 qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
1500                 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
1501                 qla2x00_write_flash_byte(ha, 0x5555, 0x10);
1502         }
1503
1504         udelay(150);
1505
1506         /* Wait for erase to complete. */
1507         return qla2x00_poll_flash(ha, 0x00, 0x80, man_id, flash_id);
1508 }
1509
1510 /**
1511  * qla2x00_erase_flash_sector() - Erase a flash sector.
1512  * @ha: HA context
1513  * @addr: Flash sector to erase
1514  * @sec_mask: Sector address mask
1515  * @man_id: Flash manufacturer ID
1516  * @flash_id: Flash ID
1517  *
1518  * Returns 0 on success, else non-zero.
1519  */
1520 static int
1521 qla2x00_erase_flash_sector(scsi_qla_host_t *ha, uint32_t addr,
1522     uint32_t sec_mask, uint8_t man_id, uint8_t flash_id)
1523 {
1524         /* Individual Sector Erase Command Sequence */
1525         qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
1526         qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
1527         qla2x00_write_flash_byte(ha, 0x5555, 0x80);
1528         qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
1529         qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
1530         if (man_id == 0x1f && flash_id == 0x13)
1531                 qla2x00_write_flash_byte(ha, addr & sec_mask, 0x10);
1532         else
1533                 qla2x00_write_flash_byte(ha, addr & sec_mask, 0x30);
1534
1535         udelay(150);
1536
1537         /* Wait for erase to complete. */
1538         return qla2x00_poll_flash(ha, addr, 0x80, man_id, flash_id);
1539 }
1540
1541 /**
1542  * qla2x00_get_flash_manufacturer() - Read manufacturer ID from flash chip.
1543  * @man_id: Flash manufacturer ID
1544  * @flash_id: Flash ID
1545  */
1546 static void
1547 qla2x00_get_flash_manufacturer(scsi_qla_host_t *ha, uint8_t *man_id,
1548     uint8_t *flash_id)
1549 {
1550         qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
1551         qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
1552         qla2x00_write_flash_byte(ha, 0x5555, 0x90);
1553         *man_id = qla2x00_read_flash_byte(ha, 0x0000);
1554         *flash_id = qla2x00_read_flash_byte(ha, 0x0001);
1555         qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
1556         qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
1557         qla2x00_write_flash_byte(ha, 0x5555, 0xf0);
1558 }
1559
1560 static void
1561 qla2x00_read_flash_data(scsi_qla_host_t *ha, uint8_t *tmp_buf, uint32_t saddr,
1562         uint32_t length)
1563 {
1564         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1565         uint32_t midpoint, ilength;
1566         uint8_t data;
1567
1568         midpoint = length / 2;
1569
1570         WRT_REG_WORD(&reg->nvram, 0);
1571         RD_REG_WORD(&reg->nvram);
1572         for (ilength = 0; ilength < length; saddr++, ilength++, tmp_buf++) {
1573                 if (ilength == midpoint) {
1574                         WRT_REG_WORD(&reg->nvram, NVR_SELECT);
1575                         RD_REG_WORD(&reg->nvram);
1576                 }
1577                 data = qla2x00_read_flash_byte(ha, saddr);
1578                 if (saddr % 100)
1579                         udelay(10);
1580                 *tmp_buf = data;
1581                 cond_resched();
1582         }
1583 }
1584
1585 static inline void
1586 qla2x00_suspend_hba(struct scsi_qla_host *ha)
1587 {
1588         int cnt;
1589         unsigned long flags;
1590         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1591
1592         /* Suspend HBA. */
1593         scsi_block_requests(ha->host);
1594         ha->isp_ops->disable_intrs(ha);
1595         set_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
1596
1597         /* Pause RISC. */
1598         spin_lock_irqsave(&ha->hardware_lock, flags);
1599         WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);
1600         RD_REG_WORD(&reg->hccr);
1601         if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) {
1602                 for (cnt = 0; cnt < 30000; cnt++) {
1603                         if ((RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) != 0)
1604                                 break;
1605                         udelay(100);
1606                 }
1607         } else {
1608                 udelay(10);
1609         }
1610         spin_unlock_irqrestore(&ha->hardware_lock, flags);
1611 }
1612
1613 static inline void
1614 qla2x00_resume_hba(struct scsi_qla_host *ha)
1615 {
1616         /* Resume HBA. */
1617         clear_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
1618         set_bit(ISP_ABORT_NEEDED, &ha->dpc_flags);
1619         qla2xxx_wake_dpc(ha);
1620         qla2x00_wait_for_hba_online(ha);
1621         scsi_unblock_requests(ha->host);
1622 }
1623
1624 uint8_t *
1625 qla2x00_read_optrom_data(struct scsi_qla_host *ha, uint8_t *buf,
1626     uint32_t offset, uint32_t length)
1627 {
1628         uint32_t addr, midpoint;
1629         uint8_t *data;
1630         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1631
1632         /* Suspend HBA. */
1633         qla2x00_suspend_hba(ha);
1634
1635         /* Go with read. */
1636         midpoint = ha->optrom_size / 2;
1637
1638         qla2x00_flash_enable(ha);
1639         WRT_REG_WORD(&reg->nvram, 0);
1640         RD_REG_WORD(&reg->nvram);               /* PCI Posting. */
1641         for (addr = offset, data = buf; addr < length; addr++, data++) {
1642                 if (addr == midpoint) {
1643                         WRT_REG_WORD(&reg->nvram, NVR_SELECT);
1644                         RD_REG_WORD(&reg->nvram);       /* PCI Posting. */
1645                 }
1646
1647                 *data = qla2x00_read_flash_byte(ha, addr);
1648         }
1649         qla2x00_flash_disable(ha);
1650
1651         /* Resume HBA. */
1652         qla2x00_resume_hba(ha);
1653
1654         return buf;
1655 }
1656
1657 int
1658 qla2x00_write_optrom_data(struct scsi_qla_host *ha, uint8_t *buf,
1659     uint32_t offset, uint32_t length)
1660 {
1661
1662         int rval;
1663         uint8_t man_id, flash_id, sec_number, data;
1664         uint16_t wd;
1665         uint32_t addr, liter, sec_mask, rest_addr;
1666         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1667
1668         /* Suspend HBA. */
1669         qla2x00_suspend_hba(ha);
1670
1671         rval = QLA_SUCCESS;
1672         sec_number = 0;
1673
1674         /* Reset ISP chip. */
1675         WRT_REG_WORD(&reg->ctrl_status, CSR_ISP_SOFT_RESET);
1676         pci_read_config_word(ha->pdev, PCI_COMMAND, &wd);
1677
1678         /* Go with write. */
1679         qla2x00_flash_enable(ha);
1680         do {    /* Loop once to provide quick error exit */
1681                 /* Structure of flash memory based on manufacturer */
1682                 if (IS_OEM_001(ha)) {
1683                         /* OEM variant with special flash part. */
1684                         man_id = flash_id = 0;
1685                         rest_addr = 0xffff;
1686                         sec_mask   = 0x10000;
1687                         goto update_flash;
1688                 }
1689                 qla2x00_get_flash_manufacturer(ha, &man_id, &flash_id);
1690                 switch (man_id) {
1691                 case 0x20: /* ST flash. */
1692                         if (flash_id == 0xd2 || flash_id == 0xe3) {
1693                                 /*
1694                                  * ST m29w008at part - 64kb sector size with
1695                                  * 32kb,8kb,8kb,16kb sectors at memory address
1696                                  * 0xf0000.
1697                                  */
1698                                 rest_addr = 0xffff;
1699                                 sec_mask = 0x10000;
1700                                 break;
1701                         }
1702                         /*
1703                          * ST m29w010b part - 16kb sector size
1704                          * Default to 16kb sectors
1705                          */
1706                         rest_addr = 0x3fff;
1707                         sec_mask = 0x1c000;
1708                         break;
1709                 case 0x40: /* Mostel flash. */
1710                         /* Mostel v29c51001 part - 512 byte sector size. */
1711                         rest_addr = 0x1ff;
1712                         sec_mask = 0x1fe00;
1713                         break;
1714                 case 0xbf: /* SST flash. */
1715                         /* SST39sf10 part - 4kb sector size. */
1716                         rest_addr = 0xfff;
1717                         sec_mask = 0x1f000;
1718                         break;
1719                 case 0xda: /* Winbond flash. */
1720                         /* Winbond W29EE011 part - 256 byte sector size. */
1721                         rest_addr = 0x7f;
1722                         sec_mask = 0x1ff80;
1723                         break;
1724                 case 0xc2: /* Macronix flash. */
1725                         /* 64k sector size. */
1726                         if (flash_id == 0x38 || flash_id == 0x4f) {
1727                                 rest_addr = 0xffff;
1728                                 sec_mask = 0x10000;
1729                                 break;
1730                         }
1731                         /* Fall through... */
1732
1733                 case 0x1f: /* Atmel flash. */
1734                         /* 512k sector size. */
1735                         if (flash_id == 0x13) {
1736                                 rest_addr = 0x7fffffff;
1737                                 sec_mask =   0x80000000;
1738                                 break;
1739                         }
1740                         /* Fall through... */
1741
1742                 case 0x01: /* AMD flash. */
1743                         if (flash_id == 0x38 || flash_id == 0x40 ||
1744                             flash_id == 0x4f) {
1745                                 /* Am29LV081 part - 64kb sector size. */
1746                                 /* Am29LV002BT part - 64kb sector size. */
1747                                 rest_addr = 0xffff;
1748                                 sec_mask = 0x10000;
1749                                 break;
1750                         } else if (flash_id == 0x3e) {
1751                                 /*
1752                                  * Am29LV008b part - 64kb sector size with
1753                                  * 32kb,8kb,8kb,16kb sector at memory address
1754                                  * h0xf0000.
1755                                  */
1756                                 rest_addr = 0xffff;
1757                                 sec_mask = 0x10000;
1758                                 break;
1759                         } else if (flash_id == 0x20 || flash_id == 0x6e) {
1760                                 /*
1761                                  * Am29LV010 part or AM29f010 - 16kb sector
1762                                  * size.
1763                                  */
1764                                 rest_addr = 0x3fff;
1765                                 sec_mask = 0x1c000;
1766                                 break;
1767                         } else if (flash_id == 0x6d) {
1768                                 /* Am29LV001 part - 8kb sector size. */
1769                                 rest_addr = 0x1fff;
1770                                 sec_mask = 0x1e000;
1771                                 break;
1772                         }
1773                 default:
1774                         /* Default to 16 kb sector size. */
1775                         rest_addr = 0x3fff;
1776                         sec_mask = 0x1c000;
1777                         break;
1778                 }
1779
1780 update_flash:
1781                 if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
1782                         if (qla2x00_erase_flash(ha, man_id, flash_id)) {
1783                                 rval = QLA_FUNCTION_FAILED;
1784                                 break;
1785                         }
1786                 }
1787
1788                 for (addr = offset, liter = 0; liter < length; liter++,
1789                     addr++) {
1790                         data = buf[liter];
1791                         /* Are we at the beginning of a sector? */
1792                         if ((addr & rest_addr) == 0) {
1793                                 if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
1794                                         if (addr >= 0x10000UL) {
1795                                                 if (((addr >> 12) & 0xf0) &&
1796                                                     ((man_id == 0x01 &&
1797                                                         flash_id == 0x3e) ||
1798                                                      (man_id == 0x20 &&
1799                                                          flash_id == 0xd2))) {
1800                                                         sec_number++;
1801                                                         if (sec_number == 1) {
1802                                                                 rest_addr =
1803                                                                     0x7fff;
1804                                                                 sec_mask =
1805                                                                     0x18000;
1806                                                         } else if (
1807                                                             sec_number == 2 ||
1808                                                             sec_number == 3) {
1809                                                                 rest_addr =
1810                                                                     0x1fff;
1811                                                                 sec_mask =
1812                                                                     0x1e000;
1813                                                         } else if (
1814                                                             sec_number == 4) {
1815                                                                 rest_addr =
1816                                                                     0x3fff;
1817                                                                 sec_mask =
1818                                                                     0x1c000;
1819                                                         }
1820                                                 }
1821                                         }
1822                                 } else if (addr == ha->optrom_size / 2) {
1823                                         WRT_REG_WORD(&reg->nvram, NVR_SELECT);
1824                                         RD_REG_WORD(&reg->nvram);
1825                                 }
1826
1827                                 if (flash_id == 0xda && man_id == 0xc1) {
1828                                         qla2x00_write_flash_byte(ha, 0x5555,
1829                                             0xaa);
1830                                         qla2x00_write_flash_byte(ha, 0x2aaa,
1831                                             0x55);
1832                                         qla2x00_write_flash_byte(ha, 0x5555,
1833                                             0xa0);
1834                                 } else if (!IS_QLA2322(ha) && !IS_QLA6322(ha)) {
1835                                         /* Then erase it */
1836                                         if (qla2x00_erase_flash_sector(ha,
1837                                             addr, sec_mask, man_id,
1838                                             flash_id)) {
1839                                                 rval = QLA_FUNCTION_FAILED;
1840                                                 break;
1841                                         }
1842                                         if (man_id == 0x01 && flash_id == 0x6d)
1843                                                 sec_number++;
1844                                 }
1845                         }
1846
1847                         if (man_id == 0x01 && flash_id == 0x6d) {
1848                                 if (sec_number == 1 &&
1849                                     addr == (rest_addr - 1)) {
1850                                         rest_addr = 0x0fff;
1851                                         sec_mask   = 0x1f000;
1852                                 } else if (sec_number == 3 && (addr & 0x7ffe)) {
1853                                         rest_addr = 0x3fff;
1854                                         sec_mask   = 0x1c000;
1855                                 }
1856                         }
1857
1858                         if (qla2x00_program_flash_address(ha, addr, data,
1859                             man_id, flash_id)) {
1860                                 rval = QLA_FUNCTION_FAILED;
1861                                 break;
1862                         }
1863                         cond_resched();
1864                 }
1865         } while (0);
1866         qla2x00_flash_disable(ha);
1867
1868         /* Resume HBA. */
1869         qla2x00_resume_hba(ha);
1870
1871         return rval;
1872 }
1873
1874 uint8_t *
1875 qla24xx_read_optrom_data(struct scsi_qla_host *ha, uint8_t *buf,
1876     uint32_t offset, uint32_t length)
1877 {
1878         /* Suspend HBA. */
1879         scsi_block_requests(ha->host);
1880         set_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
1881
1882         /* Go with read. */
1883         qla24xx_read_flash_data(ha, (uint32_t *)buf, offset >> 2, length >> 2);
1884
1885         /* Resume HBA. */
1886         clear_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
1887         scsi_unblock_requests(ha->host);
1888
1889         return buf;
1890 }
1891
1892 int
1893 qla24xx_write_optrom_data(struct scsi_qla_host *ha, uint8_t *buf,
1894     uint32_t offset, uint32_t length)
1895 {
1896         int rval;
1897
1898         /* Suspend HBA. */
1899         scsi_block_requests(ha->host);
1900         set_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
1901
1902         /* Go with write. */
1903         rval = qla24xx_write_flash_data(ha, (uint32_t *)buf, offset >> 2,
1904             length >> 2);
1905
1906         /* Resume HBA -- RISC reset needed. */
1907         clear_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
1908         set_bit(ISP_ABORT_NEEDED, &ha->dpc_flags);
1909         qla2xxx_wake_dpc(ha);
1910         qla2x00_wait_for_hba_online(ha);
1911         scsi_unblock_requests(ha->host);
1912
1913         return rval;
1914 }
1915
1916 uint8_t *
1917 qla25xx_read_optrom_data(struct scsi_qla_host *ha, uint8_t *buf,
1918     uint32_t offset, uint32_t length)
1919 {
1920         int rval;
1921         dma_addr_t optrom_dma;
1922         void *optrom;
1923         uint8_t *pbuf;
1924         uint32_t faddr, left, burst;
1925
1926         if (offset & 0xfff)
1927                 goto slow_read;
1928         if (length < OPTROM_BURST_SIZE)
1929                 goto slow_read;
1930
1931         optrom = dma_alloc_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE,
1932             &optrom_dma, GFP_KERNEL);
1933         if (!optrom) {
1934                 qla_printk(KERN_DEBUG, ha,
1935                     "Unable to allocate memory for optrom burst read "
1936                     "(%x KB).\n", OPTROM_BURST_SIZE / 1024);
1937
1938                 goto slow_read;
1939         }
1940
1941         pbuf = buf;
1942         faddr = offset >> 2;
1943         left = length >> 2;
1944         burst = OPTROM_BURST_DWORDS;
1945         while (left != 0) {
1946                 if (burst > left)
1947                         burst = left;
1948
1949                 rval = qla2x00_dump_ram(ha, optrom_dma,
1950                     flash_data_to_access_addr(faddr), burst);
1951                 if (rval) {
1952                         qla_printk(KERN_WARNING, ha,
1953                             "Unable to burst-read optrom segment "
1954                             "(%x/%x/%llx).\n", rval,
1955                             flash_data_to_access_addr(faddr),
1956                             (unsigned long long)optrom_dma);
1957                         qla_printk(KERN_WARNING, ha,
1958                             "Reverting to slow-read.\n");
1959
1960                         dma_free_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE,
1961                             optrom, optrom_dma);
1962                         goto slow_read;
1963                 }
1964
1965                 memcpy(pbuf, optrom, burst * 4);
1966
1967                 left -= burst;
1968                 faddr += burst;
1969                 pbuf += burst * 4;
1970         }
1971
1972         dma_free_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE, optrom,
1973             optrom_dma);
1974
1975         return buf;
1976
1977 slow_read:
1978     return qla24xx_read_optrom_data(ha, buf, offset, length);
1979 }
1980
1981 /**
1982  * qla2x00_get_fcode_version() - Determine an FCODE image's version.
1983  * @ha: HA context
1984  * @pcids: Pointer to the FCODE PCI data structure
1985  *
1986  * The process of retrieving the FCODE version information is at best
1987  * described as interesting.
1988  *
1989  * Within the first 100h bytes of the image an ASCII string is present
1990  * which contains several pieces of information including the FCODE
1991  * version.  Unfortunately it seems the only reliable way to retrieve
1992  * the version is by scanning for another sentinel within the string,
1993  * the FCODE build date:
1994  *
1995  *      ... 2.00.02 10/17/02 ...
1996  *
1997  * Returns QLA_SUCCESS on successful retrieval of version.
1998  */
1999 static void
2000 qla2x00_get_fcode_version(scsi_qla_host_t *ha, uint32_t pcids)
2001 {
2002         int ret = QLA_FUNCTION_FAILED;
2003         uint32_t istart, iend, iter, vend;
2004         uint8_t do_next, rbyte, *vbyte;
2005
2006         memset(ha->fcode_revision, 0, sizeof(ha->fcode_revision));
2007
2008         /* Skip the PCI data structure. */
2009         istart = pcids +
2010             ((qla2x00_read_flash_byte(ha, pcids + 0x0B) << 8) |
2011                 qla2x00_read_flash_byte(ha, pcids + 0x0A));
2012         iend = istart + 0x100;
2013         do {
2014                 /* Scan for the sentinel date string...eeewww. */
2015                 do_next = 0;
2016                 iter = istart;
2017                 while ((iter < iend) && !do_next) {
2018                         iter++;
2019                         if (qla2x00_read_flash_byte(ha, iter) == '/') {
2020                                 if (qla2x00_read_flash_byte(ha, iter + 2) ==
2021                                     '/')
2022                                         do_next++;
2023                                 else if (qla2x00_read_flash_byte(ha,
2024                                     iter + 3) == '/')
2025                                         do_next++;
2026                         }
2027                 }
2028                 if (!do_next)
2029                         break;
2030
2031                 /* Backtrack to previous ' ' (space). */
2032                 do_next = 0;
2033                 while ((iter > istart) && !do_next) {
2034                         iter--;
2035                         if (qla2x00_read_flash_byte(ha, iter) == ' ')
2036                                 do_next++;
2037                 }
2038                 if (!do_next)
2039                         break;
2040
2041                 /*
2042                  * Mark end of version tag, and find previous ' ' (space) or
2043                  * string length (recent FCODE images -- major hack ahead!!!).
2044                  */
2045                 vend = iter - 1;
2046                 do_next = 0;
2047                 while ((iter > istart) && !do_next) {
2048                         iter--;
2049                         rbyte = qla2x00_read_flash_byte(ha, iter);
2050                         if (rbyte == ' ' || rbyte == 0xd || rbyte == 0x10)
2051                                 do_next++;
2052                 }
2053                 if (!do_next)
2054                         break;
2055
2056                 /* Mark beginning of version tag, and copy data. */
2057                 iter++;
2058                 if ((vend - iter) &&
2059                     ((vend - iter) < sizeof(ha->fcode_revision))) {
2060                         vbyte = ha->fcode_revision;
2061                         while (iter <= vend) {
2062                                 *vbyte++ = qla2x00_read_flash_byte(ha, iter);
2063                                 iter++;
2064                         }
2065                         ret = QLA_SUCCESS;
2066                 }
2067         } while (0);
2068
2069         if (ret != QLA_SUCCESS)
2070                 memset(ha->fcode_revision, 0, sizeof(ha->fcode_revision));
2071 }
2072
2073 int
2074 qla2x00_get_flash_version(scsi_qla_host_t *ha, void *mbuf)
2075 {
2076         int ret = QLA_SUCCESS;
2077         uint8_t code_type, last_image;
2078         uint32_t pcihdr, pcids;
2079         uint8_t *dbyte;
2080         uint16_t *dcode;
2081
2082         if (!ha->pio_address || !mbuf)
2083                 return QLA_FUNCTION_FAILED;
2084
2085         memset(ha->bios_revision, 0, sizeof(ha->bios_revision));
2086         memset(ha->efi_revision, 0, sizeof(ha->efi_revision));
2087         memset(ha->fcode_revision, 0, sizeof(ha->fcode_revision));
2088         memset(ha->fw_revision, 0, sizeof(ha->fw_revision));
2089
2090         qla2x00_flash_enable(ha);
2091
2092         /* Begin with first PCI expansion ROM header. */
2093         pcihdr = 0;
2094         last_image = 1;
2095         do {
2096                 /* Verify PCI expansion ROM header. */
2097                 if (qla2x00_read_flash_byte(ha, pcihdr) != 0x55 ||
2098                     qla2x00_read_flash_byte(ha, pcihdr + 0x01) != 0xaa) {
2099                         /* No signature */
2100                         DEBUG2(printk("scsi(%ld): No matching ROM "
2101                             "signature.\n", ha->host_no));
2102                         ret = QLA_FUNCTION_FAILED;
2103                         break;
2104                 }
2105
2106                 /* Locate PCI data structure. */
2107                 pcids = pcihdr +
2108                     ((qla2x00_read_flash_byte(ha, pcihdr + 0x19) << 8) |
2109                         qla2x00_read_flash_byte(ha, pcihdr + 0x18));
2110
2111                 /* Validate signature of PCI data structure. */
2112                 if (qla2x00_read_flash_byte(ha, pcids) != 'P' ||
2113                     qla2x00_read_flash_byte(ha, pcids + 0x1) != 'C' ||
2114                     qla2x00_read_flash_byte(ha, pcids + 0x2) != 'I' ||
2115                     qla2x00_read_flash_byte(ha, pcids + 0x3) != 'R') {
2116                         /* Incorrect header. */
2117                         DEBUG2(printk("%s(): PCI data struct not found "
2118                             "pcir_adr=%x.\n", __func__, pcids));
2119                         ret = QLA_FUNCTION_FAILED;
2120                         break;
2121                 }
2122
2123                 /* Read version */
2124                 code_type = qla2x00_read_flash_byte(ha, pcids + 0x14);
2125                 switch (code_type) {
2126                 case ROM_CODE_TYPE_BIOS:
2127                         /* Intel x86, PC-AT compatible. */
2128                         ha->bios_revision[0] =
2129                             qla2x00_read_flash_byte(ha, pcids + 0x12);
2130                         ha->bios_revision[1] =
2131                             qla2x00_read_flash_byte(ha, pcids + 0x13);
2132                         DEBUG3(printk("%s(): read BIOS %d.%d.\n", __func__,
2133                             ha->bios_revision[1], ha->bios_revision[0]));
2134                         break;
2135                 case ROM_CODE_TYPE_FCODE:
2136                         /* Open Firmware standard for PCI (FCode). */
2137                         /* Eeeewww... */
2138                         qla2x00_get_fcode_version(ha, pcids);
2139                         break;
2140                 case ROM_CODE_TYPE_EFI:
2141                         /* Extensible Firmware Interface (EFI). */
2142                         ha->efi_revision[0] =
2143                             qla2x00_read_flash_byte(ha, pcids + 0x12);
2144                         ha->efi_revision[1] =
2145                             qla2x00_read_flash_byte(ha, pcids + 0x13);
2146                         DEBUG3(printk("%s(): read EFI %d.%d.\n", __func__,
2147                             ha->efi_revision[1], ha->efi_revision[0]));
2148                         break;
2149                 default:
2150                         DEBUG2(printk("%s(): Unrecognized code type %x at "
2151                             "pcids %x.\n", __func__, code_type, pcids));
2152                         break;
2153                 }
2154
2155                 last_image = qla2x00_read_flash_byte(ha, pcids + 0x15) & BIT_7;
2156
2157                 /* Locate next PCI expansion ROM. */
2158                 pcihdr += ((qla2x00_read_flash_byte(ha, pcids + 0x11) << 8) |
2159                     qla2x00_read_flash_byte(ha, pcids + 0x10)) * 512;
2160         } while (!last_image);
2161
2162         if (IS_QLA2322(ha)) {
2163                 /* Read firmware image information. */
2164                 memset(ha->fw_revision, 0, sizeof(ha->fw_revision));
2165                 dbyte = mbuf;
2166                 memset(dbyte, 0, 8);
2167                 dcode = (uint16_t *)dbyte;
2168
2169                 qla2x00_read_flash_data(ha, dbyte, FA_RISC_CODE_ADDR * 4 + 10,
2170                     8);
2171                 DEBUG3(printk("%s(%ld): dumping fw ver from flash:\n",
2172                     __func__, ha->host_no));
2173                 DEBUG3(qla2x00_dump_buffer((uint8_t *)dbyte, 8));
2174
2175                 if ((dcode[0] == 0xffff && dcode[1] == 0xffff &&
2176                     dcode[2] == 0xffff && dcode[3] == 0xffff) ||
2177                     (dcode[0] == 0 && dcode[1] == 0 && dcode[2] == 0 &&
2178                     dcode[3] == 0)) {
2179                         DEBUG2(printk("%s(): Unrecognized fw revision at "
2180                             "%x.\n", __func__, FA_RISC_CODE_ADDR * 4));
2181                 } else {
2182                         /* values are in big endian */
2183                         ha->fw_revision[0] = dbyte[0] << 16 | dbyte[1];
2184                         ha->fw_revision[1] = dbyte[2] << 16 | dbyte[3];
2185                         ha->fw_revision[2] = dbyte[4] << 16 | dbyte[5];
2186                 }
2187         }
2188
2189         qla2x00_flash_disable(ha);
2190
2191         return ret;
2192 }
2193
2194 int
2195 qla24xx_get_flash_version(scsi_qla_host_t *ha, void *mbuf)
2196 {
2197         int ret = QLA_SUCCESS;
2198         uint32_t pcihdr, pcids;
2199         uint32_t *dcode;
2200         uint8_t *bcode;
2201         uint8_t code_type, last_image;
2202         int i;
2203
2204         if (!mbuf)
2205                 return QLA_FUNCTION_FAILED;
2206
2207         memset(ha->bios_revision, 0, sizeof(ha->bios_revision));
2208         memset(ha->efi_revision, 0, sizeof(ha->efi_revision));
2209         memset(ha->fcode_revision, 0, sizeof(ha->fcode_revision));
2210         memset(ha->fw_revision, 0, sizeof(ha->fw_revision));
2211
2212         dcode = mbuf;
2213
2214         /* Begin with first PCI expansion ROM header. */
2215         pcihdr = 0;
2216         last_image = 1;
2217         do {
2218                 /* Verify PCI expansion ROM header. */
2219                 qla24xx_read_flash_data(ha, dcode, pcihdr >> 2, 0x20);
2220                 bcode = mbuf + (pcihdr % 4);
2221                 if (bcode[0x0] != 0x55 || bcode[0x1] != 0xaa) {
2222                         /* No signature */
2223                         DEBUG2(printk("scsi(%ld): No matching ROM "
2224                             "signature.\n", ha->host_no));
2225                         ret = QLA_FUNCTION_FAILED;
2226                         break;
2227                 }
2228
2229                 /* Locate PCI data structure. */
2230                 pcids = pcihdr + ((bcode[0x19] << 8) | bcode[0x18]);
2231
2232                 qla24xx_read_flash_data(ha, dcode, pcids >> 2, 0x20);
2233                 bcode = mbuf + (pcihdr % 4);
2234
2235                 /* Validate signature of PCI data structure. */
2236                 if (bcode[0x0] != 'P' || bcode[0x1] != 'C' ||
2237                     bcode[0x2] != 'I' || bcode[0x3] != 'R') {
2238                         /* Incorrect header. */
2239                         DEBUG2(printk("%s(): PCI data struct not found "
2240                             "pcir_adr=%x.\n", __func__, pcids));
2241                         ret = QLA_FUNCTION_FAILED;
2242                         break;
2243                 }
2244
2245                 /* Read version */
2246                 code_type = bcode[0x14];
2247                 switch (code_type) {
2248                 case ROM_CODE_TYPE_BIOS:
2249                         /* Intel x86, PC-AT compatible. */
2250                         ha->bios_revision[0] = bcode[0x12];
2251                         ha->bios_revision[1] = bcode[0x13];
2252                         DEBUG3(printk("%s(): read BIOS %d.%d.\n", __func__,
2253                             ha->bios_revision[1], ha->bios_revision[0]));
2254                         break;
2255                 case ROM_CODE_TYPE_FCODE:
2256                         /* Open Firmware standard for PCI (FCode). */
2257                         ha->fcode_revision[0] = bcode[0x12];
2258                         ha->fcode_revision[1] = bcode[0x13];
2259                         DEBUG3(printk("%s(): read FCODE %d.%d.\n", __func__,
2260                             ha->fcode_revision[1], ha->fcode_revision[0]));
2261                         break;
2262                 case ROM_CODE_TYPE_EFI:
2263                         /* Extensible Firmware Interface (EFI). */
2264                         ha->efi_revision[0] = bcode[0x12];
2265                         ha->efi_revision[1] = bcode[0x13];
2266                         DEBUG3(printk("%s(): read EFI %d.%d.\n", __func__,
2267                             ha->efi_revision[1], ha->efi_revision[0]));
2268                         break;
2269                 default:
2270                         DEBUG2(printk("%s(): Unrecognized code type %x at "
2271                             "pcids %x.\n", __func__, code_type, pcids));
2272                         break;
2273                 }
2274
2275                 last_image = bcode[0x15] & BIT_7;
2276
2277                 /* Locate next PCI expansion ROM. */
2278                 pcihdr += ((bcode[0x11] << 8) | bcode[0x10]) * 512;
2279         } while (!last_image);
2280
2281         /* Read firmware image information. */
2282         memset(ha->fw_revision, 0, sizeof(ha->fw_revision));
2283         dcode = mbuf;
2284
2285         qla24xx_read_flash_data(ha, dcode, FA_RISC_CODE_ADDR + 4, 4);
2286         for (i = 0; i < 4; i++)
2287                 dcode[i] = be32_to_cpu(dcode[i]);
2288
2289         if ((dcode[0] == 0xffffffff && dcode[1] == 0xffffffff &&
2290             dcode[2] == 0xffffffff && dcode[3] == 0xffffffff) ||
2291             (dcode[0] == 0 && dcode[1] == 0 && dcode[2] == 0 &&
2292             dcode[3] == 0)) {
2293                 DEBUG2(printk("%s(): Unrecognized fw version at %x.\n",
2294                     __func__, FA_RISC_CODE_ADDR));
2295         } else {
2296                 ha->fw_revision[0] = dcode[0];
2297                 ha->fw_revision[1] = dcode[1];
2298                 ha->fw_revision[2] = dcode[2];
2299                 ha->fw_revision[3] = dcode[3];
2300         }
2301
2302         return ret;
2303 }
2304
2305 static int
2306 qla2xxx_is_vpd_valid(uint8_t *pos, uint8_t *end)
2307 {
2308         if (pos >= end || *pos != 0x82)
2309                 return 0;
2310
2311         pos += 3 + pos[1];
2312         if (pos >= end || *pos != 0x90)
2313                 return 0;
2314
2315         pos += 3 + pos[1];
2316         if (pos >= end || *pos != 0x78)
2317                 return 0;
2318
2319         return 1;
2320 }
2321
2322 int
2323 qla2xxx_get_vpd_field(scsi_qla_host_t *ha, char *key, char *str, size_t size)
2324 {
2325         uint8_t *pos = ha->vpd;
2326         uint8_t *end = pos + ha->vpd_size;
2327         int len = 0;
2328
2329         if (!IS_FWI2_CAPABLE(ha) || !qla2xxx_is_vpd_valid(pos, end))
2330                 return 0;
2331
2332         while (pos < end && *pos != 0x78) {
2333                 len = (*pos == 0x82) ? pos[1] : pos[2];
2334
2335                 if (!strncmp(pos, key, strlen(key)))
2336                         break;
2337
2338                 if (*pos != 0x90 && *pos != 0x91)
2339                         pos += len;
2340
2341                 pos += 3;
2342         }
2343
2344         if (pos < end - len && *pos != 0x78)
2345                 return snprintf(str, size, "%.*s", len, pos + 3);
2346
2347         return 0;
2348 }
2349
2350 static int
2351 qla2xxx_hw_event_store(scsi_qla_host_t *ha, uint32_t *fdata)
2352 {
2353         uint32_t d[2], faddr;
2354
2355         /* Locate first empty entry. */
2356         for (;;) {
2357                 if (ha->hw_event_ptr >=
2358                     ha->hw_event_start + FA_HW_EVENT_SIZE) {
2359                         DEBUG2(qla_printk(KERN_WARNING, ha,
2360                             "HW event -- Log Full!\n"));
2361                         return QLA_MEMORY_ALLOC_FAILED;
2362                 }
2363
2364                 qla24xx_read_flash_data(ha, d, ha->hw_event_ptr, 2);
2365                 faddr = flash_data_to_access_addr(ha->hw_event_ptr);
2366                 ha->hw_event_ptr += FA_HW_EVENT_ENTRY_SIZE;
2367                 if (d[0] == __constant_cpu_to_le32(0xffffffff) &&
2368                     d[1] == __constant_cpu_to_le32(0xffffffff)) {
2369                         qla24xx_unprotect_flash(ha);
2370
2371                         qla24xx_write_flash_dword(ha, faddr++,
2372                             cpu_to_le32(jiffies));
2373                         qla24xx_write_flash_dword(ha, faddr++, 0);
2374                         qla24xx_write_flash_dword(ha, faddr++, *fdata++);
2375                         qla24xx_write_flash_dword(ha, faddr++, *fdata);
2376
2377                         qla24xx_protect_flash(ha);
2378                         break;
2379                 }
2380         }
2381         return QLA_SUCCESS;
2382 }
2383
2384 int
2385 qla2xxx_hw_event_log(scsi_qla_host_t *ha, uint16_t code, uint16_t d1,
2386     uint16_t d2, uint16_t d3)
2387 {
2388 #define QMARK(a, b, c, d) \
2389     cpu_to_le32(LSB(a) << 24 | LSB(b) << 16 | LSB(c) << 8 | LSB(d))
2390
2391         int rval;
2392         uint32_t marker[2], fdata[4];
2393
2394         if (ha->hw_event_start == 0)
2395                 return QLA_FUNCTION_FAILED;
2396
2397         DEBUG2(qla_printk(KERN_WARNING, ha,
2398             "HW event -- code=%x, d1=%x, d2=%x, d3=%x.\n", code, d1, d2, d3));
2399
2400         /* If marker not already found, locate or write.  */
2401         if (!ha->flags.hw_event_marker_found) {
2402                 /* Create marker. */
2403                 marker[0] = QMARK('L', ha->fw_major_version,
2404                     ha->fw_minor_version, ha->fw_subminor_version);
2405                 marker[1] = QMARK(QLA_DRIVER_MAJOR_VER, QLA_DRIVER_MINOR_VER,
2406                     QLA_DRIVER_PATCH_VER, QLA_DRIVER_BETA_VER);
2407
2408                 /* Locate marker. */
2409                 ha->hw_event_ptr = ha->hw_event_start;
2410                 for (;;) {
2411                         qla24xx_read_flash_data(ha, fdata, ha->hw_event_ptr,
2412                             4);
2413                         if (fdata[0] == __constant_cpu_to_le32(0xffffffff) &&
2414                             fdata[1] == __constant_cpu_to_le32(0xffffffff))
2415                                 break;
2416                         ha->hw_event_ptr += FA_HW_EVENT_ENTRY_SIZE;
2417                         if (ha->hw_event_ptr >=
2418                             ha->hw_event_start + FA_HW_EVENT_SIZE) {
2419                                 DEBUG2(qla_printk(KERN_WARNING, ha,
2420                                     "HW event -- Log Full!\n"));
2421                                 return QLA_MEMORY_ALLOC_FAILED;
2422                         }
2423                         if (fdata[2] == marker[0] && fdata[3] == marker[1]) {
2424                                 ha->flags.hw_event_marker_found = 1;
2425                                 break;
2426                         }
2427                 }
2428                 /* No marker, write it. */
2429                 if (!ha->flags.hw_event_marker_found) {
2430                         rval = qla2xxx_hw_event_store(ha, marker);
2431                         if (rval != QLA_SUCCESS) {
2432                                 DEBUG2(qla_printk(KERN_WARNING, ha,
2433                                     "HW event -- Failed marker write=%x.!\n",
2434                                     rval));
2435                                 return rval;
2436                         }
2437                         ha->flags.hw_event_marker_found = 1;
2438                 }
2439         }
2440
2441         /* Store error.  */
2442         fdata[0] = cpu_to_le32(code << 16 | d1);
2443         fdata[1] = cpu_to_le32(d2 << 16 | d3);
2444         rval = qla2xxx_hw_event_store(ha, fdata);
2445         if (rval != QLA_SUCCESS) {
2446                 DEBUG2(qla_printk(KERN_WARNING, ha,
2447                     "HW event -- Failed error write=%x.!\n",
2448                     rval));
2449         }
2450
2451         return rval;
2452 }