git.oblomov.eu Git - linux-2.6/blob - arch/arm/mach-ns9xxx/board-a9m9750dev.c

   1 /*
   2  * arch/arm/mach-ns9xxx/board-a9m9750dev.c
   3  *
   4  * Copyright (C) 2006,2007 by Digi International Inc.
   5  * All rights reserved.
   6  *
   7  * This program is free software; you can redistribute it and/or modify it
   8  * under the terms of the GNU General Public License version 2 as published by
   9  * the Free Software Foundation.
  10  */
  11 #include <linux/platform_device.h>
  12 #include <linux/serial_8250.h>
  13 #include <linux/irq.h>
  14
  15 #include <asm/mach/map.h>
  16 #include <asm/gpio.h>
  17
  18 #include <asm/arch-ns9xxx/board.h>
  19 #include <asm/arch-ns9xxx/regs-sys.h>
  20 #include <asm/arch-ns9xxx/regs-mem.h>
  21 #include <asm/arch-ns9xxx/regs-bbu.h>
  22 #include <asm/arch-ns9xxx/regs-board-a9m9750dev.h>
  23
  24 #include "board-a9m9750dev.h"
  25
  26 static struct map_desc board_a9m9750dev_io_desc[] __initdata = {
  27         { /* FPGA on CS0 */
  28                 .virtual = io_p2v(NS9XXX_CSxSTAT_PHYS(0)),
  29                 .pfn = __phys_to_pfn(NS9XXX_CSxSTAT_PHYS(0)),
  30                 .length = NS9XXX_CS0STAT_LENGTH,
  31                 .type = MT_DEVICE,
  32         },
  33 };
  34
  35 void __init board_a9m9750dev_map_io(void)
  36 {
  37         iotable_init(board_a9m9750dev_io_desc,
  38                      ARRAY_SIZE(board_a9m9750dev_io_desc));
  39 }
  40
  41 static void a9m9750dev_fpga_ack_irq(unsigned int irq)
  42 {
  43         /* nothing */
  44 }
  45
  46 static void a9m9750dev_fpga_mask_irq(unsigned int irq)
  47 {
  48         u8 ier;
  49
  50         ier = __raw_readb(FPGA_IER);
  51
  52         ier &= ~(1 << (irq - FPGA_IRQ(0)));
  53
  54         __raw_writeb(ier, FPGA_IER);
  55 }
  56
  57 static void a9m9750dev_fpga_maskack_irq(unsigned int irq)
  58 {
  59         a9m9750dev_fpga_mask_irq(irq);
  60         a9m9750dev_fpga_ack_irq(irq);
  61 }
  62
  63 static void a9m9750dev_fpga_unmask_irq(unsigned int irq)
  64 {
  65         u8 ier;
  66
  67         ier = __raw_readb(FPGA_IER);
  68
  69         ier |= 1 << (irq - FPGA_IRQ(0));
  70
  71         __raw_writeb(ier, FPGA_IER);
  72 }
  73
  74 static struct irq_chip a9m9750dev_fpga_chip = {
  75         .ack            = a9m9750dev_fpga_ack_irq,
  76         .mask           = a9m9750dev_fpga_mask_irq,
  77         .mask_ack       = a9m9750dev_fpga_maskack_irq,
  78         .unmask         = a9m9750dev_fpga_unmask_irq,
  79 };
  80
  81 static void a9m9750dev_fpga_demux_handler(unsigned int irq,
  82                 struct irq_desc *desc)
  83 {
  84         u8 stat = __raw_readb(FPGA_ISR);
  85
  86         desc->chip->mask_ack(irq);
  87
  88         while (stat != 0) {
  89                 int irqno = fls(stat) - 1;
  90                 struct irq_desc *fpgadesc;
  91
  92                 stat &= ~(1 << irqno);
  93
  94                 fpgadesc = irq_desc + FPGA_IRQ(irqno);
  95
  96                 desc_handle_irq(FPGA_IRQ(irqno), fpgadesc);
  97         }
  98
  99         desc->chip->unmask(irq);
 100 }
 101
 102 void __init board_a9m9750dev_init_irq(void)
 103 {
 104         u32 eic;
 105         int i;
 106
 107         if (gpio_request(11, "board a9m9750dev extirq2") == 0)
 108                 ns9xxx_gpio_configure(11, 0, 1);
 109         else
 110                 printk(KERN_ERR "%s: cannot get gpio 11 for IRQ_EXT2\n",
 111                                 __func__);
 112
 113         for (i = FPGA_IRQ(0); i <= FPGA_IRQ(7); ++i) {
 114                 set_irq_chip(i, &a9m9750dev_fpga_chip);
 115                 set_irq_handler(i, handle_level_irq);
 116                 set_irq_flags(i, IRQF_VALID);
 117         }
 118
 119         /* IRQ_EXT2: level sensitive + active low */
 120         eic = __raw_readl(SYS_EIC(2));
 121         REGSET(eic, SYS_EIC, PLTY, AL);
 122         REGSET(eic, SYS_EIC, LVEDG, LEVEL);
 123         __raw_writel(eic, SYS_EIC(2));
 124
 125         set_irq_chained_handler(IRQ_EXT2,
 126                         a9m9750dev_fpga_demux_handler);
 127 }
 128
 129 static struct plat_serial8250_port board_a9m9750dev_serial8250_port[] = {
 130         {
 131                 .iobase         = FPGA_UARTA_BASE,
 132                 .membase        = (unsigned char*)FPGA_UARTA_BASE,
 133                 .mapbase        = FPGA_UARTA_BASE,
 134                 .irq            = IRQ_FPGA_UARTA,
 135                 .iotype         = UPIO_MEM,
 136                 .uartclk        = 18432000,
 137                 .regshift       = 0,
 138                 .flags          = UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ,
 139         }, {
 140                 .iobase         = FPGA_UARTB_BASE,
 141                 .membase        = (unsigned char*)FPGA_UARTB_BASE,
 142                 .mapbase        = FPGA_UARTB_BASE,
 143                 .irq            = IRQ_FPGA_UARTB,
 144                 .iotype         = UPIO_MEM,
 145                 .uartclk        = 18432000,
 146                 .regshift       = 0,
 147                 .flags          = UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ,
 148         }, {
 149                 .iobase         = FPGA_UARTC_BASE,
 150                 .membase        = (unsigned char*)FPGA_UARTC_BASE,
 151                 .mapbase        = FPGA_UARTC_BASE,
 152                 .irq            = IRQ_FPGA_UARTC,
 153                 .iotype         = UPIO_MEM,
 154                 .uartclk        = 18432000,
 155                 .regshift       = 0,
 156                 .flags          = UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ,
 157         }, {
 158                 .iobase         = FPGA_UARTD_BASE,
 159                 .membase        = (unsigned char*)FPGA_UARTD_BASE,
 160                 .mapbase        = FPGA_UARTD_BASE,
 161                 .irq            = IRQ_FPGA_UARTD,
 162                 .iotype         = UPIO_MEM,
 163                 .uartclk        = 18432000,
 164                 .regshift       = 0,
 165                 .flags          = UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ,
 166         }, {
 167                 /* end marker */
 168         },
 169 };
 170
 171 static struct platform_device board_a9m9750dev_serial_device = {
 172         .name = "serial8250",
 173         .dev = {
 174                 .platform_data = board_a9m9750dev_serial8250_port,
 175         },
 176 };
 177
 178 static struct platform_device *board_a9m9750dev_devices[] __initdata = {
 179         &board_a9m9750dev_serial_device,
 180 };
 181
 182 void __init board_a9m9750dev_init_machine(void)
 183 {
 184         u32 reg;
 185
 186         /* setup static CS0: memory base ... */
 187         reg = __raw_readl(SYS_SMCSSMB(0));
 188         REGSETIM(reg, SYS_SMCSSMB, CSxB, NS9XXX_CSxSTAT_PHYS(0) >> 12);
 189         __raw_writel(reg, SYS_SMCSSMB(0));
 190
 191         /* ... and mask */
 192         reg = __raw_readl(SYS_SMCSSMM(0));
 193         REGSETIM(reg, SYS_SMCSSMM, CSxM, 0xfffff);
 194         REGSET(reg, SYS_SMCSSMM, CSEx, EN);
 195         __raw_writel(reg, SYS_SMCSSMM(0));
 196
 197         /* setup static CS0: memory configuration */
 198         reg = __raw_readl(MEM_SMC(0));
 199         REGSET(reg, MEM_SMC, PSMC, OFF);
 200         REGSET(reg, MEM_SMC, BSMC, OFF);
 201         REGSET(reg, MEM_SMC, EW, OFF);
 202         REGSET(reg, MEM_SMC, PB, 1);
 203         REGSET(reg, MEM_SMC, PC, AL);
 204         REGSET(reg, MEM_SMC, PM, DIS);
 205         REGSET(reg, MEM_SMC, MW, 8);
 206         __raw_writel(reg, MEM_SMC(0));
 207
 208         /* setup static CS0: timing */
 209         __raw_writel(0x2, MEM_SMWED(0));
 210         __raw_writel(0x2, MEM_SMOED(0));
 211         __raw_writel(0x6, MEM_SMRD(0));
 212         __raw_writel(0x6, MEM_SMWD(0));
 213
 214         platform_add_devices(board_a9m9750dev_devices,
 215                         ARRAY_SIZE(board_a9m9750dev_devices));
 216 }