Merge branch 'for-linus' of master.kernel.org:/pub/scm/linux/kernel/git/roland/infiniband
[linux-2.6] / arch / mips / mips-boards / malta / malta_setup.c
1 /*
2  * Carsten Langgaard, carstenl@mips.com
3  * Copyright (C) 2000 MIPS Technologies, Inc.  All rights reserved.
4  *
5  *  This program is free software; you can distribute it and/or modify it
6  *  under the terms of the GNU General Public License (Version 2) as
7  *  published by the Free Software Foundation.
8  *
9  *  This program is distributed in the hope it will be useful, but WITHOUT
10  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
12  *  for more details.
13  *
14  *  You should have received a copy of the GNU General Public License along
15  *  with this program; if not, write to the Free Software Foundation, Inc.,
16  *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
17  */
18 #include <linux/init.h>
19 #include <linux/sched.h>
20 #include <linux/ioport.h>
21 #include <linux/pci.h>
22 #include <linux/tty.h>
23
24 #ifdef CONFIG_MTD
25 #include <linux/mtd/partitions.h>
26 #include <linux/mtd/physmap.h>
27 #include <linux/mtd/mtd.h>
28 #include <linux/mtd/map.h>
29 #endif
30
31 #include <asm/cpu.h>
32 #include <asm/bootinfo.h>
33 #include <asm/irq.h>
34 #include <asm/mips-boards/generic.h>
35 #include <asm/mips-boards/prom.h>
36 #include <asm/mips-boards/malta.h>
37 #include <asm/mips-boards/maltaint.h>
38 #include <asm/dma.h>
39 #include <asm/time.h>
40 #include <asm/traps.h>
41 #ifdef CONFIG_VT
42 #include <linux/console.h>
43 #endif
44
45 extern void mips_reboot_setup(void);
46 extern void mips_time_init(void);
47 extern void mips_timer_setup(struct irqaction *irq);
48 extern unsigned long mips_rtc_get_time(void);
49
50 #ifdef CONFIG_KGDB
51 extern void kgdb_config(void);
52 #endif
53
54 struct resource standard_io_resources[] = {
55         { .name = "dma1", .start = 0x00, .end = 0x1f, .flags = IORESOURCE_BUSY },
56         { .name = "timer", .start = 0x40, .end = 0x5f, .flags = IORESOURCE_BUSY },
57         { .name = "keyboard", .start = 0x60, .end = 0x6f, .flags = IORESOURCE_BUSY },
58         { .name = "dma page reg", .start = 0x80, .end = 0x8f, .flags = IORESOURCE_BUSY },
59         { .name = "dma2", .start = 0xc0, .end = 0xdf, .flags = IORESOURCE_BUSY },
60 };
61
62 #ifdef CONFIG_MTD
63 static struct mtd_partition malta_mtd_partitions[] = {
64         {
65                 .name =         "YAMON",
66                 .offset =       0x0,
67                 .size =         0x100000,
68                 .mask_flags =   MTD_WRITEABLE
69         },
70         {
71                 .name =         "User FS",
72                 .offset =       0x100000,
73                 .size =         0x2e0000
74         },
75         {
76                 .name =         "Board Config",
77                 .offset =       0x3e0000,
78                 .size =         0x020000,
79                 .mask_flags =   MTD_WRITEABLE
80         }
81 };
82
83 #define number_partitions       (sizeof(malta_mtd_partitions)/sizeof(struct mtd_partition))
84 #endif
85
86 const char *get_system_type(void)
87 {
88         return "MIPS Malta";
89 }
90
91 #ifdef CONFIG_BLK_DEV_FD
92 void __init fd_activate(void)
93 {
94         /*
95          * Activate Floppy Controller in the SMSC FDC37M817 Super I/O
96          * Controller.
97          * Done by YAMON 2.00 onwards
98          */
99         /* Entering config state. */
100         SMSC_WRITE(SMSC_CONFIG_ENTER, SMSC_CONFIG_REG);
101
102         /* Activate floppy controller. */
103         SMSC_WRITE(SMSC_CONFIG_DEVNUM, SMSC_CONFIG_REG);
104         SMSC_WRITE(SMSC_CONFIG_DEVNUM_FLOPPY, SMSC_DATA_REG);
105         SMSC_WRITE(SMSC_CONFIG_ACTIVATE, SMSC_CONFIG_REG);
106         SMSC_WRITE(SMSC_CONFIG_ACTIVATE_ENABLE, SMSC_DATA_REG);
107
108         /* Exit config state. */
109         SMSC_WRITE(SMSC_CONFIG_EXIT, SMSC_CONFIG_REG);
110 }
111 #endif
112
113 void __init plat_mem_setup(void)
114 {
115         unsigned int i;
116
117         mips_pcibios_init();
118
119         /* Request I/O space for devices used on the Malta board. */
120         for (i = 0; i < ARRAY_SIZE(standard_io_resources); i++)
121                 request_resource(&ioport_resource, standard_io_resources+i);
122
123         /*
124          * Enable DMA channel 4 (cascade channel) in the PIIX4 south bridge.
125          */
126         enable_dma(4);
127
128 #ifdef CONFIG_KGDB
129         kgdb_config ();
130 #endif
131
132         if ((mips_revision_corid == MIPS_REVISION_CORID_BONITO64) ||
133             (mips_revision_corid == MIPS_REVISION_CORID_CORE_20K) ||
134             (mips_revision_corid == MIPS_REVISION_CORID_CORE_EMUL_BON)) {
135                 char *argptr;
136
137                 argptr = prom_getcmdline();
138                 if (strstr(argptr, "debug")) {
139                         BONITO_BONGENCFG |= BONITO_BONGENCFG_DEBUGMODE;
140                         printk ("Enabled Bonito debug mode\n");
141                 }
142                 else
143                         BONITO_BONGENCFG &= ~BONITO_BONGENCFG_DEBUGMODE;
144
145 #ifdef CONFIG_DMA_COHERENT
146                 if (BONITO_PCICACHECTRL & BONITO_PCICACHECTRL_CPUCOH_PRES) {
147                         BONITO_PCICACHECTRL |= BONITO_PCICACHECTRL_CPUCOH_EN;
148                         printk("Enabled Bonito CPU coherency\n");
149
150                         argptr = prom_getcmdline();
151                         if (strstr(argptr, "iobcuncached")) {
152                                 BONITO_PCICACHECTRL &= ~BONITO_PCICACHECTRL_IOBCCOH_EN;
153                                 BONITO_PCIMEMBASECFG = BONITO_PCIMEMBASECFG &
154                                         ~(BONITO_PCIMEMBASECFG_MEMBASE0_CACHED |
155                                           BONITO_PCIMEMBASECFG_MEMBASE1_CACHED);
156                                 printk("Disabled Bonito IOBC coherency\n");
157                         }
158                         else {
159                                 BONITO_PCICACHECTRL |= BONITO_PCICACHECTRL_IOBCCOH_EN;
160                                 BONITO_PCIMEMBASECFG |=
161                                         (BONITO_PCIMEMBASECFG_MEMBASE0_CACHED |
162                                          BONITO_PCIMEMBASECFG_MEMBASE1_CACHED);
163                                 printk("Disabled Bonito IOBC coherency\n");
164                         }
165                 }
166                 else
167                         panic("Hardware DMA cache coherency not supported");
168
169 #endif
170         }
171 #ifdef CONFIG_DMA_COHERENT
172         else {
173                 panic("Hardware DMA cache coherency not supported");
174         }
175 #endif
176
177 #ifdef CONFIG_BLK_DEV_IDE
178         /* Check PCI clock */
179         {
180                 int jmpr = (*((volatile unsigned int *)ioremap(MALTA_JMPRS_REG, sizeof(unsigned int))) >> 2) & 0x07;
181                 static const int pciclocks[] __initdata = {
182                         33, 20, 25, 30, 12, 16, 37, 10
183                 };
184                 int pciclock = pciclocks[jmpr];
185                 char *argptr = prom_getcmdline();
186
187                 if (pciclock != 33 && !strstr (argptr, "idebus=")) {
188                         printk("WARNING: PCI clock is %dMHz, setting idebus\n", pciclock);
189                         argptr += strlen(argptr);
190                         sprintf (argptr, " idebus=%d", pciclock);
191                         if (pciclock < 20 || pciclock > 66)
192                                 printk ("WARNING: IDE timing calculations will be incorrect\n");
193                 }
194         }
195 #endif
196 #ifdef CONFIG_BLK_DEV_FD
197         fd_activate ();
198 #endif
199 #ifdef CONFIG_VT
200 #if defined(CONFIG_VGA_CONSOLE)
201         screen_info = (struct screen_info) {
202                 0, 25,                  /* orig-x, orig-y */
203                 0,                      /* unused */
204                 0,                      /* orig-video-page */
205                 0,                      /* orig-video-mode */
206                 80,                     /* orig-video-cols */
207                 0,0,0,                  /* ega_ax, ega_bx, ega_cx */
208                 25,                     /* orig-video-lines */
209                 VIDEO_TYPE_VGAC,        /* orig-video-isVGA */
210                 16                      /* orig-video-points */
211         };
212 #endif
213 #endif
214
215 #ifdef CONFIG_MTD
216         /*
217          * Support for MTD on Malta. Use the generic physmap driver
218          */
219         physmap_configure(0x1e000000, 0x400000, 4, NULL);
220         physmap_set_partitions(malta_mtd_partitions, number_partitions);
221 #endif
222
223         mips_reboot_setup();
224
225         board_time_init = mips_time_init;
226         board_timer_setup = mips_timer_setup;
227         rtc_mips_get_time = mips_rtc_get_time;
228 }