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   1 /*
   2  * Copyright (C) 2002, Erich Focht, NEC
   3  *
   4  * All rights reserved.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  */
  11 #ifndef _ASM_IA64_TOPOLOGY_H
  12 #define _ASM_IA64_TOPOLOGY_H
  13
  14 #include <asm/acpi.h>
  15 #include <asm/numa.h>
  16 #include <asm/smp.h>
  17
  18 #ifdef CONFIG_NUMA
  19
  20 /* Nodes w/o CPUs are preferred for memory allocations, see build_zonelists */
  21 #define PENALTY_FOR_NODE_WITH_CPUS 255
  22
  23 /*
  24  * Distance above which we begin to use zone reclaim
  25  */
  26 #define RECLAIM_DISTANCE 15
  27
  28 /*
  29  * Returns the number of the node containing CPU 'cpu'
  30  */
  31 #define cpu_to_node(cpu) (int)(cpu_to_node_map[cpu])
  32
  33 /*
  34  * Returns a bitmask of CPUs on Node 'node'.
  35  */
  36 #define node_to_cpumask(node) (node_to_cpu_mask[node])
  37
  38 /*
  39  * Returns the number of the node containing Node 'nid'.
  40  * Not implemented here. Multi-level hierarchies detected with
  41  * the help of node_distance().
  42  */
  43 #define parent_node(nid) (nid)
  44
  45 /*
  46  * Returns the number of the first CPU on Node 'node'.
  47  */
  48 #define node_to_first_cpu(node) (first_cpu(node_to_cpumask(node)))
  49
  50 /*
  51  * Determines the node for a given pci bus
  52  */
  53 #define pcibus_to_node(bus) PCI_CONTROLLER(bus)->node
  54
  55 void build_cpu_to_node_map(void);
  56
  57 #define SD_CPU_INIT (struct sched_domain) {             \
  58         .span                   = CPU_MASK_NONE,        \
  59         .parent                 = NULL,                 \
  60         .child                  = NULL,                 \
  61         .groups                 = NULL,                 \
  62         .min_interval           = 1,                    \
  63         .max_interval           = 4,                    \
  64         .busy_factor            = 64,                   \
  65         .imbalance_pct          = 125,                  \
  66         .cache_nice_tries       = 2,                    \
  67         .busy_idx               = 2,                    \
  68         .idle_idx               = 1,                    \
  69         .newidle_idx            = 2,                    \
  70         .wake_idx               = 1,                    \
  71         .forkexec_idx           = 1,                    \
  72         .flags                  = SD_LOAD_BALANCE       \
  73                                 | SD_BALANCE_NEWIDLE    \
  74                                 | SD_BALANCE_EXEC       \
  75                                 | SD_WAKE_AFFINE,       \
  76         .last_balance           = jiffies,              \
  77         .balance_interval       = 1,                    \
  78         .nr_balance_failed      = 0,                    \
  79 }
  80
  81 /* sched_domains SD_NODE_INIT for IA64 NUMA machines */
  82 #define SD_NODE_INIT (struct sched_domain) {            \
  83         .span                   = CPU_MASK_NONE,        \
  84         .parent                 = NULL,                 \
  85         .child                  = NULL,                 \
  86         .groups                 = NULL,                 \
  87         .min_interval           = 8,                    \
  88         .max_interval           = 8*(min(num_online_cpus(), 32)), \
  89         .busy_factor            = 64,                   \
  90         .imbalance_pct          = 125,                  \
  91         .cache_nice_tries       = 2,                    \
  92         .busy_idx               = 3,                    \
  93         .idle_idx               = 2,                    \
  94         .newidle_idx            = 2,                    \
  95         .wake_idx               = 1,                    \
  96         .forkexec_idx           = 1,                    \
  97         .flags                  = SD_LOAD_BALANCE       \
  98                                 | SD_BALANCE_EXEC       \
  99                                 | SD_BALANCE_FORK       \
 100                                 | SD_SERIALIZE          \
 101                                 | SD_WAKE_BALANCE,      \
 102         .last_balance           = jiffies,              \
 103         .balance_interval       = 64,                   \
 104         .nr_balance_failed      = 0,                    \
 105 }
 106
 107 #endif /* CONFIG_NUMA */
 108
 109 #ifdef CONFIG_SMP
 110 #define topology_physical_package_id(cpu)       (cpu_data(cpu)->socket_id)
 111 #define topology_core_id(cpu)                   (cpu_data(cpu)->core_id)
 112 #define topology_core_siblings(cpu)             (cpu_core_map[cpu])
 113 #define topology_thread_siblings(cpu)           (per_cpu(cpu_sibling_map, cpu))
 114 #define smt_capable()                           (smp_num_siblings > 1)
 115 #endif
 116
 117 extern void arch_fix_phys_package_id(int num, u32 slot);
 118
 119 #define pcibus_to_cpumask(bus)  (pcibus_to_node(bus) == -1 ? \
 120                                         CPU_MASK_ALL : \
 121                                         node_to_cpumask(pcibus_to_node(bus)) \
 122                                 )
 123
 124 #include <asm-generic/topology.h>
 125
 126 #endif /* _ASM_IA64_TOPOLOGY_H */