2 * arch/arm/plat-omap/include/mach/mux.h
4 * Table of the Omap register configurations for the FUNC_MUX and
5 * PULL_DWN combinations.
7 * Copyright (C) 2004 - 2008 Texas Instruments Inc.
8 * Copyright (C) 2003 - 2008 Nokia Corporation
10 * Written by Tony Lindgren
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
26 * NOTE: Please use the following naming style for new pin entries.
27 * For example, W8_1610_MMC2_DAT0, where:
29 * - 1610 = 1510 or 1610, none if common for both 1510 and 1610
30 * - MMC2_DAT0 = function
33 #ifndef __ASM_ARCH_MUX_H
34 #define __ASM_ARCH_MUX_H
36 #define PU_PD_SEL_NA 0 /* No pu_pd reg available */
37 #define PULL_DWN_CTRL_NA 0 /* No pull-down control needed */
39 #ifdef CONFIG_OMAP_MUX_DEBUG
40 #define MUX_REG(reg, mode_offset, mode) .mux_reg_name = "FUNC_MUX_CTRL_"#reg, \
41 .mux_reg = FUNC_MUX_CTRL_##reg, \
42 .mask_offset = mode_offset, \
45 #define PULL_REG(reg, bit, status) .pull_name = "PULL_DWN_CTRL_"#reg, \
46 .pull_reg = PULL_DWN_CTRL_##reg, \
50 #define PU_PD_REG(reg, status) .pu_pd_name = "PU_PD_SEL_"#reg, \
51 .pu_pd_reg = PU_PD_SEL_##reg, \
54 #define MUX_REG_730(reg, mode_offset, mode) .mux_reg_name = "OMAP730_IO_CONF_"#reg, \
55 .mux_reg = OMAP730_IO_CONF_##reg, \
56 .mask_offset = mode_offset, \
59 #define PULL_REG_730(reg, bit, status) .pull_name = "OMAP730_IO_CONF_"#reg, \
60 .pull_reg = OMAP730_IO_CONF_##reg, \
64 #define MUX_REG_850(reg, mode_offset, mode) .mux_reg_name = "OMAP850_IO_CONF_"#reg, \
65 .mux_reg = OMAP850_IO_CONF_##reg, \
66 .mask_offset = mode_offset, \
69 #define PULL_REG_850(reg, bit, status) .pull_name = "OMAP850_IO_CONF_"#reg, \
70 .pull_reg = OMAP850_IO_CONF_##reg, \
76 #define MUX_REG(reg, mode_offset, mode) .mux_reg = FUNC_MUX_CTRL_##reg, \
77 .mask_offset = mode_offset, \
80 #define PULL_REG(reg, bit, status) .pull_reg = PULL_DWN_CTRL_##reg, \
84 #define PU_PD_REG(reg, status) .pu_pd_reg = PU_PD_SEL_##reg, \
87 #define MUX_REG_730(reg, mode_offset, mode) \
88 .mux_reg = OMAP730_IO_CONF_##reg, \
89 .mask_offset = mode_offset, \
92 #define PULL_REG_730(reg, bit, status) .pull_reg = OMAP730_IO_CONF_##reg, \
96 #define MUX_REG_850(reg, mode_offset, mode) \
97 .mux_reg = OMAP850_IO_CONF_##reg, \
98 .mask_offset = mode_offset, \
101 #define PULL_REG_850(reg, bit, status) .pull_reg = OMAP850_IO_CONF_##reg, \
105 #endif /* CONFIG_OMAP_MUX_DEBUG */
107 #define MUX_CFG(desc, mux_reg, mode_offset, mode, \
108 pull_reg, pull_bit, pull_status, \
109 pu_pd_reg, pu_pd_status, debug_status) \
112 .debug = debug_status, \
113 MUX_REG(mux_reg, mode_offset, mode) \
114 PULL_REG(pull_reg, pull_bit, pull_status) \
115 PU_PD_REG(pu_pd_reg, pu_pd_status) \
120 * OMAP730/850 has a slightly different config for the pin mux.
121 * - config regs are the OMAP730_IO_CONF_x regs (see omap730.h) regs and
122 * not the FUNC_MUX_CTRL_x regs from hardware.h
123 * - for pull-up/down, only has one enable bit which is is in the same register
126 #define MUX_CFG_730(desc, mux_reg, mode_offset, mode, \
127 pull_bit, pull_status, debug_status)\
130 .debug = debug_status, \
131 MUX_REG_730(mux_reg, mode_offset, mode) \
132 PULL_REG_730(mux_reg, pull_bit, pull_status) \
136 #define MUX_CFG_850(desc, mux_reg, mode_offset, mode, \
137 pull_bit, pull_status, debug_status)\
140 .debug = debug_status, \
141 MUX_REG_850(mux_reg, mode_offset, mode) \
142 PULL_REG_850(mux_reg, pull_bit, pull_status) \
147 #define MUX_CFG_24XX(desc, reg_offset, mode, \
148 pull_en, pull_mode, dbg) \
152 .mux_reg = reg_offset, \
154 .pull_val = pull_en, \
155 .pu_pd_val = pull_mode, \
158 /* 24xx/34xx mux bit defines */
159 #define OMAP2_PULL_ENA (1 << 3)
160 #define OMAP2_PULL_UP (1 << 4)
161 #define OMAP2_ALTELECTRICALSEL (1 << 5)
163 /* 34xx specific mux bit defines */
164 #define OMAP3_INPUT_EN (1 << 8)
165 #define OMAP3_OFF_EN (1 << 9)
166 #define OMAP3_OFFOUT_EN (1 << 10)
167 #define OMAP3_OFFOUT_VAL (1 << 11)
168 #define OMAP3_OFF_PULL_EN (1 << 12)
169 #define OMAP3_OFF_PULL_UP (1 << 13)
170 #define OMAP3_WAKEUP_EN (1 << 14)
172 /* 34xx mux mode options for each pin. See TRM for options */
173 #define OMAP34XX_MUX_MODE0 0
174 #define OMAP34XX_MUX_MODE1 1
175 #define OMAP34XX_MUX_MODE2 2
176 #define OMAP34XX_MUX_MODE3 3
177 #define OMAP34XX_MUX_MODE4 4
178 #define OMAP34XX_MUX_MODE5 5
179 #define OMAP34XX_MUX_MODE6 6
180 #define OMAP34XX_MUX_MODE7 7
182 /* 34xx active pin states */
183 #define OMAP34XX_PIN_OUTPUT 0
184 #define OMAP34XX_PIN_INPUT OMAP3_INPUT_EN
185 #define OMAP34XX_PIN_INPUT_PULLUP (OMAP2_PULL_ENA | OMAP3_INPUT_EN \
187 #define OMAP34XX_PIN_INPUT_PULLDOWN (OMAP2_PULL_ENA | OMAP3_INPUT_EN)
189 /* 34xx off mode states */
190 #define OMAP34XX_PIN_OFF_NONE 0
191 #define OMAP34XX_PIN_OFF_OUTPUT_HIGH (OMAP3_OFF_EN | OMAP3_OFFOUT_EN \
193 #define OMAP34XX_PIN_OFF_OUTPUT_LOW (OMAP3_OFF_EN | OMAP3_OFFOUT_EN)
194 #define OMAP34XX_PIN_OFF_INPUT_PULLUP (OMAP3_OFF_EN | OMAP3_OFF_PULL_EN \
196 #define OMAP34XX_PIN_OFF_INPUT_PULLDOWN (OMAP3_OFF_EN | OMAP3_OFF_PULL_EN)
197 #define OMAP34XX_PIN_OFF_WAKEUPENABLE OMAP3_WAKEUP_EN
199 #define MUX_CFG_34XX(desc, reg_offset, mux_value) { \
202 .mux_reg = reg_offset, \
203 .mux_val = mux_value \
208 const unsigned int mux_reg;
211 #if defined(CONFIG_ARCH_OMAP34XX)
212 u16 mux_val; /* Wake-up, off mode, pull, mux mode */
215 #if defined(CONFIG_ARCH_OMAP1) || defined(CONFIG_ARCH_OMAP24XX)
216 const unsigned char mask_offset;
217 const unsigned char mask;
219 const char *pull_name;
220 const unsigned int pull_reg;
221 const unsigned char pull_val;
222 const unsigned char pull_bit;
224 const char *pu_pd_name;
225 const unsigned int pu_pd_reg;
226 const unsigned char pu_pd_val;
229 #if defined(CONFIG_OMAP_MUX_DEBUG) || defined(CONFIG_OMAP_MUX_WARNINGS)
230 const char *mux_reg_name;
236 /* OMAP 730 keyboard */
255 /* OMAP 850 keyboard */
274 enum omap1xxx_index {
275 /* UART1 (BT_UART_GATING)*/
279 /* UART2 (COM_UART_GATING)*/
285 /* UART3 (GIGA_UART_GATING) */
291 UART3_BCLK, /* 12MHz clock out */
298 /* USB master generic */
381 V5_1610_MMC2_DATDIR0,
382 W19_1610_MMC2_DATDIR1,
385 /* OMAP-1610 External Trace Interface */
408 /* OMAP-1610 uWire */
427 /* OMAP-1610 Flash */
428 L3_1610_FLASH_CS2B_OE,
429 M8_1610_FLASH_CS2B_WE,
439 /* OMAP-1710 MMC CMDDIR and DATDIR0 */
442 P20_1710_MMC_DATDIR0,
444 /* OMAP-1610 USB0 alternate pin configuration */
487 /* Power management */
496 /* CompactFlash controller */
503 /* parallel camera */
527 enum omap24xx_index {
534 /* 24xx Menelaus interrupt */
540 /* 24xx GPMC chipselects, wait pin monitoring */
549 Y15_24XX_MCBSP2_CLKX,
587 /* 24xx external DMA requests */
606 F19_24XX_MMC_DAT_DIR0,
607 E20_24XX_MMC_DAT_DIR1,
608 F18_24XX_MMC_DAT_DIR2,
609 E18_24XX_MMC_DAT_DIR3,
610 G18_24XX_MMC_CMD_DIR,
635 AA4_24XX_USB2_TLLSE0,
652 /* 24xx Menelaus Keypad GPIO */
671 AD9_2430_USB0HS_DATA3,
672 Y11_2430_USB0HS_DATA4,
673 AD7_2430_USB0HS_DATA5,
674 AE7_2430_USB0HS_DATA6,
675 AD4_2430_USB0HS_DATA2,
676 AF9_2430_USB0HS_DATA0,
677 AE6_2430_USB0HS_DATA1,
682 AC7_2430_USB0HS_DATA7,
687 AB2_2430_MCBSP1_CLKR,
694 AC10_2430_MCBSP2_FSX,
695 AD16_2430_MCBSP2_CLX,
698 AC10_2430_MCBSP2_FSX_OFF,
699 AD16_2430_MCBSP2_CLX_OFF,
700 AE13_2430_MCBSP2_DX_OFF,
701 AD13_2430_MCBSP2_DR_OFF,
703 AC9_2430_MCBSP3_CLKX,
711 AC25_2430_MCBSP4_FSX,
713 AE16_2430_MCBSP5_CLKX,
714 AF12_2430_MCBSP5_FSX,
720 AD15_2430_MCSPI1_SIMO,
721 AE17_2430_MCSPI1_SOMI,
724 /* Touchscreen GPIO */
729 enum omap34xx_index {
740 /* PHY - HSUSB: 12-pin ULPI PHY: Port 1*/
741 Y8_3430_USB1HS_PHY_CLK,
742 Y9_3430_USB1HS_PHY_STP,
743 AA14_3430_USB1HS_PHY_DIR,
744 AA11_3430_USB1HS_PHY_NXT,
745 W13_3430_USB1HS_PHY_DATA0,
746 W12_3430_USB1HS_PHY_DATA1,
747 W11_3430_USB1HS_PHY_DATA2,
748 Y11_3430_USB1HS_PHY_DATA3,
749 W9_3430_USB1HS_PHY_DATA4,
750 Y12_3430_USB1HS_PHY_DATA5,
751 W8_3430_USB1HS_PHY_DATA6,
752 Y13_3430_USB1HS_PHY_DATA7,
754 /* PHY - HSUSB: 12-pin ULPI PHY: Port 2*/
755 AA8_3430_USB2HS_PHY_CLK,
756 AA10_3430_USB2HS_PHY_STP,
757 AA9_3430_USB2HS_PHY_DIR,
758 AB11_3430_USB2HS_PHY_NXT,
759 AB10_3430_USB2HS_PHY_DATA0,
760 AB9_3430_USB2HS_PHY_DATA1,
761 W3_3430_USB2HS_PHY_DATA2,
762 T4_3430_USB2HS_PHY_DATA3,
763 T3_3430_USB2HS_PHY_DATA4,
764 R3_3430_USB2HS_PHY_DATA5,
765 R4_3430_USB2HS_PHY_DATA6,
766 T2_3430_USB2HS_PHY_DATA7,
769 /* TLL - HSUSB: 12-pin TLL Port 1*/
770 Y8_3430_USB1HS_TLL_CLK,
771 Y9_3430_USB1HS_TLL_STP,
772 AA14_3430_USB1HS_TLL_DIR,
773 AA11_3430_USB1HS_TLL_NXT,
774 W13_3430_USB1HS_TLL_DATA0,
775 W12_3430_USB1HS_TLL_DATA1,
776 W11_3430_USB1HS_TLL_DATA2,
777 Y11_3430_USB1HS_TLL_DATA3,
778 W9_3430_USB1HS_TLL_DATA4,
779 Y12_3430_USB1HS_TLL_DATA5,
780 W8_3430_USB1HS_TLL_DATA6,
781 Y13_3430_USB1HS_TLL_DATA7,
783 /* TLL - HSUSB: 12-pin TLL Port 2*/
784 AA8_3430_USB2HS_TLL_CLK,
785 AA10_3430_USB2HS_TLL_STP,
786 AA9_3430_USB2HS_TLL_DIR,
787 AB11_3430_USB2HS_TLL_NXT,
788 AB10_3430_USB2HS_TLL_DATA0,
789 AB9_3430_USB2HS_TLL_DATA1,
790 W3_3430_USB2HS_TLL_DATA2,
791 T4_3430_USB2HS_TLL_DATA3,
792 T3_3430_USB2HS_TLL_DATA4,
793 R3_3430_USB2HS_TLL_DATA5,
794 R4_3430_USB2HS_TLL_DATA6,
795 T2_3430_USB2HS_TLL_DATA7,
797 /* TLL - HSUSB: 12-pin TLL Port 3*/
798 AA6_3430_USB3HS_TLL_CLK,
799 AB3_3430_USB3HS_TLL_STP,
800 AA3_3430_USB3HS_TLL_DIR,
801 Y3_3430_USB3HS_TLL_NXT,
802 AA5_3430_USB3HS_TLL_DATA0,
803 Y4_3430_USB3HS_TLL_DATA1,
804 Y5_3430_USB3HS_TLL_DATA2,
805 W5_3430_USB3HS_TLL_DATA3,
806 AB12_3430_USB3HS_TLL_DATA4,
807 AB13_3430_USB3HS_TLL_DATA5,
808 AA13_3430_USB3HS_TLL_DATA6,
809 AA12_3430_USB3HS_TLL_DATA7,
811 /* PHY FSUSB: FS Serial for Port 1 (multiple PHY modes supported) */
812 AF10_3430_USB1FS_PHY_MM1_RXDP,
813 AG9_3430_USB1FS_PHY_MM1_RXDM,
814 W13_3430_USB1FS_PHY_MM1_RXRCV,
815 W12_3430_USB1FS_PHY_MM1_TXSE0,
816 W11_3430_USB1FS_PHY_MM1_TXDAT,
817 Y11_3430_USB1FS_PHY_MM1_TXEN_N,
819 /* PHY FSUSB: FS Serial for Port 2 (multiple PHY modes supported) */
820 AF7_3430_USB2FS_PHY_MM2_RXDP,
821 AH7_3430_USB2FS_PHY_MM2_RXDM,
822 AB10_3430_USB2FS_PHY_MM2_RXRCV,
823 AB9_3430_USB2FS_PHY_MM2_TXSE0,
824 W3_3430_USB2FS_PHY_MM2_TXDAT,
825 T4_3430_USB2FS_PHY_MM2_TXEN_N,
827 /* PHY FSUSB: FS Serial for Port 3 (multiple PHY modes supported) */
828 AH3_3430_USB3FS_PHY_MM3_RXDP,
829 AE3_3430_USB3FS_PHY_MM3_RXDM,
830 AD1_3430_USB3FS_PHY_MM3_RXRCV,
831 AE1_3430_USB3FS_PHY_MM3_TXSE0,
832 AD2_3430_USB3FS_PHY_MM3_TXDAT,
833 AC1_3430_USB3FS_PHY_MM3_TXEN_N,
836 * - normally these are bidirectional, no internal pullup/pulldown
837 * - "_UP" suffix (GPIO3_UP) if internal pullup is configured
838 * - "_DOWN" suffix (GPIO3_DOWN) with internal pulldown
839 * - "_OUT" suffix (GPIO3_OUT) for output-only pins (unlike 24xx)
848 AG4_34XX_GPIO134_OUT,
849 AE4_34XX_GPIO136_OUT,
854 H19_34XX_GPIO164_OUT,
858 struct omap_mux_cfg {
859 struct pin_config *pins;
861 int (*cfg_reg)(const struct pin_config *cfg);
864 #ifdef CONFIG_OMAP_MUX
865 /* setup pin muxing in Linux */
866 extern int omap1_mux_init(void);
867 extern int omap2_mux_init(void);
868 extern int omap_mux_register(struct omap_mux_cfg *);
869 extern int omap_cfg_reg(unsigned long reg_cfg);
871 /* boot loader does it all (no warnings from CONFIG_OMAP_MUX_WARNINGS) */
872 static inline int omap1_mux_init(void) { return 0; }
873 static inline int omap2_mux_init(void) { return 0; }
874 static inline int omap_cfg_reg(unsigned long reg_cfg) { return 0; }