1 /* linux/drivers/spi/spi_s3c24xx.c
3 * Copyright (c) 2006 Ben Dooks
4 * Copyright (c) 2006 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
16 #include <linux/init.h>
17 #include <linux/spinlock.h>
18 #include <linux/workqueue.h>
19 #include <linux/interrupt.h>
20 #include <linux/delay.h>
21 #include <linux/errno.h>
22 #include <linux/err.h>
23 #include <linux/clk.h>
24 #include <linux/platform_device.h>
26 #include <linux/spi/spi.h>
27 #include <linux/spi/spi_bitbang.h>
31 #include <asm/hardware.h>
33 #include <asm/arch/regs-gpio.h>
34 #include <asm/arch/regs-spi.h>
35 #include <asm/arch/spi.h>
38 /* bitbang has to be first */
39 struct spi_bitbang bitbang;
40 struct completion done;
48 const unsigned char *tx;
52 struct resource *ioarea;
53 struct spi_master *master;
54 struct spi_device *curdev;
56 struct s3c2410_spi_info *pdata;
59 #define SPCON_DEFAULT (S3C2410_SPCON_MSTR | S3C2410_SPCON_SMOD_INT)
60 #define SPPIN_DEFAULT (S3C2410_SPPIN_KEEP)
62 static inline struct s3c24xx_spi *to_hw(struct spi_device *sdev)
64 return spi_master_get_devdata(sdev->master);
67 static void s3c24xx_spi_chipsel(struct spi_device *spi, int value)
69 struct s3c24xx_spi *hw = to_hw(spi);
70 unsigned int cspol = spi->mode & SPI_CS_HIGH ? 1 : 0;
74 case BITBANG_CS_INACTIVE:
75 if (hw->pdata->set_cs)
76 hw->pdata->set_cs(hw->pdata, value, cspol);
78 s3c2410_gpio_setpin(hw->pdata->pin_cs, cspol ^ 1);
81 case BITBANG_CS_ACTIVE:
82 spcon = readb(hw->regs + S3C2410_SPCON);
84 if (spi->mode & SPI_CPHA)
85 spcon |= S3C2410_SPCON_CPHA_FMTB;
87 spcon &= ~S3C2410_SPCON_CPHA_FMTB;
89 if (spi->mode & SPI_CPOL)
90 spcon |= S3C2410_SPCON_CPOL_HIGH;
92 spcon &= ~S3C2410_SPCON_CPOL_HIGH;
94 spcon |= S3C2410_SPCON_ENSCK;
96 /* write new configration */
98 writeb(spcon, hw->regs + S3C2410_SPCON);
100 if (hw->pdata->set_cs)
101 hw->pdata->set_cs(hw->pdata, value, cspol);
103 s3c2410_gpio_setpin(hw->pdata->pin_cs, cspol);
110 static int s3c24xx_spi_setupxfer(struct spi_device *spi,
111 struct spi_transfer *t)
113 struct s3c24xx_spi *hw = to_hw(spi);
118 bpw = t ? t->bits_per_word : spi->bits_per_word;
119 hz = t ? t->speed_hz : spi->max_speed_hz;
122 dev_err(&spi->dev, "invalid bits-per-word (%d)\n", bpw);
126 div = clk_get_rate(hw->clk) / hz;
128 /* is clk = pclk / (2 * (pre+1)), or is it
129 * clk = (pclk * 2) / ( pre + 1) */
139 dev_dbg(&spi->dev, "setting pre-scaler to %d (hz %d)\n", div, hz);
140 writeb(div, hw->regs + S3C2410_SPPRE);
142 spin_lock(&hw->bitbang.lock);
143 if (!hw->bitbang.busy) {
144 hw->bitbang.chipselect(spi, BITBANG_CS_INACTIVE);
145 /* need to ndelay for 0.5 clocktick ? */
147 spin_unlock(&hw->bitbang.lock);
152 static int s3c24xx_spi_setup(struct spi_device *spi)
156 if (!spi->bits_per_word)
157 spi->bits_per_word = 8;
159 if ((spi->mode & SPI_LSB_FIRST) != 0)
162 ret = s3c24xx_spi_setupxfer(spi, NULL);
164 dev_err(&spi->dev, "setupxfer returned %d\n", ret);
168 dev_dbg(&spi->dev, "%s: mode %d, %u bpw, %d hz\n",
169 __FUNCTION__, spi->mode, spi->bits_per_word,
175 static inline unsigned int hw_txbyte(struct s3c24xx_spi *hw, int count)
177 return hw->tx ? hw->tx[count] : 0xff;
180 static int s3c24xx_spi_txrx(struct spi_device *spi, struct spi_transfer *t)
182 struct s3c24xx_spi *hw = to_hw(spi);
184 dev_dbg(&spi->dev, "txrx: tx %p, rx %p, len %d\n",
185 t->tx_buf, t->rx_buf, t->len);
192 /* send the first byte */
193 writeb(hw_txbyte(hw, 0), hw->regs + S3C2410_SPTDAT);
194 wait_for_completion(&hw->done);
199 static irqreturn_t s3c24xx_spi_irq(int irq, void *dev)
201 struct s3c24xx_spi *hw = dev;
202 unsigned int spsta = readb(hw->regs + S3C2410_SPSTA);
203 unsigned int count = hw->count;
205 if (spsta & S3C2410_SPSTA_DCOL) {
206 dev_dbg(hw->dev, "data-collision\n");
211 if (!(spsta & S3C2410_SPSTA_READY)) {
212 dev_dbg(hw->dev, "spi not ready for tx?\n");
220 hw->rx[count] = readb(hw->regs + S3C2410_SPRDAT);
225 writeb(hw_txbyte(hw, count), hw->regs + S3C2410_SPTDAT);
233 static int s3c24xx_spi_probe(struct platform_device *pdev)
235 struct s3c24xx_spi *hw;
236 struct spi_master *master;
237 struct spi_board_info *bi;
238 struct resource *res;
242 master = spi_alloc_master(&pdev->dev, sizeof(struct s3c24xx_spi));
243 if (master == NULL) {
244 dev_err(&pdev->dev, "No memory for spi_master\n");
249 hw = spi_master_get_devdata(master);
250 memset(hw, 0, sizeof(struct s3c24xx_spi));
252 hw->master = spi_master_get(master);
253 hw->pdata = pdev->dev.platform_data;
254 hw->dev = &pdev->dev;
256 if (hw->pdata == NULL) {
257 dev_err(&pdev->dev, "No platform data supplied\n");
262 platform_set_drvdata(pdev, hw);
263 init_completion(&hw->done);
265 /* setup the state for the bitbang driver */
267 hw->bitbang.master = hw->master;
268 hw->bitbang.setup_transfer = s3c24xx_spi_setupxfer;
269 hw->bitbang.chipselect = s3c24xx_spi_chipsel;
270 hw->bitbang.txrx_bufs = s3c24xx_spi_txrx;
271 hw->bitbang.master->setup = s3c24xx_spi_setup;
273 dev_dbg(hw->dev, "bitbang at %p\n", &hw->bitbang);
275 /* find and map our resources */
277 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
279 dev_err(&pdev->dev, "Cannot get IORESOURCE_MEM\n");
284 hw->ioarea = request_mem_region(res->start, (res->end - res->start)+1,
287 if (hw->ioarea == NULL) {
288 dev_err(&pdev->dev, "Cannot reserve region\n");
293 hw->regs = ioremap(res->start, (res->end - res->start)+1);
294 if (hw->regs == NULL) {
295 dev_err(&pdev->dev, "Cannot map IO\n");
300 hw->irq = platform_get_irq(pdev, 0);
302 dev_err(&pdev->dev, "No IRQ specified\n");
307 err = request_irq(hw->irq, s3c24xx_spi_irq, 0, pdev->name, hw);
309 dev_err(&pdev->dev, "Cannot claim IRQ\n");
313 hw->clk = clk_get(&pdev->dev, "spi");
314 if (IS_ERR(hw->clk)) {
315 dev_err(&pdev->dev, "No clock for device\n");
316 err = PTR_ERR(hw->clk);
320 /* for the moment, permanently enable the clock */
324 /* program defaults into the registers */
326 writeb(0xff, hw->regs + S3C2410_SPPRE);
327 writeb(SPPIN_DEFAULT, hw->regs + S3C2410_SPPIN);
328 writeb(SPCON_DEFAULT, hw->regs + S3C2410_SPCON);
330 /* setup any gpio we can */
332 if (!hw->pdata->set_cs) {
333 s3c2410_gpio_setpin(hw->pdata->pin_cs, 1);
334 s3c2410_gpio_cfgpin(hw->pdata->pin_cs, S3C2410_GPIO_OUTPUT);
337 /* register our spi controller */
339 err = spi_bitbang_start(&hw->bitbang);
341 dev_err(&pdev->dev, "Failed to register SPI master\n");
345 dev_dbg(hw->dev, "shutdown=%d\n", hw->bitbang.shutdown);
347 /* register all the devices associated */
349 bi = &hw->pdata->board_info[0];
350 for (i = 0; i < hw->pdata->board_size; i++, bi++) {
351 dev_info(hw->dev, "registering %s\n", bi->modalias);
353 bi->controller_data = hw;
354 spi_new_device(master, bi);
360 clk_disable(hw->clk);
364 free_irq(hw->irq, hw);
370 release_resource(hw->ioarea);
375 spi_master_put(hw->master);;
381 static int s3c24xx_spi_remove(struct platform_device *dev)
383 struct s3c24xx_spi *hw = platform_get_drvdata(dev);
385 platform_set_drvdata(dev, NULL);
387 spi_unregister_master(hw->master);
389 clk_disable(hw->clk);
392 free_irq(hw->irq, hw);
395 release_resource(hw->ioarea);
398 spi_master_put(hw->master);
405 static int s3c24xx_spi_suspend(struct platform_device *pdev, pm_message_t msg)
407 struct s3c24xx_spi *hw = platform_get_drvdata(pdev);
409 clk_disable(hw->clk);
413 static int s3c24xx_spi_resume(struct platform_device *pdev)
415 struct s3c24xx_spi *hw = platform_get_drvdata(pdev);
422 #define s3c24xx_spi_suspend NULL
423 #define s3c24xx_spi_resume NULL
426 static struct platform_driver s3c24xx_spidrv = {
427 .probe = s3c24xx_spi_probe,
428 .remove = s3c24xx_spi_remove,
429 .suspend = s3c24xx_spi_suspend,
430 .resume = s3c24xx_spi_resume,
432 .name = "s3c2410-spi",
433 .owner = THIS_MODULE,
437 static int __init s3c24xx_spi_init(void)
439 return platform_driver_register(&s3c24xx_spidrv);
442 static void __exit s3c24xx_spi_exit(void)
444 platform_driver_unregister(&s3c24xx_spidrv);
447 module_init(s3c24xx_spi_init);
448 module_exit(s3c24xx_spi_exit);
450 MODULE_DESCRIPTION("S3C24XX SPI Driver");
451 MODULE_AUTHOR("Ben Dooks, <ben@simtec.co.uk>");
452 MODULE_LICENSE("GPL");