git.oblomov.eu Git - linux-2.6/blob - arch/i386/kernel/io_apic.c

   1 /*
   2  *      Intel IO-APIC support for multi-Pentium hosts.
   3  *
   4  *      Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
   5  *
   6  *      Many thanks to Stig Venaas for trying out countless experimental
   7  *      patches and reporting/debugging problems patiently!
   8  *
   9  *      (c) 1999, Multiple IO-APIC support, developed by
  10  *      Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
  11  *      Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
  12  *      further tested and cleaned up by Zach Brown <zab@redhat.com>
  13  *      and Ingo Molnar <mingo@redhat.com>
  14  *
  15  *      Fixes
  16  *      Maciej W. Rozycki       :       Bits for genuine 82489DX APICs;
  17  *                                      thanks to Eric Gilmore
  18  *                                      and Rolf G. Tews
  19  *                                      for testing these extensively
  20  *      Paul Diefenbaugh        :       Added full ACPI support
  21  */
  22
  23 #include <linux/mm.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/init.h>
  26 #include <linux/delay.h>
  27 #include <linux/sched.h>
  28 #include <linux/config.h>
  29 #include <linux/smp_lock.h>
  30 #include <linux/mc146818rtc.h>
  31 #include <linux/compiler.h>
  32 #include <linux/acpi.h>
  33 #include <linux/module.h>
  34 #include <linux/sysdev.h>
  35
  36 #include <asm/io.h>
  37 #include <asm/smp.h>
  38 #include <asm/desc.h>
  39 #include <asm/timer.h>
  40 #include <asm/i8259.h>
  41
  42 #include <mach_apic.h>
  43
  44 #include "io_ports.h"
  45
  46 int (*ioapic_renumber_irq)(int ioapic, int irq);
  47 atomic_t irq_mis_count;
  48
  49 /* Where if anywhere is the i8259 connect in external int mode */
  50 static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
  51
  52 static DEFINE_SPINLOCK(ioapic_lock);
  53
  54 /*
  55  *      Is the SiS APIC rmw bug present ?
  56  *      -1 = don't know, 0 = no, 1 = yes
  57  */
  58 int sis_apic_bug = -1;
  59
  60 /*
  61  * # of IRQ routing registers
  62  */
  63 int nr_ioapic_registers[MAX_IO_APICS];
  64
  65 int disable_timer_pin_1 __initdata;
  66
  67 /*
  68  * Rough estimation of how many shared IRQs there are, can
  69  * be changed anytime.
  70  */
  71 #define MAX_PLUS_SHARED_IRQS NR_IRQS
  72 #define PIN_MAP_SIZE (MAX_PLUS_SHARED_IRQS + NR_IRQS)
  73
  74 /*
  75  * This is performance-critical, we want to do it O(1)
  76  *
  77  * the indexing order of this array favors 1:1 mappings
  78  * between pins and IRQs.
  79  */
  80
  81 static struct irq_pin_list {
  82         int apic, pin, next;
  83 } irq_2_pin[PIN_MAP_SIZE];
  84
  85 int vector_irq[NR_VECTORS] __read_mostly = { [0 ... NR_VECTORS - 1] = -1};
  86 #ifdef CONFIG_PCI_MSI
  87 #define vector_to_irq(vector)   \
  88         (platform_legacy_irq(vector) ? vector : vector_irq[vector])
  89 #else
  90 #define vector_to_irq(vector)   (vector)
  91 #endif
  92
  93 /*
  94  * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
  95  * shared ISA-space IRQs, so we have to support them. We are super
  96  * fast in the common case, and fast for shared ISA-space IRQs.
  97  */
  98 static void add_pin_to_irq(unsigned int irq, int apic, int pin)
  99 {
 100         static int first_free_entry = NR_IRQS;
 101         struct irq_pin_list *entry = irq_2_pin + irq;
 102
 103         while (entry->next)
 104                 entry = irq_2_pin + entry->next;
 105
 106         if (entry->pin != -1) {
 107                 entry->next = first_free_entry;
 108                 entry = irq_2_pin + entry->next;
 109                 if (++first_free_entry >= PIN_MAP_SIZE)
 110                         panic("io_apic.c: whoops");
 111         }
 112         entry->apic = apic;
 113         entry->pin = pin;
 114 }
 115
 116 /*
 117  * Reroute an IRQ to a different pin.
 118  */
 119 static void __init replace_pin_at_irq(unsigned int irq,
 120                                       int oldapic, int oldpin,
 121                                       int newapic, int newpin)
 122 {
 123         struct irq_pin_list *entry = irq_2_pin + irq;
 124
 125         while (1) {
 126                 if (entry->apic == oldapic && entry->pin == oldpin) {
 127                         entry->apic = newapic;
 128                         entry->pin = newpin;
 129                 }
 130                 if (!entry->next)
 131                         break;
 132                 entry = irq_2_pin + entry->next;
 133         }
 134 }
 135
 136 static void __modify_IO_APIC_irq (unsigned int irq, unsigned long enable, unsigned long disable)
 137 {
 138         struct irq_pin_list *entry = irq_2_pin + irq;
 139         unsigned int pin, reg;
 140
 141         for (;;) {
 142                 pin = entry->pin;
 143                 if (pin == -1)
 144                         break;
 145                 reg = io_apic_read(entry->apic, 0x10 + pin*2);
 146                 reg &= ~disable;
 147                 reg |= enable;
 148                 io_apic_modify(entry->apic, 0x10 + pin*2, reg);
 149                 if (!entry->next)
 150                         break;
 151                 entry = irq_2_pin + entry->next;
 152         }
 153 }
 154
 155 /* mask = 1 */
 156 static void __mask_IO_APIC_irq (unsigned int irq)
 157 {
 158         __modify_IO_APIC_irq(irq, 0x00010000, 0);
 159 }
 160
 161 /* mask = 0 */
 162 static void __unmask_IO_APIC_irq (unsigned int irq)
 163 {
 164         __modify_IO_APIC_irq(irq, 0, 0x00010000);
 165 }
 166
 167 /* mask = 1, trigger = 0 */
 168 static void __mask_and_edge_IO_APIC_irq (unsigned int irq)
 169 {
 170         __modify_IO_APIC_irq(irq, 0x00010000, 0x00008000);
 171 }
 172
 173 /* mask = 0, trigger = 1 */
 174 static void __unmask_and_level_IO_APIC_irq (unsigned int irq)
 175 {
 176         __modify_IO_APIC_irq(irq, 0x00008000, 0x00010000);
 177 }
 178
 179 static void mask_IO_APIC_irq (unsigned int irq)
 180 {
 181         unsigned long flags;
 182
 183         spin_lock_irqsave(&ioapic_lock, flags);
 184         __mask_IO_APIC_irq(irq);
 185         spin_unlock_irqrestore(&ioapic_lock, flags);
 186 }
 187
 188 static void unmask_IO_APIC_irq (unsigned int irq)
 189 {
 190         unsigned long flags;
 191
 192         spin_lock_irqsave(&ioapic_lock, flags);
 193         __unmask_IO_APIC_irq(irq);
 194         spin_unlock_irqrestore(&ioapic_lock, flags);
 195 }
 196
 197 static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
 198 {
 199         struct IO_APIC_route_entry entry;
 200         unsigned long flags;
 201
 202         /* Check delivery_mode to be sure we're not clearing an SMI pin */
 203         spin_lock_irqsave(&ioapic_lock, flags);
 204         *(((int*)&entry) + 0) = io_apic_read(apic, 0x10 + 2 * pin);
 205         *(((int*)&entry) + 1) = io_apic_read(apic, 0x11 + 2 * pin);
 206         spin_unlock_irqrestore(&ioapic_lock, flags);
 207         if (entry.delivery_mode == dest_SMI)
 208                 return;
 209
 210         /*
 211          * Disable it in the IO-APIC irq-routing table:
 212          */
 213         memset(&entry, 0, sizeof(entry));
 214         entry.mask = 1;
 215         spin_lock_irqsave(&ioapic_lock, flags);
 216         io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry) + 0));
 217         io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry) + 1));
 218         spin_unlock_irqrestore(&ioapic_lock, flags);
 219 }
 220
 221 static void clear_IO_APIC (void)
 222 {
 223         int apic, pin;
 224
 225         for (apic = 0; apic < nr_ioapics; apic++)
 226                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
 227                         clear_IO_APIC_pin(apic, pin);
 228 }
 229
 230 #ifdef CONFIG_SMP
 231 static void set_ioapic_affinity_irq(unsigned int irq, cpumask_t cpumask)
 232 {
 233         unsigned long flags;
 234         int pin;
 235         struct irq_pin_list *entry = irq_2_pin + irq;
 236         unsigned int apicid_value;
 237         cpumask_t tmp;
 238
 239         cpus_and(tmp, cpumask, cpu_online_map);
 240         if (cpus_empty(tmp))
 241                 tmp = TARGET_CPUS;
 242
 243         cpus_and(cpumask, tmp, CPU_MASK_ALL);
 244
 245         apicid_value = cpu_mask_to_apicid(cpumask);
 246         /* Prepare to do the io_apic_write */
 247         apicid_value = apicid_value << 24;
 248         spin_lock_irqsave(&ioapic_lock, flags);
 249         for (;;) {
 250                 pin = entry->pin;
 251                 if (pin == -1)
 252                         break;
 253                 io_apic_write(entry->apic, 0x10 + 1 + pin*2, apicid_value);
 254                 if (!entry->next)
 255                         break;
 256                 entry = irq_2_pin + entry->next;
 257         }
 258         set_irq_info(irq, cpumask);
 259         spin_unlock_irqrestore(&ioapic_lock, flags);
 260 }
 261
 262 #if defined(CONFIG_IRQBALANCE)
 263 # include <asm/processor.h>     /* kernel_thread() */
 264 # include <linux/kernel_stat.h> /* kstat */
 265 # include <linux/slab.h>                /* kmalloc() */
 266 # include <linux/timer.h>       /* time_after() */
 267
 268 # ifdef CONFIG_BALANCED_IRQ_DEBUG
 269 #  define TDprintk(x...) do { printk("<%ld:%s:%d>: ", jiffies, __FILE__, __LINE__); printk(x); } while (0)
 270 #  define Dprintk(x...) do { TDprintk(x); } while (0)
 271 # else
 272 #  define TDprintk(x...)
 273 #  define Dprintk(x...)
 274 # endif
 275
 276
 277 #define IRQBALANCE_CHECK_ARCH -999
 278 static int irqbalance_disabled = IRQBALANCE_CHECK_ARCH;
 279 static int physical_balance = 0;
 280
 281 static struct irq_cpu_info {
 282         unsigned long * last_irq;
 283         unsigned long * irq_delta;
 284         unsigned long irq;
 285 } irq_cpu_data[NR_CPUS];
 286
 287 #define CPU_IRQ(cpu)            (irq_cpu_data[cpu].irq)
 288 #define LAST_CPU_IRQ(cpu,irq)   (irq_cpu_data[cpu].last_irq[irq])
 289 #define IRQ_DELTA(cpu,irq)      (irq_cpu_data[cpu].irq_delta[irq])
 290
 291 #define IDLE_ENOUGH(cpu,now) \
 292         (idle_cpu(cpu) && ((now) - per_cpu(irq_stat, (cpu)).idle_timestamp > 1))
 293
 294 #define IRQ_ALLOWED(cpu, allowed_mask)  cpu_isset(cpu, allowed_mask)
 295
 296 #define CPU_TO_PACKAGEINDEX(i) (first_cpu(cpu_sibling_map[i]))
 297
 298 #define MAX_BALANCED_IRQ_INTERVAL       (5*HZ)
 299 #define MIN_BALANCED_IRQ_INTERVAL       (HZ/2)
 300 #define BALANCED_IRQ_MORE_DELTA         (HZ/10)
 301 #define BALANCED_IRQ_LESS_DELTA         (HZ)
 302
 303 static long balanced_irq_interval = MAX_BALANCED_IRQ_INTERVAL;
 304
 305 static unsigned long move(int curr_cpu, cpumask_t allowed_mask,
 306                         unsigned long now, int direction)
 307 {
 308         int search_idle = 1;
 309         int cpu = curr_cpu;
 310
 311         goto inside;
 312
 313         do {
 314                 if (unlikely(cpu == curr_cpu))
 315                         search_idle = 0;
 316 inside:
 317                 if (direction == 1) {
 318                         cpu++;
 319                         if (cpu >= NR_CPUS)
 320                                 cpu = 0;
 321                 } else {
 322                         cpu--;
 323                         if (cpu == -1)
 324                                 cpu = NR_CPUS-1;
 325                 }
 326         } while (!cpu_online(cpu) || !IRQ_ALLOWED(cpu,allowed_mask) ||
 327                         (search_idle && !IDLE_ENOUGH(cpu,now)));
 328
 329         return cpu;
 330 }
 331
 332 static inline void balance_irq(int cpu, int irq)
 333 {
 334         unsigned long now = jiffies;
 335         cpumask_t allowed_mask;
 336         unsigned int new_cpu;
 337
 338         if (irqbalance_disabled)
 339                 return;
 340
 341         cpus_and(allowed_mask, cpu_online_map, irq_affinity[irq]);
 342         new_cpu = move(cpu, allowed_mask, now, 1);
 343         if (cpu != new_cpu) {
 344                 set_pending_irq(irq, cpumask_of_cpu(new_cpu));
 345         }
 346 }
 347
 348 static inline void rotate_irqs_among_cpus(unsigned long useful_load_threshold)
 349 {
 350         int i, j;
 351         Dprintk("Rotating IRQs among CPUs.\n");
 352         for (i = 0; i < NR_CPUS; i++) {
 353                 for (j = 0; cpu_online(i) && (j < NR_IRQS); j++) {
 354                         if (!irq_desc[j].action)
 355                                 continue;
 356                         /* Is it a significant load ?  */
 357                         if (IRQ_DELTA(CPU_TO_PACKAGEINDEX(i),j) <
 358                                                 useful_load_threshold)
 359                                 continue;
 360                         balance_irq(i, j);
 361                 }
 362         }
 363         balanced_irq_interval = max((long)MIN_BALANCED_IRQ_INTERVAL,
 364                 balanced_irq_interval - BALANCED_IRQ_LESS_DELTA);
 365         return;
 366 }
 367
 368 static void do_irq_balance(void)
 369 {
 370         int i, j;
 371         unsigned long max_cpu_irq = 0, min_cpu_irq = (~0);
 372         unsigned long move_this_load = 0;
 373         int max_loaded = 0, min_loaded = 0;
 374         int load;
 375         unsigned long useful_load_threshold = balanced_irq_interval + 10;
 376         int selected_irq;
 377         int tmp_loaded, first_attempt = 1;
 378         unsigned long tmp_cpu_irq;
 379         unsigned long imbalance = 0;
 380         cpumask_t allowed_mask, target_cpu_mask, tmp;
 381
 382         for (i = 0; i < NR_CPUS; i++) {
 383                 int package_index;
 384                 CPU_IRQ(i) = 0;
 385                 if (!cpu_online(i))
 386                         continue;
 387                 package_index = CPU_TO_PACKAGEINDEX(i);
 388                 for (j = 0; j < NR_IRQS; j++) {
 389                         unsigned long value_now, delta;
 390                         /* Is this an active IRQ? */
 391                         if (!irq_desc[j].action)
 392                                 continue;
 393                         if ( package_index == i )
 394                                 IRQ_DELTA(package_index,j) = 0;
 395                         /* Determine the total count per processor per IRQ */
 396                         value_now = (unsigned long) kstat_cpu(i).irqs[j];
 397
 398                         /* Determine the activity per processor per IRQ */
 399                         delta = value_now - LAST_CPU_IRQ(i,j);
 400
 401                         /* Update last_cpu_irq[][] for the next time */
 402                         LAST_CPU_IRQ(i,j) = value_now;
 403
 404                         /* Ignore IRQs whose rate is less than the clock */
 405                         if (delta < useful_load_threshold)
 406                                 continue;
 407                         /* update the load for the processor or package total */
 408                         IRQ_DELTA(package_index,j) += delta;
 409
 410                         /* Keep track of the higher numbered sibling as well */
 411                         if (i != package_index)
 412                                 CPU_IRQ(i) += delta;
 413                         /*
 414                          * We have sibling A and sibling B in the package
 415                          *
 416                          * cpu_irq[A] = load for cpu A + load for cpu B
 417                          * cpu_irq[B] = load for cpu B
 418                          */
 419                         CPU_IRQ(package_index) += delta;
 420                 }
 421         }
 422         /* Find the least loaded processor package */
 423         for (i = 0; i < NR_CPUS; i++) {
 424                 if (!cpu_online(i))
 425                         continue;
 426                 if (i != CPU_TO_PACKAGEINDEX(i))
 427                         continue;
 428                 if (min_cpu_irq > CPU_IRQ(i)) {
 429                         min_cpu_irq = CPU_IRQ(i);
 430                         min_loaded = i;
 431                 }
 432         }
 433         max_cpu_irq = ULONG_MAX;
 434
 435 tryanothercpu:
 436         /* Look for heaviest loaded processor.
 437          * We may come back to get the next heaviest loaded processor.
 438          * Skip processors with trivial loads.
 439          */
 440         tmp_cpu_irq = 0;
 441         tmp_loaded = -1;
 442         for (i = 0; i < NR_CPUS; i++) {
 443                 if (!cpu_online(i))
 444                         continue;
 445                 if (i != CPU_TO_PACKAGEINDEX(i))
 446                         continue;
 447                 if (max_cpu_irq <= CPU_IRQ(i))
 448                         continue;
 449                 if (tmp_cpu_irq < CPU_IRQ(i)) {
 450                         tmp_cpu_irq = CPU_IRQ(i);
 451                         tmp_loaded = i;
 452                 }
 453         }
 454
 455         if (tmp_loaded == -1) {
 456          /* In the case of small number of heavy interrupt sources,
 457           * loading some of the cpus too much. We use Ingo's original
 458           * approach to rotate them around.
 459           */
 460                 if (!first_attempt && imbalance >= useful_load_threshold) {
 461                         rotate_irqs_among_cpus(useful_load_threshold);
 462                         return;
 463                 }
 464                 goto not_worth_the_effort;
 465         }
 466
 467         first_attempt = 0;              /* heaviest search */
 468         max_cpu_irq = tmp_cpu_irq;      /* load */
 469         max_loaded = tmp_loaded;        /* processor */
 470         imbalance = (max_cpu_irq - min_cpu_irq) / 2;
 471
 472         Dprintk("max_loaded cpu = %d\n", max_loaded);
 473         Dprintk("min_loaded cpu = %d\n", min_loaded);
 474         Dprintk("max_cpu_irq load = %ld\n", max_cpu_irq);
 475         Dprintk("min_cpu_irq load = %ld\n", min_cpu_irq);
 476         Dprintk("load imbalance = %lu\n", imbalance);
 477
 478         /* if imbalance is less than approx 10% of max load, then
 479          * observe diminishing returns action. - quit
 480          */
 481         if (imbalance < (max_cpu_irq >> 3)) {
 482                 Dprintk("Imbalance too trivial\n");
 483                 goto not_worth_the_effort;
 484         }
 485
 486 tryanotherirq:
 487         /* if we select an IRQ to move that can't go where we want, then
 488          * see if there is another one to try.
 489          */
 490         move_this_load = 0;
 491         selected_irq = -1;
 492         for (j = 0; j < NR_IRQS; j++) {
 493                 /* Is this an active IRQ? */
 494                 if (!irq_desc[j].action)
 495                         continue;
 496                 if (imbalance <= IRQ_DELTA(max_loaded,j))
 497                         continue;
 498                 /* Try to find the IRQ that is closest to the imbalance
 499                  * without going over.
 500                  */
 501                 if (move_this_load < IRQ_DELTA(max_loaded,j)) {
 502                         move_this_load = IRQ_DELTA(max_loaded,j);
 503                         selected_irq = j;
 504                 }
 505         }
 506         if (selected_irq == -1) {
 507                 goto tryanothercpu;
 508         }
 509
 510         imbalance = move_this_load;
 511
 512         /* For physical_balance case, we accumlated both load
 513          * values in the one of the siblings cpu_irq[],
 514          * to use the same code for physical and logical processors
 515          * as much as possible.
 516          *
 517          * NOTE: the cpu_irq[] array holds the sum of the load for
 518          * sibling A and sibling B in the slot for the lowest numbered
 519          * sibling (A), _AND_ the load for sibling B in the slot for
 520          * the higher numbered sibling.
 521          *
 522          * We seek the least loaded sibling by making the comparison
 523          * (A+B)/2 vs B
 524          */
 525         load = CPU_IRQ(min_loaded) >> 1;
 526         for_each_cpu_mask(j, cpu_sibling_map[min_loaded]) {
 527                 if (load > CPU_IRQ(j)) {
 528                         /* This won't change cpu_sibling_map[min_loaded] */
 529                         load = CPU_IRQ(j);
 530                         min_loaded = j;
 531                 }
 532         }
 533
 534         cpus_and(allowed_mask, cpu_online_map, irq_affinity[selected_irq]);
 535         target_cpu_mask = cpumask_of_cpu(min_loaded);
 536         cpus_and(tmp, target_cpu_mask, allowed_mask);
 537
 538         if (!cpus_empty(tmp)) {
 539
 540                 Dprintk("irq = %d moved to cpu = %d\n",
 541                                 selected_irq, min_loaded);
 542                 /* mark for change destination */
 543                 set_pending_irq(selected_irq, cpumask_of_cpu(min_loaded));
 544
 545                 /* Since we made a change, come back sooner to
 546                  * check for more variation.
 547                  */
 548                 balanced_irq_interval = max((long)MIN_BALANCED_IRQ_INTERVAL,
 549                         balanced_irq_interval - BALANCED_IRQ_LESS_DELTA);
 550                 return;
 551         }
 552         goto tryanotherirq;
 553
 554 not_worth_the_effort:
 555         /*
 556          * if we did not find an IRQ to move, then adjust the time interval
 557          * upward
 558          */
 559         balanced_irq_interval = min((long)MAX_BALANCED_IRQ_INTERVAL,
 560                 balanced_irq_interval + BALANCED_IRQ_MORE_DELTA);
 561         Dprintk("IRQ worth rotating not found\n");
 562         return;
 563 }
 564
 565 static int balanced_irq(void *unused)
 566 {
 567         int i;
 568         unsigned long prev_balance_time = jiffies;
 569         long time_remaining = balanced_irq_interval;
 570
 571         daemonize("kirqd");
 572
 573         /* push everything to CPU 0 to give us a starting point.  */
 574         for (i = 0 ; i < NR_IRQS ; i++) {
 575                 pending_irq_cpumask[i] = cpumask_of_cpu(0);
 576                 set_pending_irq(i, cpumask_of_cpu(0));
 577         }
 578
 579         for ( ; ; ) {
 580                 time_remaining = schedule_timeout_interruptible(time_remaining);
 581                 try_to_freeze();
 582                 if (time_after(jiffies,
 583                                 prev_balance_time+balanced_irq_interval)) {
 584                         preempt_disable();
 585                         do_irq_balance();
 586                         prev_balance_time = jiffies;
 587                         time_remaining = balanced_irq_interval;
 588                         preempt_enable();
 589                 }
 590         }
 591         return 0;
 592 }
 593
 594 static int __init balanced_irq_init(void)
 595 {
 596         int i;
 597         struct cpuinfo_x86 *c;
 598         cpumask_t tmp;
 599
 600         cpus_shift_right(tmp, cpu_online_map, 2);
 601         c = &boot_cpu_data;
 602         /* When not overwritten by the command line ask subarchitecture. */
 603         if (irqbalance_disabled == IRQBALANCE_CHECK_ARCH)
 604                 irqbalance_disabled = NO_BALANCE_IRQ;
 605         if (irqbalance_disabled)
 606                 return 0;
 607
 608          /* disable irqbalance completely if there is only one processor online */
 609         if (num_online_cpus() < 2) {
 610                 irqbalance_disabled = 1;
 611                 return 0;
 612         }
 613         /*
 614          * Enable physical balance only if more than 1 physical processor
 615          * is present
 616          */
 617         if (smp_num_siblings > 1 && !cpus_empty(tmp))
 618                 physical_balance = 1;
 619
 620         for (i = 0; i < NR_CPUS; i++) {
 621                 if (!cpu_online(i))
 622                         continue;
 623                 irq_cpu_data[i].irq_delta = kmalloc(sizeof(unsigned long) * NR_IRQS, GFP_KERNEL);
 624                 irq_cpu_data[i].last_irq = kmalloc(sizeof(unsigned long) * NR_IRQS, GFP_KERNEL);
 625                 if (irq_cpu_data[i].irq_delta == NULL || irq_cpu_data[i].last_irq == NULL) {
 626                         printk(KERN_ERR "balanced_irq_init: out of memory");
 627                         goto failed;
 628                 }
 629                 memset(irq_cpu_data[i].irq_delta,0,sizeof(unsigned long) * NR_IRQS);
 630                 memset(irq_cpu_data[i].last_irq,0,sizeof(unsigned long) * NR_IRQS);
 631         }
 632
 633         printk(KERN_INFO "Starting balanced_irq\n");
 634         if (kernel_thread(balanced_irq, NULL, CLONE_KERNEL) >= 0)
 635                 return 0;
 636         else
 637                 printk(KERN_ERR "balanced_irq_init: failed to spawn balanced_irq");
 638 failed:
 639         for (i = 0; i < NR_CPUS; i++) {
 640                 kfree(irq_cpu_data[i].irq_delta);
 641                 kfree(irq_cpu_data[i].last_irq);
 642         }
 643         return 0;
 644 }
 645
 646 int __init irqbalance_disable(char *str)
 647 {
 648         irqbalance_disabled = 1;
 649         return 0;
 650 }
 651
 652 __setup("noirqbalance", irqbalance_disable);
 653
 654 late_initcall(balanced_irq_init);
 655 #endif /* CONFIG_IRQBALANCE */
 656 #endif /* CONFIG_SMP */
 657
 658 #ifndef CONFIG_SMP
 659 void fastcall send_IPI_self(int vector)
 660 {
 661         unsigned int cfg;
 662
 663         /*
 664          * Wait for idle.
 665          */
 666         apic_wait_icr_idle();
 667         cfg = APIC_DM_FIXED | APIC_DEST_SELF | vector | APIC_DEST_LOGICAL;
 668         /*
 669          * Send the IPI. The write to APIC_ICR fires this off.
 670          */
 671         apic_write_around(APIC_ICR, cfg);
 672 }
 673 #endif /* !CONFIG_SMP */
 674
 675
 676 /*
 677  * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
 678  * specific CPU-side IRQs.
 679  */
 680
 681 #define MAX_PIRQS 8
 682 static int pirq_entries [MAX_PIRQS];
 683 static int pirqs_enabled;
 684 int skip_ioapic_setup;
 685
 686 static int __init ioapic_setup(char *str)
 687 {
 688         skip_ioapic_setup = 1;
 689         return 1;
 690 }
 691
 692 __setup("noapic", ioapic_setup);
 693
 694 static int __init ioapic_pirq_setup(char *str)
 695 {
 696         int i, max;
 697         int ints[MAX_PIRQS+1];
 698
 699         get_options(str, ARRAY_SIZE(ints), ints);
 700
 701         for (i = 0; i < MAX_PIRQS; i++)
 702                 pirq_entries[i] = -1;
 703
 704         pirqs_enabled = 1;
 705         apic_printk(APIC_VERBOSE, KERN_INFO
 706                         "PIRQ redirection, working around broken MP-BIOS.\n");
 707         max = MAX_PIRQS;
 708         if (ints[0] < MAX_PIRQS)
 709                 max = ints[0];
 710
 711         for (i = 0; i < max; i++) {
 712                 apic_printk(APIC_VERBOSE, KERN_DEBUG
 713                                 "... PIRQ%d -> IRQ %d\n", i, ints[i+1]);
 714                 /*
 715                  * PIRQs are mapped upside down, usually.
 716                  */
 717                 pirq_entries[MAX_PIRQS-i-1] = ints[i+1];
 718         }
 719         return 1;
 720 }
 721
 722 __setup("pirq=", ioapic_pirq_setup);
 723
 724 /*
 725  * Find the IRQ entry number of a certain pin.
 726  */
 727 static int find_irq_entry(int apic, int pin, int type)
 728 {
 729         int i;
 730
 731         for (i = 0; i < mp_irq_entries; i++)
 732                 if (mp_irqs[i].mpc_irqtype == type &&
 733                     (mp_irqs[i].mpc_dstapic == mp_ioapics[apic].mpc_apicid ||
 734                      mp_irqs[i].mpc_dstapic == MP_APIC_ALL) &&
 735                     mp_irqs[i].mpc_dstirq == pin)
 736                         return i;
 737
 738         return -1;
 739 }
 740
 741 /*
 742  * Find the pin to which IRQ[irq] (ISA) is connected
 743  */
 744 static int __init find_isa_irq_pin(int irq, int type)
 745 {
 746         int i;
 747
 748         for (i = 0; i < mp_irq_entries; i++) {
 749                 int lbus = mp_irqs[i].mpc_srcbus;
 750
 751                 if ((mp_bus_id_to_type[lbus] == MP_BUS_ISA ||
 752                      mp_bus_id_to_type[lbus] == MP_BUS_EISA ||
 753                      mp_bus_id_to_type[lbus] == MP_BUS_MCA ||
 754                      mp_bus_id_to_type[lbus] == MP_BUS_NEC98
 755                     ) &&
 756                     (mp_irqs[i].mpc_irqtype == type) &&
 757                     (mp_irqs[i].mpc_srcbusirq == irq))
 758
 759                         return mp_irqs[i].mpc_dstirq;
 760         }
 761         return -1;
 762 }
 763
 764 static int __init find_isa_irq_apic(int irq, int type)
 765 {
 766         int i;
 767
 768         for (i = 0; i < mp_irq_entries; i++) {
 769                 int lbus = mp_irqs[i].mpc_srcbus;
 770
 771                 if ((mp_bus_id_to_type[lbus] == MP_BUS_ISA ||
 772                      mp_bus_id_to_type[lbus] == MP_BUS_EISA ||
 773                      mp_bus_id_to_type[lbus] == MP_BUS_MCA ||
 774                      mp_bus_id_to_type[lbus] == MP_BUS_NEC98
 775                     ) &&
 776                     (mp_irqs[i].mpc_irqtype == type) &&
 777                     (mp_irqs[i].mpc_srcbusirq == irq))
 778                         break;
 779         }
 780         if (i < mp_irq_entries) {
 781                 int apic;
 782                 for(apic = 0; apic < nr_ioapics; apic++) {
 783                         if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic)
 784                                 return apic;
 785                 }
 786         }
 787
 788         return -1;
 789 }
 790
 791 /*
 792  * Find a specific PCI IRQ entry.
 793  * Not an __init, possibly needed by modules
 794  */
 795 static int pin_2_irq(int idx, int apic, int pin);
 796
 797 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
 798 {
 799         int apic, i, best_guess = -1;
 800
 801         apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, "
 802                 "slot:%d, pin:%d.\n", bus, slot, pin);
 803         if (mp_bus_id_to_pci_bus[bus] == -1) {
 804                 printk(KERN_WARNING "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
 805                 return -1;
 806         }
 807         for (i = 0; i < mp_irq_entries; i++) {
 808                 int lbus = mp_irqs[i].mpc_srcbus;
 809
 810                 for (apic = 0; apic < nr_ioapics; apic++)
 811                         if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic ||
 812                             mp_irqs[i].mpc_dstapic == MP_APIC_ALL)
 813                                 break;
 814
 815                 if ((mp_bus_id_to_type[lbus] == MP_BUS_PCI) &&
 816                     !mp_irqs[i].mpc_irqtype &&
 817                     (bus == lbus) &&
 818                     (slot == ((mp_irqs[i].mpc_srcbusirq >> 2) & 0x1f))) {
 819                         int irq = pin_2_irq(i,apic,mp_irqs[i].mpc_dstirq);
 820
 821                         if (!(apic || IO_APIC_IRQ(irq)))
 822                                 continue;
 823
 824                         if (pin == (mp_irqs[i].mpc_srcbusirq & 3))
 825                                 return irq;
 826                         /*
 827                          * Use the first all-but-pin matching entry as a
 828                          * best-guess fuzzy result for broken mptables.
 829                          */
 830                         if (best_guess < 0)
 831                                 best_guess = irq;
 832                 }
 833         }
 834         return best_guess;
 835 }
 836 EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector);
 837
 838 /*
 839  * This function currently is only a helper for the i386 smp boot process where
 840  * we need to reprogram the ioredtbls to cater for the cpus which have come online
 841  * so mask in all cases should simply be TARGET_CPUS
 842  */
 843 #ifdef CONFIG_SMP
 844 void __init setup_ioapic_dest(void)
 845 {
 846         int pin, ioapic, irq, irq_entry;
 847
 848         if (skip_ioapic_setup == 1)
 849                 return;
 850
 851         for (ioapic = 0; ioapic < nr_ioapics; ioapic++) {
 852                 for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
 853                         irq_entry = find_irq_entry(ioapic, pin, mp_INT);
 854                         if (irq_entry == -1)
 855                                 continue;
 856                         irq = pin_2_irq(irq_entry, ioapic, pin);
 857                         set_ioapic_affinity_irq(irq, TARGET_CPUS);
 858                 }
 859
 860         }
 861 }
 862 #endif
 863
 864 /*
 865  * EISA Edge/Level control register, ELCR
 866  */
 867 static int EISA_ELCR(unsigned int irq)
 868 {
 869         if (irq < 16) {
 870                 unsigned int port = 0x4d0 + (irq >> 3);
 871                 return (inb(port) >> (irq & 7)) & 1;
 872         }
 873         apic_printk(APIC_VERBOSE, KERN_INFO
 874                         "Broken MPtable reports ISA irq %d\n", irq);
 875         return 0;
 876 }
 877
 878 /* EISA interrupts are always polarity zero and can be edge or level
 879  * trigger depending on the ELCR value.  If an interrupt is listed as
 880  * EISA conforming in the MP table, that means its trigger type must
 881  * be read in from the ELCR */
 882
 883 #define default_EISA_trigger(idx)       (EISA_ELCR(mp_irqs[idx].mpc_srcbusirq))
 884 #define default_EISA_polarity(idx)      (0)
 885
 886 /* ISA interrupts are always polarity zero edge triggered,
 887  * when listed as conforming in the MP table. */
 888
 889 #define default_ISA_trigger(idx)        (0)
 890 #define default_ISA_polarity(idx)       (0)
 891
 892 /* PCI interrupts are always polarity one level triggered,
 893  * when listed as conforming in the MP table. */
 894
 895 #define default_PCI_trigger(idx)        (1)
 896 #define default_PCI_polarity(idx)       (1)
 897
 898 /* MCA interrupts are always polarity zero level triggered,
 899  * when listed as conforming in the MP table. */
 900
 901 #define default_MCA_trigger(idx)        (1)
 902 #define default_MCA_polarity(idx)       (0)
 903
 904 /* NEC98 interrupts are always polarity zero edge triggered,
 905  * when listed as conforming in the MP table. */
 906
 907 #define default_NEC98_trigger(idx)     (0)
 908 #define default_NEC98_polarity(idx)    (0)
 909
 910 static int __init MPBIOS_polarity(int idx)
 911 {
 912         int bus = mp_irqs[idx].mpc_srcbus;
 913         int polarity;
 914
 915         /*
 916          * Determine IRQ line polarity (high active or low active):
 917          */
 918         switch (mp_irqs[idx].mpc_irqflag & 3)
 919         {
 920                 case 0: /* conforms, ie. bus-type dependent polarity */
 921                 {
 922                         switch (mp_bus_id_to_type[bus])
 923                         {
 924                                 case MP_BUS_ISA: /* ISA pin */
 925                                 {
 926                                         polarity = default_ISA_polarity(idx);
 927                                         break;
 928                                 }
 929                                 case MP_BUS_EISA: /* EISA pin */
 930                                 {
 931                                         polarity = default_EISA_polarity(idx);
 932                                         break;
 933                                 }
 934                                 case MP_BUS_PCI: /* PCI pin */
 935                                 {
 936                                         polarity = default_PCI_polarity(idx);
 937                                         break;
 938                                 }
 939                                 case MP_BUS_MCA: /* MCA pin */
 940                                 {
 941                                         polarity = default_MCA_polarity(idx);
 942                                         break;
 943                                 }
 944                                 case MP_BUS_NEC98: /* NEC 98 pin */
 945                                 {
 946                                         polarity = default_NEC98_polarity(idx);
 947                                         break;
 948                                 }
 949                                 default:
 950                                 {
 951                                         printk(KERN_WARNING "broken BIOS!!\n");
 952                                         polarity = 1;
 953                                         break;
 954                                 }
 955                         }
 956                         break;
 957                 }
 958                 case 1: /* high active */
 959                 {
 960                         polarity = 0;
 961                         break;
 962                 }
 963                 case 2: /* reserved */
 964                 {
 965                         printk(KERN_WARNING "broken BIOS!!\n");
 966                         polarity = 1;
 967                         break;
 968                 }
 969                 case 3: /* low active */
 970                 {
 971                         polarity = 1;
 972                         break;
 973                 }
 974                 default: /* invalid */
 975                 {
 976                         printk(KERN_WARNING "broken BIOS!!\n");
 977                         polarity = 1;
 978                         break;
 979                 }
 980         }
 981         return polarity;
 982 }
 983
 984 static int MPBIOS_trigger(int idx)
 985 {
 986         int bus = mp_irqs[idx].mpc_srcbus;
 987         int trigger;
 988
 989         /*
 990          * Determine IRQ trigger mode (edge or level sensitive):
 991          */
 992         switch ((mp_irqs[idx].mpc_irqflag>>2) & 3)
 993         {
 994                 case 0: /* conforms, ie. bus-type dependent */
 995                 {
 996                         switch (mp_bus_id_to_type[bus])
 997                         {
 998                                 case MP_BUS_ISA: /* ISA pin */
 999                                 {
1000                                         trigger = default_ISA_trigger(idx);
1001                                         break;
1002                                 }
1003                                 case MP_BUS_EISA: /* EISA pin */
1004                                 {
1005                                         trigger = default_EISA_trigger(idx);
1006                                         break;
1007                                 }
1008                                 case MP_BUS_PCI: /* PCI pin */
1009                                 {
1010                                         trigger = default_PCI_trigger(idx);
1011                                         break;
1012                                 }
1013                                 case MP_BUS_MCA: /* MCA pin */
1014                                 {
1015                                         trigger = default_MCA_trigger(idx);
1016                                         break;
1017                                 }
1018                                 case MP_BUS_NEC98: /* NEC 98 pin */
1019                                 {
1020                                         trigger = default_NEC98_trigger(idx);
1021                                         break;
1022                                 }
1023                                 default:
1024                                 {
1025                                         printk(KERN_WARNING "broken BIOS!!\n");
1026                                         trigger = 1;
1027                                         break;
1028                                 }
1029                         }
1030                         break;
1031                 }
1032                 case 1: /* edge */
1033                 {
1034                         trigger = 0;
1035                         break;
1036                 }
1037                 case 2: /* reserved */
1038                 {
1039                         printk(KERN_WARNING "broken BIOS!!\n");
1040                         trigger = 1;
1041                         break;
1042                 }
1043                 case 3: /* level */
1044                 {
1045                         trigger = 1;
1046                         break;
1047                 }
1048                 default: /* invalid */
1049                 {
1050                         printk(KERN_WARNING "broken BIOS!!\n");
1051                         trigger = 0;
1052                         break;
1053                 }
1054         }
1055         return trigger;
1056 }
1057
1058 static inline int irq_polarity(int idx)
1059 {
1060         return MPBIOS_polarity(idx);
1061 }
1062
1063 static inline int irq_trigger(int idx)
1064 {
1065         return MPBIOS_trigger(idx);
1066 }
1067
1068 static int pin_2_irq(int idx, int apic, int pin)
1069 {
1070         int irq, i;
1071         int bus = mp_irqs[idx].mpc_srcbus;
1072
1073         /*
1074          * Debugging check, we are in big trouble if this message pops up!
1075          */
1076         if (mp_irqs[idx].mpc_dstirq != pin)
1077                 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
1078
1079         switch (mp_bus_id_to_type[bus])
1080         {
1081                 case MP_BUS_ISA: /* ISA pin */
1082                 case MP_BUS_EISA:
1083                 case MP_BUS_MCA:
1084                 case MP_BUS_NEC98:
1085                 {
1086                         irq = mp_irqs[idx].mpc_srcbusirq;
1087                         break;
1088                 }
1089                 case MP_BUS_PCI: /* PCI pin */
1090                 {
1091                         /*
1092                          * PCI IRQs are mapped in order
1093                          */
1094                         i = irq = 0;
1095                         while (i < apic)
1096                                 irq += nr_ioapic_registers[i++];
1097                         irq += pin;
1098
1099                         /*
1100                          * For MPS mode, so far only needed by ES7000 platform
1101                          */
1102                         if (ioapic_renumber_irq)
1103                                 irq = ioapic_renumber_irq(apic, irq);
1104
1105                         break;
1106                 }
1107                 default:
1108                 {
1109                         printk(KERN_ERR "unknown bus type %d.\n",bus);
1110                         irq = 0;
1111                         break;
1112                 }
1113         }
1114
1115         /*
1116          * PCI IRQ command line redirection. Yes, limits are hardcoded.
1117          */
1118         if ((pin >= 16) && (pin <= 23)) {
1119                 if (pirq_entries[pin-16] != -1) {
1120                         if (!pirq_entries[pin-16]) {
1121                                 apic_printk(APIC_VERBOSE, KERN_DEBUG
1122                                                 "disabling PIRQ%d\n", pin-16);
1123                         } else {
1124                                 irq = pirq_entries[pin-16];
1125                                 apic_printk(APIC_VERBOSE, KERN_DEBUG
1126                                                 "using PIRQ%d -> IRQ %d\n",
1127                                                 pin-16, irq);
1128                         }
1129                 }
1130         }
1131         return irq;
1132 }
1133
1134 static inline int IO_APIC_irq_trigger(int irq)
1135 {
1136         int apic, idx, pin;
1137
1138         for (apic = 0; apic < nr_ioapics; apic++) {
1139                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1140                         idx = find_irq_entry(apic,pin,mp_INT);
1141                         if ((idx != -1) && (irq == pin_2_irq(idx,apic,pin)))
1142                                 return irq_trigger(idx);
1143                 }
1144         }
1145         /*
1146          * nonexistent IRQs are edge default
1147          */
1148         return 0;
1149 }
1150
1151 /* irq_vectors is indexed by the sum of all RTEs in all I/O APICs. */
1152 u8 irq_vector[NR_IRQ_VECTORS] __read_mostly = { FIRST_DEVICE_VECTOR , 0 };
1153
1154 int assign_irq_vector(int irq)
1155 {
1156         static int current_vector = FIRST_DEVICE_VECTOR, offset = 0;
1157
1158         BUG_ON(irq >= NR_IRQ_VECTORS);
1159         if (irq != AUTO_ASSIGN && IO_APIC_VECTOR(irq) > 0)
1160                 return IO_APIC_VECTOR(irq);
1161 next:
1162         current_vector += 8;
1163         if (current_vector == SYSCALL_VECTOR)
1164                 goto next;
1165
1166         if (current_vector >= FIRST_SYSTEM_VECTOR) {
1167                 offset++;
1168                 if (!(offset%8))
1169                         return -ENOSPC;
1170                 current_vector = FIRST_DEVICE_VECTOR + offset;
1171         }
1172
1173         vector_irq[current_vector] = irq;
1174         if (irq != AUTO_ASSIGN)
1175                 IO_APIC_VECTOR(irq) = current_vector;
1176
1177         return current_vector;
1178 }
1179
1180 static struct hw_interrupt_type ioapic_level_type;
1181 static struct hw_interrupt_type ioapic_edge_type;
1182
1183 #define IOAPIC_AUTO     -1
1184 #define IOAPIC_EDGE     0
1185 #define IOAPIC_LEVEL    1
1186
1187 static inline void ioapic_register_intr(int irq, int vector, unsigned long trigger)
1188 {
1189         if (use_pci_vector() && !platform_legacy_irq(irq)) {
1190                 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1191                                 trigger == IOAPIC_LEVEL)
1192                         irq_desc[vector].handler = &ioapic_level_type;
1193                 else
1194                         irq_desc[vector].handler = &ioapic_edge_type;
1195                 set_intr_gate(vector, interrupt[vector]);
1196         } else  {
1197                 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1198                                 trigger == IOAPIC_LEVEL)
1199                         irq_desc[irq].handler = &ioapic_level_type;
1200                 else
1201                         irq_desc[irq].handler = &ioapic_edge_type;
1202                 set_intr_gate(vector, interrupt[irq]);
1203         }
1204 }
1205
1206 static void __init setup_IO_APIC_irqs(void)
1207 {
1208         struct IO_APIC_route_entry entry;
1209         int apic, pin, idx, irq, first_notcon = 1, vector;
1210         unsigned long flags;
1211
1212         apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
1213
1214         for (apic = 0; apic < nr_ioapics; apic++) {
1215         for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1216
1217                 /*
1218                  * add it to the IO-APIC irq-routing table:
1219                  */
1220                 memset(&entry,0,sizeof(entry));
1221
1222                 entry.delivery_mode = INT_DELIVERY_MODE;
1223                 entry.dest_mode = INT_DEST_MODE;
1224                 entry.mask = 0;                         /* enable IRQ */
1225                 entry.dest.logical.logical_dest =
1226                                         cpu_mask_to_apicid(TARGET_CPUS);
1227
1228                 idx = find_irq_entry(apic,pin,mp_INT);
1229                 if (idx == -1) {
1230                         if (first_notcon) {
1231                                 apic_printk(APIC_VERBOSE, KERN_DEBUG
1232                                                 " IO-APIC (apicid-pin) %d-%d",
1233                                                 mp_ioapics[apic].mpc_apicid,
1234                                                 pin);
1235                                 first_notcon = 0;
1236                         } else
1237                                 apic_printk(APIC_VERBOSE, ", %d-%d",
1238                                         mp_ioapics[apic].mpc_apicid, pin);
1239                         continue;
1240                 }
1241
1242                 entry.trigger = irq_trigger(idx);
1243                 entry.polarity = irq_polarity(idx);
1244
1245                 if (irq_trigger(idx)) {
1246                         entry.trigger = 1;
1247                         entry.mask = 1;
1248                 }
1249
1250                 irq = pin_2_irq(idx, apic, pin);
1251                 /*
1252                  * skip adding the timer int on secondary nodes, which causes
1253                  * a small but painful rift in the time-space continuum
1254                  */
1255                 if (multi_timer_check(apic, irq))
1256                         continue;
1257                 else
1258                         add_pin_to_irq(irq, apic, pin);
1259
1260                 if (!apic && !IO_APIC_IRQ(irq))
1261                         continue;
1262
1263                 if (IO_APIC_IRQ(irq)) {
1264                         vector = assign_irq_vector(irq);
1265                         entry.vector = vector;
1266                         ioapic_register_intr(irq, vector, IOAPIC_AUTO);
1267
1268                         if (!apic && (irq < 16))
1269                                 disable_8259A_irq(irq);
1270                 }
1271                 spin_lock_irqsave(&ioapic_lock, flags);
1272                 io_apic_write(apic, 0x11+2*pin, *(((int *)&entry)+1));
1273                 io_apic_write(apic, 0x10+2*pin, *(((int *)&entry)+0));
1274                 set_native_irq_info(irq, TARGET_CPUS);
1275                 spin_unlock_irqrestore(&ioapic_lock, flags);
1276         }
1277         }
1278
1279         if (!first_notcon)
1280                 apic_printk(APIC_VERBOSE, " not connected.\n");
1281 }
1282
1283 /*
1284  * Set up the 8259A-master output pin:
1285  */
1286 static void __init setup_ExtINT_IRQ0_pin(unsigned int apic, unsigned int pin, int vector)
1287 {
1288         struct IO_APIC_route_entry entry;
1289         unsigned long flags;
1290
1291         memset(&entry,0,sizeof(entry));
1292
1293         disable_8259A_irq(0);
1294
1295         /* mask LVT0 */
1296         apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
1297
1298         /*
1299          * We use logical delivery to get the timer IRQ
1300          * to the first CPU.
1301          */
1302         entry.dest_mode = INT_DEST_MODE;
1303         entry.mask = 0;                                 /* unmask IRQ now */
1304         entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
1305         entry.delivery_mode = INT_DELIVERY_MODE;
1306         entry.polarity = 0;
1307         entry.trigger = 0;
1308         entry.vector = vector;
1309
1310         /*
1311          * The timer IRQ doesn't have to know that behind the
1312          * scene we have a 8259A-master in AEOI mode ...
1313          */
1314         irq_desc[0].handler = &ioapic_edge_type;
1315
1316         /*
1317          * Add it to the IO-APIC irq-routing table:
1318          */
1319         spin_lock_irqsave(&ioapic_lock, flags);
1320         io_apic_write(apic, 0x11+2*pin, *(((int *)&entry)+1));
1321         io_apic_write(apic, 0x10+2*pin, *(((int *)&entry)+0));
1322         spin_unlock_irqrestore(&ioapic_lock, flags);
1323
1324         enable_8259A_irq(0);
1325 }
1326
1327 static inline void UNEXPECTED_IO_APIC(void)
1328 {
1329 }
1330
1331 void __init print_IO_APIC(void)
1332 {
1333         int apic, i;
1334         union IO_APIC_reg_00 reg_00;
1335         union IO_APIC_reg_01 reg_01;
1336         union IO_APIC_reg_02 reg_02;
1337         union IO_APIC_reg_03 reg_03;
1338         unsigned long flags;
1339
1340         if (apic_verbosity == APIC_QUIET)
1341                 return;
1342
1343         printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
1344         for (i = 0; i < nr_ioapics; i++)
1345                 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
1346                        mp_ioapics[i].mpc_apicid, nr_ioapic_registers[i]);
1347
1348         /*
1349          * We are a bit conservative about what we expect.  We have to
1350          * know about every hardware change ASAP.
1351          */
1352         printk(KERN_INFO "testing the IO APIC.......................\n");
1353
1354         for (apic = 0; apic < nr_ioapics; apic++) {
1355
1356         spin_lock_irqsave(&ioapic_lock, flags);
1357         reg_00.raw = io_apic_read(apic, 0);
1358         reg_01.raw = io_apic_read(apic, 1);
1359         if (reg_01.bits.version >= 0x10)
1360                 reg_02.raw = io_apic_read(apic, 2);
1361         if (reg_01.bits.version >= 0x20)
1362                 reg_03.raw = io_apic_read(apic, 3);
1363         spin_unlock_irqrestore(&ioapic_lock, flags);
1364
1365         printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mpc_apicid);
1366         printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
1367         printk(KERN_DEBUG ".......    : physical APIC id: %02X\n", reg_00.bits.ID);
1368         printk(KERN_DEBUG ".......    : Delivery Type: %X\n", reg_00.bits.delivery_type);
1369         printk(KERN_DEBUG ".......    : LTS          : %X\n", reg_00.bits.LTS);
1370         if (reg_00.bits.ID >= get_physical_broadcast())
1371                 UNEXPECTED_IO_APIC();
1372         if (reg_00.bits.__reserved_1 || reg_00.bits.__reserved_2)
1373                 UNEXPECTED_IO_APIC();
1374
1375         printk(KERN_DEBUG ".... register #01: %08X\n", reg_01.raw);
1376         printk(KERN_DEBUG ".......     : max redirection entries: %04X\n", reg_01.bits.entries);
1377         if (    (reg_01.bits.entries != 0x0f) && /* older (Neptune) boards */
1378                 (reg_01.bits.entries != 0x17) && /* typical ISA+PCI boards */
1379                 (reg_01.bits.entries != 0x1b) && /* Compaq Proliant boards */
1380                 (reg_01.bits.entries != 0x1f) && /* dual Xeon boards */
1381                 (reg_01.bits.entries != 0x22) && /* bigger Xeon boards */
1382                 (reg_01.bits.entries != 0x2E) &&
1383                 (reg_01.bits.entries != 0x3F)
1384         )
1385                 UNEXPECTED_IO_APIC();
1386
1387         printk(KERN_DEBUG ".......     : PRQ implemented: %X\n", reg_01.bits.PRQ);
1388         printk(KERN_DEBUG ".......     : IO APIC version: %04X\n", reg_01.bits.version);
1389         if (    (reg_01.bits.version != 0x01) && /* 82489DX IO-APICs */
1390                 (reg_01.bits.version != 0x10) && /* oldest IO-APICs */
1391                 (reg_01.bits.version != 0x11) && /* Pentium/Pro IO-APICs */
1392                 (reg_01.bits.version != 0x13) && /* Xeon IO-APICs */
1393                 (reg_01.bits.version != 0x20)    /* Intel P64H (82806 AA) */
1394         )
1395                 UNEXPECTED_IO_APIC();
1396         if (reg_01.bits.__reserved_1 || reg_01.bits.__reserved_2)
1397                 UNEXPECTED_IO_APIC();
1398
1399         /*
1400          * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
1401          * but the value of reg_02 is read as the previous read register
1402          * value, so ignore it if reg_02 == reg_01.
1403          */
1404         if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) {
1405                 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
1406                 printk(KERN_DEBUG ".......     : arbitration: %02X\n", reg_02.bits.arbitration);
1407                 if (reg_02.bits.__reserved_1 || reg_02.bits.__reserved_2)
1408                         UNEXPECTED_IO_APIC();
1409         }
1410
1411         /*
1412          * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
1413          * or reg_03, but the value of reg_0[23] is read as the previous read
1414          * register value, so ignore it if reg_03 == reg_0[12].
1415          */
1416         if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw &&
1417             reg_03.raw != reg_01.raw) {
1418                 printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw);
1419                 printk(KERN_DEBUG ".......     : Boot DT    : %X\n", reg_03.bits.boot_DT);
1420                 if (reg_03.bits.__reserved_1)
1421                         UNEXPECTED_IO_APIC();
1422         }
1423
1424         printk(KERN_DEBUG ".... IRQ redirection table:\n");
1425
1426         printk(KERN_DEBUG " NR Log Phy Mask Trig IRR Pol"
1427                           " Stat Dest Deli Vect:   \n");
1428
1429         for (i = 0; i <= reg_01.bits.entries; i++) {
1430                 struct IO_APIC_route_entry entry;
1431
1432                 spin_lock_irqsave(&ioapic_lock, flags);
1433                 *(((int *)&entry)+0) = io_apic_read(apic, 0x10+i*2);
1434                 *(((int *)&entry)+1) = io_apic_read(apic, 0x11+i*2);
1435                 spin_unlock_irqrestore(&ioapic_lock, flags);
1436
1437                 printk(KERN_DEBUG " %02x %03X %02X  ",
1438                         i,
1439                         entry.dest.logical.logical_dest,
1440                         entry.dest.physical.physical_dest
1441                 );
1442
1443                 printk("%1d    %1d    %1d   %1d   %1d    %1d    %1d    %02X\n",
1444                         entry.mask,
1445                         entry.trigger,
1446                         entry.irr,
1447                         entry.polarity,
1448                         entry.delivery_status,
1449                         entry.dest_mode,
1450                         entry.delivery_mode,
1451                         entry.vector
1452                 );
1453         }
1454         }
1455         if (use_pci_vector())
1456                 printk(KERN_INFO "Using vector-based indexing\n");
1457         printk(KERN_DEBUG "IRQ to pin mappings:\n");
1458         for (i = 0; i < NR_IRQS; i++) {
1459                 struct irq_pin_list *entry = irq_2_pin + i;
1460                 if (entry->pin < 0)
1461                         continue;
1462                 if (use_pci_vector() && !platform_legacy_irq(i))
1463                         printk(KERN_DEBUG "IRQ%d ", IO_APIC_VECTOR(i));
1464                 else
1465                         printk(KERN_DEBUG "IRQ%d ", i);
1466                 for (;;) {
1467                         printk("-> %d:%d", entry->apic, entry->pin);
1468                         if (!entry->next)
1469                                 break;
1470                         entry = irq_2_pin + entry->next;
1471                 }
1472                 printk("\n");
1473         }
1474
1475         printk(KERN_INFO ".................................... done.\n");
1476
1477         return;
1478 }
1479
1480 #if 0
1481
1482 static void print_APIC_bitfield (int base)
1483 {
1484         unsigned int v;
1485         int i, j;
1486
1487         if (apic_verbosity == APIC_QUIET)
1488                 return;
1489
1490         printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG);
1491         for (i = 0; i < 8; i++) {
1492                 v = apic_read(base + i*0x10);
1493                 for (j = 0; j < 32; j++) {
1494                         if (v & (1<<j))
1495                                 printk("1");
1496                         else
1497                                 printk("0");
1498                 }
1499                 printk("\n");
1500         }
1501 }
1502
1503 void /*__init*/ print_local_APIC(void * dummy)
1504 {
1505         unsigned int v, ver, maxlvt;
1506
1507         if (apic_verbosity == APIC_QUIET)
1508                 return;
1509
1510         printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
1511                 smp_processor_id(), hard_smp_processor_id());
1512         v = apic_read(APIC_ID);
1513         printk(KERN_INFO "... APIC ID:      %08x (%01x)\n", v, GET_APIC_ID(v));
1514         v = apic_read(APIC_LVR);
1515         printk(KERN_INFO "... APIC VERSION: %08x\n", v);
1516         ver = GET_APIC_VERSION(v);
1517         maxlvt = get_maxlvt();
1518
1519         v = apic_read(APIC_TASKPRI);
1520         printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
1521
1522         if (APIC_INTEGRATED(ver)) {                     /* !82489DX */
1523                 v = apic_read(APIC_ARBPRI);
1524                 printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
1525                         v & APIC_ARBPRI_MASK);
1526                 v = apic_read(APIC_PROCPRI);
1527                 printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
1528         }
1529
1530         v = apic_read(APIC_EOI);
1531         printk(KERN_DEBUG "... APIC EOI: %08x\n", v);
1532         v = apic_read(APIC_RRR);
1533         printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1534         v = apic_read(APIC_LDR);
1535         printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
1536         v = apic_read(APIC_DFR);
1537         printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1538         v = apic_read(APIC_SPIV);
1539         printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1540
1541         printk(KERN_DEBUG "... APIC ISR field:\n");
1542         print_APIC_bitfield(APIC_ISR);
1543         printk(KERN_DEBUG "... APIC TMR field:\n");
1544         print_APIC_bitfield(APIC_TMR);
1545         printk(KERN_DEBUG "... APIC IRR field:\n");
1546         print_APIC_bitfield(APIC_IRR);
1547
1548         if (APIC_INTEGRATED(ver)) {             /* !82489DX */
1549                 if (maxlvt > 3)         /* Due to the Pentium erratum 3AP. */
1550                         apic_write(APIC_ESR, 0);
1551                 v = apic_read(APIC_ESR);
1552                 printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1553         }
1554
1555         v = apic_read(APIC_ICR);
1556         printk(KERN_DEBUG "... APIC ICR: %08x\n", v);
1557         v = apic_read(APIC_ICR2);
1558         printk(KERN_DEBUG "... APIC ICR2: %08x\n", v);
1559
1560         v = apic_read(APIC_LVTT);
1561         printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1562
1563         if (maxlvt > 3) {                       /* PC is LVT#4. */
1564                 v = apic_read(APIC_LVTPC);
1565                 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1566         }
1567         v = apic_read(APIC_LVT0);
1568         printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1569         v = apic_read(APIC_LVT1);
1570         printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1571
1572         if (maxlvt > 2) {                       /* ERR is LVT#3. */
1573                 v = apic_read(APIC_LVTERR);
1574                 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1575         }
1576
1577         v = apic_read(APIC_TMICT);
1578         printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1579         v = apic_read(APIC_TMCCT);
1580         printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1581         v = apic_read(APIC_TDCR);
1582         printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1583         printk("\n");
1584 }
1585
1586 void print_all_local_APICs (void)
1587 {
1588         on_each_cpu(print_local_APIC, NULL, 1, 1);
1589 }
1590
1591 void /*__init*/ print_PIC(void)
1592 {
1593         unsigned int v;
1594         unsigned long flags;
1595
1596         if (apic_verbosity == APIC_QUIET)
1597                 return;
1598
1599         printk(KERN_DEBUG "\nprinting PIC contents\n");
1600
1601         spin_lock_irqsave(&i8259A_lock, flags);
1602
1603         v = inb(0xa1) << 8 | inb(0x21);
1604         printk(KERN_DEBUG "... PIC  IMR: %04x\n", v);
1605
1606         v = inb(0xa0) << 8 | inb(0x20);
1607         printk(KERN_DEBUG "... PIC  IRR: %04x\n", v);
1608
1609         outb(0x0b,0xa0);
1610         outb(0x0b,0x20);
1611         v = inb(0xa0) << 8 | inb(0x20);
1612         outb(0x0a,0xa0);
1613         outb(0x0a,0x20);
1614
1615         spin_unlock_irqrestore(&i8259A_lock, flags);
1616
1617         printk(KERN_DEBUG "... PIC  ISR: %04x\n", v);
1618
1619         v = inb(0x4d1) << 8 | inb(0x4d0);
1620         printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1621 }
1622
1623 #endif  /*  0  */
1624
1625 static void __init enable_IO_APIC(void)
1626 {
1627         union IO_APIC_reg_01 reg_01;
1628         int i8259_apic, i8259_pin;
1629         int i, apic;
1630         unsigned long flags;
1631
1632         for (i = 0; i < PIN_MAP_SIZE; i++) {
1633                 irq_2_pin[i].pin = -1;
1634                 irq_2_pin[i].next = 0;
1635         }
1636         if (!pirqs_enabled)
1637                 for (i = 0; i < MAX_PIRQS; i++)
1638                         pirq_entries[i] = -1;
1639
1640         /*
1641          * The number of IO-APIC IRQ registers (== #pins):
1642          */
1643         for (apic = 0; apic < nr_ioapics; apic++) {
1644                 spin_lock_irqsave(&ioapic_lock, flags);
1645                 reg_01.raw = io_apic_read(apic, 1);
1646                 spin_unlock_irqrestore(&ioapic_lock, flags);
1647                 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
1648         }
1649         for(apic = 0; apic < nr_ioapics; apic++) {
1650                 int pin;
1651                 /* See if any of the pins is in ExtINT mode */
1652                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1653                         struct IO_APIC_route_entry entry;
1654                         spin_lock_irqsave(&ioapic_lock, flags);
1655                         *(((int *)&entry) + 0) = io_apic_read(apic, 0x10 + 2 * pin);
1656                         *(((int *)&entry) + 1) = io_apic_read(apic, 0x11 + 2 * pin);
1657                         spin_unlock_irqrestore(&ioapic_lock, flags);
1658
1659
1660                         /* If the interrupt line is enabled and in ExtInt mode
1661                          * I have found the pin where the i8259 is connected.
1662                          */
1663                         if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
1664                                 ioapic_i8259.apic = apic;
1665                                 ioapic_i8259.pin  = pin;
1666                                 goto found_i8259;
1667                         }
1668                 }
1669         }
1670  found_i8259:
1671         /* Look to see what if the MP table has reported the ExtINT */
1672         /* If we could not find the appropriate pin by looking at the ioapic
1673          * the i8259 probably is not connected the ioapic but give the
1674          * mptable a chance anyway.
1675          */
1676         i8259_pin  = find_isa_irq_pin(0, mp_ExtINT);
1677         i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
1678         /* Trust the MP table if nothing is setup in the hardware */
1679         if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
1680                 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
1681                 ioapic_i8259.pin  = i8259_pin;
1682                 ioapic_i8259.apic = i8259_apic;
1683         }
1684         /* Complain if the MP table and the hardware disagree */
1685         if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
1686                 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
1687         {
1688                 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
1689         }
1690
1691         /*
1692          * Do not trust the IO-APIC being empty at bootup
1693          */
1694         clear_IO_APIC();
1695 }
1696
1697 /*
1698  * Not an __init, needed by the reboot code
1699  */
1700 void disable_IO_APIC(void)
1701 {
1702         /*
1703          * Clear the IO-APIC before rebooting:
1704          */
1705         clear_IO_APIC();
1706
1707         /*
1708          * If the i8259 is routed through an IOAPIC
1709          * Put that IOAPIC in virtual wire mode
1710          * so legacy interrupts can be delivered.
1711          */
1712         if (ioapic_i8259.pin != -1) {
1713                 struct IO_APIC_route_entry entry;
1714                 unsigned long flags;
1715
1716                 memset(&entry, 0, sizeof(entry));
1717                 entry.mask            = 0; /* Enabled */
1718                 entry.trigger         = 0; /* Edge */
1719                 entry.irr             = 0;
1720                 entry.polarity        = 0; /* High */
1721                 entry.delivery_status = 0;
1722                 entry.dest_mode       = 0; /* Physical */
1723                 entry.delivery_mode   = dest_ExtINT; /* ExtInt */
1724                 entry.vector          = 0;
1725                 entry.dest.physical.physical_dest =
1726                                         GET_APIC_ID(apic_read(APIC_ID));
1727
1728                 /*
1729                  * Add it to the IO-APIC irq-routing table:
1730                  */
1731                 spin_lock_irqsave(&ioapic_lock, flags);
1732                 io_apic_write(ioapic_i8259.apic, 0x11+2*ioapic_i8259.pin,
1733                         *(((int *)&entry)+1));
1734                 io_apic_write(ioapic_i8259.apic, 0x10+2*ioapic_i8259.pin,
1735                         *(((int *)&entry)+0));
1736                 spin_unlock_irqrestore(&ioapic_lock, flags);
1737         }
1738         disconnect_bsp_APIC(ioapic_i8259.pin != -1);
1739 }
1740
1741 /*
1742  * function to set the IO-APIC physical IDs based on the
1743  * values stored in the MPC table.
1744  *
1745  * by Matt Domsch <Matt_Domsch@dell.com>  Tue Dec 21 12:25:05 CST 1999
1746  */
1747
1748 #ifndef CONFIG_X86_NUMAQ
1749 static void __init setup_ioapic_ids_from_mpc(void)
1750 {
1751         union IO_APIC_reg_00 reg_00;
1752         physid_mask_t phys_id_present_map;
1753         int apic;
1754         int i;
1755         unsigned char old_id;
1756         unsigned long flags;
1757
1758         /*
1759          * Don't check I/O APIC IDs for xAPIC systems.  They have
1760          * no meaning without the serial APIC bus.
1761          */
1762         if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL && boot_cpu_data.x86 < 15))
1763                 return;
1764         /*
1765          * This is broken; anything with a real cpu count has to
1766          * circumvent this idiocy regardless.
1767          */
1768         phys_id_present_map = ioapic_phys_id_map(phys_cpu_present_map);
1769
1770         /*
1771          * Set the IOAPIC ID to the value stored in the MPC table.
1772          */
1773         for (apic = 0; apic < nr_ioapics; apic++) {
1774
1775                 /* Read the register 0 value */
1776                 spin_lock_irqsave(&ioapic_lock, flags);
1777                 reg_00.raw = io_apic_read(apic, 0);
1778                 spin_unlock_irqrestore(&ioapic_lock, flags);
1779
1780                 old_id = mp_ioapics[apic].mpc_apicid;
1781
1782                 if (mp_ioapics[apic].mpc_apicid >= get_physical_broadcast()) {
1783                         printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
1784                                 apic, mp_ioapics[apic].mpc_apicid);
1785                         printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1786                                 reg_00.bits.ID);
1787                         mp_ioapics[apic].mpc_apicid = reg_00.bits.ID;
1788                 }
1789
1790                 /*
1791                  * Sanity check, is the ID really free? Every APIC in a
1792                  * system must have a unique ID or we get lots of nice
1793                  * 'stuck on smp_invalidate_needed IPI wait' messages.
1794                  */
1795                 if (check_apicid_used(phys_id_present_map,
1796                                         mp_ioapics[apic].mpc_apicid)) {
1797                         printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n",
1798                                 apic, mp_ioapics[apic].mpc_apicid);
1799                         for (i = 0; i < get_physical_broadcast(); i++)
1800                                 if (!physid_isset(i, phys_id_present_map))
1801                                         break;
1802                         if (i >= get_physical_broadcast())
1803                                 panic("Max APIC ID exceeded!\n");
1804                         printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1805                                 i);
1806                         physid_set(i, phys_id_present_map);
1807                         mp_ioapics[apic].mpc_apicid = i;
1808                 } else {
1809                         physid_mask_t tmp;
1810                         tmp = apicid_to_cpu_present(mp_ioapics[apic].mpc_apicid);
1811                         apic_printk(APIC_VERBOSE, "Setting %d in the "
1812                                         "phys_id_present_map\n",
1813                                         mp_ioapics[apic].mpc_apicid);
1814                         physids_or(phys_id_present_map, phys_id_present_map, tmp);
1815                 }
1816
1817
1818                 /*
1819                  * We need to adjust the IRQ routing table
1820                  * if the ID changed.
1821                  */
1822                 if (old_id != mp_ioapics[apic].mpc_apicid)
1823                         for (i = 0; i < mp_irq_entries; i++)
1824                                 if (mp_irqs[i].mpc_dstapic == old_id)
1825                                         mp_irqs[i].mpc_dstapic
1826                                                 = mp_ioapics[apic].mpc_apicid;
1827
1828                 /*
1829                  * Read the right value from the MPC table and
1830                  * write it into the ID register.
1831                  */
1832                 apic_printk(APIC_VERBOSE, KERN_INFO
1833                         "...changing IO-APIC physical APIC ID to %d ...",
1834                         mp_ioapics[apic].mpc_apicid);
1835
1836                 reg_00.bits.ID = mp_ioapics[apic].mpc_apicid;
1837                 spin_lock_irqsave(&ioapic_lock, flags);
1838                 io_apic_write(apic, 0, reg_00.raw);
1839                 spin_unlock_irqrestore(&ioapic_lock, flags);
1840
1841                 /*
1842                  * Sanity check
1843                  */
1844                 spin_lock_irqsave(&ioapic_lock, flags);
1845                 reg_00.raw = io_apic_read(apic, 0);
1846                 spin_unlock_irqrestore(&ioapic_lock, flags);
1847                 if (reg_00.bits.ID != mp_ioapics[apic].mpc_apicid)
1848                         printk("could not set ID!\n");
1849                 else
1850                         apic_printk(APIC_VERBOSE, " ok.\n");
1851         }
1852 }
1853 #else
1854 static void __init setup_ioapic_ids_from_mpc(void) { }
1855 #endif
1856
1857 /*
1858  * There is a nasty bug in some older SMP boards, their mptable lies
1859  * about the timer IRQ. We do the following to work around the situation:
1860  *
1861  *      - timer IRQ defaults to IO-APIC IRQ
1862  *      - if this function detects that timer IRQs are defunct, then we fall
1863  *        back to ISA timer IRQs
1864  */
1865 static int __init timer_irq_works(void)
1866 {
1867         unsigned long t1 = jiffies;
1868
1869         local_irq_enable();
1870         /* Let ten ticks pass... */
1871         mdelay((10 * 1000) / HZ);
1872
1873         /*
1874          * Expect a few ticks at least, to be sure some possible
1875          * glue logic does not lock up after one or two first
1876          * ticks in a non-ExtINT mode.  Also the local APIC
1877          * might have cached one ExtINT interrupt.  Finally, at
1878          * least one tick may be lost due to delays.
1879          */
1880         if (jiffies - t1 > 4)
1881                 return 1;
1882
1883         return 0;
1884 }
1885
1886 /*
1887  * In the SMP+IOAPIC case it might happen that there are an unspecified
1888  * number of pending IRQ events unhandled. These cases are very rare,
1889  * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1890  * better to do it this way as thus we do not have to be aware of
1891  * 'pending' interrupts in the IRQ path, except at this point.
1892  */
1893 /*
1894  * Edge triggered needs to resend any interrupt
1895  * that was delayed but this is now handled in the device
1896  * independent code.
1897  */
1898
1899 /*
1900  * Starting up a edge-triggered IO-APIC interrupt is
1901  * nasty - we need to make sure that we get the edge.
1902  * If it is already asserted for some reason, we need
1903  * return 1 to indicate that is was pending.
1904  *
1905  * This is not complete - we should be able to fake
1906  * an edge even if it isn't on the 8259A...
1907  */
1908 static unsigned int startup_edge_ioapic_irq(unsigned int irq)
1909 {
1910         int was_pending = 0;
1911         unsigned long flags;
1912
1913         spin_lock_irqsave(&ioapic_lock, flags);
1914         if (irq < 16) {
1915                 disable_8259A_irq(irq);
1916                 if (i8259A_irq_pending(irq))
1917                         was_pending = 1;
1918         }
1919         __unmask_IO_APIC_irq(irq);
1920         spin_unlock_irqrestore(&ioapic_lock, flags);
1921
1922         return was_pending;
1923 }
1924
1925 /*
1926  * Once we have recorded IRQ_PENDING already, we can mask the
1927  * interrupt for real. This prevents IRQ storms from unhandled
1928  * devices.
1929  */
1930 static void ack_edge_ioapic_irq(unsigned int irq)
1931 {
1932         move_irq(irq);
1933         if ((irq_desc[irq].status & (IRQ_PENDING | IRQ_DISABLED))
1934                                         == (IRQ_PENDING | IRQ_DISABLED))
1935                 mask_IO_APIC_irq(irq);
1936         ack_APIC_irq();
1937 }
1938
1939 /*
1940  * Level triggered interrupts can just be masked,
1941  * and shutting down and starting up the interrupt
1942  * is the same as enabling and disabling them -- except
1943  * with a startup need to return a "was pending" value.
1944  *
1945  * Level triggered interrupts are special because we
1946  * do not touch any IO-APIC register while handling
1947  * them. We ack the APIC in the end-IRQ handler, not
1948  * in the start-IRQ-handler. Protection against reentrance
1949  * from the same interrupt is still provided, both by the
1950  * generic IRQ layer and by the fact that an unacked local
1951  * APIC does not accept IRQs.
1952  */
1953 static unsigned int startup_level_ioapic_irq (unsigned int irq)
1954 {
1955         unmask_IO_APIC_irq(irq);
1956
1957         return 0; /* don't check for pending */
1958 }
1959
1960 static void end_level_ioapic_irq (unsigned int irq)
1961 {
1962         unsigned long v;
1963         int i;
1964
1965         move_irq(irq);
1966 /*
1967  * It appears there is an erratum which affects at least version 0x11
1968  * of I/O APIC (that's the 82093AA and cores integrated into various
1969  * chipsets).  Under certain conditions a level-triggered interrupt is
1970  * erroneously delivered as edge-triggered one but the respective IRR
1971  * bit gets set nevertheless.  As a result the I/O unit expects an EOI
1972  * message but it will never arrive and further interrupts are blocked
1973  * from the source.  The exact reason is so far unknown, but the
1974  * phenomenon was observed when two consecutive interrupt requests
1975  * from a given source get delivered to the same CPU and the source is
1976  * temporarily disabled in between.
1977  *
1978  * A workaround is to simulate an EOI message manually.  We achieve it
1979  * by setting the trigger mode to edge and then to level when the edge
1980  * trigger mode gets detected in the TMR of a local APIC for a
1981  * level-triggered interrupt.  We mask the source for the time of the
1982  * operation to prevent an edge-triggered interrupt escaping meanwhile.
1983  * The idea is from Manfred Spraul.  --macro
1984  */
1985         i = IO_APIC_VECTOR(irq);
1986
1987         v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1));
1988
1989         ack_APIC_irq();
1990
1991         if (!(v & (1 << (i & 0x1f)))) {
1992                 atomic_inc(&irq_mis_count);
1993                 spin_lock(&ioapic_lock);
1994                 __mask_and_edge_IO_APIC_irq(irq);
1995                 __unmask_and_level_IO_APIC_irq(irq);
1996                 spin_unlock(&ioapic_lock);
1997         }
1998 }
1999
2000 #ifdef CONFIG_PCI_MSI
2001 static unsigned int startup_edge_ioapic_vector(unsigned int vector)
2002 {
2003         int irq = vector_to_irq(vector);
2004
2005         return startup_edge_ioapic_irq(irq);
2006 }
2007
2008 static void ack_edge_ioapic_vector(unsigned int vector)
2009 {
2010         int irq = vector_to_irq(vector);
2011
2012         move_native_irq(vector);
2013         ack_edge_ioapic_irq(irq);
2014 }
2015
2016 static unsigned int startup_level_ioapic_vector (unsigned int vector)
2017 {
2018         int irq = vector_to_irq(vector);
2019
2020         return startup_level_ioapic_irq (irq);
2021 }
2022
2023 static void end_level_ioapic_vector (unsigned int vector)
2024 {
2025         int irq = vector_to_irq(vector);
2026
2027         move_native_irq(vector);
2028         end_level_ioapic_irq(irq);
2029 }
2030
2031 static void mask_IO_APIC_vector (unsigned int vector)
2032 {
2033         int irq = vector_to_irq(vector);
2034
2035         mask_IO_APIC_irq(irq);
2036 }
2037
2038 static void unmask_IO_APIC_vector (unsigned int vector)
2039 {
2040         int irq = vector_to_irq(vector);
2041
2042         unmask_IO_APIC_irq(irq);
2043 }
2044
2045 #ifdef CONFIG_SMP
2046 static void set_ioapic_affinity_vector (unsigned int vector,
2047                                         cpumask_t cpu_mask)
2048 {
2049         int irq = vector_to_irq(vector);
2050
2051         set_native_irq_info(vector, cpu_mask);
2052         set_ioapic_affinity_irq(irq, cpu_mask);
2053 }
2054 #endif
2055 #endif
2056
2057 /*
2058  * Level and edge triggered IO-APIC interrupts need different handling,
2059  * so we use two separate IRQ descriptors. Edge triggered IRQs can be
2060  * handled with the level-triggered descriptor, but that one has slightly
2061  * more overhead. Level-triggered interrupts cannot be handled with the
2062  * edge-triggered handler, without risking IRQ storms and other ugly
2063  * races.
2064  */
2065 static struct hw_interrupt_type ioapic_edge_type __read_mostly = {
2066         .typename       = "IO-APIC-edge",
2067         .startup        = startup_edge_ioapic,
2068         .shutdown       = shutdown_edge_ioapic,
2069         .enable         = enable_edge_ioapic,
2070         .disable        = disable_edge_ioapic,
2071         .ack            = ack_edge_ioapic,
2072         .end            = end_edge_ioapic,
2073 #ifdef CONFIG_SMP
2074         .set_affinity   = set_ioapic_affinity,
2075 #endif
2076 };
2077
2078 static struct hw_interrupt_type ioapic_level_type __read_mostly = {
2079         .typename       = "IO-APIC-level",
2080         .startup        = startup_level_ioapic,
2081         .shutdown       = shutdown_level_ioapic,
2082         .enable         = enable_level_ioapic,
2083         .disable        = disable_level_ioapic,
2084         .ack            = mask_and_ack_level_ioapic,
2085         .end            = end_level_ioapic,
2086 #ifdef CONFIG_SMP
2087         .set_affinity   = set_ioapic_affinity,
2088 #endif
2089 };
2090
2091 static inline void init_IO_APIC_traps(void)
2092 {
2093         int irq;
2094
2095         /*
2096          * NOTE! The local APIC isn't very good at handling
2097          * multiple interrupts at the same interrupt level.
2098          * As the interrupt level is determined by taking the
2099          * vector number and shifting that right by 4, we
2100          * want to spread these out a bit so that they don't
2101          * all fall in the same interrupt level.
2102          *
2103          * Also, we've got to be careful not to trash gate
2104          * 0x80, because int 0x80 is hm, kind of importantish. ;)
2105          */
2106         for (irq = 0; irq < NR_IRQS ; irq++) {
2107                 int tmp = irq;
2108                 if (use_pci_vector()) {
2109                         if (!platform_legacy_irq(tmp))
2110                                 if ((tmp = vector_to_irq(tmp)) == -1)
2111                                         continue;
2112                 }
2113                 if (IO_APIC_IRQ(tmp) && !IO_APIC_VECTOR(tmp)) {
2114                         /*
2115                          * Hmm.. We don't have an entry for this,
2116                          * so default to an old-fashioned 8259
2117                          * interrupt if we can..
2118                          */
2119                         if (irq < 16)
2120                                 make_8259A_irq(irq);
2121                         else
2122                                 /* Strange. Oh, well.. */
2123                                 irq_desc[irq].handler = &no_irq_type;
2124                 }
2125         }
2126 }
2127
2128 static void enable_lapic_irq (unsigned int irq)
2129 {
2130         unsigned long v;
2131
2132         v = apic_read(APIC_LVT0);
2133         apic_write_around(APIC_LVT0, v & ~APIC_LVT_MASKED);
2134 }
2135
2136 static void disable_lapic_irq (unsigned int irq)
2137 {
2138         unsigned long v;
2139
2140         v = apic_read(APIC_LVT0);
2141         apic_write_around(APIC_LVT0, v | APIC_LVT_MASKED);
2142 }
2143
2144 static void ack_lapic_irq (unsigned int irq)
2145 {
2146         ack_APIC_irq();
2147 }
2148
2149 static void end_lapic_irq (unsigned int i) { /* nothing */ }
2150
2151 static struct hw_interrupt_type lapic_irq_type __read_mostly = {
2152         .typename       = "local-APIC-edge",
2153         .startup        = NULL, /* startup_irq() not used for IRQ0 */
2154         .shutdown       = NULL, /* shutdown_irq() not used for IRQ0 */
2155         .enable         = enable_lapic_irq,
2156         .disable        = disable_lapic_irq,
2157         .ack            = ack_lapic_irq,
2158         .end            = end_lapic_irq
2159 };
2160
2161 static void setup_nmi (void)
2162 {
2163         /*
2164          * Dirty trick to enable the NMI watchdog ...
2165          * We put the 8259A master into AEOI mode and
2166          * unmask on all local APICs LVT0 as NMI.
2167          *
2168          * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
2169          * is from Maciej W. Rozycki - so we do not have to EOI from
2170          * the NMI handler or the timer interrupt.
2171          */
2172         apic_printk(APIC_VERBOSE, KERN_INFO "activating NMI Watchdog ...");
2173
2174         on_each_cpu(enable_NMI_through_LVT0, NULL, 1, 1);
2175
2176         apic_printk(APIC_VERBOSE, " done.\n");
2177 }
2178
2179 /*
2180  * This looks a bit hackish but it's about the only one way of sending
2181  * a few INTA cycles to 8259As and any associated glue logic.  ICR does
2182  * not support the ExtINT mode, unfortunately.  We need to send these
2183  * cycles as some i82489DX-based boards have glue logic that keeps the
2184  * 8259A interrupt line asserted until INTA.  --macro
2185  */
2186 static inline void unlock_ExtINT_logic(void)
2187 {
2188         int apic, pin, i;
2189         struct IO_APIC_route_entry entry0, entry1;
2190         unsigned char save_control, save_freq_select;
2191         unsigned long flags;
2192
2193         pin  = find_isa_irq_pin(8, mp_INT);
2194         apic = find_isa_irq_apic(8, mp_INT);
2195         if (pin == -1)
2196                 return;
2197
2198         spin_lock_irqsave(&ioapic_lock, flags);
2199         *(((int *)&entry0) + 1) = io_apic_read(apic, 0x11 + 2 * pin);
2200         *(((int *)&entry0) + 0) = io_apic_read(apic, 0x10 + 2 * pin);
2201         spin_unlock_irqrestore(&ioapic_lock, flags);
2202         clear_IO_APIC_pin(apic, pin);
2203
2204         memset(&entry1, 0, sizeof(entry1));
2205
2206         entry1.dest_mode = 0;                   /* physical delivery */
2207         entry1.mask = 0;                        /* unmask IRQ now */
2208         entry1.dest.physical.physical_dest = hard_smp_processor_id();
2209         entry1.delivery_mode = dest_ExtINT;
2210         entry1.polarity = entry0.polarity;
2211         entry1.trigger = 0;
2212         entry1.vector = 0;
2213
2214         spin_lock_irqsave(&ioapic_lock, flags);
2215         io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry1) + 1));
2216         io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry1) + 0));
2217         spin_unlock_irqrestore(&ioapic_lock, flags);
2218
2219         save_control = CMOS_READ(RTC_CONTROL);
2220         save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
2221         CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
2222                    RTC_FREQ_SELECT);
2223         CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
2224
2225         i = 100;
2226         while (i-- > 0) {
2227                 mdelay(10);
2228                 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
2229                         i -= 10;
2230         }
2231
2232         CMOS_WRITE(save_control, RTC_CONTROL);
2233         CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
2234         clear_IO_APIC_pin(apic, pin);
2235
2236         spin_lock_irqsave(&ioapic_lock, flags);
2237         io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry0) + 1));
2238         io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry0) + 0));
2239         spin_unlock_irqrestore(&ioapic_lock, flags);
2240 }
2241
2242 /*
2243  * This code may look a bit paranoid, but it's supposed to cooperate with
2244  * a wide range of boards and BIOS bugs.  Fortunately only the timer IRQ
2245  * is so screwy.  Thanks to Brian Perkins for testing/hacking this beast
2246  * fanatically on his truly buggy board.
2247  */
2248 static inline void check_timer(void)
2249 {
2250         int apic1, pin1, apic2, pin2;
2251         int vector;
2252
2253         /*
2254          * get/set the timer IRQ vector:
2255          */
2256         disable_8259A_irq(0);
2257         vector = assign_irq_vector(0);
2258         set_intr_gate(vector, interrupt[0]);
2259
2260         /*
2261          * Subtle, code in do_timer_interrupt() expects an AEOI
2262          * mode for the 8259A whenever interrupts are routed
2263          * through I/O APICs.  Also IRQ0 has to be enabled in
2264          * the 8259A which implies the virtual wire has to be
2265          * disabled in the local APIC.
2266          */
2267         apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
2268         init_8259A(1);
2269         timer_ack = 1;
2270         enable_8259A_irq(0);
2271
2272         pin1  = find_isa_irq_pin(0, mp_INT);
2273         apic1 = find_isa_irq_apic(0, mp_INT);
2274         pin2  = ioapic_i8259.pin;
2275         apic2 = ioapic_i8259.apic;
2276
2277         printk(KERN_INFO "..TIMER: vector=0x%02X apic1=%d pin1=%d apic2=%d pin2=%d\n",
2278                 vector, apic1, pin1, apic2, pin2);
2279
2280         if (pin1 != -1) {
2281                 /*
2282                  * Ok, does IRQ0 through the IOAPIC work?
2283                  */
2284                 unmask_IO_APIC_irq(0);
2285                 if (timer_irq_works()) {
2286                         if (nmi_watchdog == NMI_IO_APIC) {
2287                                 disable_8259A_irq(0);
2288                                 setup_nmi();
2289                                 enable_8259A_irq(0);
2290                         }
2291                         if (disable_timer_pin_1 > 0)
2292                                 clear_IO_APIC_pin(0, pin1);
2293                         return;
2294                 }
2295                 clear_IO_APIC_pin(apic1, pin1);
2296                 printk(KERN_ERR "..MP-BIOS bug: 8254 timer not connected to "
2297                                 "IO-APIC\n");
2298         }
2299
2300         printk(KERN_INFO "...trying to set up timer (IRQ0) through the 8259A ... ");
2301         if (pin2 != -1) {
2302                 printk("\n..... (found pin %d) ...", pin2);
2303                 /*
2304                  * legacy devices should be connected to IO APIC #0
2305                  */
2306                 setup_ExtINT_IRQ0_pin(apic2, pin2, vector);
2307                 if (timer_irq_works()) {
2308                         printk("works.\n");
2309                         if (pin1 != -1)
2310                                 replace_pin_at_irq(0, apic1, pin1, apic2, pin2);
2311                         else
2312                                 add_pin_to_irq(0, apic2, pin2);
2313                         if (nmi_watchdog == NMI_IO_APIC) {
2314                                 setup_nmi();
2315                         }
2316                         return;
2317                 }
2318                 /*
2319                  * Cleanup, just in case ...
2320                  */
2321                 clear_IO_APIC_pin(apic2, pin2);
2322         }
2323         printk(" failed.\n");
2324
2325         if (nmi_watchdog == NMI_IO_APIC) {
2326                 printk(KERN_WARNING "timer doesn't work through the IO-APIC - disabling NMI Watchdog!\n");
2327                 nmi_watchdog = 0;
2328         }
2329
2330         printk(KERN_INFO "...trying to set up timer as Virtual Wire IRQ...");
2331
2332         disable_8259A_irq(0);
2333         irq_desc[0].handler = &lapic_irq_type;
2334         apic_write_around(APIC_LVT0, APIC_DM_FIXED | vector);   /* Fixed mode */
2335         enable_8259A_irq(0);
2336
2337         if (timer_irq_works()) {
2338                 printk(" works.\n");
2339                 return;
2340         }
2341         apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | vector);
2342         printk(" failed.\n");
2343
2344         printk(KERN_INFO "...trying to set up timer as ExtINT IRQ...");
2345
2346         timer_ack = 0;
2347         init_8259A(0);
2348         make_8259A_irq(0);
2349         apic_write_around(APIC_LVT0, APIC_DM_EXTINT);
2350
2351         unlock_ExtINT_logic();
2352
2353         if (timer_irq_works()) {
2354                 printk(" works.\n");
2355                 return;
2356         }
2357         printk(" failed :(.\n");
2358         panic("IO-APIC + timer doesn't work!  Boot with apic=debug and send a "
2359                 "report.  Then try booting with the 'noapic' option");
2360 }
2361
2362 /*
2363  *
2364  * IRQ's that are handled by the PIC in the MPS IOAPIC case.
2365  * - IRQ2 is the cascade IRQ, and cannot be a io-apic IRQ.
2366  *   Linux doesn't really care, as it's not actually used
2367  *   for any interrupt handling anyway.
2368  */
2369 #define PIC_IRQS        (1 << PIC_CASCADE_IR)
2370
2371 void __init setup_IO_APIC(void)
2372 {
2373         enable_IO_APIC();
2374
2375         if (acpi_ioapic)
2376                 io_apic_irqs = ~0;      /* all IRQs go through IOAPIC */
2377         else
2378                 io_apic_irqs = ~PIC_IRQS;
2379
2380         printk("ENABLING IO-APIC IRQs\n");
2381
2382         /*
2383          * Set up IO-APIC IRQ routing.
2384          */
2385         if (!acpi_ioapic)
2386                 setup_ioapic_ids_from_mpc();
2387         sync_Arb_IDs();
2388         setup_IO_APIC_irqs();
2389         init_IO_APIC_traps();
2390         check_timer();
2391         if (!acpi_ioapic)
2392                 print_IO_APIC();
2393 }
2394
2395 /*
2396  *      Called after all the initialization is done. If we didnt find any
2397  *      APIC bugs then we can allow the modify fast path
2398  */
2399
2400 static int __init io_apic_bug_finalize(void)
2401 {
2402         if(sis_apic_bug == -1)
2403                 sis_apic_bug = 0;
2404         return 0;
2405 }
2406
2407 late_initcall(io_apic_bug_finalize);
2408
2409 struct sysfs_ioapic_data {
2410         struct sys_device dev;
2411         struct IO_APIC_route_entry entry[0];
2412 };
2413 static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS];
2414
2415 static int ioapic_suspend(struct sys_device *dev, pm_message_t state)
2416 {
2417         struct IO_APIC_route_entry *entry;
2418         struct sysfs_ioapic_data *data;
2419         unsigned long flags;
2420         int i;
2421
2422         data = container_of(dev, struct sysfs_ioapic_data, dev);
2423         entry = data->entry;
2424         spin_lock_irqsave(&ioapic_lock, flags);
2425         for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ ) {
2426                 *(((int *)entry) + 1) = io_apic_read(dev->id, 0x11 + 2 * i);
2427                 *(((int *)entry) + 0) = io_apic_read(dev->id, 0x10 + 2 * i);
2428         }
2429         spin_unlock_irqrestore(&ioapic_lock, flags);
2430
2431         return 0;
2432 }
2433
2434 static int ioapic_resume(struct sys_device *dev)
2435 {
2436         struct IO_APIC_route_entry *entry;
2437         struct sysfs_ioapic_data *data;
2438         unsigned long flags;
2439         union IO_APIC_reg_00 reg_00;
2440         int i;
2441
2442         data = container_of(dev, struct sysfs_ioapic_data, dev);
2443         entry = data->entry;
2444
2445         spin_lock_irqsave(&ioapic_lock, flags);
2446         reg_00.raw = io_apic_read(dev->id, 0);
2447         if (reg_00.bits.ID != mp_ioapics[dev->id].mpc_apicid) {
2448                 reg_00.bits.ID = mp_ioapics[dev->id].mpc_apicid;
2449                 io_apic_write(dev->id, 0, reg_00.raw);
2450         }
2451         for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ ) {
2452                 io_apic_write(dev->id, 0x11+2*i, *(((int *)entry)+1));
2453                 io_apic_write(dev->id, 0x10+2*i, *(((int *)entry)+0));
2454         }
2455         spin_unlock_irqrestore(&ioapic_lock, flags);
2456
2457         return 0;
2458 }
2459
2460 static struct sysdev_class ioapic_sysdev_class = {
2461         set_kset_name("ioapic"),
2462         .suspend = ioapic_suspend,
2463         .resume = ioapic_resume,
2464 };
2465
2466 static int __init ioapic_init_sysfs(void)
2467 {
2468         struct sys_device * dev;
2469         int i, size, error = 0;
2470
2471         error = sysdev_class_register(&ioapic_sysdev_class);
2472         if (error)
2473                 return error;
2474
2475         for (i = 0; i < nr_ioapics; i++ ) {
2476                 size = sizeof(struct sys_device) + nr_ioapic_registers[i]
2477                         * sizeof(struct IO_APIC_route_entry);
2478                 mp_ioapic_data[i] = kmalloc(size, GFP_KERNEL);
2479                 if (!mp_ioapic_data[i]) {
2480                         printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
2481                         continue;
2482                 }
2483                 memset(mp_ioapic_data[i], 0, size);
2484                 dev = &mp_ioapic_data[i]->dev;
2485                 dev->id = i;
2486                 dev->cls = &ioapic_sysdev_class;
2487                 error = sysdev_register(dev);
2488                 if (error) {
2489                         kfree(mp_ioapic_data[i]);
2490                         mp_ioapic_data[i] = NULL;
2491                         printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
2492                         continue;
2493                 }
2494         }
2495
2496         return 0;
2497 }
2498
2499 device_initcall(ioapic_init_sysfs);
2500
2501 /* --------------------------------------------------------------------------
2502                           ACPI-based IOAPIC Configuration
2503    -------------------------------------------------------------------------- */
2504
2505 #ifdef CONFIG_ACPI
2506
2507 int __init io_apic_get_unique_id (int ioapic, int apic_id)
2508 {
2509         union IO_APIC_reg_00 reg_00;
2510         static physid_mask_t apic_id_map = PHYSID_MASK_NONE;
2511         physid_mask_t tmp;
2512         unsigned long flags;
2513         int i = 0;
2514
2515         /*
2516          * The P4 platform supports up to 256 APIC IDs on two separate APIC
2517          * buses (one for LAPICs, one for IOAPICs), where predecessors only
2518          * supports up to 16 on one shared APIC bus.
2519          *
2520          * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
2521          *      advantage of new APIC bus architecture.
2522          */
2523
2524         if (physids_empty(apic_id_map))
2525                 apic_id_map = ioapic_phys_id_map(phys_cpu_present_map);
2526
2527         spin_lock_irqsave(&ioapic_lock, flags);
2528         reg_00.raw = io_apic_read(ioapic, 0);
2529         spin_unlock_irqrestore(&ioapic_lock, flags);
2530
2531         if (apic_id >= get_physical_broadcast()) {
2532                 printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying "
2533                         "%d\n", ioapic, apic_id, reg_00.bits.ID);
2534                 apic_id = reg_00.bits.ID;
2535         }
2536
2537         /*
2538          * Every APIC in a system must have a unique ID or we get lots of nice
2539          * 'stuck on smp_invalidate_needed IPI wait' messages.
2540          */
2541         if (check_apicid_used(apic_id_map, apic_id)) {
2542
2543                 for (i = 0; i < get_physical_broadcast(); i++) {
2544                         if (!check_apicid_used(apic_id_map, i))
2545                                 break;
2546                 }
2547
2548                 if (i == get_physical_broadcast())
2549                         panic("Max apic_id exceeded!\n");
2550
2551                 printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, "
2552                         "trying %d\n", ioapic, apic_id, i);
2553
2554                 apic_id = i;
2555         }
2556
2557         tmp = apicid_to_cpu_present(apic_id);
2558         physids_or(apic_id_map, apic_id_map, tmp);
2559
2560         if (reg_00.bits.ID != apic_id) {
2561                 reg_00.bits.ID = apic_id;
2562
2563                 spin_lock_irqsave(&ioapic_lock, flags);
2564                 io_apic_write(ioapic, 0, reg_00.raw);
2565                 reg_00.raw = io_apic_read(ioapic, 0);
2566                 spin_unlock_irqrestore(&ioapic_lock, flags);
2567
2568                 /* Sanity check */
2569                 if (reg_00.bits.ID != apic_id)
2570                         panic("IOAPIC[%d]: Unable change apic_id!\n", ioapic);
2571         }
2572
2573         apic_printk(APIC_VERBOSE, KERN_INFO
2574                         "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id);
2575
2576         return apic_id;
2577 }
2578
2579
2580 int __init io_apic_get_version (int ioapic)
2581 {
2582         union IO_APIC_reg_01    reg_01;
2583         unsigned long flags;
2584
2585         spin_lock_irqsave(&ioapic_lock, flags);
2586         reg_01.raw = io_apic_read(ioapic, 1);
2587         spin_unlock_irqrestore(&ioapic_lock, flags);
2588
2589         return reg_01.bits.version;
2590 }
2591
2592
2593 int __init io_apic_get_redir_entries (int ioapic)
2594 {
2595         union IO_APIC_reg_01    reg_01;
2596         unsigned long flags;
2597
2598         spin_lock_irqsave(&ioapic_lock, flags);
2599         reg_01.raw = io_apic_read(ioapic, 1);
2600         spin_unlock_irqrestore(&ioapic_lock, flags);
2601
2602         return reg_01.bits.entries;
2603 }
2604
2605
2606 int io_apic_set_pci_routing (int ioapic, int pin, int irq, int edge_level, int active_high_low)
2607 {
2608         struct IO_APIC_route_entry entry;
2609         unsigned long flags;
2610
2611         if (!IO_APIC_IRQ(irq)) {
2612                 printk(KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
2613                         ioapic);
2614                 return -EINVAL;
2615         }
2616
2617         /*
2618          * Generate a PCI IRQ routing entry and program the IOAPIC accordingly.
2619          * Note that we mask (disable) IRQs now -- these get enabled when the
2620          * corresponding device driver registers for this IRQ.
2621          */
2622
2623         memset(&entry,0,sizeof(entry));
2624
2625         entry.delivery_mode = INT_DELIVERY_MODE;
2626         entry.dest_mode = INT_DEST_MODE;
2627         entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
2628         entry.trigger = edge_level;
2629         entry.polarity = active_high_low;
2630         entry.mask  = 1;
2631
2632         /*
2633          * IRQs < 16 are already in the irq_2_pin[] map
2634          */
2635         if (irq >= 16)
2636                 add_pin_to_irq(irq, ioapic, pin);
2637
2638         entry.vector = assign_irq_vector(irq);
2639
2640         apic_printk(APIC_DEBUG, KERN_DEBUG "IOAPIC[%d]: Set PCI routing entry "
2641                 "(%d-%d -> 0x%x -> IRQ %d Mode:%i Active:%i)\n", ioapic,
2642                 mp_ioapics[ioapic].mpc_apicid, pin, entry.vector, irq,
2643                 edge_level, active_high_low);
2644
2645         ioapic_register_intr(irq, entry.vector, edge_level);
2646
2647         if (!ioapic && (irq < 16))
2648                 disable_8259A_irq(irq);
2649
2650         spin_lock_irqsave(&ioapic_lock, flags);
2651         io_apic_write(ioapic, 0x11+2*pin, *(((int *)&entry)+1));
2652         io_apic_write(ioapic, 0x10+2*pin, *(((int *)&entry)+0));
2653         set_native_irq_info(use_pci_vector() ? entry.vector : irq, TARGET_CPUS);
2654         spin_unlock_irqrestore(&ioapic_lock, flags);
2655
2656         return 0;
2657 }
2658
2659 #endif /* CONFIG_ACPI */