2 * arch/sh/kernel/cpu/sh4a/clock-sh7722.c
4 * SH7722 support for the clock framework
6 * Copyright (c) 2006-2007 Nomad Global Solutions Inc
7 * Based on code for sh7343 by Paul Mundt
9 * This file is subject to the terms and conditions of the GNU General Public
10 * License. See the file "COPYING" in the main directory of this archive
13 #include <linux/init.h>
14 #include <linux/kernel.h>
16 #include <linux/errno.h>
17 #include <asm/clock.h>
22 #define ROUND_NEAREST 0
26 static int adjust_algos[][3] = {
28 { NM, N, 1 }, /* N:1, N:1 */
29 { 3, 2, 2 }, /* 3:2:2 */
30 { 5, 2, 2 }, /* 5:2:2 */
31 { N, 1, 1 }, /* N:1:1 */
43 static unsigned long adjust_pair_of_clocks(unsigned long r1, unsigned long r2,
44 int m1, int m2, int round_flag)
46 unsigned long rem, div;
49 pr_debug( "Actual values: r1 = %ld\n", r1);
50 pr_debug( "...............r2 = %ld\n", r2);
54 pr_debug( "setting equal rates: r2 now %ld\n", r2);
55 } else if ((m2 == N && m1 == 1) ||
56 (m2 == NM && m1 == N)) { /* N:1 or NM:N */
57 pr_debug( "Setting rates as 1:N (N:N*M)\n");
59 pr_debug( "...remainder = %ld\n", rem);
62 pr_debug( "...div = %ld\n", div);
65 the_one = rem >= r1/2 ? 1 : 0; break;
72 r2 = r1 * (div + the_one);
73 pr_debug( "...setting r2 to %ld\n", r2);
75 } else if ((m2 == 1 && m1 == N) ||
76 (m2 == N && m1 == NM)) { /* 1:N or N:NM */
77 pr_debug( "Setting rates as N:1 (N*M:N)\n");
79 pr_debug( "...remainder = %ld\n", rem);
82 pr_debug( "...div = %ld\n", div);
85 the_one = rem > r2/2 ? 1 : 0; break;
92 r2 = r1 / (div + the_one);
93 pr_debug( "...setting r2 to %ld\n", r2);
95 } else { /* value:value */
96 pr_debug( "Setting rates as %d:%d\n", m1, m2);
99 pr_debug( "...div = %ld\n", div);
100 pr_debug( "...setting r2 to %ld\n", r2);
106 static void adjust_clocks(int originate, int *l, unsigned long v[],
111 pr_debug( "Go down from %d...\n", originate);
112 /* go up recalculation clocks */
113 for (x = originate; x>0; x -- )
114 v[x-1] = adjust_pair_of_clocks(v[x], v[x-1],
118 pr_debug( "Go up from %d...\n", originate);
119 /* go down recalculation clocks */
120 for (x = originate; x<n_in_line - 1; x ++ )
121 v[x+1] = adjust_pair_of_clocks(v[x], v[x+1],
128 * SH7722 uses a common set of multipliers and divisors, so this
133 * Instead of having two separate multipliers/divisors set, like this:
135 * static int multipliers[] = { 1, 2, 1, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1 };
136 * static int divisors[] = { 1, 3, 2, 5, 3, 4, 5, 6, 8, 10, 12, 16, 20 };
138 * I created the divisors2 array, which is used to calculate rate like
139 * rate = parent * 2 / divisors2[ divisor ];
141 static int divisors2[] = { 2, 3, 4, 5, 6, 8, 10, 12, 16, 20, 24, 32, 40 };
143 static void master_clk_recalc(struct clk *clk)
145 unsigned frqcr = ctrl_inl(FRQCR);
147 clk->rate = CONFIG_SH_PCLK_FREQ * (((frqcr >> 24) & 0x1f) + 1);
150 static void master_clk_init(struct clk *clk)
153 clk->flags |= CLK_RATE_PROPAGATES;
154 clk->rate = CONFIG_SH_PCLK_FREQ;
155 master_clk_recalc(clk);
159 static void module_clk_recalc(struct clk *clk)
161 unsigned long frqcr = ctrl_inl(FRQCR);
163 clk->rate = clk->parent->rate / (((frqcr >> 24) & 0x1f) + 1);
166 static int master_clk_setrate(struct clk *clk, unsigned long rate, int id)
168 int div = rate / clk->rate;
169 int master_divs[] = { 2, 3, 4, 6, 8, 16 };
173 for (index = 1; index < ARRAY_SIZE(master_divs); index++)
174 if (div >= master_divs[index - 1] && div < master_divs[index])
177 if (index >= ARRAY_SIZE(master_divs))
178 index = ARRAY_SIZE(master_divs);
179 div = master_divs[index - 1];
181 frqcr = ctrl_inl(FRQCR);
182 frqcr &= ~(0xF << 24);
183 frqcr |= ( (div-1) << 24);
184 ctrl_outl(frqcr, FRQCR);
189 static struct clk_ops sh7722_master_clk_ops = {
190 .init = master_clk_init,
191 .recalc = master_clk_recalc,
192 .set_rate = master_clk_setrate,
195 static struct clk_ops sh7722_module_clk_ops = {
196 .recalc = module_clk_recalc,
199 struct frqcr_context {
204 struct frqcr_context sh7722_get_clk_context(const char *name)
206 struct frqcr_context ctx = { 0, };
208 if (!strcmp(name, "peripheral_clk")) {
211 } else if (!strcmp(name, "sdram_clk")) {
214 } else if (!strcmp(name, "bus_clk")) {
217 } else if (!strcmp(name, "sh_clk")) {
220 } else if (!strcmp(name, "umem_clk")) {
223 } else if (!strcmp(name, "cpu_clk")) {
231 * sh7722_find_divisors - find divisor for setting rate
233 * All sh7722 clocks use the same set of multipliers/divisors. This function
234 * chooses correct divisor to set the rate of clock with parent clock that
235 * generates frequency of 'parent_rate'
237 * @parent_rate: rate of parent clock
238 * @rate: requested rate to be set
240 static int sh7722_find_divisors(unsigned long parent_rate, unsigned rate)
242 unsigned div2 = parent_rate * 2 / rate;
245 if (rate > parent_rate)
248 for (index = 1; index < ARRAY_SIZE(divisors2); index++) {
249 if (div2 > divisors2[index] && div2 <= divisors2[index])
252 if (index >= ARRAY_SIZE(divisors2))
253 index = ARRAY_SIZE(divisors2) - 1;
254 return divisors2[index];
257 static void sh7722_frqcr_recalc(struct clk *clk)
259 struct frqcr_context ctx = sh7722_get_clk_context(clk->name);
260 unsigned long frqcr = ctrl_inl(FRQCR);
263 index = (frqcr >> ctx.shift) & ctx.mask;
264 clk->rate = clk->parent->rate * 2 / divisors2[index];
267 static int sh7722_frqcr_set_rate(struct clk *clk, unsigned long rate,
270 struct frqcr_context ctx = sh7722_get_clk_context(clk->name);
271 unsigned long parent_rate = clk->parent->rate;
277 if (parent_rate < rate)
280 /* look for multiplier/divisor pair */
281 div = sh7722_find_divisors(parent_rate, rate);
285 /* calculate new value of clock rate */
286 clk->rate = parent_rate * 2 / div;
287 frqcr = ctrl_inl(FRQCR);
289 /* FIXME: adjust as algo_id specifies */
290 if (algo_id != NO_CHANGE) {
292 char *algo_group_1[] = { "cpu_clk", "umem_clk", "sh_clk" };
293 char *algo_group_2[] = { "sh_clk", "bus_clk" };
294 char *algo_group_3[] = { "sh_clk", "sdram_clk" };
295 char *algo_group_4[] = { "bus_clk", "peripheral_clk" };
296 char *algo_group_5[] = { "cpu_clk", "peripheral_clk" };
297 char **algo_current = NULL;
298 /* 3 is the maximum number of clocks in relation */
300 unsigned long values[3]; /* the same comment as above */
301 int part_length = -1;
305 * all the steps below only required if adjustion was
308 if (algo_id == IUS_N1_N1 ||
309 algo_id == IUS_322 ||
310 algo_id == IUS_522 ||
311 algo_id == IUS_N11) {
312 algo_current = algo_group_1;
315 if (algo_id == SB_N1) {
316 algo_current = algo_group_2;
319 if (algo_id == SB3_N1 ||
323 algo_current = algo_group_3;
326 if (algo_id == BP_N1) {
327 algo_current = algo_group_4;
330 if (algo_id == IP_N1) {
331 algo_current = algo_group_5;
335 goto incorrect_algo_id;
338 for (i = 0; i < part_length; i ++ ) {
339 if (originator >= 0 && !strcmp(clk->name,
342 ck[i] = clk_get(NULL, algo_current[i]);
343 values[i] = clk_get_rate(ck[i]);
347 adjust_clocks(originator, adjust_algos[algo_id],
348 values, part_length);
350 for (i = 0; i < part_length; i ++ ) {
351 struct frqcr_context part_ctx;
355 part_div = sh7722_find_divisors(parent_rate,
358 part_ctx = sh7722_get_clk_context(
360 frqcr &= ~(part_ctx.mask <<
362 frqcr |= part_div << part_ctx.shift;
367 ck[i]->ops->recalc(ck[i]);
372 /* was there any error during recalculation ? If so, bail out.. */
373 if (unlikely(err!=0))
376 /* clear FRQCR bits */
377 frqcr &= ~(ctx.mask << ctx.shift);
378 frqcr |= div << ctx.shift;
380 /* ...and perform actual change */
381 ctrl_outl(frqcr, FRQCR);
390 static struct clk_ops sh7722_frqcr_clk_ops = {
391 .recalc = sh7722_frqcr_recalc,
392 .set_rate = sh7722_frqcr_set_rate,
396 * clock ops methods for SIU A/B and IrDA clock
399 static int sh7722_siu_which(struct clk *clk)
401 if (!strcmp(clk->name, "siu_a_clk"))
403 if (!strcmp(clk->name, "siu_b_clk"))
405 if (!strcmp(clk->name, "irda_clk"))
410 static unsigned long sh7722_siu_regs[] = {
416 static int sh7722_siu_start_stop(struct clk *clk, int enable)
418 int siu = sh7722_siu_which(clk);
424 r = ctrl_inl(sh7722_siu_regs[siu]);
426 ctrl_outl(r & ~(1 << 8), sh7722_siu_regs[siu]);
428 ctrl_outl(r | (1 << 8), sh7722_siu_regs[siu]);
432 static void sh7722_siu_enable(struct clk *clk)
434 sh7722_siu_start_stop(clk, 1);
437 static void sh7722_siu_disable(struct clk *clk)
439 sh7722_siu_start_stop(clk, 0);
442 static void sh7722_video_enable(struct clk *clk)
446 r = ctrl_inl(VCLKCR);
447 ctrl_outl( r & ~(1<<8), VCLKCR);
450 static void sh7722_video_disable(struct clk *clk)
454 r = ctrl_inl(VCLKCR);
455 ctrl_outl( r | (1<<8), VCLKCR);
458 static int sh7722_video_set_rate(struct clk *clk, unsigned long rate,
463 r = ctrl_inl(VCLKCR);
465 r |= ((clk->parent->rate / rate - 1) & 0x3F);
466 ctrl_outl(r, VCLKCR);
470 static void sh7722_video_recalc(struct clk *clk)
474 r = ctrl_inl(VCLKCR);
475 clk->rate = clk->parent->rate / ((r & 0x3F) + 1);
478 static int sh7722_siu_set_rate(struct clk *clk, unsigned long rate, int algo_id)
480 int siu = sh7722_siu_which(clk);
487 r = ctrl_inl(sh7722_siu_regs[siu]);
488 div = sh7722_find_divisors(clk->parent->rate, rate);
491 r = (r & ~0xF) | div;
492 ctrl_outl(r, sh7722_siu_regs[siu]);
496 static void sh7722_siu_recalc(struct clk *clk)
498 int siu = sh7722_siu_which(clk);
504 r = ctrl_inl(sh7722_siu_regs[siu]);
505 clk->rate = clk->parent->rate * 2 / divisors2[r & 0xF];
508 static struct clk_ops sh7722_siu_clk_ops = {
509 .recalc = sh7722_siu_recalc,
510 .set_rate = sh7722_siu_set_rate,
511 .enable = sh7722_siu_enable,
512 .disable = sh7722_siu_disable,
515 static struct clk_ops sh7722_video_clk_ops = {
516 .recalc = sh7722_video_recalc,
517 .set_rate = sh7722_video_set_rate,
518 .enable = sh7722_video_enable,
519 .disable = sh7722_video_disable,
522 * and at last, clock definitions themselves
524 static struct clk sh7722_umem_clock = {
526 .ops = &sh7722_frqcr_clk_ops,
529 static struct clk sh7722_sh_clock = {
531 .ops = &sh7722_frqcr_clk_ops,
534 static struct clk sh7722_peripheral_clock = {
535 .name = "peripheral_clk",
536 .ops = &sh7722_frqcr_clk_ops,
539 static struct clk sh7722_sdram_clock = {
541 .ops = &sh7722_frqcr_clk_ops,
545 * these three clocks - SIU A, SIU B, IrDA - share the same clk_ops
546 * methods of clk_ops determine which register they should access by
547 * examining clk->name field
549 static struct clk sh7722_siu_a_clock = {
551 .ops = &sh7722_siu_clk_ops,
554 static struct clk sh7722_siu_b_clock = {
556 .ops = &sh7722_siu_clk_ops,
559 static struct clk sh7722_irda_clock = {
561 .ops = &sh7722_siu_clk_ops,
564 static struct clk sh7722_video_clock = {
566 .ops = &sh7722_video_clk_ops,
569 static struct clk *sh7722_clocks[] = {
572 &sh7722_peripheral_clock,
581 * init in order: master, module, bus, cpu
583 struct clk_ops *onchip_ops[] = {
584 &sh7722_master_clk_ops,
585 &sh7722_module_clk_ops,
586 &sh7722_frqcr_clk_ops,
587 &sh7722_frqcr_clk_ops,
591 arch_init_clk_ops(struct clk_ops **ops, int type)
593 BUG_ON(type < 0 || type > ARRAY_SIZE(onchip_ops));
594 *ops = onchip_ops[type];
597 int __init arch_clk_init(void)
602 master = clk_get(NULL, "master_clk");
603 for (i = 0; i < ARRAY_SIZE(sh7722_clocks); i++) {
604 pr_debug( "Registering clock '%s'\n", sh7722_clocks[i]->name);
605 sh7722_clocks[i]->parent = master;
606 clk_register(sh7722_clocks[i]);