3 * hda_intel.c - Implementation of primary alsa driver code base
6 * Copyright(c) 2004 Intel Corporation. All rights reserved.
8 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
9 * PeiSen Hou <pshou@realtek.com.tw>
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the Free
13 * Software Foundation; either version 2 of the License, or (at your option)
16 * This program is distributed in the hope that it will be useful, but WITHOUT
17 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
21 * You should have received a copy of the GNU General Public License along with
22 * this program; if not, write to the Free Software Foundation, Inc., 59
23 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
27 * Matt Jared matt.jared@intel.com
28 * Andy Kopp andy.kopp@intel.com
29 * Dan Kogan dan.d.kogan@intel.com
33 * 2004.12.01 Major rewrite by tiwai, merged the work of pshou
38 #include <linux/delay.h>
39 #include <linux/interrupt.h>
40 #include <linux/kernel.h>
41 #include <linux/module.h>
42 #include <linux/dma-mapping.h>
43 #include <linux/moduleparam.h>
44 #include <linux/init.h>
45 #include <linux/slab.h>
46 #include <linux/pci.h>
47 #include <linux/mutex.h>
48 #include <linux/reboot.h>
49 #include <sound/core.h>
50 #include <sound/initval.h>
51 #include "hda_codec.h"
54 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
55 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
56 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
57 static char *model[SNDRV_CARDS];
58 static int position_fix[SNDRV_CARDS];
59 static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
60 static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
61 static int probe_only[SNDRV_CARDS];
62 static int single_cmd;
63 static int enable_msi;
65 module_param_array(index, int, NULL, 0444);
66 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
67 module_param_array(id, charp, NULL, 0444);
68 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
69 module_param_array(enable, bool, NULL, 0444);
70 MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
71 module_param_array(model, charp, NULL, 0444);
72 MODULE_PARM_DESC(model, "Use the given board model.");
73 module_param_array(position_fix, int, NULL, 0444);
74 MODULE_PARM_DESC(position_fix, "Fix DMA pointer "
75 "(0 = auto, 1 = none, 2 = POSBUF).");
76 module_param_array(bdl_pos_adj, int, NULL, 0644);
77 MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
78 module_param_array(probe_mask, int, NULL, 0444);
79 MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
80 module_param_array(probe_only, bool, NULL, 0444);
81 MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
82 module_param(single_cmd, bool, 0444);
83 MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
84 "(for debugging only).");
85 module_param(enable_msi, int, 0444);
86 MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
88 #ifdef CONFIG_SND_HDA_POWER_SAVE
89 static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
90 module_param(power_save, int, 0644);
91 MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
92 "(in second, 0 = disable).");
94 /* reset the HD-audio controller in power save mode.
95 * this may give more power-saving, but will take longer time to
98 static int power_save_controller = 1;
99 module_param(power_save_controller, bool, 0644);
100 MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
103 MODULE_LICENSE("GPL");
104 MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
129 MODULE_DESCRIPTION("Intel HDA driver");
131 #define SFX "hda-intel: "
137 #define ICH6_REG_GCAP 0x00
138 #define ICH6_REG_VMIN 0x02
139 #define ICH6_REG_VMAJ 0x03
140 #define ICH6_REG_OUTPAY 0x04
141 #define ICH6_REG_INPAY 0x06
142 #define ICH6_REG_GCTL 0x08
143 #define ICH6_REG_WAKEEN 0x0c
144 #define ICH6_REG_STATESTS 0x0e
145 #define ICH6_REG_GSTS 0x10
146 #define ICH6_REG_INTCTL 0x20
147 #define ICH6_REG_INTSTS 0x24
148 #define ICH6_REG_WALCLK 0x30
149 #define ICH6_REG_SYNC 0x34
150 #define ICH6_REG_CORBLBASE 0x40
151 #define ICH6_REG_CORBUBASE 0x44
152 #define ICH6_REG_CORBWP 0x48
153 #define ICH6_REG_CORBRP 0x4A
154 #define ICH6_REG_CORBCTL 0x4c
155 #define ICH6_REG_CORBSTS 0x4d
156 #define ICH6_REG_CORBSIZE 0x4e
158 #define ICH6_REG_RIRBLBASE 0x50
159 #define ICH6_REG_RIRBUBASE 0x54
160 #define ICH6_REG_RIRBWP 0x58
161 #define ICH6_REG_RINTCNT 0x5a
162 #define ICH6_REG_RIRBCTL 0x5c
163 #define ICH6_REG_RIRBSTS 0x5d
164 #define ICH6_REG_RIRBSIZE 0x5e
166 #define ICH6_REG_IC 0x60
167 #define ICH6_REG_IR 0x64
168 #define ICH6_REG_IRS 0x68
169 #define ICH6_IRS_VALID (1<<1)
170 #define ICH6_IRS_BUSY (1<<0)
172 #define ICH6_REG_DPLBASE 0x70
173 #define ICH6_REG_DPUBASE 0x74
174 #define ICH6_DPLBASE_ENABLE 0x1 /* Enable position buffer */
176 /* SD offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
177 enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 };
179 /* stream register offsets from stream base */
180 #define ICH6_REG_SD_CTL 0x00
181 #define ICH6_REG_SD_STS 0x03
182 #define ICH6_REG_SD_LPIB 0x04
183 #define ICH6_REG_SD_CBL 0x08
184 #define ICH6_REG_SD_LVI 0x0c
185 #define ICH6_REG_SD_FIFOW 0x0e
186 #define ICH6_REG_SD_FIFOSIZE 0x10
187 #define ICH6_REG_SD_FORMAT 0x12
188 #define ICH6_REG_SD_BDLPL 0x18
189 #define ICH6_REG_SD_BDLPU 0x1c
192 #define ICH6_PCIREG_TCSEL 0x44
198 /* max number of SDs */
199 /* ICH, ATI and VIA have 4 playback and 4 capture */
200 #define ICH6_NUM_CAPTURE 4
201 #define ICH6_NUM_PLAYBACK 4
203 /* ULI has 6 playback and 5 capture */
204 #define ULI_NUM_CAPTURE 5
205 #define ULI_NUM_PLAYBACK 6
207 /* ATI HDMI has 1 playback and 0 capture */
208 #define ATIHDMI_NUM_CAPTURE 0
209 #define ATIHDMI_NUM_PLAYBACK 1
211 /* TERA has 4 playback and 3 capture */
212 #define TERA_NUM_CAPTURE 3
213 #define TERA_NUM_PLAYBACK 4
215 /* this number is statically defined for simplicity */
216 #define MAX_AZX_DEV 16
218 /* max number of fragments - we may use more if allocating more pages for BDL */
219 #define BDL_SIZE 4096
220 #define AZX_MAX_BDL_ENTRIES (BDL_SIZE / 16)
221 #define AZX_MAX_FRAG 32
222 /* max buffer size - no h/w limit, you can increase as you like */
223 #define AZX_MAX_BUF_SIZE (1024*1024*1024)
224 /* max number of PCM devics per card */
225 #define AZX_MAX_PCMS 8
227 /* RIRB int mask: overrun[2], response[0] */
228 #define RIRB_INT_RESPONSE 0x01
229 #define RIRB_INT_OVERRUN 0x04
230 #define RIRB_INT_MASK 0x05
232 /* STATESTS int mask: S3,SD2,SD1,SD0 */
233 #define AZX_MAX_CODECS 4
234 #define STATESTS_INT_MASK 0x0f
237 #define SD_CTL_STREAM_RESET 0x01 /* stream reset bit */
238 #define SD_CTL_DMA_START 0x02 /* stream DMA start bit */
239 #define SD_CTL_STRIPE (3 << 16) /* stripe control */
240 #define SD_CTL_TRAFFIC_PRIO (1 << 18) /* traffic priority */
241 #define SD_CTL_DIR (1 << 19) /* bi-directional stream */
242 #define SD_CTL_STREAM_TAG_MASK (0xf << 20)
243 #define SD_CTL_STREAM_TAG_SHIFT 20
245 /* SD_CTL and SD_STS */
246 #define SD_INT_DESC_ERR 0x10 /* descriptor error interrupt */
247 #define SD_INT_FIFO_ERR 0x08 /* FIFO error interrupt */
248 #define SD_INT_COMPLETE 0x04 /* completion interrupt */
249 #define SD_INT_MASK (SD_INT_DESC_ERR|SD_INT_FIFO_ERR|\
253 #define SD_STS_FIFO_READY 0x20 /* FIFO ready */
255 /* INTCTL and INTSTS */
256 #define ICH6_INT_ALL_STREAM 0xff /* all stream interrupts */
257 #define ICH6_INT_CTRL_EN 0x40000000 /* controller interrupt enable bit */
258 #define ICH6_INT_GLOBAL_EN 0x80000000 /* global interrupt enable bit */
260 /* GCTL unsolicited response enable bit */
261 #define ICH6_GCTL_UREN (1<<8)
264 #define ICH6_GCTL_RESET (1<<0)
266 /* CORB/RIRB control, read/write pointer */
267 #define ICH6_RBCTL_DMA_EN 0x02 /* enable DMA */
268 #define ICH6_RBCTL_IRQ_EN 0x01 /* enable IRQ */
269 #define ICH6_RBRWP_CLR 0x8000 /* read/write pointer clear */
270 /* below are so far hardcoded - should read registers in future */
271 #define ICH6_MAX_CORB_ENTRIES 256
272 #define ICH6_MAX_RIRB_ENTRIES 256
274 /* position fix mode */
281 /* Defines for ATI HD Audio support in SB450 south bridge */
282 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42
283 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02
285 /* Defines for Nvidia HDA support */
286 #define NVIDIA_HDA_TRANSREG_ADDR 0x4e
287 #define NVIDIA_HDA_ENABLE_COHBITS 0x0f
288 #define NVIDIA_HDA_ISTRM_COH 0x4d
289 #define NVIDIA_HDA_OSTRM_COH 0x4c
290 #define NVIDIA_HDA_ENABLE_COHBIT 0x01
292 /* Defines for Intel SCH HDA snoop control */
293 #define INTEL_SCH_HDA_DEVC 0x78
294 #define INTEL_SCH_HDA_DEVC_NOSNOOP (0x1<<11)
296 /* Define IN stream 0 FIFO size offset in VIA controller */
297 #define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90
298 /* Define VIA HD Audio Device ID*/
299 #define VIA_HDAC_DEVICE_ID 0x3288
301 /* HD Audio class code */
302 #define PCI_CLASS_MULTIMEDIA_HD_AUDIO 0x0403
308 struct snd_dma_buffer bdl; /* BDL buffer */
309 u32 *posbuf; /* position buffer pointer */
311 unsigned int bufsize; /* size of the play buffer in bytes */
312 unsigned int period_bytes; /* size of the period in bytes */
313 unsigned int frags; /* number for period in the play buffer */
314 unsigned int fifo_size; /* FIFO size */
315 unsigned long start_jiffies; /* start + minimum jiffies */
316 unsigned long min_jiffies; /* minimum jiffies before position is valid */
318 void __iomem *sd_addr; /* stream descriptor pointer */
320 u32 sd_int_sta_mask; /* stream int status mask */
323 struct snd_pcm_substream *substream; /* assigned substream,
326 unsigned int format_val; /* format value to be set in the
327 * controller and the codec
329 unsigned char stream_tag; /* assigned stream */
330 unsigned char index; /* stream index */
332 unsigned int opened :1;
333 unsigned int running :1;
334 unsigned int irq_pending :1;
335 unsigned int start_flag: 1; /* stream full start flag */
338 * A flag to ensure DMA position is 0
339 * when link position is not greater than FIFO size
341 unsigned int insufficient :1;
346 u32 *buf; /* CORB/RIRB buffer
347 * Each CORB entry is 4byte, RIRB is 8byte
349 dma_addr_t addr; /* physical address of CORB/RIRB buffer */
351 unsigned short rp, wp; /* read/write pointers */
352 int cmds; /* number of pending requests */
353 u32 res; /* last read value */
357 struct snd_card *card;
361 /* chip type specific */
363 int playback_streams;
364 int playback_index_offset;
366 int capture_index_offset;
371 void __iomem *remap_addr;
376 struct mutex open_mutex;
378 /* streams (x num_streams) */
379 struct azx_dev *azx_dev;
382 struct snd_pcm *pcm[AZX_MAX_PCMS];
385 unsigned short codec_mask;
386 int codec_probe_mask; /* copied from probe_mask option */
393 /* CORB/RIRB and position buffers */
394 struct snd_dma_buffer rb;
395 struct snd_dma_buffer posbuf;
399 unsigned int running :1;
400 unsigned int initialized :1;
401 unsigned int single_cmd :1;
402 unsigned int polling_mode :1;
404 unsigned int irq_pending_warned :1;
405 unsigned int via_dmapos_patch :1; /* enable DMA-position fix for VIA */
406 unsigned int probing :1; /* codec probing phase */
409 unsigned int last_cmd; /* last issued command (to sync) */
411 /* for pending irqs */
412 struct work_struct irq_pending_work;
414 /* reboot notifier (for mysterious hangup problem at power-down) */
415 struct notifier_block reboot_notifier;
430 AZX_NUM_DRIVERS, /* keep this as last entry */
433 static char *driver_short_names[] __devinitdata = {
434 [AZX_DRIVER_ICH] = "HDA Intel",
435 [AZX_DRIVER_SCH] = "HDA Intel MID",
436 [AZX_DRIVER_ATI] = "HDA ATI SB",
437 [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
438 [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
439 [AZX_DRIVER_SIS] = "HDA SIS966",
440 [AZX_DRIVER_ULI] = "HDA ULI M5461",
441 [AZX_DRIVER_NVIDIA] = "HDA NVidia",
442 [AZX_DRIVER_TERA] = "HDA Teradici",
443 [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
447 * macros for easy use
449 #define azx_writel(chip,reg,value) \
450 writel(value, (chip)->remap_addr + ICH6_REG_##reg)
451 #define azx_readl(chip,reg) \
452 readl((chip)->remap_addr + ICH6_REG_##reg)
453 #define azx_writew(chip,reg,value) \
454 writew(value, (chip)->remap_addr + ICH6_REG_##reg)
455 #define azx_readw(chip,reg) \
456 readw((chip)->remap_addr + ICH6_REG_##reg)
457 #define azx_writeb(chip,reg,value) \
458 writeb(value, (chip)->remap_addr + ICH6_REG_##reg)
459 #define azx_readb(chip,reg) \
460 readb((chip)->remap_addr + ICH6_REG_##reg)
462 #define azx_sd_writel(dev,reg,value) \
463 writel(value, (dev)->sd_addr + ICH6_REG_##reg)
464 #define azx_sd_readl(dev,reg) \
465 readl((dev)->sd_addr + ICH6_REG_##reg)
466 #define azx_sd_writew(dev,reg,value) \
467 writew(value, (dev)->sd_addr + ICH6_REG_##reg)
468 #define azx_sd_readw(dev,reg) \
469 readw((dev)->sd_addr + ICH6_REG_##reg)
470 #define azx_sd_writeb(dev,reg,value) \
471 writeb(value, (dev)->sd_addr + ICH6_REG_##reg)
472 #define azx_sd_readb(dev,reg) \
473 readb((dev)->sd_addr + ICH6_REG_##reg)
475 /* for pcm support */
476 #define get_azx_dev(substream) (substream->runtime->private_data)
478 static int azx_acquire_irq(struct azx *chip, int do_disconnect);
481 * Interface for HD codec
485 * CORB / RIRB interface
487 static int azx_alloc_cmd_io(struct azx *chip)
491 /* single page (at least 4096 bytes) must suffice for both ringbuffes */
492 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
493 snd_dma_pci_data(chip->pci),
494 PAGE_SIZE, &chip->rb);
496 snd_printk(KERN_ERR SFX "cannot allocate CORB/RIRB\n");
502 static void azx_init_cmd_io(struct azx *chip)
505 chip->corb.addr = chip->rb.addr;
506 chip->corb.buf = (u32 *)chip->rb.area;
507 azx_writel(chip, CORBLBASE, (u32)chip->corb.addr);
508 azx_writel(chip, CORBUBASE, upper_32_bits(chip->corb.addr));
510 /* set the corb size to 256 entries (ULI requires explicitly) */
511 azx_writeb(chip, CORBSIZE, 0x02);
512 /* set the corb write pointer to 0 */
513 azx_writew(chip, CORBWP, 0);
514 /* reset the corb hw read pointer */
515 azx_writew(chip, CORBRP, ICH6_RBRWP_CLR);
516 /* enable corb dma */
517 azx_writeb(chip, CORBCTL, ICH6_RBCTL_DMA_EN);
520 chip->rirb.addr = chip->rb.addr + 2048;
521 chip->rirb.buf = (u32 *)(chip->rb.area + 2048);
522 azx_writel(chip, RIRBLBASE, (u32)chip->rirb.addr);
523 azx_writel(chip, RIRBUBASE, upper_32_bits(chip->rirb.addr));
525 /* set the rirb size to 256 entries (ULI requires explicitly) */
526 azx_writeb(chip, RIRBSIZE, 0x02);
527 /* reset the rirb hw write pointer */
528 azx_writew(chip, RIRBWP, ICH6_RBRWP_CLR);
529 /* set N=1, get RIRB response interrupt for new entry */
530 azx_writew(chip, RINTCNT, 1);
531 /* enable rirb dma and response irq */
532 azx_writeb(chip, RIRBCTL, ICH6_RBCTL_DMA_EN | ICH6_RBCTL_IRQ_EN);
533 chip->rirb.rp = chip->rirb.cmds = 0;
536 static void azx_free_cmd_io(struct azx *chip)
538 /* disable ringbuffer DMAs */
539 azx_writeb(chip, RIRBCTL, 0);
540 azx_writeb(chip, CORBCTL, 0);
544 static int azx_corb_send_cmd(struct hda_bus *bus, u32 val)
546 struct azx *chip = bus->private_data;
549 /* add command to corb */
550 wp = azx_readb(chip, CORBWP);
552 wp %= ICH6_MAX_CORB_ENTRIES;
554 spin_lock_irq(&chip->reg_lock);
556 chip->corb.buf[wp] = cpu_to_le32(val);
557 azx_writel(chip, CORBWP, wp);
558 spin_unlock_irq(&chip->reg_lock);
563 #define ICH6_RIRB_EX_UNSOL_EV (1<<4)
565 /* retrieve RIRB entry - called from interrupt handler */
566 static void azx_update_rirb(struct azx *chip)
571 wp = azx_readb(chip, RIRBWP);
572 if (wp == chip->rirb.wp)
576 while (chip->rirb.rp != wp) {
578 chip->rirb.rp %= ICH6_MAX_RIRB_ENTRIES;
580 rp = chip->rirb.rp << 1; /* an RIRB entry is 8-bytes */
581 res_ex = le32_to_cpu(chip->rirb.buf[rp + 1]);
582 res = le32_to_cpu(chip->rirb.buf[rp]);
583 if (res_ex & ICH6_RIRB_EX_UNSOL_EV)
584 snd_hda_queue_unsol_event(chip->bus, res, res_ex);
585 else if (chip->rirb.cmds) {
586 chip->rirb.res = res;
593 /* receive a response */
594 static unsigned int azx_rirb_get_response(struct hda_bus *bus)
596 struct azx *chip = bus->private_data;
597 unsigned long timeout;
600 timeout = jiffies + msecs_to_jiffies(1000);
602 if (chip->polling_mode) {
603 spin_lock_irq(&chip->reg_lock);
604 azx_update_rirb(chip);
605 spin_unlock_irq(&chip->reg_lock);
607 if (!chip->rirb.cmds) {
610 return chip->rirb.res; /* the last value */
612 if (time_after(jiffies, timeout))
614 if (bus->needs_damn_long_delay)
615 msleep(2); /* temporary workaround */
623 snd_printk(KERN_WARNING "hda_intel: No response from codec, "
624 "disabling MSI: last cmd=0x%08x\n", chip->last_cmd);
625 free_irq(chip->irq, chip);
627 pci_disable_msi(chip->pci);
629 if (azx_acquire_irq(chip, 1) < 0) {
636 if (!chip->polling_mode) {
637 snd_printk(KERN_WARNING "hda_intel: azx_get_response timeout, "
638 "switching to polling mode: last cmd=0x%08x\n",
640 chip->polling_mode = 1;
645 /* If this critical timeout happens during the codec probing
646 * phase, this is likely an access to a non-existing codec
647 * slot. Better to return an error and reset the system.
652 snd_printk(KERN_ERR "hda_intel: azx_get_response timeout (ERROR): "
653 "last cmd=0x%08x\n", chip->last_cmd);
654 spin_lock_irq(&chip->reg_lock);
655 chip->rirb.cmds = 0; /* reset the index */
657 spin_unlock_irq(&chip->reg_lock);
662 * Use the single immediate command instead of CORB/RIRB for simplicity
664 * Note: according to Intel, this is not preferred use. The command was
665 * intended for the BIOS only, and may get confused with unsolicited
666 * responses. So, we shouldn't use it for normal operation from the
668 * I left the codes, however, for debugging/testing purposes.
672 static int azx_single_send_cmd(struct hda_bus *bus, u32 val)
674 struct azx *chip = bus->private_data;
678 /* check ICB busy bit */
679 if (!((azx_readw(chip, IRS) & ICH6_IRS_BUSY))) {
680 /* Clear IRV valid bit */
681 azx_writew(chip, IRS, azx_readw(chip, IRS) |
683 azx_writel(chip, IC, val);
684 azx_writew(chip, IRS, azx_readw(chip, IRS) |
690 if (printk_ratelimit())
691 snd_printd(SFX "send_cmd timeout: IRS=0x%x, val=0x%x\n",
692 azx_readw(chip, IRS), val);
696 /* receive a response */
697 static unsigned int azx_single_get_response(struct hda_bus *bus)
699 struct azx *chip = bus->private_data;
703 /* check IRV busy bit */
704 if (azx_readw(chip, IRS) & ICH6_IRS_VALID)
705 return azx_readl(chip, IR);
708 if (printk_ratelimit())
709 snd_printd(SFX "get_response timeout: IRS=0x%x\n",
710 azx_readw(chip, IRS));
711 return (unsigned int)-1;
715 * The below are the main callbacks from hda_codec.
717 * They are just the skeleton to call sub-callbacks according to the
718 * current setting of chip->single_cmd.
722 static int azx_send_cmd(struct hda_bus *bus, unsigned int val)
724 struct azx *chip = bus->private_data;
726 chip->last_cmd = val;
727 if (chip->single_cmd)
728 return azx_single_send_cmd(bus, val);
730 return azx_corb_send_cmd(bus, val);
734 static unsigned int azx_get_response(struct hda_bus *bus)
736 struct azx *chip = bus->private_data;
737 if (chip->single_cmd)
738 return azx_single_get_response(bus);
740 return azx_rirb_get_response(bus);
743 #ifdef CONFIG_SND_HDA_POWER_SAVE
744 static void azx_power_notify(struct hda_bus *bus);
747 /* reset codec link */
748 static int azx_reset(struct azx *chip)
753 azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
755 /* reset controller */
756 azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_RESET);
759 while (azx_readb(chip, GCTL) && --count)
762 /* delay for >= 100us for codec PLL to settle per spec
763 * Rev 0.9 section 5.5.1
767 /* Bring controller out of reset */
768 azx_writeb(chip, GCTL, azx_readb(chip, GCTL) | ICH6_GCTL_RESET);
771 while (!azx_readb(chip, GCTL) && --count)
774 /* Brent Chartrand said to wait >= 540us for codecs to initialize */
777 /* check to see if controller is ready */
778 if (!azx_readb(chip, GCTL)) {
779 snd_printd("azx_reset: controller not ready!\n");
783 /* Accept unsolicited responses */
784 azx_writel(chip, GCTL, azx_readl(chip, GCTL) | ICH6_GCTL_UREN);
787 if (!chip->codec_mask) {
788 chip->codec_mask = azx_readw(chip, STATESTS);
789 snd_printdd("codec_mask = 0x%x\n", chip->codec_mask);
800 /* enable interrupts */
801 static void azx_int_enable(struct azx *chip)
803 /* enable controller CIE and GIE */
804 azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) |
805 ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN);
808 /* disable interrupts */
809 static void azx_int_disable(struct azx *chip)
813 /* disable interrupts in stream descriptor */
814 for (i = 0; i < chip->num_streams; i++) {
815 struct azx_dev *azx_dev = &chip->azx_dev[i];
816 azx_sd_writeb(azx_dev, SD_CTL,
817 azx_sd_readb(azx_dev, SD_CTL) & ~SD_INT_MASK);
820 /* disable SIE for all streams */
821 azx_writeb(chip, INTCTL, 0);
823 /* disable controller CIE and GIE */
824 azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) &
825 ~(ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN));
828 /* clear interrupts */
829 static void azx_int_clear(struct azx *chip)
833 /* clear stream status */
834 for (i = 0; i < chip->num_streams; i++) {
835 struct azx_dev *azx_dev = &chip->azx_dev[i];
836 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
840 azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
842 /* clear rirb status */
843 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
845 /* clear int status */
846 azx_writel(chip, INTSTS, ICH6_INT_CTRL_EN | ICH6_INT_ALL_STREAM);
850 static void azx_stream_start(struct azx *chip, struct azx_dev *azx_dev)
853 * Before stream start, initialize parameter
855 azx_dev->insufficient = 1;
858 azx_writeb(chip, INTCTL,
859 azx_readb(chip, INTCTL) | (1 << azx_dev->index));
860 /* set DMA start and interrupt mask */
861 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
862 SD_CTL_DMA_START | SD_INT_MASK);
866 static void azx_stream_clear(struct azx *chip, struct azx_dev *azx_dev)
868 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) &
869 ~(SD_CTL_DMA_START | SD_INT_MASK));
870 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK); /* to be sure */
874 static void azx_stream_stop(struct azx *chip, struct azx_dev *azx_dev)
876 azx_stream_clear(chip, azx_dev);
878 azx_writeb(chip, INTCTL,
879 azx_readb(chip, INTCTL) & ~(1 << azx_dev->index));
884 * reset and start the controller registers
886 static void azx_init_chip(struct azx *chip)
888 if (chip->initialized)
891 /* reset controller */
894 /* initialize interrupts */
896 azx_int_enable(chip);
898 /* initialize the codec command I/O */
899 if (!chip->single_cmd)
900 azx_init_cmd_io(chip);
902 /* program the position buffer */
903 azx_writel(chip, DPLBASE, (u32)chip->posbuf.addr);
904 azx_writel(chip, DPUBASE, upper_32_bits(chip->posbuf.addr));
906 chip->initialized = 1;
910 * initialize the PCI registers
912 /* update bits in a PCI register byte */
913 static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
914 unsigned char mask, unsigned char val)
918 pci_read_config_byte(pci, reg, &data);
920 data |= (val & mask);
921 pci_write_config_byte(pci, reg, data);
924 static void azx_init_pci(struct azx *chip)
926 unsigned short snoop;
928 /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
929 * TCSEL == Traffic Class Select Register, which sets PCI express QOS
930 * Ensuring these bits are 0 clears playback static on some HD Audio
933 update_pci_byte(chip->pci, ICH6_PCIREG_TCSEL, 0x07, 0);
935 switch (chip->driver_type) {
937 /* For ATI SB450 azalia HD audio, we need to enable snoop */
938 update_pci_byte(chip->pci,
939 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR,
940 0x07, ATI_SB450_HDAUDIO_ENABLE_SNOOP);
942 case AZX_DRIVER_NVIDIA:
943 /* For NVIDIA HDA, enable snoop */
944 update_pci_byte(chip->pci,
945 NVIDIA_HDA_TRANSREG_ADDR,
946 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
947 update_pci_byte(chip->pci,
948 NVIDIA_HDA_ISTRM_COH,
949 0x01, NVIDIA_HDA_ENABLE_COHBIT);
950 update_pci_byte(chip->pci,
951 NVIDIA_HDA_OSTRM_COH,
952 0x01, NVIDIA_HDA_ENABLE_COHBIT);
955 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
956 if (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) {
957 pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, \
958 snoop & (~INTEL_SCH_HDA_DEVC_NOSNOOP));
959 pci_read_config_word(chip->pci,
960 INTEL_SCH_HDA_DEVC, &snoop);
961 snd_printdd("HDA snoop disabled, enabling ... %s\n",\
962 (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) \
971 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
976 static irqreturn_t azx_interrupt(int irq, void *dev_id)
978 struct azx *chip = dev_id;
979 struct azx_dev *azx_dev;
983 spin_lock(&chip->reg_lock);
985 status = azx_readl(chip, INTSTS);
987 spin_unlock(&chip->reg_lock);
991 for (i = 0; i < chip->num_streams; i++) {
992 azx_dev = &chip->azx_dev[i];
993 if (status & azx_dev->sd_int_sta_mask) {
994 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
995 if (!azx_dev->substream || !azx_dev->running)
997 /* check whether this IRQ is really acceptable */
998 ok = azx_position_ok(chip, azx_dev);
1000 azx_dev->irq_pending = 0;
1001 spin_unlock(&chip->reg_lock);
1002 snd_pcm_period_elapsed(azx_dev->substream);
1003 spin_lock(&chip->reg_lock);
1004 } else if (ok == 0 && chip->bus && chip->bus->workq) {
1005 /* bogus IRQ, process it later */
1006 azx_dev->irq_pending = 1;
1007 queue_work(chip->bus->workq,
1008 &chip->irq_pending_work);
1013 /* clear rirb int */
1014 status = azx_readb(chip, RIRBSTS);
1015 if (status & RIRB_INT_MASK) {
1016 if (!chip->single_cmd && (status & RIRB_INT_RESPONSE))
1017 azx_update_rirb(chip);
1018 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
1022 /* clear state status int */
1023 if (azx_readb(chip, STATESTS) & 0x04)
1024 azx_writeb(chip, STATESTS, 0x04);
1026 spin_unlock(&chip->reg_lock);
1033 * set up a BDL entry
1035 static int setup_bdle(struct snd_pcm_substream *substream,
1036 struct azx_dev *azx_dev, u32 **bdlp,
1037 int ofs, int size, int with_ioc)
1045 if (azx_dev->frags >= AZX_MAX_BDL_ENTRIES)
1048 addr = snd_pcm_sgbuf_get_addr(substream, ofs);
1049 /* program the address field of the BDL entry */
1050 bdl[0] = cpu_to_le32((u32)addr);
1051 bdl[1] = cpu_to_le32(upper_32_bits(addr));
1052 /* program the size field of the BDL entry */
1053 chunk = snd_pcm_sgbuf_get_chunk_size(substream, ofs, size);
1054 bdl[2] = cpu_to_le32(chunk);
1055 /* program the IOC to enable interrupt
1056 * only when the whole fragment is processed
1059 bdl[3] = (size || !with_ioc) ? 0 : cpu_to_le32(0x01);
1069 * set up BDL entries
1071 static int azx_setup_periods(struct azx *chip,
1072 struct snd_pcm_substream *substream,
1073 struct azx_dev *azx_dev)
1076 int i, ofs, periods, period_bytes;
1079 /* reset BDL address */
1080 azx_sd_writel(azx_dev, SD_BDLPL, 0);
1081 azx_sd_writel(azx_dev, SD_BDLPU, 0);
1083 period_bytes = azx_dev->period_bytes;
1084 periods = azx_dev->bufsize / period_bytes;
1086 /* program the initial BDL entries */
1087 bdl = (u32 *)azx_dev->bdl.area;
1090 pos_adj = bdl_pos_adj[chip->dev_index];
1092 struct snd_pcm_runtime *runtime = substream->runtime;
1093 int pos_align = pos_adj;
1094 pos_adj = (pos_adj * runtime->rate + 47999) / 48000;
1096 pos_adj = pos_align;
1098 pos_adj = ((pos_adj + pos_align - 1) / pos_align) *
1100 pos_adj = frames_to_bytes(runtime, pos_adj);
1101 if (pos_adj >= period_bytes) {
1102 snd_printk(KERN_WARNING "Too big adjustment %d\n",
1103 bdl_pos_adj[chip->dev_index]);
1106 ofs = setup_bdle(substream, azx_dev,
1107 &bdl, ofs, pos_adj, 1);
1113 for (i = 0; i < periods; i++) {
1114 if (i == periods - 1 && pos_adj)
1115 ofs = setup_bdle(substream, azx_dev, &bdl, ofs,
1116 period_bytes - pos_adj, 0);
1118 ofs = setup_bdle(substream, azx_dev, &bdl, ofs,
1126 snd_printk(KERN_ERR "Too many BDL entries: buffer=%d, period=%d\n",
1127 azx_dev->bufsize, period_bytes);
1132 static void azx_stream_reset(struct azx *chip, struct azx_dev *azx_dev)
1137 azx_stream_clear(chip, azx_dev);
1139 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
1140 SD_CTL_STREAM_RESET);
1143 while (!((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1146 val &= ~SD_CTL_STREAM_RESET;
1147 azx_sd_writeb(azx_dev, SD_CTL, val);
1151 /* waiting for hardware to report that the stream is out of reset */
1152 while (((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1156 /* reset first position - may not be synced with hw at this time */
1157 *azx_dev->posbuf = 0;
1161 * set up the SD for streaming
1163 static int azx_setup_controller(struct azx *chip, struct azx_dev *azx_dev)
1165 /* make sure the run bit is zero for SD */
1166 azx_stream_clear(chip, azx_dev);
1167 /* program the stream_tag */
1168 azx_sd_writel(azx_dev, SD_CTL,
1169 (azx_sd_readl(azx_dev, SD_CTL) & ~SD_CTL_STREAM_TAG_MASK)|
1170 (azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT));
1172 /* program the length of samples in cyclic buffer */
1173 azx_sd_writel(azx_dev, SD_CBL, azx_dev->bufsize);
1175 /* program the stream format */
1176 /* this value needs to be the same as the one programmed */
1177 azx_sd_writew(azx_dev, SD_FORMAT, azx_dev->format_val);
1179 /* program the stream LVI (last valid index) of the BDL */
1180 azx_sd_writew(azx_dev, SD_LVI, azx_dev->frags - 1);
1182 /* program the BDL address */
1183 /* lower BDL address */
1184 azx_sd_writel(azx_dev, SD_BDLPL, (u32)azx_dev->bdl.addr);
1185 /* upper BDL address */
1186 azx_sd_writel(azx_dev, SD_BDLPU, upper_32_bits(azx_dev->bdl.addr));
1188 /* enable the position buffer */
1189 if (chip->position_fix == POS_FIX_POSBUF ||
1190 chip->position_fix == POS_FIX_AUTO ||
1191 chip->via_dmapos_patch) {
1192 if (!(azx_readl(chip, DPLBASE) & ICH6_DPLBASE_ENABLE))
1193 azx_writel(chip, DPLBASE,
1194 (u32)chip->posbuf.addr | ICH6_DPLBASE_ENABLE);
1197 /* set the interrupt enable bits in the descriptor control register */
1198 azx_sd_writel(azx_dev, SD_CTL,
1199 azx_sd_readl(azx_dev, SD_CTL) | SD_INT_MASK);
1205 * Probe the given codec address
1207 static int probe_codec(struct azx *chip, int addr)
1209 unsigned int cmd = (addr << 28) | (AC_NODE_ROOT << 20) |
1210 (AC_VERB_PARAMETERS << 8) | AC_PAR_VENDOR_ID;
1214 azx_send_cmd(chip->bus, cmd);
1215 res = azx_get_response(chip->bus);
1219 snd_printdd("hda_intel: codec #%d probed OK\n", addr);
1223 static int azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
1224 struct hda_pcm *cpcm);
1225 static void azx_stop_chip(struct azx *chip);
1228 * Codec initialization
1231 /* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
1232 static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] __devinitdata = {
1233 [AZX_DRIVER_TERA] = 1,
1236 static int __devinit azx_codec_create(struct azx *chip, const char *model,
1239 struct hda_bus_template bus_temp;
1243 memset(&bus_temp, 0, sizeof(bus_temp));
1244 bus_temp.private_data = chip;
1245 bus_temp.modelname = model;
1246 bus_temp.pci = chip->pci;
1247 bus_temp.ops.command = azx_send_cmd;
1248 bus_temp.ops.get_response = azx_get_response;
1249 bus_temp.ops.attach_pcm = azx_attach_pcm_stream;
1250 #ifdef CONFIG_SND_HDA_POWER_SAVE
1251 bus_temp.power_save = &power_save;
1252 bus_temp.ops.pm_notify = azx_power_notify;
1255 err = snd_hda_bus_new(chip->card, &bus_temp, &chip->bus);
1259 if (chip->driver_type == AZX_DRIVER_NVIDIA)
1260 chip->bus->needs_damn_long_delay = 1;
1263 max_slots = azx_max_codecs[chip->driver_type];
1265 max_slots = AZX_MAX_CODECS;
1267 /* First try to probe all given codec slots */
1268 for (c = 0; c < max_slots; c++) {
1269 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
1270 if (probe_codec(chip, c) < 0) {
1271 /* Some BIOSen give you wrong codec addresses
1274 snd_printk(KERN_WARNING
1275 "hda_intel: Codec #%d probe error; "
1276 "disabling it...\n", c);
1277 chip->codec_mask &= ~(1 << c);
1278 /* More badly, accessing to a non-existing
1279 * codec often screws up the controller chip,
1280 * and distrubs the further communications.
1281 * Thus if an error occurs during probing,
1282 * better to reset the controller chip to
1283 * get back to the sanity state.
1285 azx_stop_chip(chip);
1286 azx_init_chip(chip);
1291 /* Then create codec instances */
1292 for (c = 0; c < max_slots; c++) {
1293 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
1294 struct hda_codec *codec;
1295 err = snd_hda_codec_new(chip->bus, c, !no_init, &codec);
1302 snd_printk(KERN_ERR SFX "no codecs initialized\n");
1314 /* assign a stream for the PCM */
1315 static inline struct azx_dev *azx_assign_device(struct azx *chip, int stream)
1318 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
1319 dev = chip->playback_index_offset;
1320 nums = chip->playback_streams;
1322 dev = chip->capture_index_offset;
1323 nums = chip->capture_streams;
1325 for (i = 0; i < nums; i++, dev++)
1326 if (!chip->azx_dev[dev].opened) {
1327 chip->azx_dev[dev].opened = 1;
1328 return &chip->azx_dev[dev];
1333 /* release the assigned stream */
1334 static inline void azx_release_device(struct azx_dev *azx_dev)
1336 azx_dev->opened = 0;
1339 static struct snd_pcm_hardware azx_pcm_hw = {
1340 .info = (SNDRV_PCM_INFO_MMAP |
1341 SNDRV_PCM_INFO_INTERLEAVED |
1342 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1343 SNDRV_PCM_INFO_MMAP_VALID |
1344 /* No full-resume yet implemented */
1345 /* SNDRV_PCM_INFO_RESUME |*/
1346 SNDRV_PCM_INFO_PAUSE |
1347 SNDRV_PCM_INFO_SYNC_START),
1348 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1349 .rates = SNDRV_PCM_RATE_48000,
1354 .buffer_bytes_max = AZX_MAX_BUF_SIZE,
1355 .period_bytes_min = 128,
1356 .period_bytes_max = AZX_MAX_BUF_SIZE / 2,
1358 .periods_max = AZX_MAX_FRAG,
1364 struct hda_codec *codec;
1365 struct hda_pcm_stream *hinfo[2];
1368 static int azx_pcm_open(struct snd_pcm_substream *substream)
1370 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1371 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1372 struct azx *chip = apcm->chip;
1373 struct azx_dev *azx_dev;
1374 struct snd_pcm_runtime *runtime = substream->runtime;
1375 unsigned long flags;
1378 mutex_lock(&chip->open_mutex);
1379 azx_dev = azx_assign_device(chip, substream->stream);
1380 if (azx_dev == NULL) {
1381 mutex_unlock(&chip->open_mutex);
1384 runtime->hw = azx_pcm_hw;
1385 runtime->hw.channels_min = hinfo->channels_min;
1386 runtime->hw.channels_max = hinfo->channels_max;
1387 runtime->hw.formats = hinfo->formats;
1388 runtime->hw.rates = hinfo->rates;
1389 snd_pcm_limit_hw_rates(runtime);
1390 snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
1391 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
1393 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
1395 snd_hda_power_up(apcm->codec);
1396 err = hinfo->ops.open(hinfo, apcm->codec, substream);
1398 azx_release_device(azx_dev);
1399 snd_hda_power_down(apcm->codec);
1400 mutex_unlock(&chip->open_mutex);
1403 spin_lock_irqsave(&chip->reg_lock, flags);
1404 azx_dev->substream = substream;
1405 azx_dev->running = 0;
1406 spin_unlock_irqrestore(&chip->reg_lock, flags);
1408 runtime->private_data = azx_dev;
1409 snd_pcm_set_sync(substream);
1410 mutex_unlock(&chip->open_mutex);
1415 static int azx_pcm_close(struct snd_pcm_substream *substream)
1417 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1418 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1419 struct azx *chip = apcm->chip;
1420 struct azx_dev *azx_dev = get_azx_dev(substream);
1421 unsigned long flags;
1423 mutex_lock(&chip->open_mutex);
1424 spin_lock_irqsave(&chip->reg_lock, flags);
1425 azx_dev->substream = NULL;
1426 azx_dev->running = 0;
1427 spin_unlock_irqrestore(&chip->reg_lock, flags);
1428 azx_release_device(azx_dev);
1429 hinfo->ops.close(hinfo, apcm->codec, substream);
1430 snd_hda_power_down(apcm->codec);
1431 mutex_unlock(&chip->open_mutex);
1435 static int azx_pcm_hw_params(struct snd_pcm_substream *substream,
1436 struct snd_pcm_hw_params *hw_params)
1438 struct azx_dev *azx_dev = get_azx_dev(substream);
1440 azx_dev->bufsize = 0;
1441 azx_dev->period_bytes = 0;
1442 azx_dev->format_val = 0;
1443 return snd_pcm_lib_malloc_pages(substream,
1444 params_buffer_bytes(hw_params));
1447 static int azx_pcm_hw_free(struct snd_pcm_substream *substream)
1449 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1450 struct azx_dev *azx_dev = get_azx_dev(substream);
1451 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1453 /* reset BDL address */
1454 azx_sd_writel(azx_dev, SD_BDLPL, 0);
1455 azx_sd_writel(azx_dev, SD_BDLPU, 0);
1456 azx_sd_writel(azx_dev, SD_CTL, 0);
1457 azx_dev->bufsize = 0;
1458 azx_dev->period_bytes = 0;
1459 azx_dev->format_val = 0;
1461 hinfo->ops.cleanup(hinfo, apcm->codec, substream);
1463 return snd_pcm_lib_free_pages(substream);
1466 static int azx_pcm_prepare(struct snd_pcm_substream *substream)
1468 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1469 struct azx *chip = apcm->chip;
1470 struct azx_dev *azx_dev = get_azx_dev(substream);
1471 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1472 struct snd_pcm_runtime *runtime = substream->runtime;
1473 unsigned int bufsize, period_bytes, format_val;
1476 azx_stream_reset(chip, azx_dev);
1477 format_val = snd_hda_calc_stream_format(runtime->rate,
1482 snd_printk(KERN_ERR SFX
1483 "invalid format_val, rate=%d, ch=%d, format=%d\n",
1484 runtime->rate, runtime->channels, runtime->format);
1488 bufsize = snd_pcm_lib_buffer_bytes(substream);
1489 period_bytes = snd_pcm_lib_period_bytes(substream);
1491 snd_printdd("azx_pcm_prepare: bufsize=0x%x, format=0x%x\n",
1492 bufsize, format_val);
1494 if (bufsize != azx_dev->bufsize ||
1495 period_bytes != azx_dev->period_bytes ||
1496 format_val != azx_dev->format_val) {
1497 azx_dev->bufsize = bufsize;
1498 azx_dev->period_bytes = period_bytes;
1499 azx_dev->format_val = format_val;
1500 err = azx_setup_periods(chip, substream, azx_dev);
1505 azx_dev->min_jiffies = (runtime->period_size * HZ) /
1506 (runtime->rate * 2);
1507 azx_setup_controller(chip, azx_dev);
1508 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1509 azx_dev->fifo_size = azx_sd_readw(azx_dev, SD_FIFOSIZE) + 1;
1511 azx_dev->fifo_size = 0;
1513 return hinfo->ops.prepare(hinfo, apcm->codec, azx_dev->stream_tag,
1514 azx_dev->format_val, substream);
1517 static int azx_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
1519 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1520 struct azx *chip = apcm->chip;
1521 struct azx_dev *azx_dev;
1522 struct snd_pcm_substream *s;
1523 int rstart = 0, start, nsync = 0, sbits = 0;
1527 case SNDRV_PCM_TRIGGER_START:
1529 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1530 case SNDRV_PCM_TRIGGER_RESUME:
1533 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1534 case SNDRV_PCM_TRIGGER_SUSPEND:
1535 case SNDRV_PCM_TRIGGER_STOP:
1542 snd_pcm_group_for_each_entry(s, substream) {
1543 if (s->pcm->card != substream->pcm->card)
1545 azx_dev = get_azx_dev(s);
1546 sbits |= 1 << azx_dev->index;
1548 snd_pcm_trigger_done(s, substream);
1551 spin_lock(&chip->reg_lock);
1553 /* first, set SYNC bits of corresponding streams */
1554 azx_writel(chip, SYNC, azx_readl(chip, SYNC) | sbits);
1556 snd_pcm_group_for_each_entry(s, substream) {
1557 if (s->pcm->card != substream->pcm->card)
1559 azx_dev = get_azx_dev(s);
1561 azx_dev->start_flag = 1;
1562 azx_dev->start_jiffies = jiffies + azx_dev->min_jiffies;
1565 azx_stream_start(chip, azx_dev);
1567 azx_stream_stop(chip, azx_dev);
1568 azx_dev->running = start;
1570 spin_unlock(&chip->reg_lock);
1574 /* wait until all FIFOs get ready */
1575 for (timeout = 5000; timeout; timeout--) {
1577 snd_pcm_group_for_each_entry(s, substream) {
1578 if (s->pcm->card != substream->pcm->card)
1580 azx_dev = get_azx_dev(s);
1581 if (!(azx_sd_readb(azx_dev, SD_STS) &
1590 /* wait until all RUN bits are cleared */
1591 for (timeout = 5000; timeout; timeout--) {
1593 snd_pcm_group_for_each_entry(s, substream) {
1594 if (s->pcm->card != substream->pcm->card)
1596 azx_dev = get_azx_dev(s);
1597 if (azx_sd_readb(azx_dev, SD_CTL) &
1607 spin_lock(&chip->reg_lock);
1608 /* reset SYNC bits */
1609 azx_writel(chip, SYNC, azx_readl(chip, SYNC) & ~sbits);
1610 spin_unlock(&chip->reg_lock);
1615 /* get the current DMA position with correction on VIA chips */
1616 static unsigned int azx_via_get_position(struct azx *chip,
1617 struct azx_dev *azx_dev)
1619 unsigned int link_pos, mini_pos, bound_pos;
1620 unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
1621 unsigned int fifo_size;
1623 link_pos = azx_sd_readl(azx_dev, SD_LPIB);
1624 if (azx_dev->index >= 4) {
1625 /* Playback, no problem using link position */
1631 * use mod to get the DMA position just like old chipset
1633 mod_dma_pos = le32_to_cpu(*azx_dev->posbuf);
1634 mod_dma_pos %= azx_dev->period_bytes;
1636 /* azx_dev->fifo_size can't get FIFO size of in stream.
1637 * Get from base address + offset.
1639 fifo_size = readw(chip->remap_addr + VIA_IN_STREAM0_FIFO_SIZE_OFFSET);
1641 if (azx_dev->insufficient) {
1642 /* Link position never gather than FIFO size */
1643 if (link_pos <= fifo_size)
1646 azx_dev->insufficient = 0;
1649 if (link_pos <= fifo_size)
1650 mini_pos = azx_dev->bufsize + link_pos - fifo_size;
1652 mini_pos = link_pos - fifo_size;
1654 /* Find nearest previous boudary */
1655 mod_mini_pos = mini_pos % azx_dev->period_bytes;
1656 mod_link_pos = link_pos % azx_dev->period_bytes;
1657 if (mod_link_pos >= fifo_size)
1658 bound_pos = link_pos - mod_link_pos;
1659 else if (mod_dma_pos >= mod_mini_pos)
1660 bound_pos = mini_pos - mod_mini_pos;
1662 bound_pos = mini_pos - mod_mini_pos + azx_dev->period_bytes;
1663 if (bound_pos >= azx_dev->bufsize)
1667 /* Calculate real DMA position we want */
1668 return bound_pos + mod_dma_pos;
1671 static unsigned int azx_get_position(struct azx *chip,
1672 struct azx_dev *azx_dev)
1676 if (chip->via_dmapos_patch)
1677 pos = azx_via_get_position(chip, azx_dev);
1678 else if (chip->position_fix == POS_FIX_POSBUF ||
1679 chip->position_fix == POS_FIX_AUTO) {
1680 /* use the position buffer */
1681 pos = le32_to_cpu(*azx_dev->posbuf);
1684 pos = azx_sd_readl(azx_dev, SD_LPIB);
1686 if (pos >= azx_dev->bufsize)
1691 static snd_pcm_uframes_t azx_pcm_pointer(struct snd_pcm_substream *substream)
1693 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1694 struct azx *chip = apcm->chip;
1695 struct azx_dev *azx_dev = get_azx_dev(substream);
1696 return bytes_to_frames(substream->runtime,
1697 azx_get_position(chip, azx_dev));
1701 * Check whether the current DMA position is acceptable for updating
1702 * periods. Returns non-zero if it's OK.
1704 * Many HD-audio controllers appear pretty inaccurate about
1705 * the update-IRQ timing. The IRQ is issued before actually the
1706 * data is processed. So, we need to process it afterwords in a
1709 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
1713 if (azx_dev->start_flag &&
1714 time_before_eq(jiffies, azx_dev->start_jiffies))
1715 return -1; /* bogus (too early) interrupt */
1716 azx_dev->start_flag = 0;
1718 pos = azx_get_position(chip, azx_dev);
1719 if (chip->position_fix == POS_FIX_AUTO) {
1722 "hda-intel: Invalid position buffer, "
1723 "using LPIB read method instead.\n");
1724 chip->position_fix = POS_FIX_LPIB;
1725 pos = azx_get_position(chip, azx_dev);
1727 chip->position_fix = POS_FIX_POSBUF;
1730 if (!bdl_pos_adj[chip->dev_index])
1731 return 1; /* no delayed ack */
1732 if (pos % azx_dev->period_bytes > azx_dev->period_bytes / 2)
1733 return 0; /* NG - it's below the period boundary */
1734 return 1; /* OK, it's fine */
1738 * The work for pending PCM period updates.
1740 static void azx_irq_pending_work(struct work_struct *work)
1742 struct azx *chip = container_of(work, struct azx, irq_pending_work);
1745 if (!chip->irq_pending_warned) {
1747 "hda-intel: IRQ timing workaround is activated "
1748 "for card #%d. Suggest a bigger bdl_pos_adj.\n",
1749 chip->card->number);
1750 chip->irq_pending_warned = 1;
1755 spin_lock_irq(&chip->reg_lock);
1756 for (i = 0; i < chip->num_streams; i++) {
1757 struct azx_dev *azx_dev = &chip->azx_dev[i];
1758 if (!azx_dev->irq_pending ||
1759 !azx_dev->substream ||
1762 if (azx_position_ok(chip, azx_dev)) {
1763 azx_dev->irq_pending = 0;
1764 spin_unlock(&chip->reg_lock);
1765 snd_pcm_period_elapsed(azx_dev->substream);
1766 spin_lock(&chip->reg_lock);
1770 spin_unlock_irq(&chip->reg_lock);
1777 /* clear irq_pending flags and assure no on-going workq */
1778 static void azx_clear_irq_pending(struct azx *chip)
1782 spin_lock_irq(&chip->reg_lock);
1783 for (i = 0; i < chip->num_streams; i++)
1784 chip->azx_dev[i].irq_pending = 0;
1785 spin_unlock_irq(&chip->reg_lock);
1788 static struct snd_pcm_ops azx_pcm_ops = {
1789 .open = azx_pcm_open,
1790 .close = azx_pcm_close,
1791 .ioctl = snd_pcm_lib_ioctl,
1792 .hw_params = azx_pcm_hw_params,
1793 .hw_free = azx_pcm_hw_free,
1794 .prepare = azx_pcm_prepare,
1795 .trigger = azx_pcm_trigger,
1796 .pointer = azx_pcm_pointer,
1797 .page = snd_pcm_sgbuf_ops_page,
1800 static void azx_pcm_free(struct snd_pcm *pcm)
1802 struct azx_pcm *apcm = pcm->private_data;
1804 apcm->chip->pcm[pcm->device] = NULL;
1810 azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
1811 struct hda_pcm *cpcm)
1813 struct azx *chip = bus->private_data;
1814 struct snd_pcm *pcm;
1815 struct azx_pcm *apcm;
1816 int pcm_dev = cpcm->device;
1819 if (pcm_dev >= AZX_MAX_PCMS) {
1820 snd_printk(KERN_ERR SFX "Invalid PCM device number %d\n",
1824 if (chip->pcm[pcm_dev]) {
1825 snd_printk(KERN_ERR SFX "PCM %d already exists\n", pcm_dev);
1828 err = snd_pcm_new(chip->card, cpcm->name, pcm_dev,
1829 cpcm->stream[SNDRV_PCM_STREAM_PLAYBACK].substreams,
1830 cpcm->stream[SNDRV_PCM_STREAM_CAPTURE].substreams,
1834 strlcpy(pcm->name, cpcm->name, sizeof(pcm->name));
1835 apcm = kzalloc(sizeof(*apcm), GFP_KERNEL);
1839 apcm->codec = codec;
1840 pcm->private_data = apcm;
1841 pcm->private_free = azx_pcm_free;
1842 if (cpcm->pcm_type == HDA_PCM_TYPE_MODEM)
1843 pcm->dev_class = SNDRV_PCM_CLASS_MODEM;
1844 chip->pcm[pcm_dev] = pcm;
1846 for (s = 0; s < 2; s++) {
1847 apcm->hinfo[s] = &cpcm->stream[s];
1848 if (cpcm->stream[s].substreams)
1849 snd_pcm_set_ops(pcm, s, &azx_pcm_ops);
1851 /* buffer pre-allocation */
1852 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV_SG,
1853 snd_dma_pci_data(chip->pci),
1854 1024 * 64, 32 * 1024 * 1024);
1859 * mixer creation - all stuff is implemented in hda module
1861 static int __devinit azx_mixer_create(struct azx *chip)
1863 return snd_hda_build_controls(chip->bus);
1868 * initialize SD streams
1870 static int __devinit azx_init_stream(struct azx *chip)
1874 /* initialize each stream (aka device)
1875 * assign the starting bdl address to each stream (device)
1878 for (i = 0; i < chip->num_streams; i++) {
1879 struct azx_dev *azx_dev = &chip->azx_dev[i];
1880 azx_dev->posbuf = (u32 __iomem *)(chip->posbuf.area + i * 8);
1881 /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
1882 azx_dev->sd_addr = chip->remap_addr + (0x20 * i + 0x80);
1883 /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */
1884 azx_dev->sd_int_sta_mask = 1 << i;
1885 /* stream tag: must be non-zero and unique */
1887 azx_dev->stream_tag = i + 1;
1893 static int azx_acquire_irq(struct azx *chip, int do_disconnect)
1895 if (request_irq(chip->pci->irq, azx_interrupt,
1896 chip->msi ? 0 : IRQF_SHARED,
1897 "HDA Intel", chip)) {
1898 printk(KERN_ERR "hda-intel: unable to grab IRQ %d, "
1899 "disabling device\n", chip->pci->irq);
1901 snd_card_disconnect(chip->card);
1904 chip->irq = chip->pci->irq;
1905 pci_intx(chip->pci, !chip->msi);
1910 static void azx_stop_chip(struct azx *chip)
1912 if (!chip->initialized)
1915 /* disable interrupts */
1916 azx_int_disable(chip);
1917 azx_int_clear(chip);
1919 /* disable CORB/RIRB */
1920 azx_free_cmd_io(chip);
1922 /* disable position buffer */
1923 azx_writel(chip, DPLBASE, 0);
1924 azx_writel(chip, DPUBASE, 0);
1926 chip->initialized = 0;
1929 #ifdef CONFIG_SND_HDA_POWER_SAVE
1930 /* power-up/down the controller */
1931 static void azx_power_notify(struct hda_bus *bus)
1933 struct azx *chip = bus->private_data;
1934 struct hda_codec *c;
1937 list_for_each_entry(c, &bus->codec_list, list) {
1944 azx_init_chip(chip);
1945 else if (chip->running && power_save_controller)
1946 azx_stop_chip(chip);
1948 #endif /* CONFIG_SND_HDA_POWER_SAVE */
1955 static int snd_hda_codecs_inuse(struct hda_bus *bus)
1957 struct hda_codec *codec;
1959 list_for_each_entry(codec, &bus->codec_list, list) {
1960 if (snd_hda_codec_needs_resume(codec))
1966 static int azx_suspend(struct pci_dev *pci, pm_message_t state)
1968 struct snd_card *card = pci_get_drvdata(pci);
1969 struct azx *chip = card->private_data;
1972 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
1973 azx_clear_irq_pending(chip);
1974 for (i = 0; i < AZX_MAX_PCMS; i++)
1975 snd_pcm_suspend_all(chip->pcm[i]);
1976 if (chip->initialized)
1977 snd_hda_suspend(chip->bus, state);
1978 azx_stop_chip(chip);
1979 if (chip->irq >= 0) {
1980 free_irq(chip->irq, chip);
1984 pci_disable_msi(chip->pci);
1985 pci_disable_device(pci);
1986 pci_save_state(pci);
1987 pci_set_power_state(pci, pci_choose_state(pci, state));
1991 static int azx_resume(struct pci_dev *pci)
1993 struct snd_card *card = pci_get_drvdata(pci);
1994 struct azx *chip = card->private_data;
1996 pci_set_power_state(pci, PCI_D0);
1997 pci_restore_state(pci);
1998 if (pci_enable_device(pci) < 0) {
1999 printk(KERN_ERR "hda-intel: pci_enable_device failed, "
2000 "disabling device\n");
2001 snd_card_disconnect(card);
2004 pci_set_master(pci);
2006 if (pci_enable_msi(pci) < 0)
2008 if (azx_acquire_irq(chip, 1) < 0)
2012 if (snd_hda_codecs_inuse(chip->bus))
2013 azx_init_chip(chip);
2015 snd_hda_resume(chip->bus);
2016 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
2019 #endif /* CONFIG_PM */
2023 * reboot notifier for hang-up problem at power-down
2025 static int azx_halt(struct notifier_block *nb, unsigned long event, void *buf)
2027 struct azx *chip = container_of(nb, struct azx, reboot_notifier);
2028 azx_stop_chip(chip);
2032 static void azx_notifier_register(struct azx *chip)
2034 chip->reboot_notifier.notifier_call = azx_halt;
2035 register_reboot_notifier(&chip->reboot_notifier);
2038 static void azx_notifier_unregister(struct azx *chip)
2040 if (chip->reboot_notifier.notifier_call)
2041 unregister_reboot_notifier(&chip->reboot_notifier);
2047 static int azx_free(struct azx *chip)
2051 azx_notifier_unregister(chip);
2053 if (chip->initialized) {
2054 azx_clear_irq_pending(chip);
2055 for (i = 0; i < chip->num_streams; i++)
2056 azx_stream_stop(chip, &chip->azx_dev[i]);
2057 azx_stop_chip(chip);
2061 free_irq(chip->irq, (void*)chip);
2063 pci_disable_msi(chip->pci);
2064 if (chip->remap_addr)
2065 iounmap(chip->remap_addr);
2067 if (chip->azx_dev) {
2068 for (i = 0; i < chip->num_streams; i++)
2069 if (chip->azx_dev[i].bdl.area)
2070 snd_dma_free_pages(&chip->azx_dev[i].bdl);
2073 snd_dma_free_pages(&chip->rb);
2074 if (chip->posbuf.area)
2075 snd_dma_free_pages(&chip->posbuf);
2076 pci_release_regions(chip->pci);
2077 pci_disable_device(chip->pci);
2078 kfree(chip->azx_dev);
2084 static int azx_dev_free(struct snd_device *device)
2086 return azx_free(device->device_data);
2090 * white/black-listing for position_fix
2092 static struct snd_pci_quirk position_fix_list[] __devinitdata = {
2093 SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
2094 SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
2095 SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
2099 static int __devinit check_position_fix(struct azx *chip, int fix)
2101 const struct snd_pci_quirk *q;
2105 case POS_FIX_POSBUF:
2109 /* Check VIA/ATI HD Audio Controller exist */
2110 switch (chip->driver_type) {
2111 case AZX_DRIVER_VIA:
2112 case AZX_DRIVER_ATI:
2113 chip->via_dmapos_patch = 1;
2114 /* Use link position directly, avoid any transfer problem. */
2115 return POS_FIX_LPIB;
2117 chip->via_dmapos_patch = 0;
2119 q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
2122 "hda_intel: position_fix set to %d "
2123 "for device %04x:%04x\n",
2124 q->value, q->subvendor, q->subdevice);
2127 return POS_FIX_AUTO;
2131 * black-lists for probe_mask
2133 static struct snd_pci_quirk probe_mask_list[] __devinitdata = {
2134 /* Thinkpad often breaks the controller communication when accessing
2135 * to the non-working (or non-existing) modem codec slot.
2137 SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
2138 SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
2139 SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
2141 SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
2142 /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
2143 SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
2144 /* forced codec slots */
2145 SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
2149 #define AZX_FORCE_CODEC_MASK 0x100
2151 static void __devinit check_probe_mask(struct azx *chip, int dev)
2153 const struct snd_pci_quirk *q;
2155 chip->codec_probe_mask = probe_mask[dev];
2156 if (chip->codec_probe_mask == -1) {
2157 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
2160 "hda_intel: probe_mask set to 0x%x "
2161 "for device %04x:%04x\n",
2162 q->value, q->subvendor, q->subdevice);
2163 chip->codec_probe_mask = q->value;
2167 /* check forced option */
2168 if (chip->codec_probe_mask != -1 &&
2169 (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
2170 chip->codec_mask = chip->codec_probe_mask & 0xff;
2171 printk(KERN_INFO "hda_intel: codec_mask forced to 0x%x\n",
2180 static int __devinit azx_create(struct snd_card *card, struct pci_dev *pci,
2181 int dev, int driver_type,
2186 unsigned short gcap;
2187 static struct snd_device_ops ops = {
2188 .dev_free = azx_dev_free,
2193 err = pci_enable_device(pci);
2197 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
2199 snd_printk(KERN_ERR SFX "cannot allocate chip\n");
2200 pci_disable_device(pci);
2204 spin_lock_init(&chip->reg_lock);
2205 mutex_init(&chip->open_mutex);
2209 chip->driver_type = driver_type;
2210 chip->msi = enable_msi;
2211 chip->dev_index = dev;
2212 INIT_WORK(&chip->irq_pending_work, azx_irq_pending_work);
2214 chip->position_fix = check_position_fix(chip, position_fix[dev]);
2215 check_probe_mask(chip, dev);
2217 chip->single_cmd = single_cmd;
2219 if (bdl_pos_adj[dev] < 0) {
2220 switch (chip->driver_type) {
2221 case AZX_DRIVER_ICH:
2222 bdl_pos_adj[dev] = 1;
2225 bdl_pos_adj[dev] = 32;
2230 #if BITS_PER_LONG != 64
2231 /* Fix up base address on ULI M5461 */
2232 if (chip->driver_type == AZX_DRIVER_ULI) {
2234 pci_read_config_word(pci, 0x40, &tmp3);
2235 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
2236 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
2240 err = pci_request_regions(pci, "ICH HD audio");
2243 pci_disable_device(pci);
2247 chip->addr = pci_resource_start(pci, 0);
2248 chip->remap_addr = pci_ioremap_bar(pci, 0);
2249 if (chip->remap_addr == NULL) {
2250 snd_printk(KERN_ERR SFX "ioremap error\n");
2256 if (pci_enable_msi(pci) < 0)
2259 if (azx_acquire_irq(chip, 0) < 0) {
2264 pci_set_master(pci);
2265 synchronize_irq(chip->irq);
2267 gcap = azx_readw(chip, GCAP);
2268 snd_printdd("chipset global capabilities = 0x%x\n", gcap);
2270 /* ATI chips seems buggy about 64bit DMA addresses */
2271 if (chip->driver_type == AZX_DRIVER_ATI)
2274 /* allow 64bit DMA address if supported by H/W */
2275 if ((gcap & 0x01) && !pci_set_dma_mask(pci, DMA_BIT_MASK(64)))
2276 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(64));
2278 pci_set_dma_mask(pci, DMA_BIT_MASK(32));
2279 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(32));
2282 /* read number of streams from GCAP register instead of using
2285 chip->capture_streams = (gcap >> 8) & 0x0f;
2286 chip->playback_streams = (gcap >> 12) & 0x0f;
2287 if (!chip->playback_streams && !chip->capture_streams) {
2288 /* gcap didn't give any info, switching to old method */
2290 switch (chip->driver_type) {
2291 case AZX_DRIVER_ULI:
2292 chip->playback_streams = ULI_NUM_PLAYBACK;
2293 chip->capture_streams = ULI_NUM_CAPTURE;
2295 case AZX_DRIVER_ATIHDMI:
2296 chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
2297 chip->capture_streams = ATIHDMI_NUM_CAPTURE;
2299 case AZX_DRIVER_GENERIC:
2301 chip->playback_streams = ICH6_NUM_PLAYBACK;
2302 chip->capture_streams = ICH6_NUM_CAPTURE;
2306 chip->capture_index_offset = 0;
2307 chip->playback_index_offset = chip->capture_streams;
2308 chip->num_streams = chip->playback_streams + chip->capture_streams;
2309 chip->azx_dev = kcalloc(chip->num_streams, sizeof(*chip->azx_dev),
2311 if (!chip->azx_dev) {
2312 snd_printk(KERN_ERR "cannot malloc azx_dev\n");
2316 for (i = 0; i < chip->num_streams; i++) {
2317 /* allocate memory for the BDL for each stream */
2318 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
2319 snd_dma_pci_data(chip->pci),
2320 BDL_SIZE, &chip->azx_dev[i].bdl);
2322 snd_printk(KERN_ERR SFX "cannot allocate BDL\n");
2326 /* allocate memory for the position buffer */
2327 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
2328 snd_dma_pci_data(chip->pci),
2329 chip->num_streams * 8, &chip->posbuf);
2331 snd_printk(KERN_ERR SFX "cannot allocate posbuf\n");
2334 /* allocate CORB/RIRB */
2335 if (!chip->single_cmd) {
2336 err = azx_alloc_cmd_io(chip);
2341 /* initialize streams */
2342 azx_init_stream(chip);
2344 /* initialize chip */
2346 azx_init_chip(chip);
2348 /* codec detection */
2349 if (!chip->codec_mask) {
2350 snd_printk(KERN_ERR SFX "no codecs found!\n");
2355 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
2357 snd_printk(KERN_ERR SFX "Error creating device [card]!\n");
2361 strcpy(card->driver, "HDA-Intel");
2362 strlcpy(card->shortname, driver_short_names[chip->driver_type],
2363 sizeof(card->shortname));
2364 snprintf(card->longname, sizeof(card->longname),
2365 "%s at 0x%lx irq %i",
2366 card->shortname, chip->addr, chip->irq);
2376 static void power_down_all_codecs(struct azx *chip)
2378 #ifdef CONFIG_SND_HDA_POWER_SAVE
2379 /* The codecs were powered up in snd_hda_codec_new().
2380 * Now all initialization done, so turn them down if possible
2382 struct hda_codec *codec;
2383 list_for_each_entry(codec, &chip->bus->codec_list, list) {
2384 snd_hda_power_down(codec);
2389 static int __devinit azx_probe(struct pci_dev *pci,
2390 const struct pci_device_id *pci_id)
2393 struct snd_card *card;
2397 if (dev >= SNDRV_CARDS)
2404 err = snd_card_create(index[dev], id[dev], THIS_MODULE, 0, &card);
2406 snd_printk(KERN_ERR SFX "Error creating card!\n");
2410 err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
2413 card->private_data = chip;
2415 /* create codec instances */
2416 err = azx_codec_create(chip, model[dev], probe_only[dev]);
2420 /* create PCM streams */
2421 err = snd_hda_build_pcms(chip->bus);
2425 /* create mixer controls */
2426 err = azx_mixer_create(chip);
2430 snd_card_set_dev(card, &pci->dev);
2432 err = snd_card_register(card);
2436 pci_set_drvdata(pci, card);
2438 power_down_all_codecs(chip);
2439 azx_notifier_register(chip);
2444 snd_card_free(card);
2448 static void __devexit azx_remove(struct pci_dev *pci)
2450 snd_card_free(pci_get_drvdata(pci));
2451 pci_set_drvdata(pci, NULL);
2455 static struct pci_device_id azx_ids[] = {
2457 { PCI_DEVICE(0x8086, 0x2668), .driver_data = AZX_DRIVER_ICH },
2458 { PCI_DEVICE(0x8086, 0x27d8), .driver_data = AZX_DRIVER_ICH },
2459 { PCI_DEVICE(0x8086, 0x269a), .driver_data = AZX_DRIVER_ICH },
2460 { PCI_DEVICE(0x8086, 0x284b), .driver_data = AZX_DRIVER_ICH },
2461 { PCI_DEVICE(0x8086, 0x2911), .driver_data = AZX_DRIVER_ICH },
2462 { PCI_DEVICE(0x8086, 0x293e), .driver_data = AZX_DRIVER_ICH },
2463 { PCI_DEVICE(0x8086, 0x293f), .driver_data = AZX_DRIVER_ICH },
2464 { PCI_DEVICE(0x8086, 0x3a3e), .driver_data = AZX_DRIVER_ICH },
2465 { PCI_DEVICE(0x8086, 0x3a6e), .driver_data = AZX_DRIVER_ICH },
2467 { PCI_DEVICE(0x8086, 0x3b56), .driver_data = AZX_DRIVER_ICH },
2469 { PCI_DEVICE(0x8086, 0x811b), .driver_data = AZX_DRIVER_SCH },
2470 /* ATI SB 450/600 */
2471 { PCI_DEVICE(0x1002, 0x437b), .driver_data = AZX_DRIVER_ATI },
2472 { PCI_DEVICE(0x1002, 0x4383), .driver_data = AZX_DRIVER_ATI },
2474 { PCI_DEVICE(0x1002, 0x793b), .driver_data = AZX_DRIVER_ATIHDMI },
2475 { PCI_DEVICE(0x1002, 0x7919), .driver_data = AZX_DRIVER_ATIHDMI },
2476 { PCI_DEVICE(0x1002, 0x960f), .driver_data = AZX_DRIVER_ATIHDMI },
2477 { PCI_DEVICE(0x1002, 0x970f), .driver_data = AZX_DRIVER_ATIHDMI },
2478 { PCI_DEVICE(0x1002, 0xaa00), .driver_data = AZX_DRIVER_ATIHDMI },
2479 { PCI_DEVICE(0x1002, 0xaa08), .driver_data = AZX_DRIVER_ATIHDMI },
2480 { PCI_DEVICE(0x1002, 0xaa10), .driver_data = AZX_DRIVER_ATIHDMI },
2481 { PCI_DEVICE(0x1002, 0xaa18), .driver_data = AZX_DRIVER_ATIHDMI },
2482 { PCI_DEVICE(0x1002, 0xaa20), .driver_data = AZX_DRIVER_ATIHDMI },
2483 { PCI_DEVICE(0x1002, 0xaa28), .driver_data = AZX_DRIVER_ATIHDMI },
2484 { PCI_DEVICE(0x1002, 0xaa30), .driver_data = AZX_DRIVER_ATIHDMI },
2485 { PCI_DEVICE(0x1002, 0xaa38), .driver_data = AZX_DRIVER_ATIHDMI },
2486 { PCI_DEVICE(0x1002, 0xaa40), .driver_data = AZX_DRIVER_ATIHDMI },
2487 { PCI_DEVICE(0x1002, 0xaa48), .driver_data = AZX_DRIVER_ATIHDMI },
2488 /* VIA VT8251/VT8237A */
2489 { PCI_DEVICE(0x1106, 0x3288), .driver_data = AZX_DRIVER_VIA },
2491 { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
2493 { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
2495 { PCI_DEVICE(0x10de, 0x026c), .driver_data = AZX_DRIVER_NVIDIA },
2496 { PCI_DEVICE(0x10de, 0x0371), .driver_data = AZX_DRIVER_NVIDIA },
2497 { PCI_DEVICE(0x10de, 0x03e4), .driver_data = AZX_DRIVER_NVIDIA },
2498 { PCI_DEVICE(0x10de, 0x03f0), .driver_data = AZX_DRIVER_NVIDIA },
2499 { PCI_DEVICE(0x10de, 0x044a), .driver_data = AZX_DRIVER_NVIDIA },
2500 { PCI_DEVICE(0x10de, 0x044b), .driver_data = AZX_DRIVER_NVIDIA },
2501 { PCI_DEVICE(0x10de, 0x055c), .driver_data = AZX_DRIVER_NVIDIA },
2502 { PCI_DEVICE(0x10de, 0x055d), .driver_data = AZX_DRIVER_NVIDIA },
2503 { PCI_DEVICE(0x10de, 0x0774), .driver_data = AZX_DRIVER_NVIDIA },
2504 { PCI_DEVICE(0x10de, 0x0775), .driver_data = AZX_DRIVER_NVIDIA },
2505 { PCI_DEVICE(0x10de, 0x0776), .driver_data = AZX_DRIVER_NVIDIA },
2506 { PCI_DEVICE(0x10de, 0x0777), .driver_data = AZX_DRIVER_NVIDIA },
2507 { PCI_DEVICE(0x10de, 0x07fc), .driver_data = AZX_DRIVER_NVIDIA },
2508 { PCI_DEVICE(0x10de, 0x07fd), .driver_data = AZX_DRIVER_NVIDIA },
2509 { PCI_DEVICE(0x10de, 0x0ac0), .driver_data = AZX_DRIVER_NVIDIA },
2510 { PCI_DEVICE(0x10de, 0x0ac1), .driver_data = AZX_DRIVER_NVIDIA },
2511 { PCI_DEVICE(0x10de, 0x0ac2), .driver_data = AZX_DRIVER_NVIDIA },
2512 { PCI_DEVICE(0x10de, 0x0ac3), .driver_data = AZX_DRIVER_NVIDIA },
2513 { PCI_DEVICE(0x10de, 0x0d94), .driver_data = AZX_DRIVER_NVIDIA },
2514 { PCI_DEVICE(0x10de, 0x0d95), .driver_data = AZX_DRIVER_NVIDIA },
2515 { PCI_DEVICE(0x10de, 0x0d96), .driver_data = AZX_DRIVER_NVIDIA },
2516 { PCI_DEVICE(0x10de, 0x0d97), .driver_data = AZX_DRIVER_NVIDIA },
2518 { PCI_DEVICE(0x6549, 0x1200), .driver_data = AZX_DRIVER_TERA },
2519 /* Creative X-Fi (CA0110-IBG) */
2520 { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID),
2521 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2522 .class_mask = 0xffffff,
2523 .driver_data = AZX_DRIVER_GENERIC },
2524 /* AMD Generic, PCI class code and Vendor ID for HD Audio */
2525 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
2526 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2527 .class_mask = 0xffffff,
2528 .driver_data = AZX_DRIVER_GENERIC },
2531 MODULE_DEVICE_TABLE(pci, azx_ids);
2533 /* pci_driver definition */
2534 static struct pci_driver driver = {
2535 .name = "HDA Intel",
2536 .id_table = azx_ids,
2538 .remove = __devexit_p(azx_remove),
2540 .suspend = azx_suspend,
2541 .resume = azx_resume,
2545 static int __init alsa_card_azx_init(void)
2547 return pci_register_driver(&driver);
2550 static void __exit alsa_card_azx_exit(void)
2552 pci_unregister_driver(&driver);
2555 module_init(alsa_card_azx_init)
2556 module_exit(alsa_card_azx_exit)