2 * Copyright (c) 2000-2004 by David Brownell
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the
6 * Free Software Foundation; either version 2 of the License, or (at your
7 * option) any later version.
9 * This program is distributed in the hope that it will be useful, but
10 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
11 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software Foundation,
16 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
19 #include <linux/config.h>
21 #ifdef CONFIG_USB_DEBUG
27 #include <linux/module.h>
28 #include <linux/pci.h>
29 #include <linux/dmapool.h>
30 #include <linux/kernel.h>
31 #include <linux/delay.h>
32 #include <linux/ioport.h>
33 #include <linux/sched.h>
34 #include <linux/slab.h>
35 #include <linux/smp_lock.h>
36 #include <linux/errno.h>
37 #include <linux/init.h>
38 #include <linux/timer.h>
39 #include <linux/list.h>
40 #include <linux/interrupt.h>
41 #include <linux/reboot.h>
42 #include <linux/usb.h>
43 #include <linux/moduleparam.h>
44 #include <linux/dma-mapping.h>
46 #include "../core/hcd.h"
48 #include <asm/byteorder.h>
51 #include <asm/system.h>
52 #include <asm/unaligned.h>
55 /*-------------------------------------------------------------------------*/
58 * EHCI hc_driver implementation ... experimental, incomplete.
59 * Based on the final 1.0 register interface specification.
61 * USB 2.0 shows up in upcoming www.pcmcia.org technology.
62 * First was PCMCIA, like ISA; then CardBus, which is PCI.
63 * Next comes "CardBay", using USB 2.0 signals.
65 * Contains additional contributions by Brad Hards, Rory Bolt, and others.
66 * Special thanks to Intel and VIA for providing host controllers to
67 * test this driver on, and Cypress (including In-System Design) for
68 * providing early devices for those host controllers to talk to!
72 * 2004-05-10 Root hub and PCI suspend/resume support; remote wakeup. (db)
73 * 2004-02-24 Replace pci_* with generic dma_* API calls (dsaxena@plexity.net)
74 * 2003-12-29 Rewritten high speed iso transfer support (by Michal Sojka,
75 * <sojkam@centrum.cz>, updates by DB).
77 * 2002-11-29 Correct handling for hw async_next register.
78 * 2002-08-06 Handling for bulk and interrupt transfers is mostly shared;
79 * only scheduling is different, no arbitrary limitations.
80 * 2002-07-25 Sanity check PCI reads, mostly for better cardbus support,
81 * clean up HC run state handshaking.
82 * 2002-05-24 Preliminary FS/LS interrupts, using scheduling shortcuts
83 * 2002-05-11 Clear TT errors for FS/LS ctrl/bulk. Fill in some other
84 * missing pieces: enabling 64bit dma, handoff from BIOS/SMM.
85 * 2002-05-07 Some error path cleanups to report better errors; wmb();
86 * use non-CVS version id; better iso bandwidth claim.
87 * 2002-04-19 Control/bulk/interrupt submit no longer uses giveback() on
88 * errors in submit path. Bugfixes to interrupt scheduling/processing.
89 * 2002-03-05 Initial high-speed ISO support; reduce ITD memory; shift
90 * more checking to generic hcd framework (db). Make it work with
91 * Philips EHCI; reduce PCI traffic; shorten IRQ path (Rory Bolt).
92 * 2002-01-14 Minor cleanup; version synch.
93 * 2002-01-08 Fix roothub handoff of FS/LS to companion controllers.
94 * 2002-01-04 Control/Bulk queuing behaves.
96 * 2001-12-12 Initial patch version for Linux 2.5.1 kernel.
97 * 2001-June Works with usb-storage and NEC EHCI on 2.4
100 #define DRIVER_VERSION "10 Dec 2004"
101 #define DRIVER_AUTHOR "David Brownell"
102 #define DRIVER_DESC "USB 2.0 'Enhanced' Host Controller (EHCI) Driver"
104 static const char hcd_name [] = "ehci_hcd";
107 #undef EHCI_VERBOSE_DEBUG
108 #undef EHCI_URB_TRACE
114 /* magic numbers that can affect system performance */
115 #define EHCI_TUNE_CERR 3 /* 0-3 qtd retries; 0 == don't stop */
116 #define EHCI_TUNE_RL_HS 4 /* nak throttle; see 4.9 */
117 #define EHCI_TUNE_RL_TT 0
118 #define EHCI_TUNE_MULT_HS 1 /* 1-3 transactions/uframe; 4.10.3 */
119 #define EHCI_TUNE_MULT_TT 1
120 #define EHCI_TUNE_FLS 2 /* (small) 256 frame schedule */
122 #define EHCI_IAA_JIFFIES (HZ/100) /* arbitrary; ~10 msec */
123 #define EHCI_IO_JIFFIES (HZ/10) /* io watchdog > irq_thresh */
124 #define EHCI_ASYNC_JIFFIES (HZ/20) /* async idle timeout */
125 #define EHCI_SHRINK_JIFFIES (HZ/200) /* async qh unlink delay */
127 /* Initial IRQ latency: faster than hw default */
128 static int log2_irq_thresh = 0; // 0 to 6
129 module_param (log2_irq_thresh, int, S_IRUGO);
130 MODULE_PARM_DESC (log2_irq_thresh, "log2 IRQ latency, 1-64 microframes");
132 /* initial park setting: slower than hw default */
133 static unsigned park = 0;
134 module_param (park, uint, S_IRUGO);
135 MODULE_PARM_DESC (park, "park setting; 1-3 back-to-back async packets");
137 #define INTR_MASK (STS_IAA | STS_FATAL | STS_PCD | STS_ERR | STS_INT)
139 /*-------------------------------------------------------------------------*/
142 #include "ehci-dbg.c"
144 /*-------------------------------------------------------------------------*/
147 * handshake - spin reading hc until handshake completes or fails
148 * @ptr: address of hc register to be read
149 * @mask: bits to look at in result of read
150 * @done: value of those bits when handshake succeeds
151 * @usec: timeout in microseconds
153 * Returns negative errno, or zero on success
155 * Success happens when the "mask" bits have the specified value (hardware
156 * handshake done). There are two failure modes: "usec" have passed (major
157 * hardware flakeout), or the register reads as all-ones (hardware removed).
159 * That last failure should_only happen in cases like physical cardbus eject
160 * before driver shutdown. But it also seems to be caused by bugs in cardbus
161 * bridge shutdown: shutting down the bridge before the devices using it.
163 static int handshake (void __iomem *ptr, u32 mask, u32 done, int usec)
168 result = readl (ptr);
169 if (result == ~(u32)0) /* card removed */
180 /* force HC to halt state from unknown (EHCI spec section 2.3) */
181 static int ehci_halt (struct ehci_hcd *ehci)
183 u32 temp = readl (&ehci->regs->status);
185 if ((temp & STS_HALT) != 0)
188 temp = readl (&ehci->regs->command);
190 writel (temp, &ehci->regs->command);
191 return handshake (&ehci->regs->status, STS_HALT, STS_HALT, 16 * 125);
194 /* put TDI/ARC silicon into EHCI mode */
195 static void tdi_reset (struct ehci_hcd *ehci)
197 u32 __iomem *reg_ptr;
200 reg_ptr = (u32 __iomem *)(((u8 __iomem *)ehci->regs) + 0x68);
201 tmp = readl (reg_ptr);
203 writel (tmp, reg_ptr);
206 /* reset a non-running (STS_HALT == 1) controller */
207 static int ehci_reset (struct ehci_hcd *ehci)
210 u32 command = readl (&ehci->regs->command);
212 command |= CMD_RESET;
213 dbg_cmd (ehci, "reset", command);
214 writel (command, &ehci->regs->command);
215 ehci_to_hcd(ehci)->state = HC_STATE_HALT;
216 ehci->next_statechange = jiffies;
217 retval = handshake (&ehci->regs->command, CMD_RESET, 0, 250 * 1000);
222 if (ehci_is_TDI(ehci))
228 /* idle the controller (from running) */
229 static void ehci_quiesce (struct ehci_hcd *ehci)
234 if (!HC_IS_RUNNING (ehci_to_hcd(ehci)->state))
238 /* wait for any schedule enables/disables to take effect */
239 temp = readl (&ehci->regs->command) << 10;
240 temp &= STS_ASS | STS_PSS;
241 if (handshake (&ehci->regs->status, STS_ASS | STS_PSS,
242 temp, 16 * 125) != 0) {
243 ehci_to_hcd(ehci)->state = HC_STATE_HALT;
247 /* then disable anything that's still active */
248 temp = readl (&ehci->regs->command);
249 temp &= ~(CMD_ASE | CMD_IAAD | CMD_PSE);
250 writel (temp, &ehci->regs->command);
252 /* hardware can take 16 microframes to turn off ... */
253 if (handshake (&ehci->regs->status, STS_ASS | STS_PSS,
255 ehci_to_hcd(ehci)->state = HC_STATE_HALT;
260 /*-------------------------------------------------------------------------*/
262 static void ehci_work(struct ehci_hcd *ehci, struct pt_regs *regs);
264 #include "ehci-hub.c"
265 #include "ehci-mem.c"
267 #include "ehci-sched.c"
269 /*-------------------------------------------------------------------------*/
271 static void ehci_watchdog (unsigned long param)
273 struct ehci_hcd *ehci = (struct ehci_hcd *) param;
276 spin_lock_irqsave (&ehci->lock, flags);
278 /* lost IAA irqs wedge things badly; seen with a vt8235 */
280 u32 status = readl (&ehci->regs->status);
282 if (status & STS_IAA) {
283 ehci_vdbg (ehci, "lost IAA\n");
284 COUNT (ehci->stats.lost_iaa);
285 writel (STS_IAA, &ehci->regs->status);
286 ehci->reclaim_ready = 1;
290 /* stop async processing after it's idled a bit */
291 if (test_bit (TIMER_ASYNC_OFF, &ehci->actions))
292 start_unlink_async (ehci, ehci->async);
294 /* ehci could run by timer, without IRQs ... */
295 ehci_work (ehci, NULL);
297 spin_unlock_irqrestore (&ehci->lock, flags);
302 /* EHCI 0.96 (and later) section 5.1 says how to kick BIOS/SMM/...
303 * off the controller (maybe it can boot from highspeed USB disks).
305 static int bios_handoff (struct ehci_hcd *ehci, int where, u32 cap)
307 struct pci_dev *pdev = to_pci_dev(ehci_to_hcd(ehci)->self.controller);
309 /* always say Linux will own the hardware */
310 pci_write_config_byte(pdev, where + 3, 1);
312 /* maybe wait a while for BIOS to respond */
313 if (cap & (1 << 16)) {
319 pci_read_config_dword(pdev, where, &cap);
320 } while ((cap & (1 << 16)) && msec);
321 if (cap & (1 << 16)) {
322 ehci_err(ehci, "BIOS handoff failed (%d, %08x)\n",
324 // some BIOS versions seem buggy...
326 ehci_warn (ehci, "continuing after BIOS bug...\n");
327 /* disable all SMIs, and clear "BIOS owns" flag */
328 pci_write_config_dword(pdev, where + 4, 0);
329 pci_write_config_byte(pdev, where + 2, 0);
331 ehci_dbg(ehci, "BIOS handoff succeeded\n");
339 ehci_reboot (struct notifier_block *self, unsigned long code, void *null)
341 struct ehci_hcd *ehci;
343 ehci = container_of (self, struct ehci_hcd, reboot_notifier);
345 /* make BIOS/etc use companion controller during reboot */
346 writel (0, &ehci->regs->configured_flag);
350 static void ehci_port_power (struct ehci_hcd *ehci, int is_on)
354 if (!HCS_PPC (ehci->hcs_params))
357 ehci_dbg (ehci, "...power%s ports...\n", is_on ? "up" : "down");
358 for (port = HCS_N_PORTS (ehci->hcs_params); port > 0; )
359 (void) ehci_hub_control(ehci_to_hcd(ehci),
360 is_on ? SetPortFeature : ClearPortFeature,
367 /* called by khubd or root hub init threads */
369 static int ehci_hc_reset (struct usb_hcd *hcd)
371 struct ehci_hcd *ehci = hcd_to_ehci (hcd);
373 unsigned count = 256/4;
375 spin_lock_init (&ehci->lock);
377 ehci->caps = hcd->regs;
378 ehci->regs = hcd->regs + HC_LENGTH (readl (&ehci->caps->hc_capbase));
379 dbg_hcs_params (ehci, "reset");
380 dbg_hcc_params (ehci, "reset");
382 /* cache this readonly data; minimize chip reads */
383 ehci->hcs_params = readl (&ehci->caps->hcs_params);
386 if (hcd->self.controller->bus == &pci_bus_type) {
387 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
389 switch (pdev->vendor) {
390 case PCI_VENDOR_ID_TDI:
391 if (pdev->device == PCI_DEVICE_ID_TDI_EHCI) {
392 ehci->is_tdi_rh_tt = 1;
396 case PCI_VENDOR_ID_AMD:
397 /* AMD8111 EHCI doesn't work, according to AMD errata */
398 if (pdev->device == 0x7463) {
399 ehci_info (ehci, "ignoring AMD8111 (errata)\n");
405 /* optional debug port, normally in the first BAR */
406 temp = pci_find_capability (pdev, 0x0a);
408 pci_read_config_dword(pdev, temp, &temp);
410 if ((temp & (3 << 13)) == (1 << 13)) {
412 ehci->debug = hcd->regs + temp;
413 temp = readl (&ehci->debug->control);
414 ehci_info (ehci, "debug port %d%s\n",
415 HCS_DEBUG_PORT(ehci->hcs_params),
416 (temp & DBGP_ENABLED)
419 if (!(temp & DBGP_ENABLED))
424 temp = HCC_EXT_CAPS (readl (&ehci->caps->hcc_params));
428 /* EHCI 0.96 and later may have "extended capabilities" */
429 while (temp && count--) {
432 pci_read_config_dword (to_pci_dev(hcd->self.controller),
434 ehci_dbg (ehci, "capability %04x at %02x\n", cap, temp);
435 switch (cap & 0xff) {
436 case 1: /* BIOS/SMM/... handoff */
437 if (bios_handoff (ehci, temp, cap) != 0)
440 case 0: /* illegal reserved capability */
441 ehci_warn (ehci, "illegal capability!\n");
444 default: /* unknown */
447 temp = (cap >> 8) & 0xff;
450 ehci_err (ehci, "bogus capabilities ... PCI problems!\n");
453 if (ehci_is_TDI(ehci))
457 ehci_port_power (ehci, 0);
459 /* at least the Genesys GL880S needs fixup here */
460 temp = HCS_N_CC(ehci->hcs_params) * HCS_N_PCC(ehci->hcs_params);
462 if (temp && HCS_N_PORTS(ehci->hcs_params) > temp) {
463 ehci_dbg (ehci, "bogus port configuration: "
464 "cc=%d x pcc=%d < ports=%d\n",
465 HCS_N_CC(ehci->hcs_params),
466 HCS_N_PCC(ehci->hcs_params),
467 HCS_N_PORTS(ehci->hcs_params));
470 if (hcd->self.controller->bus == &pci_bus_type) {
471 struct pci_dev *pdev;
473 pdev = to_pci_dev(hcd->self.controller);
474 switch (pdev->vendor) {
475 case 0x17a0: /* GENESYS */
476 /* GL880S: should be PORTS=2 */
477 temp |= (ehci->hcs_params & ~0xf);
478 ehci->hcs_params = temp;
480 case PCI_VENDOR_ID_NVIDIA:
481 /* NF4: should be PCC=10 */
488 /* force HC to halt state */
489 return ehci_halt (ehci);
492 static int ehci_start (struct usb_hcd *hcd)
494 struct ehci_hcd *ehci = hcd_to_ehci (hcd);
501 /* skip some things on restart paths */
502 first = (ehci->watchdog.data == 0);
504 init_timer (&ehci->watchdog);
505 ehci->watchdog.function = ehci_watchdog;
506 ehci->watchdog.data = (unsigned long) ehci;
510 * hw default: 1K periodic list heads, one per frame.
511 * periodic_size can shrink by USBCMD update if hcc_params allows.
513 ehci->periodic_size = DEFAULT_I_TDPS;
514 if (first && (retval = ehci_mem_init (ehci, GFP_KERNEL)) < 0)
517 /* controllers may cache some of the periodic schedule ... */
518 hcc_params = readl (&ehci->caps->hcc_params);
519 if (HCC_ISOC_CACHE (hcc_params)) // full frame cache
521 else // N microframes cached
522 ehci->i_thresh = 2 + HCC_ISOC_THRES (hcc_params);
524 ehci->reclaim = NULL;
525 ehci->reclaim_ready = 0;
526 ehci->next_uframe = -1;
528 /* controller state: unknown --> reset */
530 /* EHCI spec section 4.1 */
531 if ((retval = ehci_reset (ehci)) != 0) {
532 ehci_mem_cleanup (ehci);
535 writel (ehci->periodic_dma, &ehci->regs->frame_list);
538 if (hcd->self.controller->bus == &pci_bus_type) {
539 struct pci_dev *pdev;
542 pdev = to_pci_dev(hcd->self.controller);
544 /* Serial Bus Release Number is at PCI 0x60 offset */
545 pci_read_config_byte(pdev, 0x60, &sbrn);
547 /* port wake capability, reported by boot firmware */
548 pci_read_config_word(pdev, 0x62, &port_wake);
549 hcd->can_wakeup = (port_wake & 1) != 0;
551 /* help hc dma work well with cachelines */
552 retval = pci_set_mwi(pdev);
554 ehci_dbg(ehci, "unable to enable MWI - not fatal.\n");
559 * dedicate a qh for the async ring head, since we couldn't unlink
560 * a 'real' qh without stopping the async schedule [4.8]. use it
561 * as the 'reclamation list head' too.
562 * its dummy is used in hw_alt_next of many tds, to prevent the qh
563 * from automatically advancing to the next td after short reads.
566 ehci->async->qh_next.qh = NULL;
567 ehci->async->hw_next = QH_NEXT (ehci->async->qh_dma);
568 ehci->async->hw_info1 = cpu_to_le32 (QH_HEAD);
569 ehci->async->hw_token = cpu_to_le32 (QTD_STS_HALT);
570 ehci->async->hw_qtd_next = EHCI_LIST_END;
571 ehci->async->qh_state = QH_STATE_LINKED;
572 ehci->async->hw_alt_next = QTD_NEXT (ehci->async->dummy->qtd_dma);
574 writel ((u32)ehci->async->qh_dma, &ehci->regs->async_next);
577 * hcc_params controls whether ehci->regs->segment must (!!!)
578 * be used; it constrains QH/ITD/SITD and QTD locations.
579 * pci_pool consistent memory always uses segment zero.
580 * streaming mappings for I/O buffers, like pci_map_single(),
581 * can return segments above 4GB, if the device allows.
583 * NOTE: the dma mask is visible through dma_supported(), so
584 * drivers can pass this info along ... like NETIF_F_HIGHDMA,
585 * Scsi_Host.highmem_io, and so forth. It's readonly to all
586 * host side drivers though.
588 if (HCC_64BIT_ADDR (hcc_params)) {
589 writel (0, &ehci->regs->segment);
591 // this is deeply broken on almost all architectures
592 if (!dma_set_mask (hcd->self.controller, DMA_64BIT_MASK))
593 ehci_info (ehci, "enabled 64bit DMA\n");
597 /* clear interrupt enables, set irq latency */
598 if (log2_irq_thresh < 0 || log2_irq_thresh > 6)
600 temp = 1 << (16 + log2_irq_thresh);
601 if (HCC_CANPARK(hcc_params)) {
602 /* HW default park == 3, on hardware that supports it (like
603 * NVidia and ALI silicon), maximizes throughput on the async
604 * schedule by avoiding QH fetches between transfers.
606 * With fast usb storage devices and NForce2, "park" seems to
607 * make problems: throughput reduction (!), data errors...
610 park = min (park, (unsigned) 3);
614 ehci_info (ehci, "park %d\n", park);
616 if (HCC_PGM_FRAMELISTLEN (hcc_params)) {
617 /* periodic schedule size can be smaller than default */
619 temp |= (EHCI_TUNE_FLS << 2);
620 switch (EHCI_TUNE_FLS) {
621 case 0: ehci->periodic_size = 1024; break;
622 case 1: ehci->periodic_size = 512; break;
623 case 2: ehci->periodic_size = 256; break;
627 // Philips, Intel, and maybe others need CMD_RUN before the
628 // root hub will detect new devices (why?); NEC doesn't
630 writel (temp, &ehci->regs->command);
631 dbg_cmd (ehci, "init", temp);
633 /* set async sleep time = 10 us ... ? */
636 * Start, enabling full USB 2.0 functionality ... usb 1.1 devices
637 * are explicitly handed to companion controller(s), so no TT is
638 * involved with the root hub. (Except where one is integrated,
639 * and there's no companion controller unless maybe for USB OTG.)
642 ehci->reboot_notifier.notifier_call = ehci_reboot;
643 register_reboot_notifier (&ehci->reboot_notifier);
646 hcd->state = HC_STATE_RUNNING;
647 writel (FLAG_CF, &ehci->regs->configured_flag);
648 readl (&ehci->regs->command); /* unblock posted write */
650 temp = HC_VERSION(readl (&ehci->caps->hc_capbase));
652 "USB %x.%x %s, EHCI %x.%02x, driver %s\n",
653 ((sbrn & 0xf0)>>4), (sbrn & 0x0f),
654 first ? "initialized" : "restarted",
655 temp >> 8, temp & 0xff, DRIVER_VERSION);
657 writel (INTR_MASK, &ehci->regs->intr_enable); /* Turn On Interrupts */
660 create_debug_files (ehci);
665 /* always called by thread; normally rmmod */
667 static void ehci_stop (struct usb_hcd *hcd)
669 struct ehci_hcd *ehci = hcd_to_ehci (hcd);
671 ehci_dbg (ehci, "stop\n");
673 /* Turn off port power on all root hub ports. */
674 ehci_port_power (ehci, 0);
676 /* no more interrupts ... */
677 del_timer_sync (&ehci->watchdog);
679 spin_lock_irq(&ehci->lock);
680 if (HC_IS_RUNNING (hcd->state))
684 writel (0, &ehci->regs->intr_enable);
685 spin_unlock_irq(&ehci->lock);
687 /* let companion controllers work when we aren't */
688 writel (0, &ehci->regs->configured_flag);
689 unregister_reboot_notifier (&ehci->reboot_notifier);
691 remove_debug_files (ehci);
693 /* root hub is shut down separately (first, when possible) */
694 spin_lock_irq (&ehci->lock);
696 ehci_work (ehci, NULL);
697 spin_unlock_irq (&ehci->lock);
698 ehci_mem_cleanup (ehci);
701 ehci_dbg (ehci, "irq normal %ld err %ld reclaim %ld (lost %ld)\n",
702 ehci->stats.normal, ehci->stats.error, ehci->stats.reclaim,
703 ehci->stats.lost_iaa);
704 ehci_dbg (ehci, "complete %ld unlink %ld\n",
705 ehci->stats.complete, ehci->stats.unlink);
708 dbg_status (ehci, "ehci_stop completed", readl (&ehci->regs->status));
711 static int ehci_get_frame (struct usb_hcd *hcd)
713 struct ehci_hcd *ehci = hcd_to_ehci (hcd);
714 return (readl (&ehci->regs->frame_index) >> 3) % ehci->periodic_size;
717 /*-------------------------------------------------------------------------*/
721 /* suspend/resume, section 4.3 */
723 /* These routines rely on the bus (pci, platform, etc)
724 * to handle powerdown and wakeup, and currently also on
725 * transceivers that don't need any software attention to set up
726 * the right sort of wakeup.
729 static int ehci_suspend (struct usb_hcd *hcd, pm_message_t message)
731 struct ehci_hcd *ehci = hcd_to_ehci (hcd);
733 if (time_before (jiffies, ehci->next_statechange))
736 #ifdef CONFIG_USB_SUSPEND
737 (void) usb_suspend_device (hcd->self.root_hub, message);
739 usb_lock_device (hcd->self.root_hub);
740 (void) ehci_hub_suspend (hcd);
741 usb_unlock_device (hcd->self.root_hub);
744 // save (PCI) FLADJ in case of Vaux power loss
745 // ... we'd only use it to handle clock skew
750 static int ehci_resume (struct usb_hcd *hcd)
752 struct ehci_hcd *ehci = hcd_to_ehci (hcd);
754 struct usb_device *root = hcd->self.root_hub;
755 int retval = -EINVAL;
757 // maybe restore (PCI) FLADJ
759 if (time_before (jiffies, ehci->next_statechange))
762 /* If any port is suspended, we know we can/must resume the HC. */
763 for (port = HCS_N_PORTS (ehci->hcs_params); port > 0; ) {
766 status = readl (&ehci->regs->port_status [port]);
767 if (status & PORT_SUSPEND) {
768 down (&hcd->self.root_hub->serialize);
769 retval = ehci_hub_resume (hcd);
770 up (&hcd->self.root_hub->serialize);
773 if (!root->children [port])
775 dbg_port (ehci, __FUNCTION__, port + 1, status);
776 usb_set_device_state (root->children[port],
777 USB_STATE_NOTATTACHED);
780 /* Else reset, to cope with power loss or flush-to-storage
781 * style "resume" having activated BIOS during reboot.
784 (void) ehci_halt (ehci);
785 (void) ehci_reset (ehci);
786 (void) ehci_hc_reset (hcd);
788 /* emptying the schedule aborts any urbs */
789 spin_lock_irq (&ehci->lock);
791 ehci->reclaim_ready = 1;
792 ehci_work (ehci, NULL);
793 spin_unlock_irq (&ehci->lock);
795 /* restart; khubd will disconnect devices */
796 retval = ehci_start (hcd);
798 /* here we "know" root ports should always stay powered;
799 * but some controllers may lose all power.
801 ehci_port_power (ehci, 1);
809 /*-------------------------------------------------------------------------*/
812 * ehci_work is called from some interrupts, timers, and so on.
813 * it calls driver completion functions, after dropping ehci->lock.
815 static void ehci_work (struct ehci_hcd *ehci, struct pt_regs *regs)
817 timer_action_done (ehci, TIMER_IO_WATCHDOG);
818 if (ehci->reclaim_ready)
819 end_unlink_async (ehci, regs);
821 /* another CPU may drop ehci->lock during a schedule scan while
822 * it reports urb completions. this flag guards against bogus
823 * attempts at re-entrant schedule scanning.
828 scan_async (ehci, regs);
829 if (ehci->next_uframe != -1)
830 scan_periodic (ehci, regs);
833 /* the IO watchdog guards against hardware or driver bugs that
834 * misplace IRQs, and should let us run completely without IRQs.
835 * such lossage has been observed on both VT6202 and VT8235.
837 if (HC_IS_RUNNING (ehci_to_hcd(ehci)->state) &&
838 (ehci->async->qh_next.ptr != NULL ||
839 ehci->periodic_sched != 0))
840 timer_action (ehci, TIMER_IO_WATCHDOG);
843 /*-------------------------------------------------------------------------*/
845 static irqreturn_t ehci_irq (struct usb_hcd *hcd, struct pt_regs *regs)
847 struct ehci_hcd *ehci = hcd_to_ehci (hcd);
851 spin_lock (&ehci->lock);
853 status = readl (&ehci->regs->status);
855 /* e.g. cardbus physical eject */
856 if (status == ~(u32) 0) {
857 ehci_dbg (ehci, "device removed\n");
862 if (!status) { /* irq sharing? */
863 spin_unlock(&ehci->lock);
867 /* clear (just) interrupts */
868 writel (status, &ehci->regs->status);
869 readl (&ehci->regs->command); /* unblock posted write */
872 #ifdef EHCI_VERBOSE_DEBUG
873 /* unrequested/ignored: Frame List Rollover */
874 dbg_status (ehci, "irq", status);
877 /* INT, ERR, and IAA interrupt rates can be throttled */
879 /* normal [4.15.1.2] or error [4.15.1.1] completion */
880 if (likely ((status & (STS_INT|STS_ERR)) != 0)) {
881 if (likely ((status & STS_ERR) == 0))
882 COUNT (ehci->stats.normal);
884 COUNT (ehci->stats.error);
888 /* complete the unlinking of some qh [4.15.2.3] */
889 if (status & STS_IAA) {
890 COUNT (ehci->stats.reclaim);
891 ehci->reclaim_ready = 1;
895 /* remote wakeup [4.3.1] */
896 if ((status & STS_PCD) && hcd->remote_wakeup) {
897 unsigned i = HCS_N_PORTS (ehci->hcs_params);
899 /* resume root hub? */
900 status = readl (&ehci->regs->command);
901 if (!(status & CMD_RUN))
902 writel (status | CMD_RUN, &ehci->regs->command);
905 status = readl (&ehci->regs->port_status [i]);
906 if (status & PORT_OWNER)
908 if (!(status & PORT_RESUME)
909 || ehci->reset_done [i] != 0)
912 /* start 20 msec resume signaling from this port,
913 * and make khubd collect PORT_STAT_C_SUSPEND to
914 * stop that signaling.
916 ehci->reset_done [i] = jiffies + msecs_to_jiffies (20);
917 mod_timer (&hcd->rh_timer,
918 ehci->reset_done [i] + 1);
919 ehci_dbg (ehci, "port %d remote wakeup\n", i + 1);
923 /* PCI errors [4.15.2.4] */
924 if (unlikely ((status & STS_FATAL) != 0)) {
925 /* bogus "fatal" IRQs appear on some chips... why? */
926 status = readl (&ehci->regs->status);
927 dbg_cmd (ehci, "fatal", readl (&ehci->regs->command));
928 dbg_status (ehci, "fatal", status);
929 if (status & STS_HALT) {
930 ehci_err (ehci, "fatal error\n");
933 writel (0, &ehci->regs->configured_flag);
934 /* generic layer kills/unlinks all urbs, then
935 * uses ehci_stop to clean up the rest
942 ehci_work (ehci, regs);
943 spin_unlock (&ehci->lock);
947 /*-------------------------------------------------------------------------*/
950 * non-error returns are a promise to giveback() the urb later
951 * we drop ownership so next owner (or urb unlink) can get it
953 * urb + dev is in hcd.self.controller.urb_list
954 * we're queueing TDs onto software and hardware lists
956 * hcd-specific init for hcpriv hasn't been done yet
958 * NOTE: control, bulk, and interrupt share the same code to append TDs
959 * to a (possibly active) QH, and the same QH scanning code.
961 static int ehci_urb_enqueue (
963 struct usb_host_endpoint *ep,
967 struct ehci_hcd *ehci = hcd_to_ehci (hcd);
968 struct list_head qtd_list;
970 INIT_LIST_HEAD (&qtd_list);
972 switch (usb_pipetype (urb->pipe)) {
973 // case PIPE_CONTROL:
976 if (!qh_urb_transaction (ehci, urb, &qtd_list, mem_flags))
978 return submit_async (ehci, ep, urb, &qtd_list, mem_flags);
981 if (!qh_urb_transaction (ehci, urb, &qtd_list, mem_flags))
983 return intr_submit (ehci, ep, urb, &qtd_list, mem_flags);
985 case PIPE_ISOCHRONOUS:
986 if (urb->dev->speed == USB_SPEED_HIGH)
987 return itd_submit (ehci, urb, mem_flags);
989 return sitd_submit (ehci, urb, mem_flags);
993 static void unlink_async (struct ehci_hcd *ehci, struct ehci_qh *qh)
995 /* if we need to use IAA and it's busy, defer */
996 if (qh->qh_state == QH_STATE_LINKED
998 && HC_IS_RUNNING (ehci_to_hcd(ehci)->state)) {
999 struct ehci_qh *last;
1001 for (last = ehci->reclaim;
1003 last = last->reclaim)
1005 qh->qh_state = QH_STATE_UNLINK_WAIT;
1008 /* bypass IAA if the hc can't care */
1009 } else if (!HC_IS_RUNNING (ehci_to_hcd(ehci)->state) && ehci->reclaim)
1010 end_unlink_async (ehci, NULL);
1012 /* something else might have unlinked the qh by now */
1013 if (qh->qh_state == QH_STATE_LINKED)
1014 start_unlink_async (ehci, qh);
1017 /* remove from hardware lists
1018 * completions normally happen asynchronously
1021 static int ehci_urb_dequeue (struct usb_hcd *hcd, struct urb *urb)
1023 struct ehci_hcd *ehci = hcd_to_ehci (hcd);
1025 unsigned long flags;
1027 spin_lock_irqsave (&ehci->lock, flags);
1028 switch (usb_pipetype (urb->pipe)) {
1029 // case PIPE_CONTROL:
1032 qh = (struct ehci_qh *) urb->hcpriv;
1035 unlink_async (ehci, qh);
1038 case PIPE_INTERRUPT:
1039 qh = (struct ehci_qh *) urb->hcpriv;
1042 switch (qh->qh_state) {
1043 case QH_STATE_LINKED:
1044 intr_deschedule (ehci, qh);
1047 qh_completions (ehci, qh, NULL);
1050 ehci_dbg (ehci, "bogus qh %p state %d\n",
1055 /* reschedule QH iff another request is queued */
1056 if (!list_empty (&qh->qtd_list)
1057 && HC_IS_RUNNING (hcd->state)) {
1060 status = qh_schedule (ehci, qh);
1061 spin_unlock_irqrestore (&ehci->lock, flags);
1064 // shouldn't happen often, but ...
1065 // FIXME kill those tds' urbs
1066 err ("can't reschedule qh %p, err %d",
1073 case PIPE_ISOCHRONOUS:
1076 // wait till next completion, do it then.
1077 // completion irqs can wait up to 1024 msec,
1081 spin_unlock_irqrestore (&ehci->lock, flags);
1085 /*-------------------------------------------------------------------------*/
1087 // bulk qh holds the data toggle
1090 ehci_endpoint_disable (struct usb_hcd *hcd, struct usb_host_endpoint *ep)
1092 struct ehci_hcd *ehci = hcd_to_ehci (hcd);
1093 unsigned long flags;
1094 struct ehci_qh *qh, *tmp;
1096 /* ASSERT: any requests/urbs are being unlinked */
1097 /* ASSERT: nobody can be submitting urbs for this any more */
1100 spin_lock_irqsave (&ehci->lock, flags);
1105 /* endpoints can be iso streams. for now, we don't
1106 * accelerate iso completions ... so spin a while.
1108 if (qh->hw_info1 == 0) {
1109 ehci_vdbg (ehci, "iso delay\n");
1113 if (!HC_IS_RUNNING (hcd->state))
1114 qh->qh_state = QH_STATE_IDLE;
1115 switch (qh->qh_state) {
1116 case QH_STATE_LINKED:
1117 for (tmp = ehci->async->qh_next.qh;
1119 tmp = tmp->qh_next.qh)
1121 /* periodic qh self-unlinks on empty */
1124 unlink_async (ehci, qh);
1126 case QH_STATE_UNLINK: /* wait for hw to finish? */
1128 spin_unlock_irqrestore (&ehci->lock, flags);
1129 set_current_state (TASK_UNINTERRUPTIBLE);
1130 schedule_timeout (1);
1132 case QH_STATE_IDLE: /* fully unlinked */
1133 if (list_empty (&qh->qtd_list)) {
1137 /* else FALL THROUGH */
1140 /* caller was supposed to have unlinked any requests;
1141 * that's not our job. just leak this memory.
1143 ehci_err (ehci, "qh %p (#%02x) state %d%s\n",
1144 qh, ep->desc.bEndpointAddress, qh->qh_state,
1145 list_empty (&qh->qtd_list) ? "" : "(has tds)");
1150 spin_unlock_irqrestore (&ehci->lock, flags);
1154 /*-------------------------------------------------------------------------*/
1156 static const struct hc_driver ehci_driver = {
1157 .description = hcd_name,
1158 .product_desc = "EHCI Host Controller",
1159 .hcd_priv_size = sizeof(struct ehci_hcd),
1162 * generic hardware linkage
1165 .flags = HCD_MEMORY | HCD_USB2,
1168 * basic lifecycle operations
1170 .reset = ehci_hc_reset,
1171 .start = ehci_start,
1173 .suspend = ehci_suspend,
1174 .resume = ehci_resume,
1179 * managing i/o requests and associated device resources
1181 .urb_enqueue = ehci_urb_enqueue,
1182 .urb_dequeue = ehci_urb_dequeue,
1183 .endpoint_disable = ehci_endpoint_disable,
1186 * scheduling support
1188 .get_frame_number = ehci_get_frame,
1193 .hub_status_data = ehci_hub_status_data,
1194 .hub_control = ehci_hub_control,
1195 .hub_suspend = ehci_hub_suspend,
1196 .hub_resume = ehci_hub_resume,
1199 /*-------------------------------------------------------------------------*/
1201 /* EHCI 1.0 doesn't require PCI */
1205 /* PCI driver selection metadata; PCI hotplugging uses this */
1206 static const struct pci_device_id pci_ids [] = { {
1207 /* handle any USB 2.0 EHCI controller */
1208 PCI_DEVICE_CLASS(((PCI_CLASS_SERIAL_USB << 8) | 0x20), ~0),
1209 .driver_data = (unsigned long) &ehci_driver,
1211 { /* end: all zeroes */ }
1213 MODULE_DEVICE_TABLE (pci, pci_ids);
1215 /* pci driver glue; this is a "new style" PCI driver module */
1216 static struct pci_driver ehci_pci_driver = {
1217 .name = (char *) hcd_name,
1218 .id_table = pci_ids,
1220 .probe = usb_hcd_pci_probe,
1221 .remove = usb_hcd_pci_remove,
1224 .suspend = usb_hcd_pci_suspend,
1225 .resume = usb_hcd_pci_resume,
1232 #define DRIVER_INFO DRIVER_VERSION " " DRIVER_DESC
1234 MODULE_DESCRIPTION (DRIVER_INFO);
1235 MODULE_AUTHOR (DRIVER_AUTHOR);
1236 MODULE_LICENSE ("GPL");
1238 static int __init init (void)
1243 pr_debug ("%s: block sizes: qh %Zd qtd %Zd itd %Zd sitd %Zd\n",
1245 sizeof (struct ehci_qh), sizeof (struct ehci_qtd),
1246 sizeof (struct ehci_itd), sizeof (struct ehci_sitd));
1248 return pci_register_driver (&ehci_pci_driver);
1252 static void __exit cleanup (void)
1254 pci_unregister_driver (&ehci_pci_driver);
1256 module_exit (cleanup);