Pull cpuidle into release branch
[linux-2.6] / drivers / media / dvb / frontends / dib3000mb.c
1 /*
2  * Frontend driver for mobile DVB-T demodulator DiBcom 3000M-B
3  * DiBcom (http://www.dibcom.fr/)
4  *
5  * Copyright (C) 2004-5 Patrick Boettcher (patrick.boettcher@desy.de)
6  *
7  * based on GPL code from DibCom, which has
8  *
9  * Copyright (C) 2004 Amaury Demol for DiBcom (ademol@dibcom.fr)
10  *
11  *      This program is free software; you can redistribute it and/or
12  *      modify it under the terms of the GNU General Public License as
13  *      published by the Free Software Foundation, version 2.
14  *
15  * Acknowledgements
16  *
17  *  Amaury Demol (ademol@dibcom.fr) from DiBcom for providing specs and driver
18  *  sources, on which this driver (and the dvb-dibusb) are based.
19  *
20  * see Documentation/dvb/README.dibusb for more information
21  *
22  */
23
24 #include <linux/kernel.h>
25 #include <linux/module.h>
26 #include <linux/init.h>
27 #include <linux/delay.h>
28 #include <linux/string.h>
29 #include <linux/slab.h>
30
31 #include "dvb_frontend.h"
32
33 #include "dib3000.h"
34 #include "dib3000mb_priv.h"
35
36 /* Version information */
37 #define DRIVER_VERSION "0.1"
38 #define DRIVER_DESC "DiBcom 3000M-B DVB-T demodulator"
39 #define DRIVER_AUTHOR "Patrick Boettcher, patrick.boettcher@desy.de"
40
41 #ifdef CONFIG_DVB_DIBCOM_DEBUG
42 static int debug;
43 module_param(debug, int, 0644);
44 MODULE_PARM_DESC(debug, "set debugging level (1=info,2=xfer,4=setfe,8=getfe (|-able)).");
45 #endif
46 #define deb_info(args...) dprintk(0x01,args)
47 #define deb_i2c(args...)  dprintk(0x02,args)
48 #define deb_srch(args...) dprintk(0x04,args)
49 #define deb_info(args...) dprintk(0x01,args)
50 #define deb_xfer(args...) dprintk(0x02,args)
51 #define deb_setf(args...) dprintk(0x04,args)
52 #define deb_getf(args...) dprintk(0x08,args)
53
54 #ifdef CONFIG_DVB_DIBCOM_DEBUG
55 static int debug;
56 module_param(debug, int, 0644);
57 MODULE_PARM_DESC(debug, "set debugging level (1=info,2=i2c,4=srch (|-able)).");
58 #endif
59
60 static int dib3000_read_reg(struct dib3000_state *state, u16 reg)
61 {
62         u8 wb[] = { ((reg >> 8) | 0x80) & 0xff, reg & 0xff };
63         u8 rb[2];
64         struct i2c_msg msg[] = {
65                 { .addr = state->config.demod_address, .flags = 0,        .buf = wb, .len = 2 },
66                 { .addr = state->config.demod_address, .flags = I2C_M_RD, .buf = rb, .len = 2 },
67         };
68
69         if (i2c_transfer(state->i2c, msg, 2) != 2)
70                 deb_i2c("i2c read error\n");
71
72         deb_i2c("reading i2c bus (reg: %5d 0x%04x, val: %5d 0x%04x)\n",reg,reg,
73                         (rb[0] << 8) | rb[1],(rb[0] << 8) | rb[1]);
74
75         return (rb[0] << 8) | rb[1];
76 }
77
78 static int dib3000_write_reg(struct dib3000_state *state, u16 reg, u16 val)
79 {
80         u8 b[] = {
81                 (reg >> 8) & 0xff, reg & 0xff,
82                 (val >> 8) & 0xff, val & 0xff,
83         };
84         struct i2c_msg msg[] = {
85                 { .addr = state->config.demod_address, .flags = 0, .buf = b, .len = 4 }
86         };
87         deb_i2c("writing i2c bus (reg: %5d 0x%04x, val: %5d 0x%04x)\n",reg,reg,val,val);
88
89         return i2c_transfer(state->i2c,msg, 1) != 1 ? -EREMOTEIO : 0;
90 }
91
92 static int dib3000_search_status(u16 irq,u16 lock)
93 {
94         if (irq & 0x02) {
95                 if (lock & 0x01) {
96                         deb_srch("auto search succeeded\n");
97                         return 1; // auto search succeeded
98                 } else {
99                         deb_srch("auto search not successful\n");
100                         return 0; // auto search failed
101                 }
102         } else if (irq & 0x01)  {
103                 deb_srch("auto search failed\n");
104                 return 0; // auto search failed
105         }
106         return -1; // try again
107 }
108
109 /* for auto search */
110 static u16 dib3000_seq[2][2][2] =     /* fft,gua,   inv   */
111         { /* fft */
112                 { /* gua */
113                         { 0, 1 },                   /*  0   0   { 0,1 } */
114                         { 3, 9 },                   /*  0   1   { 0,1 } */
115                 },
116                 {
117                         { 2, 5 },                   /*  1   0   { 0,1 } */
118                         { 6, 11 },                  /*  1   1   { 0,1 } */
119                 }
120         };
121
122 static int dib3000mb_get_frontend(struct dvb_frontend* fe,
123                                   struct dvb_frontend_parameters *fep);
124
125 static int dib3000mb_set_frontend(struct dvb_frontend* fe,
126                                   struct dvb_frontend_parameters *fep, int tuner)
127 {
128         struct dib3000_state* state = fe->demodulator_priv;
129         struct dvb_ofdm_parameters *ofdm = &fep->u.ofdm;
130         fe_code_rate_t fe_cr = FEC_NONE;
131         int search_state, seq;
132
133         if (tuner && fe->ops.tuner_ops.set_params) {
134                 fe->ops.tuner_ops.set_params(fe, fep);
135                 if (fe->ops.i2c_gate_ctrl) fe->ops.i2c_gate_ctrl(fe, 0);
136
137                 deb_setf("bandwidth: ");
138                 switch (ofdm->bandwidth) {
139                         case BANDWIDTH_8_MHZ:
140                                 deb_setf("8 MHz\n");
141                                 wr_foreach(dib3000mb_reg_timing_freq, dib3000mb_timing_freq[2]);
142                                 wr_foreach(dib3000mb_reg_bandwidth, dib3000mb_bandwidth_8mhz);
143                                 break;
144                         case BANDWIDTH_7_MHZ:
145                                 deb_setf("7 MHz\n");
146                                 wr_foreach(dib3000mb_reg_timing_freq, dib3000mb_timing_freq[1]);
147                                 wr_foreach(dib3000mb_reg_bandwidth, dib3000mb_bandwidth_7mhz);
148                                 break;
149                         case BANDWIDTH_6_MHZ:
150                                 deb_setf("6 MHz\n");
151                                 wr_foreach(dib3000mb_reg_timing_freq, dib3000mb_timing_freq[0]);
152                                 wr_foreach(dib3000mb_reg_bandwidth, dib3000mb_bandwidth_6mhz);
153                                 break;
154                         case BANDWIDTH_AUTO:
155                                 return -EOPNOTSUPP;
156                         default:
157                                 err("unkown bandwidth value.");
158                                 return -EINVAL;
159                 }
160         }
161         wr(DIB3000MB_REG_LOCK1_MASK, DIB3000MB_LOCK1_SEARCH_4);
162
163         deb_setf("transmission mode: ");
164         switch (ofdm->transmission_mode) {
165                 case TRANSMISSION_MODE_2K:
166                         deb_setf("2k\n");
167                         wr(DIB3000MB_REG_FFT, DIB3000_TRANSMISSION_MODE_2K);
168                         break;
169                 case TRANSMISSION_MODE_8K:
170                         deb_setf("8k\n");
171                         wr(DIB3000MB_REG_FFT, DIB3000_TRANSMISSION_MODE_8K);
172                         break;
173                 case TRANSMISSION_MODE_AUTO:
174                         deb_setf("auto\n");
175                         break;
176                 default:
177                         return -EINVAL;
178         }
179
180         deb_setf("guard: ");
181         switch (ofdm->guard_interval) {
182                 case GUARD_INTERVAL_1_32:
183                         deb_setf("1_32\n");
184                         wr(DIB3000MB_REG_GUARD_TIME, DIB3000_GUARD_TIME_1_32);
185                         break;
186                 case GUARD_INTERVAL_1_16:
187                         deb_setf("1_16\n");
188                         wr(DIB3000MB_REG_GUARD_TIME, DIB3000_GUARD_TIME_1_16);
189                         break;
190                 case GUARD_INTERVAL_1_8:
191                         deb_setf("1_8\n");
192                         wr(DIB3000MB_REG_GUARD_TIME, DIB3000_GUARD_TIME_1_8);
193                         break;
194                 case GUARD_INTERVAL_1_4:
195                         deb_setf("1_4\n");
196                         wr(DIB3000MB_REG_GUARD_TIME, DIB3000_GUARD_TIME_1_4);
197                         break;
198                 case GUARD_INTERVAL_AUTO:
199                         deb_setf("auto\n");
200                         break;
201                 default:
202                         return -EINVAL;
203         }
204
205         deb_setf("inversion: ");
206         switch (fep->inversion) {
207                 case INVERSION_OFF:
208                         deb_setf("off\n");
209                         wr(DIB3000MB_REG_DDS_INV, DIB3000_DDS_INVERSION_OFF);
210                         break;
211                 case INVERSION_AUTO:
212                         deb_setf("auto ");
213                         break;
214                 case INVERSION_ON:
215                         deb_setf("on\n");
216                         wr(DIB3000MB_REG_DDS_INV, DIB3000_DDS_INVERSION_ON);
217                         break;
218                 default:
219                         return -EINVAL;
220         }
221
222         deb_setf("constellation: ");
223         switch (ofdm->constellation) {
224                 case QPSK:
225                         deb_setf("qpsk\n");
226                         wr(DIB3000MB_REG_QAM, DIB3000_CONSTELLATION_QPSK);
227                         break;
228                 case QAM_16:
229                         deb_setf("qam16\n");
230                         wr(DIB3000MB_REG_QAM, DIB3000_CONSTELLATION_16QAM);
231                         break;
232                 case QAM_64:
233                         deb_setf("qam64\n");
234                         wr(DIB3000MB_REG_QAM, DIB3000_CONSTELLATION_64QAM);
235                         break;
236                 case QAM_AUTO:
237                         break;
238                 default:
239                         return -EINVAL;
240         }
241         deb_setf("hierarchy: ");
242         switch (ofdm->hierarchy_information) {
243                 case HIERARCHY_NONE:
244                         deb_setf("none ");
245                         /* fall through */
246                 case HIERARCHY_1:
247                         deb_setf("alpha=1\n");
248                         wr(DIB3000MB_REG_VIT_ALPHA, DIB3000_ALPHA_1);
249                         break;
250                 case HIERARCHY_2:
251                         deb_setf("alpha=2\n");
252                         wr(DIB3000MB_REG_VIT_ALPHA, DIB3000_ALPHA_2);
253                         break;
254                 case HIERARCHY_4:
255                         deb_setf("alpha=4\n");
256                         wr(DIB3000MB_REG_VIT_ALPHA, DIB3000_ALPHA_4);
257                         break;
258                 case HIERARCHY_AUTO:
259                         deb_setf("alpha=auto\n");
260                         break;
261                 default:
262                         return -EINVAL;
263         }
264
265         deb_setf("hierarchy: ");
266         if (ofdm->hierarchy_information == HIERARCHY_NONE) {
267                 deb_setf("none\n");
268                 wr(DIB3000MB_REG_VIT_HRCH, DIB3000_HRCH_OFF);
269                 wr(DIB3000MB_REG_VIT_HP, DIB3000_SELECT_HP);
270                 fe_cr = ofdm->code_rate_HP;
271         } else if (ofdm->hierarchy_information != HIERARCHY_AUTO) {
272                 deb_setf("on\n");
273                 wr(DIB3000MB_REG_VIT_HRCH, DIB3000_HRCH_ON);
274                 wr(DIB3000MB_REG_VIT_HP, DIB3000_SELECT_LP);
275                 fe_cr = ofdm->code_rate_LP;
276         }
277         deb_setf("fec: ");
278         switch (fe_cr) {
279                 case FEC_1_2:
280                         deb_setf("1_2\n");
281                         wr(DIB3000MB_REG_VIT_CODE_RATE, DIB3000_FEC_1_2);
282                         break;
283                 case FEC_2_3:
284                         deb_setf("2_3\n");
285                         wr(DIB3000MB_REG_VIT_CODE_RATE, DIB3000_FEC_2_3);
286                         break;
287                 case FEC_3_4:
288                         deb_setf("3_4\n");
289                         wr(DIB3000MB_REG_VIT_CODE_RATE, DIB3000_FEC_3_4);
290                         break;
291                 case FEC_5_6:
292                         deb_setf("5_6\n");
293                         wr(DIB3000MB_REG_VIT_CODE_RATE, DIB3000_FEC_5_6);
294                         break;
295                 case FEC_7_8:
296                         deb_setf("7_8\n");
297                         wr(DIB3000MB_REG_VIT_CODE_RATE, DIB3000_FEC_7_8);
298                         break;
299                 case FEC_NONE:
300                         deb_setf("none ");
301                         break;
302                 case FEC_AUTO:
303                         deb_setf("auto\n");
304                         break;
305                 default:
306                         return -EINVAL;
307         }
308
309         seq = dib3000_seq
310                 [ofdm->transmission_mode == TRANSMISSION_MODE_AUTO]
311                 [ofdm->guard_interval == GUARD_INTERVAL_AUTO]
312                 [fep->inversion == INVERSION_AUTO];
313
314         deb_setf("seq? %d\n", seq);
315
316         wr(DIB3000MB_REG_SEQ, seq);
317
318         wr(DIB3000MB_REG_ISI, seq ? DIB3000MB_ISI_INHIBIT : DIB3000MB_ISI_ACTIVATE);
319
320         if (ofdm->transmission_mode == TRANSMISSION_MODE_2K) {
321                 if (ofdm->guard_interval == GUARD_INTERVAL_1_8) {
322                         wr(DIB3000MB_REG_SYNC_IMPROVEMENT, DIB3000MB_SYNC_IMPROVE_2K_1_8);
323                 } else {
324                         wr(DIB3000MB_REG_SYNC_IMPROVEMENT, DIB3000MB_SYNC_IMPROVE_DEFAULT);
325                 }
326
327                 wr(DIB3000MB_REG_UNK_121, DIB3000MB_UNK_121_2K);
328         } else {
329                 wr(DIB3000MB_REG_UNK_121, DIB3000MB_UNK_121_DEFAULT);
330         }
331
332         wr(DIB3000MB_REG_MOBILE_ALGO, DIB3000MB_MOBILE_ALGO_OFF);
333         wr(DIB3000MB_REG_MOBILE_MODE_QAM, DIB3000MB_MOBILE_MODE_QAM_OFF);
334         wr(DIB3000MB_REG_MOBILE_MODE, DIB3000MB_MOBILE_MODE_OFF);
335
336         wr_foreach(dib3000mb_reg_agc_bandwidth, dib3000mb_agc_bandwidth_high);
337
338         wr(DIB3000MB_REG_ISI, DIB3000MB_ISI_ACTIVATE);
339
340         wr(DIB3000MB_REG_RESTART, DIB3000MB_RESTART_AGC + DIB3000MB_RESTART_CTRL);
341         wr(DIB3000MB_REG_RESTART, DIB3000MB_RESTART_OFF);
342
343         /* wait for AGC lock */
344         msleep(70);
345
346         wr_foreach(dib3000mb_reg_agc_bandwidth, dib3000mb_agc_bandwidth_low);
347
348         /* something has to be auto searched */
349         if (ofdm->constellation == QAM_AUTO ||
350                 ofdm->hierarchy_information == HIERARCHY_AUTO ||
351                 fe_cr == FEC_AUTO ||
352                 fep->inversion == INVERSION_AUTO) {
353                 int as_count=0;
354
355                 deb_setf("autosearch enabled.\n");
356
357                 wr(DIB3000MB_REG_ISI, DIB3000MB_ISI_INHIBIT);
358
359                 wr(DIB3000MB_REG_RESTART, DIB3000MB_RESTART_AUTO_SEARCH);
360                 wr(DIB3000MB_REG_RESTART, DIB3000MB_RESTART_OFF);
361
362                 while ((search_state =
363                                 dib3000_search_status(
364                                         rd(DIB3000MB_REG_AS_IRQ_PENDING),
365                                         rd(DIB3000MB_REG_LOCK2_VALUE))) < 0 && as_count++ < 100)
366                         msleep(1);
367
368                 deb_setf("search_state after autosearch %d after %d checks\n",search_state,as_count);
369
370                 if (search_state == 1) {
371                         struct dvb_frontend_parameters feps;
372                         if (dib3000mb_get_frontend(fe, &feps) == 0) {
373                                 deb_setf("reading tuning data from frontend succeeded.\n");
374                                 return dib3000mb_set_frontend(fe, &feps, 0);
375                         }
376                 }
377
378         } else {
379                 wr(DIB3000MB_REG_RESTART, DIB3000MB_RESTART_CTRL);
380                 wr(DIB3000MB_REG_RESTART, DIB3000MB_RESTART_OFF);
381         }
382
383         return 0;
384 }
385
386 static int dib3000mb_fe_init(struct dvb_frontend* fe, int mobile_mode)
387 {
388         struct dib3000_state* state = fe->demodulator_priv;
389
390         deb_info("dib3000mb is getting up.\n");
391         wr(DIB3000MB_REG_POWER_CONTROL, DIB3000MB_POWER_UP);
392
393         wr(DIB3000MB_REG_RESTART, DIB3000MB_RESTART_AGC);
394
395         wr(DIB3000MB_REG_RESET_DEVICE, DIB3000MB_RESET_DEVICE);
396         wr(DIB3000MB_REG_RESET_DEVICE, DIB3000MB_RESET_DEVICE_RST);
397
398         wr(DIB3000MB_REG_CLOCK, DIB3000MB_CLOCK_DEFAULT);
399
400         wr(DIB3000MB_REG_ELECT_OUT_MODE, DIB3000MB_ELECT_OUT_MODE_ON);
401
402         wr(DIB3000MB_REG_DDS_FREQ_MSB, DIB3000MB_DDS_FREQ_MSB);
403         wr(DIB3000MB_REG_DDS_FREQ_LSB, DIB3000MB_DDS_FREQ_LSB);
404
405         wr_foreach(dib3000mb_reg_timing_freq, dib3000mb_timing_freq[2]);
406
407         wr_foreach(dib3000mb_reg_impulse_noise,
408                         dib3000mb_impulse_noise_values[DIB3000MB_IMPNOISE_OFF]);
409
410         wr_foreach(dib3000mb_reg_agc_gain, dib3000mb_default_agc_gain);
411
412         wr(DIB3000MB_REG_PHASE_NOISE, DIB3000MB_PHASE_NOISE_DEFAULT);
413
414         wr_foreach(dib3000mb_reg_phase_noise, dib3000mb_default_noise_phase);
415
416         wr_foreach(dib3000mb_reg_lock_duration, dib3000mb_default_lock_duration);
417
418         wr_foreach(dib3000mb_reg_agc_bandwidth, dib3000mb_agc_bandwidth_low);
419
420         wr(DIB3000MB_REG_LOCK0_MASK, DIB3000MB_LOCK0_DEFAULT);
421         wr(DIB3000MB_REG_LOCK1_MASK, DIB3000MB_LOCK1_SEARCH_4);
422         wr(DIB3000MB_REG_LOCK2_MASK, DIB3000MB_LOCK2_DEFAULT);
423         wr(DIB3000MB_REG_SEQ, dib3000_seq[1][1][1]);
424
425         wr_foreach(dib3000mb_reg_bandwidth, dib3000mb_bandwidth_8mhz);
426
427         wr(DIB3000MB_REG_UNK_68, DIB3000MB_UNK_68);
428         wr(DIB3000MB_REG_UNK_69, DIB3000MB_UNK_69);
429         wr(DIB3000MB_REG_UNK_71, DIB3000MB_UNK_71);
430         wr(DIB3000MB_REG_UNK_77, DIB3000MB_UNK_77);
431         wr(DIB3000MB_REG_UNK_78, DIB3000MB_UNK_78);
432         wr(DIB3000MB_REG_ISI, DIB3000MB_ISI_INHIBIT);
433         wr(DIB3000MB_REG_UNK_92, DIB3000MB_UNK_92);
434         wr(DIB3000MB_REG_UNK_96, DIB3000MB_UNK_96);
435         wr(DIB3000MB_REG_UNK_97, DIB3000MB_UNK_97);
436         wr(DIB3000MB_REG_UNK_106, DIB3000MB_UNK_106);
437         wr(DIB3000MB_REG_UNK_107, DIB3000MB_UNK_107);
438         wr(DIB3000MB_REG_UNK_108, DIB3000MB_UNK_108);
439         wr(DIB3000MB_REG_UNK_122, DIB3000MB_UNK_122);
440         wr(DIB3000MB_REG_MOBILE_MODE_QAM, DIB3000MB_MOBILE_MODE_QAM_OFF);
441         wr(DIB3000MB_REG_BERLEN, DIB3000MB_BERLEN_DEFAULT);
442
443         wr_foreach(dib3000mb_reg_filter_coeffs, dib3000mb_filter_coeffs);
444
445         wr(DIB3000MB_REG_MOBILE_ALGO, DIB3000MB_MOBILE_ALGO_ON);
446         wr(DIB3000MB_REG_MULTI_DEMOD_MSB, DIB3000MB_MULTI_DEMOD_MSB);
447         wr(DIB3000MB_REG_MULTI_DEMOD_LSB, DIB3000MB_MULTI_DEMOD_LSB);
448
449         wr(DIB3000MB_REG_OUTPUT_MODE, DIB3000MB_OUTPUT_MODE_SLAVE);
450
451         wr(DIB3000MB_REG_FIFO_142, DIB3000MB_FIFO_142);
452         wr(DIB3000MB_REG_MPEG2_OUT_MODE, DIB3000MB_MPEG2_OUT_MODE_188);
453         wr(DIB3000MB_REG_PID_PARSE, DIB3000MB_PID_PARSE_ACTIVATE);
454         wr(DIB3000MB_REG_FIFO, DIB3000MB_FIFO_INHIBIT);
455         wr(DIB3000MB_REG_FIFO_146, DIB3000MB_FIFO_146);
456         wr(DIB3000MB_REG_FIFO_147, DIB3000MB_FIFO_147);
457
458         wr(DIB3000MB_REG_DATA_IN_DIVERSITY, DIB3000MB_DATA_DIVERSITY_IN_OFF);
459
460         return 0;
461 }
462
463 static int dib3000mb_get_frontend(struct dvb_frontend* fe,
464                                   struct dvb_frontend_parameters *fep)
465 {
466         struct dib3000_state* state = fe->demodulator_priv;
467         struct dvb_ofdm_parameters *ofdm = &fep->u.ofdm;
468         fe_code_rate_t *cr;
469         u16 tps_val;
470         int inv_test1,inv_test2;
471         u32 dds_val, threshold = 0x800000;
472
473         if (!rd(DIB3000MB_REG_TPS_LOCK))
474                 return 0;
475
476         dds_val = ((rd(DIB3000MB_REG_DDS_VALUE_MSB) & 0xff) << 16) + rd(DIB3000MB_REG_DDS_VALUE_LSB);
477         deb_getf("DDS_VAL: %x %x %x",dds_val, rd(DIB3000MB_REG_DDS_VALUE_MSB), rd(DIB3000MB_REG_DDS_VALUE_LSB));
478         if (dds_val < threshold)
479                 inv_test1 = 0;
480         else if (dds_val == threshold)
481                 inv_test1 = 1;
482         else
483                 inv_test1 = 2;
484
485         dds_val = ((rd(DIB3000MB_REG_DDS_FREQ_MSB) & 0xff) << 16) + rd(DIB3000MB_REG_DDS_FREQ_LSB);
486         deb_getf("DDS_FREQ: %x %x %x",dds_val, rd(DIB3000MB_REG_DDS_FREQ_MSB), rd(DIB3000MB_REG_DDS_FREQ_LSB));
487         if (dds_val < threshold)
488                 inv_test2 = 0;
489         else if (dds_val == threshold)
490                 inv_test2 = 1;
491         else
492                 inv_test2 = 2;
493
494         fep->inversion =
495                 ((inv_test2 == 2) && (inv_test1==1 || inv_test1==0)) ||
496                 ((inv_test2 == 0) && (inv_test1==1 || inv_test1==2)) ?
497                 INVERSION_ON : INVERSION_OFF;
498
499         deb_getf("inversion %d %d, %d\n", inv_test2, inv_test1, fep->inversion);
500
501         switch ((tps_val = rd(DIB3000MB_REG_TPS_QAM))) {
502                 case DIB3000_CONSTELLATION_QPSK:
503                         deb_getf("QPSK ");
504                         ofdm->constellation = QPSK;
505                         break;
506                 case DIB3000_CONSTELLATION_16QAM:
507                         deb_getf("QAM16 ");
508                         ofdm->constellation = QAM_16;
509                         break;
510                 case DIB3000_CONSTELLATION_64QAM:
511                         deb_getf("QAM64 ");
512                         ofdm->constellation = QAM_64;
513                         break;
514                 default:
515                         err("Unexpected constellation returned by TPS (%d)", tps_val);
516                         break;
517         }
518         deb_getf("TPS: %d\n", tps_val);
519
520         if (rd(DIB3000MB_REG_TPS_HRCH)) {
521                 deb_getf("HRCH ON\n");
522                 cr = &ofdm->code_rate_LP;
523                 ofdm->code_rate_HP = FEC_NONE;
524                 switch ((tps_val = rd(DIB3000MB_REG_TPS_VIT_ALPHA))) {
525                         case DIB3000_ALPHA_0:
526                                 deb_getf("HIERARCHY_NONE ");
527                                 ofdm->hierarchy_information = HIERARCHY_NONE;
528                                 break;
529                         case DIB3000_ALPHA_1:
530                                 deb_getf("HIERARCHY_1 ");
531                                 ofdm->hierarchy_information = HIERARCHY_1;
532                                 break;
533                         case DIB3000_ALPHA_2:
534                                 deb_getf("HIERARCHY_2 ");
535                                 ofdm->hierarchy_information = HIERARCHY_2;
536                                 break;
537                         case DIB3000_ALPHA_4:
538                                 deb_getf("HIERARCHY_4 ");
539                                 ofdm->hierarchy_information = HIERARCHY_4;
540                                 break;
541                         default:
542                                 err("Unexpected ALPHA value returned by TPS (%d)", tps_val);
543                                 break;
544                 }
545                 deb_getf("TPS: %d\n", tps_val);
546
547                 tps_val = rd(DIB3000MB_REG_TPS_CODE_RATE_LP);
548         } else {
549                 deb_getf("HRCH OFF\n");
550                 cr = &ofdm->code_rate_HP;
551                 ofdm->code_rate_LP = FEC_NONE;
552                 ofdm->hierarchy_information = HIERARCHY_NONE;
553
554                 tps_val = rd(DIB3000MB_REG_TPS_CODE_RATE_HP);
555         }
556
557         switch (tps_val) {
558                 case DIB3000_FEC_1_2:
559                         deb_getf("FEC_1_2 ");
560                         *cr = FEC_1_2;
561                         break;
562                 case DIB3000_FEC_2_3:
563                         deb_getf("FEC_2_3 ");
564                         *cr = FEC_2_3;
565                         break;
566                 case DIB3000_FEC_3_4:
567                         deb_getf("FEC_3_4 ");
568                         *cr = FEC_3_4;
569                         break;
570                 case DIB3000_FEC_5_6:
571                         deb_getf("FEC_5_6 ");
572                         *cr = FEC_4_5;
573                         break;
574                 case DIB3000_FEC_7_8:
575                         deb_getf("FEC_7_8 ");
576                         *cr = FEC_7_8;
577                         break;
578                 default:
579                         err("Unexpected FEC returned by TPS (%d)", tps_val);
580                         break;
581         }
582         deb_getf("TPS: %d\n",tps_val);
583
584         switch ((tps_val = rd(DIB3000MB_REG_TPS_GUARD_TIME))) {
585                 case DIB3000_GUARD_TIME_1_32:
586                         deb_getf("GUARD_INTERVAL_1_32 ");
587                         ofdm->guard_interval = GUARD_INTERVAL_1_32;
588                         break;
589                 case DIB3000_GUARD_TIME_1_16:
590                         deb_getf("GUARD_INTERVAL_1_16 ");
591                         ofdm->guard_interval = GUARD_INTERVAL_1_16;
592                         break;
593                 case DIB3000_GUARD_TIME_1_8:
594                         deb_getf("GUARD_INTERVAL_1_8 ");
595                         ofdm->guard_interval = GUARD_INTERVAL_1_8;
596                         break;
597                 case DIB3000_GUARD_TIME_1_4:
598                         deb_getf("GUARD_INTERVAL_1_4 ");
599                         ofdm->guard_interval = GUARD_INTERVAL_1_4;
600                         break;
601                 default:
602                         err("Unexpected Guard Time returned by TPS (%d)", tps_val);
603                         break;
604         }
605         deb_getf("TPS: %d\n", tps_val);
606
607         switch ((tps_val = rd(DIB3000MB_REG_TPS_FFT))) {
608                 case DIB3000_TRANSMISSION_MODE_2K:
609                         deb_getf("TRANSMISSION_MODE_2K ");
610                         ofdm->transmission_mode = TRANSMISSION_MODE_2K;
611                         break;
612                 case DIB3000_TRANSMISSION_MODE_8K:
613                         deb_getf("TRANSMISSION_MODE_8K ");
614                         ofdm->transmission_mode = TRANSMISSION_MODE_8K;
615                         break;
616                 default:
617                         err("unexpected transmission mode return by TPS (%d)", tps_val);
618                         break;
619         }
620         deb_getf("TPS: %d\n", tps_val);
621
622         return 0;
623 }
624
625 static int dib3000mb_read_status(struct dvb_frontend* fe, fe_status_t *stat)
626 {
627         struct dib3000_state* state = fe->demodulator_priv;
628
629         *stat = 0;
630
631         if (rd(DIB3000MB_REG_AGC_LOCK))
632                 *stat |= FE_HAS_SIGNAL;
633         if (rd(DIB3000MB_REG_CARRIER_LOCK))
634                 *stat |= FE_HAS_CARRIER;
635         if (rd(DIB3000MB_REG_VIT_LCK))
636                 *stat |= FE_HAS_VITERBI;
637         if (rd(DIB3000MB_REG_TS_SYNC_LOCK))
638                 *stat |= (FE_HAS_SYNC | FE_HAS_LOCK);
639
640         deb_getf("actual status is %2x\n",*stat);
641
642         deb_getf("autoval: tps: %d, qam: %d, hrch: %d, alpha: %d, hp: %d, lp: %d, guard: %d, fft: %d cell: %d\n",
643                         rd(DIB3000MB_REG_TPS_LOCK),
644                         rd(DIB3000MB_REG_TPS_QAM),
645                         rd(DIB3000MB_REG_TPS_HRCH),
646                         rd(DIB3000MB_REG_TPS_VIT_ALPHA),
647                         rd(DIB3000MB_REG_TPS_CODE_RATE_HP),
648                         rd(DIB3000MB_REG_TPS_CODE_RATE_LP),
649                         rd(DIB3000MB_REG_TPS_GUARD_TIME),
650                         rd(DIB3000MB_REG_TPS_FFT),
651                         rd(DIB3000MB_REG_TPS_CELL_ID));
652
653         //*stat = FE_HAS_SIGNAL | FE_HAS_CARRIER | FE_HAS_VITERBI | FE_HAS_SYNC | FE_HAS_LOCK;
654         return 0;
655 }
656
657 static int dib3000mb_read_ber(struct dvb_frontend* fe, u32 *ber)
658 {
659         struct dib3000_state* state = fe->demodulator_priv;
660
661         *ber = ((rd(DIB3000MB_REG_BER_MSB) << 16) | rd(DIB3000MB_REG_BER_LSB));
662         return 0;
663 }
664
665 /* see dib3000-watch dvb-apps for exact calcuations of signal_strength and snr */
666 static int dib3000mb_read_signal_strength(struct dvb_frontend* fe, u16 *strength)
667 {
668         struct dib3000_state* state = fe->demodulator_priv;
669
670         *strength = rd(DIB3000MB_REG_SIGNAL_POWER) * 0xffff / 0x170;
671         return 0;
672 }
673
674 static int dib3000mb_read_snr(struct dvb_frontend* fe, u16 *snr)
675 {
676         struct dib3000_state* state = fe->demodulator_priv;
677         short sigpow = rd(DIB3000MB_REG_SIGNAL_POWER);
678         int icipow = ((rd(DIB3000MB_REG_NOISE_POWER_MSB) & 0xff) << 16) |
679                 rd(DIB3000MB_REG_NOISE_POWER_LSB);
680         *snr = (sigpow << 8) / ((icipow > 0) ? icipow : 1);
681         return 0;
682 }
683
684 static int dib3000mb_read_unc_blocks(struct dvb_frontend* fe, u32 *unc)
685 {
686         struct dib3000_state* state = fe->demodulator_priv;
687
688         *unc = rd(DIB3000MB_REG_PACKET_ERROR_RATE);
689         return 0;
690 }
691
692 static int dib3000mb_sleep(struct dvb_frontend* fe)
693 {
694         struct dib3000_state* state = fe->demodulator_priv;
695         deb_info("dib3000mb is going to bed.\n");
696         wr(DIB3000MB_REG_POWER_CONTROL, DIB3000MB_POWER_DOWN);
697         return 0;
698 }
699
700 static int dib3000mb_fe_get_tune_settings(struct dvb_frontend* fe, struct dvb_frontend_tune_settings *tune)
701 {
702         tune->min_delay_ms = 800;
703         return 0;
704 }
705
706 static int dib3000mb_fe_init_nonmobile(struct dvb_frontend* fe)
707 {
708         return dib3000mb_fe_init(fe, 0);
709 }
710
711 static int dib3000mb_set_frontend_and_tuner(struct dvb_frontend* fe, struct dvb_frontend_parameters *fep)
712 {
713         return dib3000mb_set_frontend(fe, fep, 1);
714 }
715
716 static void dib3000mb_release(struct dvb_frontend* fe)
717 {
718         struct dib3000_state *state = fe->demodulator_priv;
719         kfree(state);
720 }
721
722 /* pid filter and transfer stuff */
723 static int dib3000mb_pid_control(struct dvb_frontend *fe,int index, int pid,int onoff)
724 {
725         struct dib3000_state *state = fe->demodulator_priv;
726         pid = (onoff ? pid | DIB3000_ACTIVATE_PID_FILTERING : 0);
727         wr(index+DIB3000MB_REG_FIRST_PID,pid);
728         return 0;
729 }
730
731 static int dib3000mb_fifo_control(struct dvb_frontend *fe, int onoff)
732 {
733         struct dib3000_state *state = fe->demodulator_priv;
734
735         deb_xfer("%s fifo\n",onoff ? "enabling" : "disabling");
736         if (onoff) {
737                 wr(DIB3000MB_REG_FIFO, DIB3000MB_FIFO_ACTIVATE);
738         } else {
739                 wr(DIB3000MB_REG_FIFO, DIB3000MB_FIFO_INHIBIT);
740         }
741         return 0;
742 }
743
744 static int dib3000mb_pid_parse(struct dvb_frontend *fe, int onoff)
745 {
746         struct dib3000_state *state = fe->demodulator_priv;
747         deb_xfer("%s pid parsing\n",onoff ? "enabling" : "disabling");
748         wr(DIB3000MB_REG_PID_PARSE,onoff);
749         return 0;
750 }
751
752 static int dib3000mb_tuner_pass_ctrl(struct dvb_frontend *fe, int onoff, u8 pll_addr)
753 {
754         struct dib3000_state *state = fe->demodulator_priv;
755         if (onoff) {
756                 wr(DIB3000MB_REG_TUNER, DIB3000_TUNER_WRITE_ENABLE(pll_addr));
757         } else {
758                 wr(DIB3000MB_REG_TUNER, DIB3000_TUNER_WRITE_DISABLE(pll_addr));
759         }
760         return 0;
761 }
762
763 static struct dvb_frontend_ops dib3000mb_ops;
764
765 struct dvb_frontend* dib3000mb_attach(const struct dib3000_config* config,
766                                       struct i2c_adapter* i2c, struct dib_fe_xfer_ops *xfer_ops)
767 {
768         struct dib3000_state* state = NULL;
769
770         /* allocate memory for the internal state */
771         state = kzalloc(sizeof(struct dib3000_state), GFP_KERNEL);
772         if (state == NULL)
773                 goto error;
774
775         /* setup the state */
776         state->i2c = i2c;
777         memcpy(&state->config,config,sizeof(struct dib3000_config));
778
779         /* check for the correct demod */
780         if (rd(DIB3000_REG_MANUFACTOR_ID) != DIB3000_I2C_ID_DIBCOM)
781                 goto error;
782
783         if (rd(DIB3000_REG_DEVICE_ID) != DIB3000MB_DEVICE_ID)
784                 goto error;
785
786         /* create dvb_frontend */
787         memcpy(&state->frontend.ops, &dib3000mb_ops, sizeof(struct dvb_frontend_ops));
788         state->frontend.demodulator_priv = state;
789
790         /* set the xfer operations */
791         xfer_ops->pid_parse = dib3000mb_pid_parse;
792         xfer_ops->fifo_ctrl = dib3000mb_fifo_control;
793         xfer_ops->pid_ctrl = dib3000mb_pid_control;
794         xfer_ops->tuner_pass_ctrl = dib3000mb_tuner_pass_ctrl;
795
796         return &state->frontend;
797
798 error:
799         kfree(state);
800         return NULL;
801 }
802
803 static struct dvb_frontend_ops dib3000mb_ops = {
804
805         .info = {
806                 .name                   = "DiBcom 3000M-B DVB-T",
807                 .type                   = FE_OFDM,
808                 .frequency_min          = 44250000,
809                 .frequency_max          = 867250000,
810                 .frequency_stepsize     = 62500,
811                 .caps = FE_CAN_INVERSION_AUTO |
812                                 FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
813                                 FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
814                                 FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 | FE_CAN_QAM_AUTO |
815                                 FE_CAN_TRANSMISSION_MODE_AUTO |
816                                 FE_CAN_GUARD_INTERVAL_AUTO |
817                                 FE_CAN_RECOVER |
818                                 FE_CAN_HIERARCHY_AUTO,
819         },
820
821         .release = dib3000mb_release,
822
823         .init = dib3000mb_fe_init_nonmobile,
824         .sleep = dib3000mb_sleep,
825
826         .set_frontend = dib3000mb_set_frontend_and_tuner,
827         .get_frontend = dib3000mb_get_frontend,
828         .get_tune_settings = dib3000mb_fe_get_tune_settings,
829
830         .read_status = dib3000mb_read_status,
831         .read_ber = dib3000mb_read_ber,
832         .read_signal_strength = dib3000mb_read_signal_strength,
833         .read_snr = dib3000mb_read_snr,
834         .read_ucblocks = dib3000mb_read_unc_blocks,
835 };
836
837 MODULE_AUTHOR(DRIVER_AUTHOR);
838 MODULE_DESCRIPTION(DRIVER_DESC);
839 MODULE_LICENSE("GPL");
840
841 EXPORT_SYMBOL(dib3000mb_attach);