git.oblomov.eu Git - linux-2.6/blob - sound/pci/cs46xx/cs46xx_lib.c

   1 /*
   2  *  Copyright (c) by Jaroslav Kysela <perex@perex.cz>
   3  *                   Abramo Bagnara <abramo@alsa-project.org>
   4  *                   Cirrus Logic, Inc.
   5  *  Routines for control of Cirrus Logic CS461x chips
   6  *
   7  *  KNOWN BUGS:
   8  *    - Sometimes the SPDIF input DSP tasks get's unsynchronized
   9  *      and the SPDIF get somewhat "distorcionated", or/and left right channel
  10  *      are swapped. To get around this problem when it happens, mute and unmute
  11  *      the SPDIF input mixer controll.
  12  *    - On the Hercules Game Theater XP the amplifier are sometimes turned
  13  *      off on inadecuate moments which causes distorcions on sound.
  14  *
  15  *  TODO:
  16  *    - Secondary CODEC on some soundcards
  17  *    - SPDIF input support for other sample rates then 48khz
  18  *    - Posibility to mix the SPDIF output with analog sources.
  19  *    - PCM channels for Center and LFE on secondary codec
  20  *
  21  *  NOTE: with CONFIG_SND_CS46XX_NEW_DSP unset uses old DSP image (which
  22  *        is default configuration), no SPDIF, no secondary codec, no
  23  *        multi channel PCM.  But known to work.
  24  *
  25  *  FINALLY: A credit to the developers Tom and Jordan
  26  *           at Cirrus for have helping me out with the DSP, however we
  27  *           still don't have sufficient documentation and technical
  28  *           references to be able to implement all fancy feutures
  29  *           supported by the cs46xx DSP's.
  30  *           Benny <benny@hostmobility.com>
  31  *
  32  *   This program is free software; you can redistribute it and/or modify
  33  *   it under the terms of the GNU General Public License as published by
  34  *   the Free Software Foundation; either version 2 of the License, or
  35  *   (at your option) any later version.
  36  *
  37  *   This program is distributed in the hope that it will be useful,
  38  *   but WITHOUT ANY WARRANTY; without even the implied warranty of
  39  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  40  *   GNU General Public License for more details.
  41  *
  42  *   You should have received a copy of the GNU General Public License
  43  *   along with this program; if not, write to the Free Software
  44  *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
  45  *
  46  */
  47
  48 #include <sound/driver.h>
  49 #include <linux/delay.h>
  50 #include <linux/pci.h>
  51 #include <linux/pm.h>
  52 #include <linux/init.h>
  53 #include <linux/interrupt.h>
  54 #include <linux/slab.h>
  55 #include <linux/gameport.h>
  56 #include <linux/mutex.h>
  57
  58
  59 #include <sound/core.h>
  60 #include <sound/control.h>
  61 #include <sound/info.h>
  62 #include <sound/pcm.h>
  63 #include <sound/pcm_params.h>
  64 #include <sound/cs46xx.h>
  65
  66 #include <asm/io.h>
  67
  68 #include "cs46xx_lib.h"
  69 #include "dsp_spos.h"
  70
  71 static void amp_voyetra(struct snd_cs46xx *chip, int change);
  72
  73 #ifdef CONFIG_SND_CS46XX_NEW_DSP
  74 static struct snd_pcm_ops snd_cs46xx_playback_rear_ops;
  75 static struct snd_pcm_ops snd_cs46xx_playback_indirect_rear_ops;
  76 static struct snd_pcm_ops snd_cs46xx_playback_clfe_ops;
  77 static struct snd_pcm_ops snd_cs46xx_playback_indirect_clfe_ops;
  78 static struct snd_pcm_ops snd_cs46xx_playback_iec958_ops;
  79 static struct snd_pcm_ops snd_cs46xx_playback_indirect_iec958_ops;
  80 #endif
  81
  82 static struct snd_pcm_ops snd_cs46xx_playback_ops;
  83 static struct snd_pcm_ops snd_cs46xx_playback_indirect_ops;
  84 static struct snd_pcm_ops snd_cs46xx_capture_ops;
  85 static struct snd_pcm_ops snd_cs46xx_capture_indirect_ops;
  86
  87 static unsigned short snd_cs46xx_codec_read(struct snd_cs46xx *chip,
  88                                             unsigned short reg,
  89                                             int codec_index)
  90 {
  91         int count;
  92         unsigned short result,tmp;
  93         u32 offset = 0;
  94         snd_assert ( (codec_index == CS46XX_PRIMARY_CODEC_INDEX) ||
  95                      (codec_index == CS46XX_SECONDARY_CODEC_INDEX),
  96                      return -EINVAL);
  97
  98         chip->active_ctrl(chip, 1);
  99
 100         if (codec_index == CS46XX_SECONDARY_CODEC_INDEX)
 101                 offset = CS46XX_SECONDARY_CODEC_OFFSET;
 102
 103         /*
 104          *  1. Write ACCAD = Command Address Register = 46Ch for AC97 register address
 105          *  2. Write ACCDA = Command Data Register = 470h    for data to write to AC97
 106          *  3. Write ACCTL = Control Register = 460h for initiating the write7---55
 107          *  4. Read ACCTL = 460h, DCV should be reset by now and 460h = 17h
 108          *  5. if DCV not cleared, break and return error
 109          *  6. Read ACSTS = Status Register = 464h, check VSTS bit
 110          */
 111
 112         snd_cs46xx_peekBA0(chip, BA0_ACSDA + offset);
 113
 114         tmp = snd_cs46xx_peekBA0(chip, BA0_ACCTL);
 115         if ((tmp & ACCTL_VFRM) == 0) {
 116                 snd_printk(KERN_WARNING  "cs46xx: ACCTL_VFRM not set 0x%x\n",tmp);
 117                 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, (tmp & (~ACCTL_ESYN)) | ACCTL_VFRM );
 118                 msleep(50);
 119                 tmp = snd_cs46xx_peekBA0(chip, BA0_ACCTL + offset);
 120                 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, tmp | ACCTL_ESYN | ACCTL_VFRM );
 121
 122         }
 123
 124         /*
 125          *  Setup the AC97 control registers on the CS461x to send the
 126          *  appropriate command to the AC97 to perform the read.
 127          *  ACCAD = Command Address Register = 46Ch
 128          *  ACCDA = Command Data Register = 470h
 129          *  ACCTL = Control Register = 460h
 130          *  set DCV - will clear when process completed
 131          *  set CRW - Read command
 132          *  set VFRM - valid frame enabled
 133          *  set ESYN - ASYNC generation enabled
 134          *  set RSTN - ARST# inactive, AC97 codec not reset
 135          */
 136
 137         snd_cs46xx_pokeBA0(chip, BA0_ACCAD, reg);
 138         snd_cs46xx_pokeBA0(chip, BA0_ACCDA, 0);
 139         if (codec_index == CS46XX_PRIMARY_CODEC_INDEX) {
 140                 snd_cs46xx_pokeBA0(chip, BA0_ACCTL,/* clear ACCTL_DCV */ ACCTL_CRW |
 141                                    ACCTL_VFRM | ACCTL_ESYN |
 142                                    ACCTL_RSTN);
 143                 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_DCV | ACCTL_CRW |
 144                                    ACCTL_VFRM | ACCTL_ESYN |
 145                                    ACCTL_RSTN);
 146         } else {
 147                 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_DCV | ACCTL_TC |
 148                                    ACCTL_CRW | ACCTL_VFRM | ACCTL_ESYN |
 149                                    ACCTL_RSTN);
 150         }
 151
 152         /*
 153          *  Wait for the read to occur.
 154          */
 155         for (count = 0; count < 1000; count++) {
 156                 /*
 157                  *  First, we want to wait for a short time.
 158                  */
 159                 udelay(10);
 160                 /*
 161                  *  Now, check to see if the read has completed.
 162                  *  ACCTL = 460h, DCV should be reset by now and 460h = 17h
 163                  */
 164                 if (!(snd_cs46xx_peekBA0(chip, BA0_ACCTL) & ACCTL_DCV))
 165                         goto ok1;
 166         }
 167
 168         snd_printk(KERN_ERR "AC'97 read problem (ACCTL_DCV), reg = 0x%x\n", reg);
 169         result = 0xffff;
 170         goto end;
 171
 172  ok1:
 173         /*
 174          *  Wait for the valid status bit to go active.
 175          */
 176         for (count = 0; count < 100; count++) {
 177                 /*
 178                  *  Read the AC97 status register.
 179                  *  ACSTS = Status Register = 464h
 180                  *  VSTS - Valid Status
 181                  */
 182                 if (snd_cs46xx_peekBA0(chip, BA0_ACSTS + offset) & ACSTS_VSTS)
 183                         goto ok2;
 184                 udelay(10);
 185         }
 186
 187         snd_printk(KERN_ERR "AC'97 read problem (ACSTS_VSTS), codec_index %d, reg = 0x%x\n", codec_index, reg);
 188         result = 0xffff;
 189         goto end;
 190
 191  ok2:
 192         /*
 193          *  Read the data returned from the AC97 register.
 194          *  ACSDA = Status Data Register = 474h
 195          */
 196 #if 0
 197         printk("e) reg = 0x%x, val = 0x%x, BA0_ACCAD = 0x%x\n", reg,
 198                         snd_cs46xx_peekBA0(chip, BA0_ACSDA),
 199                         snd_cs46xx_peekBA0(chip, BA0_ACCAD));
 200 #endif
 201
 202         //snd_cs46xx_peekBA0(chip, BA0_ACCAD);
 203         result = snd_cs46xx_peekBA0(chip, BA0_ACSDA + offset);
 204  end:
 205         chip->active_ctrl(chip, -1);
 206         return result;
 207 }
 208
 209 static unsigned short snd_cs46xx_ac97_read(struct snd_ac97 * ac97,
 210                                             unsigned short reg)
 211 {
 212         struct snd_cs46xx *chip = ac97->private_data;
 213         unsigned short val;
 214         int codec_index = ac97->num;
 215
 216         snd_assert(codec_index == CS46XX_PRIMARY_CODEC_INDEX ||
 217                    codec_index == CS46XX_SECONDARY_CODEC_INDEX,
 218                    return 0xffff);
 219
 220         val = snd_cs46xx_codec_read(chip, reg, codec_index);
 221
 222         return val;
 223 }
 224
 225
 226 static void snd_cs46xx_codec_write(struct snd_cs46xx *chip,
 227                                    unsigned short reg,
 228                                    unsigned short val,
 229                                    int codec_index)
 230 {
 231         int count;
 232
 233         snd_assert ((codec_index == CS46XX_PRIMARY_CODEC_INDEX) ||
 234                     (codec_index == CS46XX_SECONDARY_CODEC_INDEX),
 235                     return);
 236
 237         chip->active_ctrl(chip, 1);
 238
 239         /*
 240          *  1. Write ACCAD = Command Address Register = 46Ch for AC97 register address
 241          *  2. Write ACCDA = Command Data Register = 470h    for data to write to AC97
 242          *  3. Write ACCTL = Control Register = 460h for initiating the write
 243          *  4. Read ACCTL = 460h, DCV should be reset by now and 460h = 07h
 244          *  5. if DCV not cleared, break and return error
 245          */
 246
 247         /*
 248          *  Setup the AC97 control registers on the CS461x to send the
 249          *  appropriate command to the AC97 to perform the read.
 250          *  ACCAD = Command Address Register = 46Ch
 251          *  ACCDA = Command Data Register = 470h
 252          *  ACCTL = Control Register = 460h
 253          *  set DCV - will clear when process completed
 254          *  reset CRW - Write command
 255          *  set VFRM - valid frame enabled
 256          *  set ESYN - ASYNC generation enabled
 257          *  set RSTN - ARST# inactive, AC97 codec not reset
 258          */
 259         snd_cs46xx_pokeBA0(chip, BA0_ACCAD , reg);
 260         snd_cs46xx_pokeBA0(chip, BA0_ACCDA , val);
 261         snd_cs46xx_peekBA0(chip, BA0_ACCTL);
 262
 263         if (codec_index == CS46XX_PRIMARY_CODEC_INDEX) {
 264                 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, /* clear ACCTL_DCV */ ACCTL_VFRM |
 265                                    ACCTL_ESYN | ACCTL_RSTN);
 266                 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_DCV | ACCTL_VFRM |
 267                                    ACCTL_ESYN | ACCTL_RSTN);
 268         } else {
 269                 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_DCV | ACCTL_TC |
 270                                    ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN);
 271         }
 272
 273         for (count = 0; count < 4000; count++) {
 274                 /*
 275                  *  First, we want to wait for a short time.
 276                  */
 277                 udelay(10);
 278                 /*
 279                  *  Now, check to see if the write has completed.
 280                  *  ACCTL = 460h, DCV should be reset by now and 460h = 07h
 281                  */
 282                 if (!(snd_cs46xx_peekBA0(chip, BA0_ACCTL) & ACCTL_DCV)) {
 283                         goto end;
 284                 }
 285         }
 286         snd_printk(KERN_ERR "AC'97 write problem, codec_index = %d, reg = 0x%x, val = 0x%x\n", codec_index, reg, val);
 287  end:
 288         chip->active_ctrl(chip, -1);
 289 }
 290
 291 static void snd_cs46xx_ac97_write(struct snd_ac97 *ac97,
 292                                    unsigned short reg,
 293                                    unsigned short val)
 294 {
 295         struct snd_cs46xx *chip = ac97->private_data;
 296         int codec_index = ac97->num;
 297
 298         snd_assert(codec_index == CS46XX_PRIMARY_CODEC_INDEX ||
 299                    codec_index == CS46XX_SECONDARY_CODEC_INDEX,
 300                    return);
 301
 302         snd_cs46xx_codec_write(chip, reg, val, codec_index);
 303 }
 304
 305
 306 /*
 307  *  Chip initialization
 308  */
 309
 310 int snd_cs46xx_download(struct snd_cs46xx *chip,
 311                         u32 *src,
 312                         unsigned long offset,
 313                         unsigned long len)
 314 {
 315         void __iomem *dst;
 316         unsigned int bank = offset >> 16;
 317         offset = offset & 0xffff;
 318
 319         snd_assert(!(offset & 3) && !(len & 3), return -EINVAL);
 320         dst = chip->region.idx[bank+1].remap_addr + offset;
 321         len /= sizeof(u32);
 322
 323         /* writel already converts 32-bit value to right endianess */
 324         while (len-- > 0) {
 325                 writel(*src++, dst);
 326                 dst += sizeof(u32);
 327         }
 328         return 0;
 329 }
 330
 331 #ifdef CONFIG_SND_CS46XX_NEW_DSP
 332
 333 #include "imgs/cwc4630.h"
 334 #include "imgs/cwcasync.h"
 335 #include "imgs/cwcsnoop.h"
 336 #include "imgs/cwcbinhack.h"
 337 #include "imgs/cwcdma.h"
 338
 339 int snd_cs46xx_clear_BA1(struct snd_cs46xx *chip,
 340                          unsigned long offset,
 341                          unsigned long len)
 342 {
 343         void __iomem *dst;
 344         unsigned int bank = offset >> 16;
 345         offset = offset & 0xffff;
 346
 347         snd_assert(!(offset & 3) && !(len & 3), return -EINVAL);
 348         dst = chip->region.idx[bank+1].remap_addr + offset;
 349         len /= sizeof(u32);
 350
 351         /* writel already converts 32-bit value to right endianess */
 352         while (len-- > 0) {
 353                 writel(0, dst);
 354                 dst += sizeof(u32);
 355         }
 356         return 0;
 357 }
 358
 359 #else /* old DSP image */
 360
 361 #include "cs46xx_image.h"
 362
 363 int snd_cs46xx_download_image(struct snd_cs46xx *chip)
 364 {
 365         int idx, err;
 366         unsigned long offset = 0;
 367
 368         for (idx = 0; idx < BA1_MEMORY_COUNT; idx++) {
 369                 if ((err = snd_cs46xx_download(chip,
 370                                                &BA1Struct.map[offset],
 371                                                BA1Struct.memory[idx].offset,
 372                                                BA1Struct.memory[idx].size)) < 0)
 373                         return err;
 374                 offset += BA1Struct.memory[idx].size >> 2;
 375         }
 376         return 0;
 377 }
 378 #endif /* CONFIG_SND_CS46XX_NEW_DSP */
 379
 380 /*
 381  *  Chip reset
 382  */
 383
 384 static void snd_cs46xx_reset(struct snd_cs46xx *chip)
 385 {
 386         int idx;
 387
 388         /*
 389          *  Write the reset bit of the SP control register.
 390          */
 391         snd_cs46xx_poke(chip, BA1_SPCR, SPCR_RSTSP);
 392
 393         /*
 394          *  Write the control register.
 395          */
 396         snd_cs46xx_poke(chip, BA1_SPCR, SPCR_DRQEN);
 397
 398         /*
 399          *  Clear the trap registers.
 400          */
 401         for (idx = 0; idx < 8; idx++) {
 402                 snd_cs46xx_poke(chip, BA1_DREG, DREG_REGID_TRAP_SELECT + idx);
 403                 snd_cs46xx_poke(chip, BA1_TWPR, 0xFFFF);
 404         }
 405         snd_cs46xx_poke(chip, BA1_DREG, 0);
 406
 407         /*
 408          *  Set the frame timer to reflect the number of cycles per frame.
 409          */
 410         snd_cs46xx_poke(chip, BA1_FRMT, 0xadf);
 411 }
 412
 413 static int cs46xx_wait_for_fifo(struct snd_cs46xx * chip,int retry_timeout)
 414 {
 415         u32 i, status = 0;
 416         /*
 417          * Make sure the previous FIFO write operation has completed.
 418          */
 419         for(i = 0; i < 50; i++){
 420                 status = snd_cs46xx_peekBA0(chip, BA0_SERBST);
 421
 422                 if( !(status & SERBST_WBSY) )
 423                         break;
 424
 425                 mdelay(retry_timeout);
 426         }
 427
 428         if(status & SERBST_WBSY) {
 429                 snd_printk( KERN_ERR "cs46xx: failure waiting for FIFO command to complete\n");
 430
 431                 return -EINVAL;
 432         }
 433
 434         return 0;
 435 }
 436
 437 static void snd_cs46xx_clear_serial_FIFOs(struct snd_cs46xx *chip)
 438 {
 439         int idx, powerdown = 0;
 440         unsigned int tmp;
 441
 442         /*
 443          *  See if the devices are powered down.  If so, we must power them up first
 444          *  or they will not respond.
 445          */
 446         tmp = snd_cs46xx_peekBA0(chip, BA0_CLKCR1);
 447         if (!(tmp & CLKCR1_SWCE)) {
 448                 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp | CLKCR1_SWCE);
 449                 powerdown = 1;
 450         }
 451
 452         /*
 453          *  We want to clear out the serial port FIFOs so we don't end up playing
 454          *  whatever random garbage happens to be in them.  We fill the sample FIFOS
 455          *  with zero (silence).
 456          */
 457         snd_cs46xx_pokeBA0(chip, BA0_SERBWP, 0);
 458
 459         /*
 460          *  Fill all 256 sample FIFO locations.
 461          */
 462         for (idx = 0; idx < 0xFF; idx++) {
 463                 /*
 464                  *  Make sure the previous FIFO write operation has completed.
 465                  */
 466                 if (cs46xx_wait_for_fifo(chip,1)) {
 467                         snd_printdd ("failed waiting for FIFO at addr (%02X)\n",idx);
 468
 469                         if (powerdown)
 470                                 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp);
 471
 472                         break;
 473                 }
 474                 /*
 475                  *  Write the serial port FIFO index.
 476                  */
 477                 snd_cs46xx_pokeBA0(chip, BA0_SERBAD, idx);
 478                 /*
 479                  *  Tell the serial port to load the new value into the FIFO location.
 480                  */
 481                 snd_cs46xx_pokeBA0(chip, BA0_SERBCM, SERBCM_WRC);
 482         }
 483         /*
 484          *  Now, if we powered up the devices, then power them back down again.
 485          *  This is kinda ugly, but should never happen.
 486          */
 487         if (powerdown)
 488                 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp);
 489 }
 490
 491 static void snd_cs46xx_proc_start(struct snd_cs46xx *chip)
 492 {
 493         int cnt;
 494
 495         /*
 496          *  Set the frame timer to reflect the number of cycles per frame.
 497          */
 498         snd_cs46xx_poke(chip, BA1_FRMT, 0xadf);
 499         /*
 500          *  Turn on the run, run at frame, and DMA enable bits in the local copy of
 501          *  the SP control register.
 502          */
 503         snd_cs46xx_poke(chip, BA1_SPCR, SPCR_RUN | SPCR_RUNFR | SPCR_DRQEN);
 504         /*
 505          *  Wait until the run at frame bit resets itself in the SP control
 506          *  register.
 507          */
 508         for (cnt = 0; cnt < 25; cnt++) {
 509                 udelay(50);
 510                 if (!(snd_cs46xx_peek(chip, BA1_SPCR) & SPCR_RUNFR))
 511                         break;
 512         }
 513
 514         if (snd_cs46xx_peek(chip, BA1_SPCR) & SPCR_RUNFR)
 515                 snd_printk(KERN_ERR "SPCR_RUNFR never reset\n");
 516 }
 517
 518 static void snd_cs46xx_proc_stop(struct snd_cs46xx *chip)
 519 {
 520         /*
 521          *  Turn off the run, run at frame, and DMA enable bits in the local copy of
 522          *  the SP control register.
 523          */
 524         snd_cs46xx_poke(chip, BA1_SPCR, 0);
 525 }
 526
 527 /*
 528  *  Sample rate routines
 529  */
 530
 531 #define GOF_PER_SEC 200
 532
 533 static void snd_cs46xx_set_play_sample_rate(struct snd_cs46xx *chip, unsigned int rate)
 534 {
 535         unsigned long flags;
 536         unsigned int tmp1, tmp2;
 537         unsigned int phiIncr;
 538         unsigned int correctionPerGOF, correctionPerSec;
 539
 540         /*
 541          *  Compute the values used to drive the actual sample rate conversion.
 542          *  The following formulas are being computed, using inline assembly
 543          *  since we need to use 64 bit arithmetic to compute the values:
 544          *
 545          *  phiIncr = floor((Fs,in * 2^26) / Fs,out)
 546          *  correctionPerGOF = floor((Fs,in * 2^26 - Fs,out * phiIncr) /
 547          *                                   GOF_PER_SEC)
 548          *  ulCorrectionPerSec = Fs,in * 2^26 - Fs,out * phiIncr -M
 549          *                       GOF_PER_SEC * correctionPerGOF
 550          *
 551          *  i.e.
 552          *
 553          *  phiIncr:other = dividend:remainder((Fs,in * 2^26) / Fs,out)
 554          *  correctionPerGOF:correctionPerSec =
 555          *      dividend:remainder(ulOther / GOF_PER_SEC)
 556          */
 557         tmp1 = rate << 16;
 558         phiIncr = tmp1 / 48000;
 559         tmp1 -= phiIncr * 48000;
 560         tmp1 <<= 10;
 561         phiIncr <<= 10;
 562         tmp2 = tmp1 / 48000;
 563         phiIncr += tmp2;
 564         tmp1 -= tmp2 * 48000;
 565         correctionPerGOF = tmp1 / GOF_PER_SEC;
 566         tmp1 -= correctionPerGOF * GOF_PER_SEC;
 567         correctionPerSec = tmp1;
 568
 569         /*
 570          *  Fill in the SampleRateConverter control block.
 571          */
 572         spin_lock_irqsave(&chip->reg_lock, flags);
 573         snd_cs46xx_poke(chip, BA1_PSRC,
 574           ((correctionPerSec << 16) & 0xFFFF0000) | (correctionPerGOF & 0xFFFF));
 575         snd_cs46xx_poke(chip, BA1_PPI, phiIncr);
 576         spin_unlock_irqrestore(&chip->reg_lock, flags);
 577 }
 578
 579 static void snd_cs46xx_set_capture_sample_rate(struct snd_cs46xx *chip, unsigned int rate)
 580 {
 581         unsigned long flags;
 582         unsigned int phiIncr, coeffIncr, tmp1, tmp2;
 583         unsigned int correctionPerGOF, correctionPerSec, initialDelay;
 584         unsigned int frameGroupLength, cnt;
 585
 586         /*
 587          *  We can only decimate by up to a factor of 1/9th the hardware rate.
 588          *  Correct the value if an attempt is made to stray outside that limit.
 589          */
 590         if ((rate * 9) < 48000)
 591                 rate = 48000 / 9;
 592
 593         /*
 594          *  We can not capture at at rate greater than the Input Rate (48000).
 595          *  Return an error if an attempt is made to stray outside that limit.
 596          */
 597         if (rate > 48000)
 598                 rate = 48000;
 599
 600         /*
 601          *  Compute the values used to drive the actual sample rate conversion.
 602          *  The following formulas are being computed, using inline assembly
 603          *  since we need to use 64 bit arithmetic to compute the values:
 604          *
 605          *     coeffIncr = -floor((Fs,out * 2^23) / Fs,in)
 606          *     phiIncr = floor((Fs,in * 2^26) / Fs,out)
 607          *     correctionPerGOF = floor((Fs,in * 2^26 - Fs,out * phiIncr) /
 608          *                                GOF_PER_SEC)
 609          *     correctionPerSec = Fs,in * 2^26 - Fs,out * phiIncr -
 610          *                          GOF_PER_SEC * correctionPerGOF
 611          *     initialDelay = ceil((24 * Fs,in) / Fs,out)
 612          *
 613          * i.e.
 614          *
 615          *     coeffIncr = neg(dividend((Fs,out * 2^23) / Fs,in))
 616          *     phiIncr:ulOther = dividend:remainder((Fs,in * 2^26) / Fs,out)
 617          *     correctionPerGOF:correctionPerSec =
 618          *          dividend:remainder(ulOther / GOF_PER_SEC)
 619          *     initialDelay = dividend(((24 * Fs,in) + Fs,out - 1) / Fs,out)
 620          */
 621
 622         tmp1 = rate << 16;
 623         coeffIncr = tmp1 / 48000;
 624         tmp1 -= coeffIncr * 48000;
 625         tmp1 <<= 7;
 626         coeffIncr <<= 7;
 627         coeffIncr += tmp1 / 48000;
 628         coeffIncr ^= 0xFFFFFFFF;
 629         coeffIncr++;
 630         tmp1 = 48000 << 16;
 631         phiIncr = tmp1 / rate;
 632         tmp1 -= phiIncr * rate;
 633         tmp1 <<= 10;
 634         phiIncr <<= 10;
 635         tmp2 = tmp1 / rate;
 636         phiIncr += tmp2;
 637         tmp1 -= tmp2 * rate;
 638         correctionPerGOF = tmp1 / GOF_PER_SEC;
 639         tmp1 -= correctionPerGOF * GOF_PER_SEC;
 640         correctionPerSec = tmp1;
 641         initialDelay = ((48000 * 24) + rate - 1) / rate;
 642
 643         /*
 644          *  Fill in the VariDecimate control block.
 645          */
 646         spin_lock_irqsave(&chip->reg_lock, flags);
 647         snd_cs46xx_poke(chip, BA1_CSRC,
 648                 ((correctionPerSec << 16) & 0xFFFF0000) | (correctionPerGOF & 0xFFFF));
 649         snd_cs46xx_poke(chip, BA1_CCI, coeffIncr);
 650         snd_cs46xx_poke(chip, BA1_CD,
 651                 (((BA1_VARIDEC_BUF_1 + (initialDelay << 2)) << 16) & 0xFFFF0000) | 0x80);
 652         snd_cs46xx_poke(chip, BA1_CPI, phiIncr);
 653         spin_unlock_irqrestore(&chip->reg_lock, flags);
 654
 655         /*
 656          *  Figure out the frame group length for the write back task.  Basically,
 657          *  this is just the factors of 24000 (2^6*3*5^3) that are not present in
 658          *  the output sample rate.
 659          */
 660         frameGroupLength = 1;
 661         for (cnt = 2; cnt <= 64; cnt *= 2) {
 662                 if (((rate / cnt) * cnt) != rate)
 663                         frameGroupLength *= 2;
 664         }
 665         if (((rate / 3) * 3) != rate) {
 666                 frameGroupLength *= 3;
 667         }
 668         for (cnt = 5; cnt <= 125; cnt *= 5) {
 669                 if (((rate / cnt) * cnt) != rate)
 670                         frameGroupLength *= 5;
 671         }
 672
 673         /*
 674          * Fill in the WriteBack control block.
 675          */
 676         spin_lock_irqsave(&chip->reg_lock, flags);
 677         snd_cs46xx_poke(chip, BA1_CFG1, frameGroupLength);
 678         snd_cs46xx_poke(chip, BA1_CFG2, (0x00800000 | frameGroupLength));
 679         snd_cs46xx_poke(chip, BA1_CCST, 0x0000FFFF);
 680         snd_cs46xx_poke(chip, BA1_CSPB, ((65536 * rate) / 24000));
 681         snd_cs46xx_poke(chip, (BA1_CSPB + 4), 0x0000FFFF);
 682         spin_unlock_irqrestore(&chip->reg_lock, flags);
 683 }
 684
 685 /*
 686  *  PCM part
 687  */
 688
 689 static void snd_cs46xx_pb_trans_copy(struct snd_pcm_substream *substream,
 690                                      struct snd_pcm_indirect *rec, size_t bytes)
 691 {
 692         struct snd_pcm_runtime *runtime = substream->runtime;
 693         struct snd_cs46xx_pcm * cpcm = runtime->private_data;
 694         memcpy(cpcm->hw_buf.area + rec->hw_data, runtime->dma_area + rec->sw_data, bytes);
 695 }
 696
 697 static int snd_cs46xx_playback_transfer(struct snd_pcm_substream *substream)
 698 {
 699         struct snd_pcm_runtime *runtime = substream->runtime;
 700         struct snd_cs46xx_pcm * cpcm = runtime->private_data;
 701         snd_pcm_indirect_playback_transfer(substream, &cpcm->pcm_rec, snd_cs46xx_pb_trans_copy);
 702         return 0;
 703 }
 704
 705 static void snd_cs46xx_cp_trans_copy(struct snd_pcm_substream *substream,
 706                                      struct snd_pcm_indirect *rec, size_t bytes)
 707 {
 708         struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
 709         struct snd_pcm_runtime *runtime = substream->runtime;
 710         memcpy(runtime->dma_area + rec->sw_data,
 711                chip->capt.hw_buf.area + rec->hw_data, bytes);
 712 }
 713
 714 static int snd_cs46xx_capture_transfer(struct snd_pcm_substream *substream)
 715 {
 716         struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
 717         snd_pcm_indirect_capture_transfer(substream, &chip->capt.pcm_rec, snd_cs46xx_cp_trans_copy);
 718         return 0;
 719 }
 720
 721 static snd_pcm_uframes_t snd_cs46xx_playback_direct_pointer(struct snd_pcm_substream *substream)
 722 {
 723         struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
 724         size_t ptr;
 725         struct snd_cs46xx_pcm *cpcm = substream->runtime->private_data;
 726         snd_assert (cpcm->pcm_channel,return -ENXIO);
 727
 728 #ifdef CONFIG_SND_CS46XX_NEW_DSP
 729         ptr = snd_cs46xx_peek(chip, (cpcm->pcm_channel->pcm_reader_scb->address + 2) << 2);
 730 #else
 731         ptr = snd_cs46xx_peek(chip, BA1_PBA);
 732 #endif
 733         ptr -= cpcm->hw_buf.addr;
 734         return ptr >> cpcm->shift;
 735 }
 736
 737 static snd_pcm_uframes_t snd_cs46xx_playback_indirect_pointer(struct snd_pcm_substream *substream)
 738 {
 739         struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
 740         size_t ptr;
 741         struct snd_cs46xx_pcm *cpcm = substream->runtime->private_data;
 742
 743 #ifdef CONFIG_SND_CS46XX_NEW_DSP
 744         snd_assert (cpcm->pcm_channel,return -ENXIO);
 745         ptr = snd_cs46xx_peek(chip, (cpcm->pcm_channel->pcm_reader_scb->address + 2) << 2);
 746 #else
 747         ptr = snd_cs46xx_peek(chip, BA1_PBA);
 748 #endif
 749         ptr -= cpcm->hw_buf.addr;
 750         return snd_pcm_indirect_playback_pointer(substream, &cpcm->pcm_rec, ptr);
 751 }
 752
 753 static snd_pcm_uframes_t snd_cs46xx_capture_direct_pointer(struct snd_pcm_substream *substream)
 754 {
 755         struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
 756         size_t ptr = snd_cs46xx_peek(chip, BA1_CBA) - chip->capt.hw_buf.addr;
 757         return ptr >> chip->capt.shift;
 758 }
 759
 760 static snd_pcm_uframes_t snd_cs46xx_capture_indirect_pointer(struct snd_pcm_substream *substream)
 761 {
 762         struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
 763         size_t ptr = snd_cs46xx_peek(chip, BA1_CBA) - chip->capt.hw_buf.addr;
 764         return snd_pcm_indirect_capture_pointer(substream, &chip->capt.pcm_rec, ptr);
 765 }
 766
 767 static int snd_cs46xx_playback_trigger(struct snd_pcm_substream *substream,
 768                                        int cmd)
 769 {
 770         struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
 771         /*struct snd_pcm_runtime *runtime = substream->runtime;*/
 772         int result = 0;
 773
 774 #ifdef CONFIG_SND_CS46XX_NEW_DSP
 775         struct snd_cs46xx_pcm *cpcm = substream->runtime->private_data;
 776         if (! cpcm->pcm_channel) {
 777                 return -ENXIO;
 778         }
 779 #endif
 780         switch (cmd) {
 781         case SNDRV_PCM_TRIGGER_START:
 782         case SNDRV_PCM_TRIGGER_RESUME:
 783 #ifdef CONFIG_SND_CS46XX_NEW_DSP
 784                 /* magic value to unmute PCM stream  playback volume */
 785                 snd_cs46xx_poke(chip, (cpcm->pcm_channel->pcm_reader_scb->address +
 786                                        SCBVolumeCtrl) << 2, 0x80008000);
 787
 788                 if (cpcm->pcm_channel->unlinked)
 789                         cs46xx_dsp_pcm_link(chip,cpcm->pcm_channel);
 790
 791                 if (substream->runtime->periods != CS46XX_FRAGS)
 792                         snd_cs46xx_playback_transfer(substream);
 793 #else
 794                 spin_lock(&chip->reg_lock);
 795                 if (substream->runtime->periods != CS46XX_FRAGS)
 796                         snd_cs46xx_playback_transfer(substream);
 797                 { unsigned int tmp;
 798                 tmp = snd_cs46xx_peek(chip, BA1_PCTL);
 799                 tmp &= 0x0000ffff;
 800                 snd_cs46xx_poke(chip, BA1_PCTL, chip->play_ctl | tmp);
 801                 }
 802                 spin_unlock(&chip->reg_lock);
 803 #endif
 804                 break;
 805         case SNDRV_PCM_TRIGGER_STOP:
 806         case SNDRV_PCM_TRIGGER_SUSPEND:
 807 #ifdef CONFIG_SND_CS46XX_NEW_DSP
 808                 /* magic mute channel */
 809                 snd_cs46xx_poke(chip, (cpcm->pcm_channel->pcm_reader_scb->address +
 810                                        SCBVolumeCtrl) << 2, 0xffffffff);
 811
 812                 if (!cpcm->pcm_channel->unlinked)
 813                         cs46xx_dsp_pcm_unlink(chip,cpcm->pcm_channel);
 814 #else
 815                 spin_lock(&chip->reg_lock);
 816                 { unsigned int tmp;
 817                 tmp = snd_cs46xx_peek(chip, BA1_PCTL);
 818                 tmp &= 0x0000ffff;
 819                 snd_cs46xx_poke(chip, BA1_PCTL, tmp);
 820                 }
 821                 spin_unlock(&chip->reg_lock);
 822 #endif
 823                 break;
 824         default:
 825                 result = -EINVAL;
 826                 break;
 827         }
 828
 829         return result;
 830 }
 831
 832 static int snd_cs46xx_capture_trigger(struct snd_pcm_substream *substream,
 833                                       int cmd)
 834 {
 835         struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
 836         unsigned int tmp;
 837         int result = 0;
 838
 839         spin_lock(&chip->reg_lock);
 840         switch (cmd) {
 841         case SNDRV_PCM_TRIGGER_START:
 842         case SNDRV_PCM_TRIGGER_RESUME:
 843                 tmp = snd_cs46xx_peek(chip, BA1_CCTL);
 844                 tmp &= 0xffff0000;
 845                 snd_cs46xx_poke(chip, BA1_CCTL, chip->capt.ctl | tmp);
 846                 break;
 847         case SNDRV_PCM_TRIGGER_STOP:
 848         case SNDRV_PCM_TRIGGER_SUSPEND:
 849                 tmp = snd_cs46xx_peek(chip, BA1_CCTL);
 850                 tmp &= 0xffff0000;
 851                 snd_cs46xx_poke(chip, BA1_CCTL, tmp);
 852                 break;
 853         default:
 854                 result = -EINVAL;
 855                 break;
 856         }
 857         spin_unlock(&chip->reg_lock);
 858
 859         return result;
 860 }
 861
 862 #ifdef CONFIG_SND_CS46XX_NEW_DSP
 863 static int _cs46xx_adjust_sample_rate (struct snd_cs46xx *chip, struct snd_cs46xx_pcm *cpcm,
 864                                        int sample_rate)
 865 {
 866
 867         /* If PCMReaderSCB and SrcTaskSCB not created yet ... */
 868         if ( cpcm->pcm_channel == NULL) {
 869                 cpcm->pcm_channel = cs46xx_dsp_create_pcm_channel (chip, sample_rate,
 870                                                                    cpcm, cpcm->hw_buf.addr,cpcm->pcm_channel_id);
 871                 if (cpcm->pcm_channel == NULL) {
 872                         snd_printk(KERN_ERR "cs46xx: failed to create virtual PCM channel\n");
 873                         return -ENOMEM;
 874                 }
 875                 cpcm->pcm_channel->sample_rate = sample_rate;
 876         } else
 877         /* if sample rate is changed */
 878         if ((int)cpcm->pcm_channel->sample_rate != sample_rate) {
 879                 int unlinked = cpcm->pcm_channel->unlinked;
 880                 cs46xx_dsp_destroy_pcm_channel (chip,cpcm->pcm_channel);
 881
 882                 if ( (cpcm->pcm_channel = cs46xx_dsp_create_pcm_channel (chip, sample_rate, cpcm,
 883                                                                          cpcm->hw_buf.addr,
 884                                                                          cpcm->pcm_channel_id)) == NULL) {
 885                         snd_printk(KERN_ERR "cs46xx: failed to re-create virtual PCM channel\n");
 886                         return -ENOMEM;
 887                 }
 888
 889                 if (!unlinked) cs46xx_dsp_pcm_link (chip,cpcm->pcm_channel);
 890                 cpcm->pcm_channel->sample_rate = sample_rate;
 891         }
 892
 893         return 0;
 894 }
 895 #endif
 896
 897
 898 static int snd_cs46xx_playback_hw_params(struct snd_pcm_substream *substream,
 899                                          struct snd_pcm_hw_params *hw_params)
 900 {
 901         struct snd_pcm_runtime *runtime = substream->runtime;
 902         struct snd_cs46xx_pcm *cpcm;
 903         int err;
 904 #ifdef CONFIG_SND_CS46XX_NEW_DSP
 905         struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
 906         int sample_rate = params_rate(hw_params);
 907         int period_size = params_period_bytes(hw_params);
 908 #endif
 909         cpcm = runtime->private_data;
 910
 911 #ifdef CONFIG_SND_CS46XX_NEW_DSP
 912         snd_assert (sample_rate != 0, return -ENXIO);
 913
 914         mutex_lock(&chip->spos_mutex);
 915
 916         if (_cs46xx_adjust_sample_rate (chip,cpcm,sample_rate)) {
 917                 mutex_unlock(&chip->spos_mutex);
 918                 return -ENXIO;
 919         }
 920
 921         snd_assert (cpcm->pcm_channel != NULL);
 922         if (!cpcm->pcm_channel) {
 923                 mutex_unlock(&chip->spos_mutex);
 924                 return -ENXIO;
 925         }
 926
 927
 928         if (cs46xx_dsp_pcm_channel_set_period (chip,cpcm->pcm_channel,period_size)) {
 929                  mutex_unlock(&chip->spos_mutex);
 930                  return -EINVAL;
 931          }
 932
 933         snd_printdd ("period_size (%d), periods (%d) buffer_size(%d)\n",
 934                      period_size, params_periods(hw_params),
 935                      params_buffer_bytes(hw_params));
 936 #endif
 937
 938         if (params_periods(hw_params) == CS46XX_FRAGS) {
 939                 if (runtime->dma_area != cpcm->hw_buf.area)
 940                         snd_pcm_lib_free_pages(substream);
 941                 runtime->dma_area = cpcm->hw_buf.area;
 942                 runtime->dma_addr = cpcm->hw_buf.addr;
 943                 runtime->dma_bytes = cpcm->hw_buf.bytes;
 944
 945
 946 #ifdef CONFIG_SND_CS46XX_NEW_DSP
 947                 if (cpcm->pcm_channel_id == DSP_PCM_MAIN_CHANNEL) {
 948                         substream->ops = &snd_cs46xx_playback_ops;
 949                 } else if (cpcm->pcm_channel_id == DSP_PCM_REAR_CHANNEL) {
 950                         substream->ops = &snd_cs46xx_playback_rear_ops;
 951                 } else if (cpcm->pcm_channel_id == DSP_PCM_CENTER_LFE_CHANNEL) {
 952                         substream->ops = &snd_cs46xx_playback_clfe_ops;
 953                 } else if (cpcm->pcm_channel_id == DSP_IEC958_CHANNEL) {
 954                         substream->ops = &snd_cs46xx_playback_iec958_ops;
 955                 } else {
 956                         snd_assert(0);
 957                 }
 958 #else
 959                 substream->ops = &snd_cs46xx_playback_ops;
 960 #endif
 961
 962         } else {
 963                 if (runtime->dma_area == cpcm->hw_buf.area) {
 964                         runtime->dma_area = NULL;
 965                         runtime->dma_addr = 0;
 966                         runtime->dma_bytes = 0;
 967                 }
 968                 if ((err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params))) < 0) {
 969 #ifdef CONFIG_SND_CS46XX_NEW_DSP
 970                         mutex_unlock(&chip->spos_mutex);
 971 #endif
 972                         return err;
 973                 }
 974
 975 #ifdef CONFIG_SND_CS46XX_NEW_DSP
 976                 if (cpcm->pcm_channel_id == DSP_PCM_MAIN_CHANNEL) {
 977                         substream->ops = &snd_cs46xx_playback_indirect_ops;
 978                 } else if (cpcm->pcm_channel_id == DSP_PCM_REAR_CHANNEL) {
 979                         substream->ops = &snd_cs46xx_playback_indirect_rear_ops;
 980                 } else if (cpcm->pcm_channel_id == DSP_PCM_CENTER_LFE_CHANNEL) {
 981                         substream->ops = &snd_cs46xx_playback_indirect_clfe_ops;
 982                 } else if (cpcm->pcm_channel_id == DSP_IEC958_CHANNEL) {
 983                         substream->ops = &snd_cs46xx_playback_indirect_iec958_ops;
 984                 } else {
 985                         snd_assert(0);
 986                 }
 987 #else
 988                 substream->ops = &snd_cs46xx_playback_indirect_ops;
 989 #endif
 990
 991         }
 992
 993 #ifdef CONFIG_SND_CS46XX_NEW_DSP
 994         mutex_unlock(&chip->spos_mutex);
 995 #endif
 996
 997         return 0;
 998 }
 999
1000 static int snd_cs46xx_playback_hw_free(struct snd_pcm_substream *substream)
1001 {
1002         /*struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);*/
1003         struct snd_pcm_runtime *runtime = substream->runtime;
1004         struct snd_cs46xx_pcm *cpcm;
1005
1006         cpcm = runtime->private_data;
1007
1008         /* if play_back open fails, then this function
1009            is called and cpcm can actually be NULL here */
1010         if (!cpcm) return -ENXIO;
1011
1012         if (runtime->dma_area != cpcm->hw_buf.area)
1013                 snd_pcm_lib_free_pages(substream);
1014
1015         runtime->dma_area = NULL;
1016         runtime->dma_addr = 0;
1017         runtime->dma_bytes = 0;
1018
1019         return 0;
1020 }
1021
1022 static int snd_cs46xx_playback_prepare(struct snd_pcm_substream *substream)
1023 {
1024         unsigned int tmp;
1025         unsigned int pfie;
1026         struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1027         struct snd_pcm_runtime *runtime = substream->runtime;
1028         struct snd_cs46xx_pcm *cpcm;
1029
1030         cpcm = runtime->private_data;
1031
1032 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1033     snd_assert (cpcm->pcm_channel != NULL, return -ENXIO);
1034
1035         pfie = snd_cs46xx_peek(chip, (cpcm->pcm_channel->pcm_reader_scb->address + 1) << 2 );
1036         pfie &= ~0x0000f03f;
1037 #else
1038         /* old dsp */
1039         pfie = snd_cs46xx_peek(chip, BA1_PFIE);
1040         pfie &= ~0x0000f03f;
1041 #endif
1042
1043         cpcm->shift = 2;
1044         /* if to convert from stereo to mono */
1045         if (runtime->channels == 1) {
1046                 cpcm->shift--;
1047                 pfie |= 0x00002000;
1048         }
1049         /* if to convert from 8 bit to 16 bit */
1050         if (snd_pcm_format_width(runtime->format) == 8) {
1051                 cpcm->shift--;
1052                 pfie |= 0x00001000;
1053         }
1054         /* if to convert to unsigned */
1055         if (snd_pcm_format_unsigned(runtime->format))
1056                 pfie |= 0x00008000;
1057
1058         /* Never convert byte order when sample stream is 8 bit */
1059         if (snd_pcm_format_width(runtime->format) != 8) {
1060                 /* convert from big endian to little endian */
1061                 if (snd_pcm_format_big_endian(runtime->format))
1062                         pfie |= 0x00004000;
1063         }
1064
1065         memset(&cpcm->pcm_rec, 0, sizeof(cpcm->pcm_rec));
1066         cpcm->pcm_rec.sw_buffer_size = snd_pcm_lib_buffer_bytes(substream);
1067         cpcm->pcm_rec.hw_buffer_size = runtime->period_size * CS46XX_FRAGS << cpcm->shift;
1068
1069 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1070
1071         tmp = snd_cs46xx_peek(chip, (cpcm->pcm_channel->pcm_reader_scb->address) << 2);
1072         tmp &= ~0x000003ff;
1073         tmp |= (4 << cpcm->shift) - 1;
1074         /* playback transaction count register */
1075         snd_cs46xx_poke(chip, (cpcm->pcm_channel->pcm_reader_scb->address) << 2, tmp);
1076
1077         /* playback format && interrupt enable */
1078         snd_cs46xx_poke(chip, (cpcm->pcm_channel->pcm_reader_scb->address + 1) << 2, pfie | cpcm->pcm_channel->pcm_slot);
1079 #else
1080         snd_cs46xx_poke(chip, BA1_PBA, cpcm->hw_buf.addr);
1081         tmp = snd_cs46xx_peek(chip, BA1_PDTC);
1082         tmp &= ~0x000003ff;
1083         tmp |= (4 << cpcm->shift) - 1;
1084         snd_cs46xx_poke(chip, BA1_PDTC, tmp);
1085         snd_cs46xx_poke(chip, BA1_PFIE, pfie);
1086         snd_cs46xx_set_play_sample_rate(chip, runtime->rate);
1087 #endif
1088
1089         return 0;
1090 }
1091
1092 static int snd_cs46xx_capture_hw_params(struct snd_pcm_substream *substream,
1093                                         struct snd_pcm_hw_params *hw_params)
1094 {
1095         struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1096         struct snd_pcm_runtime *runtime = substream->runtime;
1097         int err;
1098
1099 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1100         cs46xx_dsp_pcm_ostream_set_period (chip, params_period_bytes(hw_params));
1101 #endif
1102         if (runtime->periods == CS46XX_FRAGS) {
1103                 if (runtime->dma_area != chip->capt.hw_buf.area)
1104                         snd_pcm_lib_free_pages(substream);
1105                 runtime->dma_area = chip->capt.hw_buf.area;
1106                 runtime->dma_addr = chip->capt.hw_buf.addr;
1107                 runtime->dma_bytes = chip->capt.hw_buf.bytes;
1108                 substream->ops = &snd_cs46xx_capture_ops;
1109         } else {
1110                 if (runtime->dma_area == chip->capt.hw_buf.area) {
1111                         runtime->dma_area = NULL;
1112                         runtime->dma_addr = 0;
1113                         runtime->dma_bytes = 0;
1114                 }
1115                 if ((err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params))) < 0)
1116                         return err;
1117                 substream->ops = &snd_cs46xx_capture_indirect_ops;
1118         }
1119
1120         return 0;
1121 }
1122
1123 static int snd_cs46xx_capture_hw_free(struct snd_pcm_substream *substream)
1124 {
1125         struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1126         struct snd_pcm_runtime *runtime = substream->runtime;
1127
1128         if (runtime->dma_area != chip->capt.hw_buf.area)
1129                 snd_pcm_lib_free_pages(substream);
1130         runtime->dma_area = NULL;
1131         runtime->dma_addr = 0;
1132         runtime->dma_bytes = 0;
1133
1134         return 0;
1135 }
1136
1137 static int snd_cs46xx_capture_prepare(struct snd_pcm_substream *substream)
1138 {
1139         struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1140         struct snd_pcm_runtime *runtime = substream->runtime;
1141
1142         snd_cs46xx_poke(chip, BA1_CBA, chip->capt.hw_buf.addr);
1143         chip->capt.shift = 2;
1144         memset(&chip->capt.pcm_rec, 0, sizeof(chip->capt.pcm_rec));
1145         chip->capt.pcm_rec.sw_buffer_size = snd_pcm_lib_buffer_bytes(substream);
1146         chip->capt.pcm_rec.hw_buffer_size = runtime->period_size * CS46XX_FRAGS << 2;
1147         snd_cs46xx_set_capture_sample_rate(chip, runtime->rate);
1148
1149         return 0;
1150 }
1151
1152 static irqreturn_t snd_cs46xx_interrupt(int irq, void *dev_id)
1153 {
1154         struct snd_cs46xx *chip = dev_id;
1155         u32 status1;
1156 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1157         struct dsp_spos_instance * ins = chip->dsp_spos_instance;
1158         u32 status2;
1159         int i;
1160         struct snd_cs46xx_pcm *cpcm = NULL;
1161 #endif
1162
1163         /*
1164          *  Read the Interrupt Status Register to clear the interrupt
1165          */
1166         status1 = snd_cs46xx_peekBA0(chip, BA0_HISR);
1167         if ((status1 & 0x7fffffff) == 0) {
1168                 snd_cs46xx_pokeBA0(chip, BA0_HICR, HICR_CHGM | HICR_IEV);
1169                 return IRQ_NONE;
1170         }
1171
1172 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1173         status2 = snd_cs46xx_peekBA0(chip, BA0_HSR0);
1174
1175         for (i = 0; i < DSP_MAX_PCM_CHANNELS; ++i) {
1176                 if (i <= 15) {
1177                         if ( status1 & (1 << i) ) {
1178                                 if (i == CS46XX_DSP_CAPTURE_CHANNEL) {
1179                                         if (chip->capt.substream)
1180                                                 snd_pcm_period_elapsed(chip->capt.substream);
1181                                 } else {
1182                                         if (ins->pcm_channels[i].active &&
1183                                             ins->pcm_channels[i].private_data &&
1184                                             !ins->pcm_channels[i].unlinked) {
1185                                                 cpcm = ins->pcm_channels[i].private_data;
1186                                                 snd_pcm_period_elapsed(cpcm->substream);
1187                                         }
1188                                 }
1189                         }
1190                 } else {
1191                         if ( status2 & (1 << (i - 16))) {
1192                                 if (ins->pcm_channels[i].active &&
1193                                     ins->pcm_channels[i].private_data &&
1194                                     !ins->pcm_channels[i].unlinked) {
1195                                         cpcm = ins->pcm_channels[i].private_data;
1196                                         snd_pcm_period_elapsed(cpcm->substream);
1197                                 }
1198                         }
1199                 }
1200         }
1201
1202 #else
1203         /* old dsp */
1204         if ((status1 & HISR_VC0) && chip->playback_pcm) {
1205                 if (chip->playback_pcm->substream)
1206                         snd_pcm_period_elapsed(chip->playback_pcm->substream);
1207         }
1208         if ((status1 & HISR_VC1) && chip->pcm) {
1209                 if (chip->capt.substream)
1210                         snd_pcm_period_elapsed(chip->capt.substream);
1211         }
1212 #endif
1213
1214         if ((status1 & HISR_MIDI) && chip->rmidi) {
1215                 unsigned char c;
1216
1217                 spin_lock(&chip->reg_lock);
1218                 while ((snd_cs46xx_peekBA0(chip, BA0_MIDSR) & MIDSR_RBE) == 0) {
1219                         c = snd_cs46xx_peekBA0(chip, BA0_MIDRP);
1220                         if ((chip->midcr & MIDCR_RIE) == 0)
1221                                 continue;
1222                         snd_rawmidi_receive(chip->midi_input, &c, 1);
1223                 }
1224                 while ((snd_cs46xx_peekBA0(chip, BA0_MIDSR) & MIDSR_TBF) == 0) {
1225                         if ((chip->midcr & MIDCR_TIE) == 0)
1226                                 break;
1227                         if (snd_rawmidi_transmit(chip->midi_output, &c, 1) != 1) {
1228                                 chip->midcr &= ~MIDCR_TIE;
1229                                 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1230                                 break;
1231                         }
1232                         snd_cs46xx_pokeBA0(chip, BA0_MIDWP, c);
1233                 }
1234                 spin_unlock(&chip->reg_lock);
1235         }
1236         /*
1237          *  EOI to the PCI part....reenables interrupts
1238          */
1239         snd_cs46xx_pokeBA0(chip, BA0_HICR, HICR_CHGM | HICR_IEV);
1240
1241         return IRQ_HANDLED;
1242 }
1243
1244 static struct snd_pcm_hardware snd_cs46xx_playback =
1245 {
1246         .info =                 (SNDRV_PCM_INFO_MMAP |
1247                                  SNDRV_PCM_INFO_INTERLEAVED |
1248                                  SNDRV_PCM_INFO_BLOCK_TRANSFER /*|*/
1249                                  /*SNDRV_PCM_INFO_RESUME*/),
1250         .formats =              (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_U8 |
1251                                  SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S16_BE |
1252                                  SNDRV_PCM_FMTBIT_U16_LE | SNDRV_PCM_FMTBIT_U16_BE),
1253         .rates =                SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
1254         .rate_min =             5500,
1255         .rate_max =             48000,
1256         .channels_min =         1,
1257         .channels_max =         2,
1258         .buffer_bytes_max =     (256 * 1024),
1259         .period_bytes_min =     CS46XX_MIN_PERIOD_SIZE,
1260         .period_bytes_max =     CS46XX_MAX_PERIOD_SIZE,
1261         .periods_min =          CS46XX_FRAGS,
1262         .periods_max =          1024,
1263         .fifo_size =            0,
1264 };
1265
1266 static struct snd_pcm_hardware snd_cs46xx_capture =
1267 {
1268         .info =                 (SNDRV_PCM_INFO_MMAP |
1269                                  SNDRV_PCM_INFO_INTERLEAVED |
1270                                  SNDRV_PCM_INFO_BLOCK_TRANSFER /*|*/
1271                                  /*SNDRV_PCM_INFO_RESUME*/),
1272         .formats =              SNDRV_PCM_FMTBIT_S16_LE,
1273         .rates =                SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
1274         .rate_min =             5500,
1275         .rate_max =             48000,
1276         .channels_min =         2,
1277         .channels_max =         2,
1278         .buffer_bytes_max =     (256 * 1024),
1279         .period_bytes_min =     CS46XX_MIN_PERIOD_SIZE,
1280         .period_bytes_max =     CS46XX_MAX_PERIOD_SIZE,
1281         .periods_min =          CS46XX_FRAGS,
1282         .periods_max =          1024,
1283         .fifo_size =            0,
1284 };
1285
1286 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1287
1288 static unsigned int period_sizes[] = { 32, 64, 128, 256, 512, 1024, 2048 };
1289
1290 static struct snd_pcm_hw_constraint_list hw_constraints_period_sizes = {
1291         .count = ARRAY_SIZE(period_sizes),
1292         .list = period_sizes,
1293         .mask = 0
1294 };
1295
1296 #endif
1297
1298 static void snd_cs46xx_pcm_free_substream(struct snd_pcm_runtime *runtime)
1299 {
1300         kfree(runtime->private_data);
1301 }
1302
1303 static int _cs46xx_playback_open_channel (struct snd_pcm_substream *substream,int pcm_channel_id)
1304 {
1305         struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1306         struct snd_cs46xx_pcm * cpcm;
1307         struct snd_pcm_runtime *runtime = substream->runtime;
1308
1309         cpcm = kzalloc(sizeof(*cpcm), GFP_KERNEL);
1310         if (cpcm == NULL)
1311                 return -ENOMEM;
1312         if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(chip->pci),
1313                                 PAGE_SIZE, &cpcm->hw_buf) < 0) {
1314                 kfree(cpcm);
1315                 return -ENOMEM;
1316         }
1317
1318         runtime->hw = snd_cs46xx_playback;
1319         runtime->private_data = cpcm;
1320         runtime->private_free = snd_cs46xx_pcm_free_substream;
1321
1322         cpcm->substream = substream;
1323 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1324         mutex_lock(&chip->spos_mutex);
1325         cpcm->pcm_channel = NULL;
1326         cpcm->pcm_channel_id = pcm_channel_id;
1327
1328
1329         snd_pcm_hw_constraint_list(runtime, 0,
1330                                    SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
1331                                    &hw_constraints_period_sizes);
1332
1333         mutex_unlock(&chip->spos_mutex);
1334 #else
1335         chip->playback_pcm = cpcm; /* HACK */
1336 #endif
1337
1338         if (chip->accept_valid)
1339                 substream->runtime->hw.info |= SNDRV_PCM_INFO_MMAP_VALID;
1340         chip->active_ctrl(chip, 1);
1341
1342         return 0;
1343 }
1344
1345 static int snd_cs46xx_playback_open(struct snd_pcm_substream *substream)
1346 {
1347         snd_printdd("open front channel\n");
1348         return _cs46xx_playback_open_channel(substream,DSP_PCM_MAIN_CHANNEL);
1349 }
1350
1351 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1352 static int snd_cs46xx_playback_open_rear(struct snd_pcm_substream *substream)
1353 {
1354         snd_printdd("open rear channel\n");
1355
1356         return _cs46xx_playback_open_channel(substream,DSP_PCM_REAR_CHANNEL);
1357 }
1358
1359 static int snd_cs46xx_playback_open_clfe(struct snd_pcm_substream *substream)
1360 {
1361         snd_printdd("open center - LFE channel\n");
1362
1363         return _cs46xx_playback_open_channel(substream,DSP_PCM_CENTER_LFE_CHANNEL);
1364 }
1365
1366 static int snd_cs46xx_playback_open_iec958(struct snd_pcm_substream *substream)
1367 {
1368         struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1369
1370         snd_printdd("open raw iec958 channel\n");
1371
1372         mutex_lock(&chip->spos_mutex);
1373         cs46xx_iec958_pre_open (chip);
1374         mutex_unlock(&chip->spos_mutex);
1375
1376         return _cs46xx_playback_open_channel(substream,DSP_IEC958_CHANNEL);
1377 }
1378
1379 static int snd_cs46xx_playback_close(struct snd_pcm_substream *substream);
1380
1381 static int snd_cs46xx_playback_close_iec958(struct snd_pcm_substream *substream)
1382 {
1383         int err;
1384         struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1385
1386         snd_printdd("close raw iec958 channel\n");
1387
1388         err = snd_cs46xx_playback_close(substream);
1389
1390         mutex_lock(&chip->spos_mutex);
1391         cs46xx_iec958_post_close (chip);
1392         mutex_unlock(&chip->spos_mutex);
1393
1394         return err;
1395 }
1396 #endif
1397
1398 static int snd_cs46xx_capture_open(struct snd_pcm_substream *substream)
1399 {
1400         struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1401
1402         if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(chip->pci),
1403                                 PAGE_SIZE, &chip->capt.hw_buf) < 0)
1404                 return -ENOMEM;
1405         chip->capt.substream = substream;
1406         substream->runtime->hw = snd_cs46xx_capture;
1407
1408         if (chip->accept_valid)
1409                 substream->runtime->hw.info |= SNDRV_PCM_INFO_MMAP_VALID;
1410
1411         chip->active_ctrl(chip, 1);
1412
1413 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1414         snd_pcm_hw_constraint_list(substream->runtime, 0,
1415                                    SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
1416                                    &hw_constraints_period_sizes);
1417 #endif
1418         return 0;
1419 }
1420
1421 static int snd_cs46xx_playback_close(struct snd_pcm_substream *substream)
1422 {
1423         struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1424         struct snd_pcm_runtime *runtime = substream->runtime;
1425         struct snd_cs46xx_pcm * cpcm;
1426
1427         cpcm = runtime->private_data;
1428
1429         /* when playback_open fails, then cpcm can be NULL */
1430         if (!cpcm) return -ENXIO;
1431
1432 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1433         mutex_lock(&chip->spos_mutex);
1434         if (cpcm->pcm_channel) {
1435                 cs46xx_dsp_destroy_pcm_channel(chip,cpcm->pcm_channel);
1436                 cpcm->pcm_channel = NULL;
1437         }
1438         mutex_unlock(&chip->spos_mutex);
1439 #else
1440         chip->playback_pcm = NULL;
1441 #endif
1442
1443         cpcm->substream = NULL;
1444         snd_dma_free_pages(&cpcm->hw_buf);
1445         chip->active_ctrl(chip, -1);
1446
1447         return 0;
1448 }
1449
1450 static int snd_cs46xx_capture_close(struct snd_pcm_substream *substream)
1451 {
1452         struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1453
1454         chip->capt.substream = NULL;
1455         snd_dma_free_pages(&chip->capt.hw_buf);
1456         chip->active_ctrl(chip, -1);
1457
1458         return 0;
1459 }
1460
1461 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1462 static struct snd_pcm_ops snd_cs46xx_playback_rear_ops = {
1463         .open =                 snd_cs46xx_playback_open_rear,
1464         .close =                snd_cs46xx_playback_close,
1465         .ioctl =                snd_pcm_lib_ioctl,
1466         .hw_params =            snd_cs46xx_playback_hw_params,
1467         .hw_free =              snd_cs46xx_playback_hw_free,
1468         .prepare =              snd_cs46xx_playback_prepare,
1469         .trigger =              snd_cs46xx_playback_trigger,
1470         .pointer =              snd_cs46xx_playback_direct_pointer,
1471 };
1472
1473 static struct snd_pcm_ops snd_cs46xx_playback_indirect_rear_ops = {
1474         .open =                 snd_cs46xx_playback_open_rear,
1475         .close =                snd_cs46xx_playback_close,
1476         .ioctl =                snd_pcm_lib_ioctl,
1477         .hw_params =            snd_cs46xx_playback_hw_params,
1478         .hw_free =              snd_cs46xx_playback_hw_free,
1479         .prepare =              snd_cs46xx_playback_prepare,
1480         .trigger =              snd_cs46xx_playback_trigger,
1481         .pointer =              snd_cs46xx_playback_indirect_pointer,
1482         .ack =                  snd_cs46xx_playback_transfer,
1483 };
1484
1485 static struct snd_pcm_ops snd_cs46xx_playback_clfe_ops = {
1486         .open =                 snd_cs46xx_playback_open_clfe,
1487         .close =                snd_cs46xx_playback_close,
1488         .ioctl =                snd_pcm_lib_ioctl,
1489         .hw_params =            snd_cs46xx_playback_hw_params,
1490         .hw_free =              snd_cs46xx_playback_hw_free,
1491         .prepare =              snd_cs46xx_playback_prepare,
1492         .trigger =              snd_cs46xx_playback_trigger,
1493         .pointer =              snd_cs46xx_playback_direct_pointer,
1494 };
1495
1496 static struct snd_pcm_ops snd_cs46xx_playback_indirect_clfe_ops = {
1497         .open =                 snd_cs46xx_playback_open_clfe,
1498         .close =                snd_cs46xx_playback_close,
1499         .ioctl =                snd_pcm_lib_ioctl,
1500         .hw_params =            snd_cs46xx_playback_hw_params,
1501         .hw_free =              snd_cs46xx_playback_hw_free,
1502         .prepare =              snd_cs46xx_playback_prepare,
1503         .trigger =              snd_cs46xx_playback_trigger,
1504         .pointer =              snd_cs46xx_playback_indirect_pointer,
1505         .ack =                  snd_cs46xx_playback_transfer,
1506 };
1507
1508 static struct snd_pcm_ops snd_cs46xx_playback_iec958_ops = {
1509         .open =                 snd_cs46xx_playback_open_iec958,
1510         .close =                snd_cs46xx_playback_close_iec958,
1511         .ioctl =                snd_pcm_lib_ioctl,
1512         .hw_params =            snd_cs46xx_playback_hw_params,
1513         .hw_free =              snd_cs46xx_playback_hw_free,
1514         .prepare =              snd_cs46xx_playback_prepare,
1515         .trigger =              snd_cs46xx_playback_trigger,
1516         .pointer =              snd_cs46xx_playback_direct_pointer,
1517 };
1518
1519 static struct snd_pcm_ops snd_cs46xx_playback_indirect_iec958_ops = {
1520         .open =                 snd_cs46xx_playback_open_iec958,
1521         .close =                snd_cs46xx_playback_close_iec958,
1522         .ioctl =                snd_pcm_lib_ioctl,
1523         .hw_params =            snd_cs46xx_playback_hw_params,
1524         .hw_free =              snd_cs46xx_playback_hw_free,
1525         .prepare =              snd_cs46xx_playback_prepare,
1526         .trigger =              snd_cs46xx_playback_trigger,
1527         .pointer =              snd_cs46xx_playback_indirect_pointer,
1528         .ack =                  snd_cs46xx_playback_transfer,
1529 };
1530
1531 #endif
1532
1533 static struct snd_pcm_ops snd_cs46xx_playback_ops = {
1534         .open =                 snd_cs46xx_playback_open,
1535         .close =                snd_cs46xx_playback_close,
1536         .ioctl =                snd_pcm_lib_ioctl,
1537         .hw_params =            snd_cs46xx_playback_hw_params,
1538         .hw_free =              snd_cs46xx_playback_hw_free,
1539         .prepare =              snd_cs46xx_playback_prepare,
1540         .trigger =              snd_cs46xx_playback_trigger,
1541         .pointer =              snd_cs46xx_playback_direct_pointer,
1542 };
1543
1544 static struct snd_pcm_ops snd_cs46xx_playback_indirect_ops = {
1545         .open =                 snd_cs46xx_playback_open,
1546         .close =                snd_cs46xx_playback_close,
1547         .ioctl =                snd_pcm_lib_ioctl,
1548         .hw_params =            snd_cs46xx_playback_hw_params,
1549         .hw_free =              snd_cs46xx_playback_hw_free,
1550         .prepare =              snd_cs46xx_playback_prepare,
1551         .trigger =              snd_cs46xx_playback_trigger,
1552         .pointer =              snd_cs46xx_playback_indirect_pointer,
1553         .ack =                  snd_cs46xx_playback_transfer,
1554 };
1555
1556 static struct snd_pcm_ops snd_cs46xx_capture_ops = {
1557         .open =                 snd_cs46xx_capture_open,
1558         .close =                snd_cs46xx_capture_close,
1559         .ioctl =                snd_pcm_lib_ioctl,
1560         .hw_params =            snd_cs46xx_capture_hw_params,
1561         .hw_free =              snd_cs46xx_capture_hw_free,
1562         .prepare =              snd_cs46xx_capture_prepare,
1563         .trigger =              snd_cs46xx_capture_trigger,
1564         .pointer =              snd_cs46xx_capture_direct_pointer,
1565 };
1566
1567 static struct snd_pcm_ops snd_cs46xx_capture_indirect_ops = {
1568         .open =                 snd_cs46xx_capture_open,
1569         .close =                snd_cs46xx_capture_close,
1570         .ioctl =                snd_pcm_lib_ioctl,
1571         .hw_params =            snd_cs46xx_capture_hw_params,
1572         .hw_free =              snd_cs46xx_capture_hw_free,
1573         .prepare =              snd_cs46xx_capture_prepare,
1574         .trigger =              snd_cs46xx_capture_trigger,
1575         .pointer =              snd_cs46xx_capture_indirect_pointer,
1576         .ack =                  snd_cs46xx_capture_transfer,
1577 };
1578
1579 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1580 #define MAX_PLAYBACK_CHANNELS   (DSP_MAX_PCM_CHANNELS - 1)
1581 #else
1582 #define MAX_PLAYBACK_CHANNELS   1
1583 #endif
1584
1585 int __devinit snd_cs46xx_pcm(struct snd_cs46xx *chip, int device, struct snd_pcm ** rpcm)
1586 {
1587         struct snd_pcm *pcm;
1588         int err;
1589
1590         if (rpcm)
1591                 *rpcm = NULL;
1592         if ((err = snd_pcm_new(chip->card, "CS46xx", device, MAX_PLAYBACK_CHANNELS, 1, &pcm)) < 0)
1593                 return err;
1594
1595         pcm->private_data = chip;
1596
1597         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cs46xx_playback_ops);
1598         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_cs46xx_capture_ops);
1599
1600         /* global setup */
1601         pcm->info_flags = 0;
1602         strcpy(pcm->name, "CS46xx");
1603         chip->pcm = pcm;
1604
1605         snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1606                                               snd_dma_pci_data(chip->pci), 64*1024, 256*1024);
1607
1608         if (rpcm)
1609                 *rpcm = pcm;
1610
1611         return 0;
1612 }
1613
1614
1615 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1616 int __devinit snd_cs46xx_pcm_rear(struct snd_cs46xx *chip, int device, struct snd_pcm ** rpcm)
1617 {
1618         struct snd_pcm *pcm;
1619         int err;
1620
1621         if (rpcm)
1622                 *rpcm = NULL;
1623
1624         if ((err = snd_pcm_new(chip->card, "CS46xx - Rear", device, MAX_PLAYBACK_CHANNELS, 0, &pcm)) < 0)
1625                 return err;
1626
1627         pcm->private_data = chip;
1628
1629         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cs46xx_playback_rear_ops);
1630
1631         /* global setup */
1632         pcm->info_flags = 0;
1633         strcpy(pcm->name, "CS46xx - Rear");
1634         chip->pcm_rear = pcm;
1635
1636         snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1637                                               snd_dma_pci_data(chip->pci), 64*1024, 256*1024);
1638
1639         if (rpcm)
1640                 *rpcm = pcm;
1641
1642         return 0;
1643 }
1644
1645 int __devinit snd_cs46xx_pcm_center_lfe(struct snd_cs46xx *chip, int device, struct snd_pcm ** rpcm)
1646 {
1647         struct snd_pcm *pcm;
1648         int err;
1649
1650         if (rpcm)
1651                 *rpcm = NULL;
1652
1653         if ((err = snd_pcm_new(chip->card, "CS46xx - Center LFE", device, MAX_PLAYBACK_CHANNELS, 0, &pcm)) < 0)
1654                 return err;
1655
1656         pcm->private_data = chip;
1657
1658         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cs46xx_playback_clfe_ops);
1659
1660         /* global setup */
1661         pcm->info_flags = 0;
1662         strcpy(pcm->name, "CS46xx - Center LFE");
1663         chip->pcm_center_lfe = pcm;
1664
1665         snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1666                                               snd_dma_pci_data(chip->pci), 64*1024, 256*1024);
1667
1668         if (rpcm)
1669                 *rpcm = pcm;
1670
1671         return 0;
1672 }
1673
1674 int __devinit snd_cs46xx_pcm_iec958(struct snd_cs46xx *chip, int device, struct snd_pcm ** rpcm)
1675 {
1676         struct snd_pcm *pcm;
1677         int err;
1678
1679         if (rpcm)
1680                 *rpcm = NULL;
1681
1682         if ((err = snd_pcm_new(chip->card, "CS46xx - IEC958", device, 1, 0, &pcm)) < 0)
1683                 return err;
1684
1685         pcm->private_data = chip;
1686
1687         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cs46xx_playback_iec958_ops);
1688
1689         /* global setup */
1690         pcm->info_flags = 0;
1691         strcpy(pcm->name, "CS46xx - IEC958");
1692         chip->pcm_rear = pcm;
1693
1694         snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1695                                               snd_dma_pci_data(chip->pci), 64*1024, 256*1024);
1696
1697         if (rpcm)
1698                 *rpcm = pcm;
1699
1700         return 0;
1701 }
1702 #endif
1703
1704 /*
1705  *  Mixer routines
1706  */
1707 static void snd_cs46xx_mixer_free_ac97_bus(struct snd_ac97_bus *bus)
1708 {
1709         struct snd_cs46xx *chip = bus->private_data;
1710
1711         chip->ac97_bus = NULL;
1712 }
1713
1714 static void snd_cs46xx_mixer_free_ac97(struct snd_ac97 *ac97)
1715 {
1716         struct snd_cs46xx *chip = ac97->private_data;
1717
1718         snd_assert ((ac97 == chip->ac97[CS46XX_PRIMARY_CODEC_INDEX]) ||
1719                     (ac97 == chip->ac97[CS46XX_SECONDARY_CODEC_INDEX]),
1720                     return);
1721
1722         if (ac97 == chip->ac97[CS46XX_PRIMARY_CODEC_INDEX]) {
1723                 chip->ac97[CS46XX_PRIMARY_CODEC_INDEX] = NULL;
1724                 chip->eapd_switch = NULL;
1725         }
1726         else
1727                 chip->ac97[CS46XX_SECONDARY_CODEC_INDEX] = NULL;
1728 }
1729
1730 static int snd_cs46xx_vol_info(struct snd_kcontrol *kcontrol,
1731                                struct snd_ctl_elem_info *uinfo)
1732 {
1733         uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
1734         uinfo->count = 2;
1735         uinfo->value.integer.min = 0;
1736         uinfo->value.integer.max = 0x7fff;
1737         return 0;
1738 }
1739
1740 static int snd_cs46xx_vol_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1741 {
1742         struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
1743         int reg = kcontrol->private_value;
1744         unsigned int val = snd_cs46xx_peek(chip, reg);
1745         ucontrol->value.integer.value[0] = 0xffff - (val >> 16);
1746         ucontrol->value.integer.value[1] = 0xffff - (val & 0xffff);
1747         return 0;
1748 }
1749
1750 static int snd_cs46xx_vol_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1751 {
1752         struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
1753         int reg = kcontrol->private_value;
1754         unsigned int val = ((0xffff - ucontrol->value.integer.value[0]) << 16 |
1755                             (0xffff - ucontrol->value.integer.value[1]));
1756         unsigned int old = snd_cs46xx_peek(chip, reg);
1757         int change = (old != val);
1758
1759         if (change) {
1760                 snd_cs46xx_poke(chip, reg, val);
1761         }
1762
1763         return change;
1764 }
1765
1766 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1767
1768 static int snd_cs46xx_vol_dac_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1769 {
1770         struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
1771
1772         ucontrol->value.integer.value[0] = chip->dsp_spos_instance->dac_volume_left;
1773         ucontrol->value.integer.value[1] = chip->dsp_spos_instance->dac_volume_right;
1774
1775         return 0;
1776 }
1777
1778 static int snd_cs46xx_vol_dac_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1779 {
1780         struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
1781         int change = 0;
1782
1783         if (chip->dsp_spos_instance->dac_volume_right != ucontrol->value.integer.value[0] ||
1784             chip->dsp_spos_instance->dac_volume_left != ucontrol->value.integer.value[1]) {
1785                 cs46xx_dsp_set_dac_volume(chip,
1786                                           ucontrol->value.integer.value[0],
1787                                           ucontrol->value.integer.value[1]);
1788                 change = 1;
1789         }
1790
1791         return change;
1792 }
1793
1794 #if 0
1795 static int snd_cs46xx_vol_iec958_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1796 {
1797         struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
1798
1799         ucontrol->value.integer.value[0] = chip->dsp_spos_instance->spdif_input_volume_left;
1800         ucontrol->value.integer.value[1] = chip->dsp_spos_instance->spdif_input_volume_right;
1801         return 0;
1802 }
1803
1804 static int snd_cs46xx_vol_iec958_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1805 {
1806         struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
1807         int change = 0;
1808
1809         if (chip->dsp_spos_instance->spdif_input_volume_left  != ucontrol->value.integer.value[0] ||
1810             chip->dsp_spos_instance->spdif_input_volume_right!= ucontrol->value.integer.value[1]) {
1811                 cs46xx_dsp_set_iec958_volume (chip,
1812                                               ucontrol->value.integer.value[0],
1813                                               ucontrol->value.integer.value[1]);
1814                 change = 1;
1815         }
1816
1817         return change;
1818 }
1819 #endif
1820
1821 #define snd_mixer_boolean_info          snd_ctl_boolean_mono_info
1822
1823 static int snd_cs46xx_iec958_get(struct snd_kcontrol *kcontrol,
1824                                  struct snd_ctl_elem_value *ucontrol)
1825 {
1826         struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
1827         int reg = kcontrol->private_value;
1828
1829         if (reg == CS46XX_MIXER_SPDIF_OUTPUT_ELEMENT)
1830                 ucontrol->value.integer.value[0] = (chip->dsp_spos_instance->spdif_status_out & DSP_SPDIF_STATUS_OUTPUT_ENABLED);
1831         else
1832                 ucontrol->value.integer.value[0] = chip->dsp_spos_instance->spdif_status_in;
1833
1834         return 0;
1835 }
1836
1837 static int snd_cs46xx_iec958_put(struct snd_kcontrol *kcontrol,
1838                                   struct snd_ctl_elem_value *ucontrol)
1839 {
1840         struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
1841         int change, res;
1842
1843         switch (kcontrol->private_value) {
1844         case CS46XX_MIXER_SPDIF_OUTPUT_ELEMENT:
1845                 mutex_lock(&chip->spos_mutex);
1846                 change = (chip->dsp_spos_instance->spdif_status_out & DSP_SPDIF_STATUS_OUTPUT_ENABLED);
1847                 if (ucontrol->value.integer.value[0] && !change)
1848                         cs46xx_dsp_enable_spdif_out(chip);
1849                 else if (change && !ucontrol->value.integer.value[0])
1850                         cs46xx_dsp_disable_spdif_out(chip);
1851
1852                 res = (change != (chip->dsp_spos_instance->spdif_status_out & DSP_SPDIF_STATUS_OUTPUT_ENABLED));
1853                 mutex_unlock(&chip->spos_mutex);
1854                 break;
1855         case CS46XX_MIXER_SPDIF_INPUT_ELEMENT:
1856                 change = chip->dsp_spos_instance->spdif_status_in;
1857                 if (ucontrol->value.integer.value[0] && !change) {
1858                         cs46xx_dsp_enable_spdif_in(chip);
1859                         /* restore volume */
1860                 }
1861                 else if (change && !ucontrol->value.integer.value[0])
1862                         cs46xx_dsp_disable_spdif_in(chip);
1863
1864                 res = (change != chip->dsp_spos_instance->spdif_status_in);
1865                 break;
1866         default:
1867                 res = -EINVAL;
1868                 snd_assert(0, (void)0);
1869         }
1870
1871         return res;
1872 }
1873
1874 static int snd_cs46xx_adc_capture_get(struct snd_kcontrol *kcontrol,
1875                                       struct snd_ctl_elem_value *ucontrol)
1876 {
1877         struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
1878         struct dsp_spos_instance * ins = chip->dsp_spos_instance;
1879
1880         if (ins->adc_input != NULL)
1881                 ucontrol->value.integer.value[0] = 1;
1882         else
1883                 ucontrol->value.integer.value[0] = 0;
1884
1885         return 0;
1886 }
1887
1888 static int snd_cs46xx_adc_capture_put(struct snd_kcontrol *kcontrol,
1889                                       struct snd_ctl_elem_value *ucontrol)
1890 {
1891         struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
1892         struct dsp_spos_instance * ins = chip->dsp_spos_instance;
1893         int change = 0;
1894
1895         if (ucontrol->value.integer.value[0] && !ins->adc_input) {
1896                 cs46xx_dsp_enable_adc_capture(chip);
1897                 change = 1;
1898         } else  if (!ucontrol->value.integer.value[0] && ins->adc_input) {
1899                 cs46xx_dsp_disable_adc_capture(chip);
1900                 change = 1;
1901         }
1902         return change;
1903 }
1904
1905 static int snd_cs46xx_pcm_capture_get(struct snd_kcontrol *kcontrol,
1906                                       struct snd_ctl_elem_value *ucontrol)
1907 {
1908         struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
1909         struct dsp_spos_instance * ins = chip->dsp_spos_instance;
1910
1911         if (ins->pcm_input != NULL)
1912                 ucontrol->value.integer.value[0] = 1;
1913         else
1914                 ucontrol->value.integer.value[0] = 0;
1915
1916         return 0;
1917 }
1918
1919
1920 static int snd_cs46xx_pcm_capture_put(struct snd_kcontrol *kcontrol,
1921                                       struct snd_ctl_elem_value *ucontrol)
1922 {
1923         struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
1924         struct dsp_spos_instance * ins = chip->dsp_spos_instance;
1925         int change = 0;
1926
1927         if (ucontrol->value.integer.value[0] && !ins->pcm_input) {
1928                 cs46xx_dsp_enable_pcm_capture(chip);
1929                 change = 1;
1930         } else  if (!ucontrol->value.integer.value[0] && ins->pcm_input) {
1931                 cs46xx_dsp_disable_pcm_capture(chip);
1932                 change = 1;
1933         }
1934
1935         return change;
1936 }
1937
1938 static int snd_herc_spdif_select_get(struct snd_kcontrol *kcontrol,
1939                                      struct snd_ctl_elem_value *ucontrol)
1940 {
1941         struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
1942
1943         int val1 = snd_cs46xx_peekBA0(chip, BA0_EGPIODR);
1944
1945         if (val1 & EGPIODR_GPOE0)
1946                 ucontrol->value.integer.value[0] = 1;
1947         else
1948                 ucontrol->value.integer.value[0] = 0;
1949
1950         return 0;
1951 }
1952
1953 /*
1954  *      Game Theatre XP card - EGPIO[0] is used to select SPDIF input optical or coaxial.
1955  */
1956 static int snd_herc_spdif_select_put(struct snd_kcontrol *kcontrol,
1957                                        struct snd_ctl_elem_value *ucontrol)
1958 {
1959         struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
1960         int val1 = snd_cs46xx_peekBA0(chip, BA0_EGPIODR);
1961         int val2 = snd_cs46xx_peekBA0(chip, BA0_EGPIOPTR);
1962
1963         if (ucontrol->value.integer.value[0]) {
1964                 /* optical is default */
1965                 snd_cs46xx_pokeBA0(chip, BA0_EGPIODR,
1966                                    EGPIODR_GPOE0 | val1);  /* enable EGPIO0 output */
1967                 snd_cs46xx_pokeBA0(chip, BA0_EGPIOPTR,
1968                                    EGPIOPTR_GPPT0 | val2); /* open-drain on output */
1969         } else {
1970                 /* coaxial */
1971                 snd_cs46xx_pokeBA0(chip, BA0_EGPIODR,  val1 & ~EGPIODR_GPOE0); /* disable */
1972                 snd_cs46xx_pokeBA0(chip, BA0_EGPIOPTR, val2 & ~EGPIOPTR_GPPT0); /* disable */
1973         }
1974
1975         /* checking diff from the EGPIO direction register
1976            should be enough */
1977         return (val1 != (int)snd_cs46xx_peekBA0(chip, BA0_EGPIODR));
1978 }
1979
1980
1981 static int snd_cs46xx_spdif_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1982 {
1983         uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1984         uinfo->count = 1;
1985         return 0;
1986 }
1987
1988 static int snd_cs46xx_spdif_default_get(struct snd_kcontrol *kcontrol,
1989                                         struct snd_ctl_elem_value *ucontrol)
1990 {
1991         struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
1992         struct dsp_spos_instance * ins = chip->dsp_spos_instance;
1993
1994         mutex_lock(&chip->spos_mutex);
1995         ucontrol->value.iec958.status[0] = _wrap_all_bits((ins->spdif_csuv_default >> 24) & 0xff);
1996         ucontrol->value.iec958.status[1] = _wrap_all_bits((ins->spdif_csuv_default >> 16) & 0xff);
1997         ucontrol->value.iec958.status[2] = 0;
1998         ucontrol->value.iec958.status[3] = _wrap_all_bits((ins->spdif_csuv_default) & 0xff);
1999         mutex_unlock(&chip->spos_mutex);
2000
2001         return 0;
2002 }
2003
2004 static int snd_cs46xx_spdif_default_put(struct snd_kcontrol *kcontrol,
2005                                         struct snd_ctl_elem_value *ucontrol)
2006 {
2007         struct snd_cs46xx * chip = snd_kcontrol_chip(kcontrol);
2008         struct dsp_spos_instance * ins = chip->dsp_spos_instance;
2009         unsigned int val;
2010         int change;
2011
2012         mutex_lock(&chip->spos_mutex);
2013         val = ((unsigned int)_wrap_all_bits(ucontrol->value.iec958.status[0]) << 24) |
2014                 ((unsigned int)_wrap_all_bits(ucontrol->value.iec958.status[2]) << 16) |
2015                 ((unsigned int)_wrap_all_bits(ucontrol->value.iec958.status[3]))  |
2016                 /* left and right validity bit */
2017                 (1 << 13) | (1 << 12);
2018
2019
2020         change = (unsigned int)ins->spdif_csuv_default != val;
2021         ins->spdif_csuv_default = val;
2022
2023         if ( !(ins->spdif_status_out & DSP_SPDIF_STATUS_PLAYBACK_OPEN) )
2024                 cs46xx_poke_via_dsp (chip,SP_SPDOUT_CSUV,val);
2025
2026         mutex_unlock(&chip->spos_mutex);
2027
2028         return change;
2029 }
2030
2031 static int snd_cs46xx_spdif_mask_get(struct snd_kcontrol *kcontrol,
2032                                      struct snd_ctl_elem_value *ucontrol)
2033 {
2034         ucontrol->value.iec958.status[0] = 0xff;
2035         ucontrol->value.iec958.status[1] = 0xff;
2036         ucontrol->value.iec958.status[2] = 0x00;
2037         ucontrol->value.iec958.status[3] = 0xff;
2038         return 0;
2039 }
2040
2041 static int snd_cs46xx_spdif_stream_get(struct snd_kcontrol *kcontrol,
2042                                          struct snd_ctl_elem_value *ucontrol)
2043 {
2044         struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
2045         struct dsp_spos_instance * ins = chip->dsp_spos_instance;
2046
2047         mutex_lock(&chip->spos_mutex);
2048         ucontrol->value.iec958.status[0] = _wrap_all_bits((ins->spdif_csuv_stream >> 24) & 0xff);
2049         ucontrol->value.iec958.status[1] = _wrap_all_bits((ins->spdif_csuv_stream >> 16) & 0xff);
2050         ucontrol->value.iec958.status[2] = 0;
2051         ucontrol->value.iec958.status[3] = _wrap_all_bits((ins->spdif_csuv_stream) & 0xff);
2052         mutex_unlock(&chip->spos_mutex);
2053
2054         return 0;
2055 }
2056
2057 static int snd_cs46xx_spdif_stream_put(struct snd_kcontrol *kcontrol,
2058                                         struct snd_ctl_elem_value *ucontrol)
2059 {
2060         struct snd_cs46xx * chip = snd_kcontrol_chip(kcontrol);
2061         struct dsp_spos_instance * ins = chip->dsp_spos_instance;
2062         unsigned int val;
2063         int change;
2064
2065         mutex_lock(&chip->spos_mutex);
2066         val = ((unsigned int)_wrap_all_bits(ucontrol->value.iec958.status[0]) << 24) |
2067                 ((unsigned int)_wrap_all_bits(ucontrol->value.iec958.status[1]) << 16) |
2068                 ((unsigned int)_wrap_all_bits(ucontrol->value.iec958.status[3])) |
2069                 /* left and right validity bit */
2070                 (1 << 13) | (1 << 12);
2071
2072
2073         change = ins->spdif_csuv_stream != val;
2074         ins->spdif_csuv_stream = val;
2075
2076         if ( ins->spdif_status_out & DSP_SPDIF_STATUS_PLAYBACK_OPEN )
2077                 cs46xx_poke_via_dsp (chip,SP_SPDOUT_CSUV,val);
2078
2079         mutex_unlock(&chip->spos_mutex);
2080
2081         return change;
2082 }
2083
2084 #endif /* CONFIG_SND_CS46XX_NEW_DSP */
2085
2086
2087 #ifdef CONFIG_SND_CS46XX_DEBUG_GPIO
2088 static int snd_cs46xx_egpio_select_info(struct snd_kcontrol *kcontrol,
2089                                         struct snd_ctl_elem_info *uinfo)
2090 {
2091         uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
2092         uinfo->count = 1;
2093         uinfo->value.integer.min = 0;
2094         uinfo->value.integer.max = 8;
2095         return 0;
2096 }
2097
2098 static int snd_cs46xx_egpio_select_get(struct snd_kcontrol *kcontrol,
2099                                        struct snd_ctl_elem_value *ucontrol)
2100 {
2101         struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
2102         ucontrol->value.integer.value[0] = chip->current_gpio;
2103
2104         return 0;
2105 }
2106
2107 static int snd_cs46xx_egpio_select_put(struct snd_kcontrol *kcontrol,
2108                                        struct snd_ctl_elem_value *ucontrol)
2109 {
2110         struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
2111         int change = (chip->current_gpio != ucontrol->value.integer.value[0]);
2112         chip->current_gpio = ucontrol->value.integer.value[0];
2113
2114         return change;
2115 }
2116
2117
2118 static int snd_cs46xx_egpio_get(struct snd_kcontrol *kcontrol,
2119                                        struct snd_ctl_elem_value *ucontrol)
2120 {
2121         struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
2122         int reg = kcontrol->private_value;
2123
2124         snd_printdd ("put: reg = %04x, gpio %02x\n",reg,chip->current_gpio);
2125         ucontrol->value.integer.value[0] =
2126                 (snd_cs46xx_peekBA0(chip, reg) & (1 << chip->current_gpio)) ? 1 : 0;
2127
2128         return 0;
2129 }
2130
2131 static int snd_cs46xx_egpio_put(struct snd_kcontrol *kcontrol,
2132                                        struct snd_ctl_elem_value *ucontrol)
2133 {
2134         struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
2135         int reg = kcontrol->private_value;
2136         int val = snd_cs46xx_peekBA0(chip, reg);
2137         int oldval = val;
2138         snd_printdd ("put: reg = %04x, gpio %02x\n",reg,chip->current_gpio);
2139
2140         if (ucontrol->value.integer.value[0])
2141                 val |= (1 << chip->current_gpio);
2142         else
2143                 val &= ~(1 << chip->current_gpio);
2144
2145         snd_cs46xx_pokeBA0(chip, reg,val);
2146         snd_printdd ("put: val %08x oldval %08x\n",val,oldval);
2147
2148         return (oldval != val);
2149 }
2150 #endif /* CONFIG_SND_CS46XX_DEBUG_GPIO */
2151
2152 static struct snd_kcontrol_new snd_cs46xx_controls[] __devinitdata = {
2153 {
2154         .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2155         .name = "DAC Volume",
2156         .info = snd_cs46xx_vol_info,
2157 #ifndef CONFIG_SND_CS46XX_NEW_DSP
2158         .get = snd_cs46xx_vol_get,
2159         .put = snd_cs46xx_vol_put,
2160         .private_value = BA1_PVOL,
2161 #else
2162         .get = snd_cs46xx_vol_dac_get,
2163         .put = snd_cs46xx_vol_dac_put,
2164 #endif
2165 },
2166
2167 {
2168         .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2169         .name = "ADC Volume",
2170         .info = snd_cs46xx_vol_info,
2171         .get = snd_cs46xx_vol_get,
2172         .put = snd_cs46xx_vol_put,
2173 #ifndef CONFIG_SND_CS46XX_NEW_DSP
2174         .private_value = BA1_CVOL,
2175 #else
2176         .private_value = (VARIDECIMATE_SCB_ADDR + 0xE) << 2,
2177 #endif
2178 },
2179 #ifdef CONFIG_SND_CS46XX_NEW_DSP
2180 {
2181         .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2182         .name = "ADC Capture Switch",
2183         .info = snd_mixer_boolean_info,
2184         .get = snd_cs46xx_adc_capture_get,
2185         .put = snd_cs46xx_adc_capture_put
2186 },
2187 {
2188         .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2189         .name = "DAC Capture Switch",
2190         .info = snd_mixer_boolean_info,
2191         .get = snd_cs46xx_pcm_capture_get,
2192         .put = snd_cs46xx_pcm_capture_put
2193 },
2194 {
2195         .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2196         .name = SNDRV_CTL_NAME_IEC958("Output ",NONE,SWITCH),
2197         .info = snd_mixer_boolean_info,
2198         .get = snd_cs46xx_iec958_get,
2199         .put = snd_cs46xx_iec958_put,
2200         .private_value = CS46XX_MIXER_SPDIF_OUTPUT_ELEMENT,
2201 },
2202 {
2203         .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2204         .name = SNDRV_CTL_NAME_IEC958("Input ",NONE,SWITCH),
2205         .info = snd_mixer_boolean_info,
2206         .get = snd_cs46xx_iec958_get,
2207         .put = snd_cs46xx_iec958_put,
2208         .private_value = CS46XX_MIXER_SPDIF_INPUT_ELEMENT,
2209 },
2210 #if 0
2211 /* Input IEC958 volume does not work for the moment. (Benny) */
2212 {
2213         .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2214         .name = SNDRV_CTL_NAME_IEC958("Input ",NONE,VOLUME),
2215         .info = snd_cs46xx_vol_info,
2216         .get = snd_cs46xx_vol_iec958_get,
2217         .put = snd_cs46xx_vol_iec958_put,
2218         .private_value = (ASYNCRX_SCB_ADDR + 0xE) << 2,
2219 },
2220 #endif
2221 {
2222         .iface = SNDRV_CTL_ELEM_IFACE_PCM,
2223         .name =  SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT),
2224         .info =  snd_cs46xx_spdif_info,
2225         .get =   snd_cs46xx_spdif_default_get,
2226         .put =   snd_cs46xx_spdif_default_put,
2227 },
2228 {
2229         .iface = SNDRV_CTL_ELEM_IFACE_PCM,
2230         .name =  SNDRV_CTL_NAME_IEC958("",PLAYBACK,MASK),
2231         .info =  snd_cs46xx_spdif_info,
2232         .get =   snd_cs46xx_spdif_mask_get,
2233         .access = SNDRV_CTL_ELEM_ACCESS_READ
2234 },
2235 {
2236         .iface = SNDRV_CTL_ELEM_IFACE_PCM,
2237         .name =  SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM),
2238         .info =  snd_cs46xx_spdif_info,
2239         .get =   snd_cs46xx_spdif_stream_get,
2240         .put =   snd_cs46xx_spdif_stream_put
2241 },
2242
2243 #endif
2244 #ifdef CONFIG_SND_CS46XX_DEBUG_GPIO
2245 {
2246         .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2247         .name = "EGPIO select",
2248         .info = snd_cs46xx_egpio_select_info,
2249         .get = snd_cs46xx_egpio_select_get,
2250         .put = snd_cs46xx_egpio_select_put,
2251         .private_value = 0,
2252 },
2253 {
2254         .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2255         .name = "EGPIO Input/Output",
2256         .info = snd_mixer_boolean_info,
2257         .get = snd_cs46xx_egpio_get,
2258         .put = snd_cs46xx_egpio_put,
2259         .private_value = BA0_EGPIODR,
2260 },
2261 {
2262         .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2263         .name = "EGPIO CMOS/Open drain",
2264         .info = snd_mixer_boolean_info,
2265         .get = snd_cs46xx_egpio_get,
2266         .put = snd_cs46xx_egpio_put,
2267         .private_value = BA0_EGPIOPTR,
2268 },
2269 {
2270         .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2271         .name = "EGPIO On/Off",
2272         .info = snd_mixer_boolean_info,
2273         .get = snd_cs46xx_egpio_get,
2274         .put = snd_cs46xx_egpio_put,
2275         .private_value = BA0_EGPIOSR,
2276 },
2277 #endif
2278 };
2279
2280 #ifdef CONFIG_SND_CS46XX_NEW_DSP
2281 /* set primary cs4294 codec into Extended Audio Mode */
2282 static int snd_cs46xx_front_dup_get(struct snd_kcontrol *kcontrol,
2283                                     struct snd_ctl_elem_value *ucontrol)
2284 {
2285         struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
2286         unsigned short val;
2287         val = snd_ac97_read(chip->ac97[CS46XX_PRIMARY_CODEC_INDEX], AC97_CSR_ACMODE);
2288         ucontrol->value.integer.value[0] = (val & 0x200) ? 0 : 1;
2289         return 0;
2290 }
2291
2292 static int snd_cs46xx_front_dup_put(struct snd_kcontrol *kcontrol,
2293                                     struct snd_ctl_elem_value *ucontrol)
2294 {
2295         struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
2296         return snd_ac97_update_bits(chip->ac97[CS46XX_PRIMARY_CODEC_INDEX],
2297                                     AC97_CSR_ACMODE, 0x200,
2298                                     ucontrol->value.integer.value[0] ? 0 : 0x200);
2299 }
2300
2301 static struct snd_kcontrol_new snd_cs46xx_front_dup_ctl = {
2302         .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2303         .name = "Duplicate Front",
2304         .info = snd_mixer_boolean_info,
2305         .get = snd_cs46xx_front_dup_get,
2306         .put = snd_cs46xx_front_dup_put,
2307 };
2308 #endif
2309
2310 #ifdef CONFIG_SND_CS46XX_NEW_DSP
2311 /* Only available on the Hercules Game Theater XP soundcard */
2312 static struct snd_kcontrol_new snd_hercules_controls[] = {
2313 {
2314         .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2315         .name = "Optical/Coaxial SPDIF Input Switch",
2316         .info = snd_mixer_boolean_info,
2317         .get = snd_herc_spdif_select_get,
2318         .put = snd_herc_spdif_select_put,
2319 },
2320 };
2321
2322
2323 static void snd_cs46xx_codec_reset (struct snd_ac97 * ac97)
2324 {
2325         unsigned long end_time;
2326         int err;
2327
2328         /* reset to defaults */
2329         snd_ac97_write(ac97, AC97_RESET, 0);
2330
2331         /* set the desired CODEC mode */
2332         if (ac97->num == CS46XX_PRIMARY_CODEC_INDEX) {
2333                 snd_printdd("cs46xx: CODOEC1 mode %04x\n",0x0);
2334                 snd_cs46xx_ac97_write(ac97,AC97_CSR_ACMODE,0x0);
2335         } else if (ac97->num == CS46XX_SECONDARY_CODEC_INDEX) {
2336                 snd_printdd("cs46xx: CODOEC2 mode %04x\n",0x3);
2337                 snd_cs46xx_ac97_write(ac97,AC97_CSR_ACMODE,0x3);
2338         } else {
2339                 snd_assert(0); /* should never happen ... */
2340         }
2341
2342         udelay(50);
2343
2344         /* it's necessary to wait awhile until registers are accessible after RESET */
2345         /* because the PCM or MASTER volume registers can be modified, */
2346         /* the REC_GAIN register is used for tests */
2347         end_time = jiffies + HZ;
2348         do {
2349                 unsigned short ext_mid;
2350
2351                 /* use preliminary reads to settle the communication */
2352                 snd_ac97_read(ac97, AC97_RESET);
2353                 snd_ac97_read(ac97, AC97_VENDOR_ID1);
2354                 snd_ac97_read(ac97, AC97_VENDOR_ID2);
2355                 /* modem? */
2356                 ext_mid = snd_ac97_read(ac97, AC97_EXTENDED_MID);
2357                 if (ext_mid != 0xffff && (ext_mid & 1) != 0)
2358                         return;
2359
2360                 /* test if we can write to the record gain volume register */
2361                 snd_ac97_write_cache(ac97, AC97_REC_GAIN, 0x8a05);
2362                 if ((err = snd_ac97_read(ac97, AC97_REC_GAIN)) == 0x8a05)
2363                         return;
2364
2365                 msleep(10);
2366         } while (time_after_eq(end_time, jiffies));
2367
2368         snd_printk(KERN_ERR "CS46xx secondary codec doesn't respond!\n");
2369 }
2370 #endif
2371
2372 static int __devinit cs46xx_detect_codec(struct snd_cs46xx *chip, int codec)
2373 {
2374         int idx, err;
2375         struct snd_ac97_template ac97;
2376
2377         memset(&ac97, 0, sizeof(ac97));
2378         ac97.private_data = chip;
2379         ac97.private_free = snd_cs46xx_mixer_free_ac97;
2380         ac97.num = codec;
2381         if (chip->amplifier_ctrl == amp_voyetra)
2382                 ac97.scaps = AC97_SCAP_INV_EAPD;
2383
2384         if (codec == CS46XX_SECONDARY_CODEC_INDEX) {
2385                 snd_cs46xx_codec_write(chip, AC97_RESET, 0, codec);
2386                 udelay(10);
2387                 if (snd_cs46xx_codec_read(chip, AC97_RESET, codec) & 0x8000) {
2388                         snd_printdd("snd_cs46xx: seconadry codec not present\n");
2389                         return -ENXIO;
2390                 }
2391         }
2392
2393         snd_cs46xx_codec_write(chip, AC97_MASTER, 0x8000, codec);
2394         for (idx = 0; idx < 100; ++idx) {
2395                 if (snd_cs46xx_codec_read(chip, AC97_MASTER, codec) == 0x8000) {
2396                         err = snd_ac97_mixer(chip->ac97_bus, &ac97, &chip->ac97[codec]);
2397                         return err;
2398                 }
2399                 msleep(10);
2400         }
2401         snd_printdd("snd_cs46xx: codec %d detection timeout\n", codec);
2402         return -ENXIO;
2403 }
2404
2405 int __devinit snd_cs46xx_mixer(struct snd_cs46xx *chip, int spdif_device)
2406 {
2407         struct snd_card *card = chip->card;
2408         struct snd_ctl_elem_id id;
2409         int err;
2410         unsigned int idx;
2411         static struct snd_ac97_bus_ops ops = {
2412 #ifdef CONFIG_SND_CS46XX_NEW_DSP
2413                 .reset = snd_cs46xx_codec_reset,
2414 #endif
2415                 .write = snd_cs46xx_ac97_write,
2416                 .read = snd_cs46xx_ac97_read,
2417         };
2418
2419         /* detect primary codec */
2420         chip->nr_ac97_codecs = 0;
2421         snd_printdd("snd_cs46xx: detecting primary codec\n");
2422         if ((err = snd_ac97_bus(card, 0, &ops, chip, &chip->ac97_bus)) < 0)
2423                 return err;
2424         chip->ac97_bus->private_free = snd_cs46xx_mixer_free_ac97_bus;
2425
2426         if (cs46xx_detect_codec(chip, CS46XX_PRIMARY_CODEC_INDEX) < 0)
2427                 return -ENXIO;
2428         chip->nr_ac97_codecs = 1;
2429
2430 #ifdef CONFIG_SND_CS46XX_NEW_DSP
2431         snd_printdd("snd_cs46xx: detecting seconadry codec\n");
2432         /* try detect a secondary codec */
2433         if (! cs46xx_detect_codec(chip, CS46XX_SECONDARY_CODEC_INDEX))
2434                 chip->nr_ac97_codecs = 2;
2435 #endif /* CONFIG_SND_CS46XX_NEW_DSP */
2436
2437         /* add cs4630 mixer controls */
2438         for (idx = 0; idx < ARRAY_SIZE(snd_cs46xx_controls); idx++) {
2439                 struct snd_kcontrol *kctl;
2440                 kctl = snd_ctl_new1(&snd_cs46xx_controls[idx], chip);
2441                 if (kctl && kctl->id.iface == SNDRV_CTL_ELEM_IFACE_PCM)
2442                         kctl->id.device = spdif_device;
2443                 if ((err = snd_ctl_add(card, kctl)) < 0)
2444                         return err;
2445         }
2446
2447         /* get EAPD mixer switch (for voyetra hack) */
2448         memset(&id, 0, sizeof(id));
2449         id.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
2450         strcpy(id.name, "External Amplifier");
2451         chip->eapd_switch = snd_ctl_find_id(chip->card, &id);
2452
2453 #ifdef CONFIG_SND_CS46XX_NEW_DSP
2454         if (chip->nr_ac97_codecs == 1) {
2455                 unsigned int id2 = chip->ac97[CS46XX_PRIMARY_CODEC_INDEX]->id & 0xffff;
2456                 if (id2 == 0x592b || id2 == 0x592d) {
2457                         err = snd_ctl_add(card, snd_ctl_new1(&snd_cs46xx_front_dup_ctl, chip));
2458                         if (err < 0)
2459                                 return err;
2460                         snd_ac97_write_cache(chip->ac97[CS46XX_PRIMARY_CODEC_INDEX],
2461                                              AC97_CSR_ACMODE, 0x200);
2462                 }
2463         }
2464         /* do soundcard specific mixer setup */
2465         if (chip->mixer_init) {
2466                 snd_printdd ("calling chip->mixer_init(chip);\n");
2467                 chip->mixer_init(chip);
2468         }
2469 #endif
2470
2471         /* turn on amplifier */
2472         chip->amplifier_ctrl(chip, 1);
2473
2474         return 0;
2475 }
2476
2477 /*
2478  *  RawMIDI interface
2479  */
2480
2481 static void snd_cs46xx_midi_reset(struct snd_cs46xx *chip)
2482 {
2483         snd_cs46xx_pokeBA0(chip, BA0_MIDCR, MIDCR_MRST);
2484         udelay(100);
2485         snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2486 }
2487
2488 static int snd_cs46xx_midi_input_open(struct snd_rawmidi_substream *substream)
2489 {
2490         struct snd_cs46xx *chip = substream->rmidi->private_data;
2491
2492         chip->active_ctrl(chip, 1);
2493         spin_lock_irq(&chip->reg_lock);
2494         chip->uartm |= CS46XX_MODE_INPUT;
2495         chip->midcr |= MIDCR_RXE;
2496         chip->midi_input = substream;
2497         if (!(chip->uartm & CS46XX_MODE_OUTPUT)) {
2498                 snd_cs46xx_midi_reset(chip);
2499         } else {
2500                 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2501         }
2502         spin_unlock_irq(&chip->reg_lock);
2503         return 0;
2504 }
2505
2506 static int snd_cs46xx_midi_input_close(struct snd_rawmidi_substream *substream)
2507 {
2508         struct snd_cs46xx *chip = substream->rmidi->private_data;
2509
2510         spin_lock_irq(&chip->reg_lock);
2511         chip->midcr &= ~(MIDCR_RXE | MIDCR_RIE);
2512         chip->midi_input = NULL;
2513         if (!(chip->uartm & CS46XX_MODE_OUTPUT)) {
2514                 snd_cs46xx_midi_reset(chip);
2515         } else {
2516                 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2517         }
2518         chip->uartm &= ~CS46XX_MODE_INPUT;
2519         spin_unlock_irq(&chip->reg_lock);
2520         chip->active_ctrl(chip, -1);
2521         return 0;
2522 }
2523
2524 static int snd_cs46xx_midi_output_open(struct snd_rawmidi_substream *substream)
2525 {
2526         struct snd_cs46xx *chip = substream->rmidi->private_data;
2527
2528         chip->active_ctrl(chip, 1);
2529
2530         spin_lock_irq(&chip->reg_lock);
2531         chip->uartm |= CS46XX_MODE_OUTPUT;
2532         chip->midcr |= MIDCR_TXE;
2533         chip->midi_output = substream;
2534         if (!(chip->uartm & CS46XX_MODE_INPUT)) {
2535                 snd_cs46xx_midi_reset(chip);
2536         } else {
2537                 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2538         }
2539         spin_unlock_irq(&chip->reg_lock);
2540         return 0;
2541 }
2542
2543 static int snd_cs46xx_midi_output_close(struct snd_rawmidi_substream *substream)
2544 {
2545         struct snd_cs46xx *chip = substream->rmidi->private_data;
2546
2547         spin_lock_irq(&chip->reg_lock);
2548         chip->midcr &= ~(MIDCR_TXE | MIDCR_TIE);
2549         chip->midi_output = NULL;
2550         if (!(chip->uartm & CS46XX_MODE_INPUT)) {
2551                 snd_cs46xx_midi_reset(chip);
2552         } else {
2553                 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2554         }
2555         chip->uartm &= ~CS46XX_MODE_OUTPUT;
2556         spin_unlock_irq(&chip->reg_lock);
2557         chip->active_ctrl(chip, -1);
2558         return 0;
2559 }
2560
2561 static void snd_cs46xx_midi_input_trigger(struct snd_rawmidi_substream *substream, int up)
2562 {
2563         unsigned long flags;
2564         struct snd_cs46xx *chip = substream->rmidi->private_data;
2565
2566         spin_lock_irqsave(&chip->reg_lock, flags);
2567         if (up) {
2568                 if ((chip->midcr & MIDCR_RIE) == 0) {
2569                         chip->midcr |= MIDCR_RIE;
2570                         snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2571                 }
2572         } else {
2573                 if (chip->midcr & MIDCR_RIE) {
2574                         chip->midcr &= ~MIDCR_RIE;
2575                         snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2576                 }
2577         }
2578         spin_unlock_irqrestore(&chip->reg_lock, flags);
2579 }
2580
2581 static void snd_cs46xx_midi_output_trigger(struct snd_rawmidi_substream *substream, int up)
2582 {
2583         unsigned long flags;
2584         struct snd_cs46xx *chip = substream->rmidi->private_data;
2585         unsigned char byte;
2586
2587         spin_lock_irqsave(&chip->reg_lock, flags);
2588         if (up) {
2589                 if ((chip->midcr & MIDCR_TIE) == 0) {
2590                         chip->midcr |= MIDCR_TIE;
2591                         /* fill UART FIFO buffer at first, and turn Tx interrupts only if necessary */
2592                         while ((chip->midcr & MIDCR_TIE) &&
2593                                (snd_cs46xx_peekBA0(chip, BA0_MIDSR) & MIDSR_TBF) == 0) {
2594                                 if (snd_rawmidi_transmit(substream, &byte, 1) != 1) {
2595                                         chip->midcr &= ~MIDCR_TIE;
2596                                 } else {
2597                                         snd_cs46xx_pokeBA0(chip, BA0_MIDWP, byte);
2598                                 }
2599                         }
2600                         snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2601                 }
2602         } else {
2603                 if (chip->midcr & MIDCR_TIE) {
2604                         chip->midcr &= ~MIDCR_TIE;
2605                         snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2606                 }
2607         }
2608         spin_unlock_irqrestore(&chip->reg_lock, flags);
2609 }
2610
2611 static struct snd_rawmidi_ops snd_cs46xx_midi_output =
2612 {
2613         .open =         snd_cs46xx_midi_output_open,
2614         .close =        snd_cs46xx_midi_output_close,
2615         .trigger =      snd_cs46xx_midi_output_trigger,
2616 };
2617
2618 static struct snd_rawmidi_ops snd_cs46xx_midi_input =
2619 {
2620         .open =         snd_cs46xx_midi_input_open,
2621         .close =        snd_cs46xx_midi_input_close,
2622         .trigger =      snd_cs46xx_midi_input_trigger,
2623 };
2624
2625 int __devinit snd_cs46xx_midi(struct snd_cs46xx *chip, int device, struct snd_rawmidi **rrawmidi)
2626 {
2627         struct snd_rawmidi *rmidi;
2628         int err;
2629
2630         if (rrawmidi)
2631                 *rrawmidi = NULL;
2632         if ((err = snd_rawmidi_new(chip->card, "CS46XX", device, 1, 1, &rmidi)) < 0)
2633                 return err;
2634         strcpy(rmidi->name, "CS46XX");
2635         snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_OUTPUT, &snd_cs46xx_midi_output);
2636         snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_INPUT, &snd_cs46xx_midi_input);
2637         rmidi->info_flags |= SNDRV_RAWMIDI_INFO_OUTPUT | SNDRV_RAWMIDI_INFO_INPUT | SNDRV_RAWMIDI_INFO_DUPLEX;
2638         rmidi->private_data = chip;
2639         chip->rmidi = rmidi;
2640         if (rrawmidi)
2641                 *rrawmidi = NULL;
2642         return 0;
2643 }
2644
2645
2646 /*
2647  * gameport interface
2648  */
2649
2650 #if defined(CONFIG_GAMEPORT) || (defined(MODULE) && defined(CONFIG_GAMEPORT_MODULE))
2651
2652 static void snd_cs46xx_gameport_trigger(struct gameport *gameport)
2653 {
2654         struct snd_cs46xx *chip = gameport_get_port_data(gameport);
2655
2656         snd_assert(chip, return);
2657         snd_cs46xx_pokeBA0(chip, BA0_JSPT, 0xFF);  //outb(gameport->io, 0xFF);
2658 }
2659
2660 static unsigned char snd_cs46xx_gameport_read(struct gameport *gameport)
2661 {
2662         struct snd_cs46xx *chip = gameport_get_port_data(gameport);
2663
2664         snd_assert(chip, return 0);
2665         return snd_cs46xx_peekBA0(chip, BA0_JSPT); //inb(gameport->io);
2666 }
2667
2668 static int snd_cs46xx_gameport_cooked_read(struct gameport *gameport, int *axes, int *buttons)
2669 {
2670         struct snd_cs46xx *chip = gameport_get_port_data(gameport);
2671         unsigned js1, js2, jst;
2672
2673         snd_assert(chip, return 0);
2674
2675         js1 = snd_cs46xx_peekBA0(chip, BA0_JSC1);
2676         js2 = snd_cs46xx_peekBA0(chip, BA0_JSC2);
2677         jst = snd_cs46xx_peekBA0(chip, BA0_JSPT);
2678
2679         *buttons = (~jst >> 4) & 0x0F;
2680
2681         axes[0] = ((js1 & JSC1_Y1V_MASK) >> JSC1_Y1V_SHIFT) & 0xFFFF;
2682         axes[1] = ((js1 & JSC1_X1V_MASK) >> JSC1_X1V_SHIFT) & 0xFFFF;
2683         axes[2] = ((js2 & JSC2_Y2V_MASK) >> JSC2_Y2V_SHIFT) & 0xFFFF;
2684         axes[3] = ((js2 & JSC2_X2V_MASK) >> JSC2_X2V_SHIFT) & 0xFFFF;
2685
2686         for(jst=0;jst<4;++jst)
2687                 if(axes[jst]==0xFFFF) axes[jst] = -1;
2688         return 0;
2689 }
2690
2691 static int snd_cs46xx_gameport_open(struct gameport *gameport, int mode)
2692 {
2693         switch (mode) {
2694         case GAMEPORT_MODE_COOKED:
2695                 return 0;
2696         case GAMEPORT_MODE_RAW:
2697                 return 0;
2698         default:
2699                 return -1;
2700         }
2701         return 0;
2702 }
2703
2704 int __devinit snd_cs46xx_gameport(struct snd_cs46xx *chip)
2705 {
2706         struct gameport *gp;
2707
2708         chip->gameport = gp = gameport_allocate_port();
2709         if (!gp) {
2710                 printk(KERN_ERR "cs46xx: cannot allocate memory for gameport\n");
2711                 return -ENOMEM;
2712         }
2713
2714         gameport_set_name(gp, "CS46xx Gameport");
2715         gameport_set_phys(gp, "pci%s/gameport0", pci_name(chip->pci));
2716         gameport_set_dev_parent(gp, &chip->pci->dev);
2717         gameport_set_port_data(gp, chip);
2718
2719         gp->open = snd_cs46xx_gameport_open;
2720         gp->read = snd_cs46xx_gameport_read;
2721         gp->trigger = snd_cs46xx_gameport_trigger;
2722         gp->cooked_read = snd_cs46xx_gameport_cooked_read;
2723
2724         snd_cs46xx_pokeBA0(chip, BA0_JSIO, 0xFF); // ?
2725         snd_cs46xx_pokeBA0(chip, BA0_JSCTL, JSCTL_SP_MEDIUM_SLOW);
2726
2727         gameport_register_port(gp);
2728
2729         return 0;
2730 }
2731
2732 static inline void snd_cs46xx_remove_gameport(struct snd_cs46xx *chip)
2733 {
2734         if (chip->gameport) {
2735                 gameport_unregister_port(chip->gameport);
2736                 chip->gameport = NULL;
2737         }
2738 }
2739 #else
2740 int __devinit snd_cs46xx_gameport(struct snd_cs46xx *chip) { return -ENOSYS; }
2741 static inline void snd_cs46xx_remove_gameport(struct snd_cs46xx *chip) { }
2742 #endif /* CONFIG_GAMEPORT */
2743
2744 #ifdef CONFIG_PROC_FS
2745 /*
2746  *  proc interface
2747  */
2748
2749 static long snd_cs46xx_io_read(struct snd_info_entry *entry, void *file_private_data,
2750                                struct file *file, char __user *buf,
2751                                unsigned long count, unsigned long pos)
2752 {
2753         long size;
2754         struct snd_cs46xx_region *region = entry->private_data;
2755
2756         size = count;
2757         if (pos + (size_t)size > region->size)
2758                 size = region->size - pos;
2759         if (size > 0) {
2760                 if (copy_to_user_fromio(buf, region->remap_addr + pos, size))
2761                         return -EFAULT;
2762         }
2763         return size;
2764 }
2765
2766 static struct snd_info_entry_ops snd_cs46xx_proc_io_ops = {
2767         .read = snd_cs46xx_io_read,
2768 };
2769
2770 static int __devinit snd_cs46xx_proc_init(struct snd_card *card, struct snd_cs46xx *chip)
2771 {
2772         struct snd_info_entry *entry;
2773         int idx;
2774
2775         for (idx = 0; idx < 5; idx++) {
2776                 struct snd_cs46xx_region *region = &chip->region.idx[idx];
2777                 if (! snd_card_proc_new(card, region->name, &entry)) {
2778                         entry->content = SNDRV_INFO_CONTENT_DATA;
2779                         entry->private_data = chip;
2780                         entry->c.ops = &snd_cs46xx_proc_io_ops;
2781                         entry->size = region->size;
2782                         entry->mode = S_IFREG | S_IRUSR;
2783                 }
2784         }
2785 #ifdef CONFIG_SND_CS46XX_NEW_DSP
2786         cs46xx_dsp_proc_init(card, chip);
2787 #endif
2788         return 0;
2789 }
2790
2791 static int snd_cs46xx_proc_done(struct snd_cs46xx *chip)
2792 {
2793 #ifdef CONFIG_SND_CS46XX_NEW_DSP
2794         cs46xx_dsp_proc_done(chip);
2795 #endif
2796         return 0;
2797 }
2798 #else /* !CONFIG_PROC_FS */
2799 #define snd_cs46xx_proc_init(card, chip)
2800 #define snd_cs46xx_proc_done(chip)
2801 #endif
2802
2803 /*
2804  * stop the h/w
2805  */
2806 static void snd_cs46xx_hw_stop(struct snd_cs46xx *chip)
2807 {
2808         unsigned int tmp;
2809
2810         tmp = snd_cs46xx_peek(chip, BA1_PFIE);
2811         tmp &= ~0x0000f03f;
2812         tmp |=  0x00000010;
2813         snd_cs46xx_poke(chip, BA1_PFIE, tmp);   /* playback interrupt disable */
2814
2815         tmp = snd_cs46xx_peek(chip, BA1_CIE);
2816         tmp &= ~0x0000003f;
2817         tmp |=  0x00000011;
2818         snd_cs46xx_poke(chip, BA1_CIE, tmp);    /* capture interrupt disable */
2819
2820         /*
2821          *  Stop playback DMA.
2822          */
2823         tmp = snd_cs46xx_peek(chip, BA1_PCTL);
2824         snd_cs46xx_poke(chip, BA1_PCTL, tmp & 0x0000ffff);
2825
2826         /*
2827          *  Stop capture DMA.
2828          */
2829         tmp = snd_cs46xx_peek(chip, BA1_CCTL);
2830         snd_cs46xx_poke(chip, BA1_CCTL, tmp & 0xffff0000);
2831
2832         /*
2833          *  Reset the processor.
2834          */
2835         snd_cs46xx_reset(chip);
2836
2837         snd_cs46xx_proc_stop(chip);
2838
2839         /*
2840          *  Power down the PLL.
2841          */
2842         snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, 0);
2843
2844         /*
2845          *  Turn off the Processor by turning off the software clock enable flag in
2846          *  the clock control register.
2847          */
2848         tmp = snd_cs46xx_peekBA0(chip, BA0_CLKCR1) & ~CLKCR1_SWCE;
2849         snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp);
2850 }
2851
2852
2853 static int snd_cs46xx_free(struct snd_cs46xx *chip)
2854 {
2855         int idx;
2856
2857         snd_assert(chip != NULL, return -EINVAL);
2858
2859         if (chip->active_ctrl)
2860                 chip->active_ctrl(chip, 1);
2861
2862         snd_cs46xx_remove_gameport(chip);
2863
2864         if (chip->amplifier_ctrl)
2865                 chip->amplifier_ctrl(chip, -chip->amplifier); /* force to off */
2866
2867         snd_cs46xx_proc_done(chip);
2868
2869         if (chip->region.idx[0].resource)
2870                 snd_cs46xx_hw_stop(chip);
2871
2872         if (chip->irq >= 0)
2873                 free_irq(chip->irq, chip);
2874
2875         for (idx = 0; idx < 5; idx++) {
2876                 struct snd_cs46xx_region *region = &chip->region.idx[idx];
2877                 if (region->remap_addr)
2878                         iounmap(region->remap_addr);
2879                 release_and_free_resource(region->resource);
2880         }
2881
2882         if (chip->active_ctrl)
2883                 chip->active_ctrl(chip, -chip->amplifier);
2884
2885 #ifdef CONFIG_SND_CS46XX_NEW_DSP
2886         if (chip->dsp_spos_instance) {
2887                 cs46xx_dsp_spos_destroy(chip);
2888                 chip->dsp_spos_instance = NULL;
2889         }
2890 #endif
2891
2892 #ifdef CONFIG_PM
2893         kfree(chip->saved_regs);
2894 #endif
2895
2896         pci_disable_device(chip->pci);
2897         kfree(chip);
2898         return 0;
2899 }
2900
2901 static int snd_cs46xx_dev_free(struct snd_device *device)
2902 {
2903         struct snd_cs46xx *chip = device->device_data;
2904         return snd_cs46xx_free(chip);
2905 }
2906
2907 /*
2908  *  initialize chip
2909  */
2910 static int snd_cs46xx_chip_init(struct snd_cs46xx *chip)
2911 {
2912         int timeout;
2913
2914         /*
2915          *  First, blast the clock control register to zero so that the PLL starts
2916          *  out in a known state, and blast the master serial port control register
2917          *  to zero so that the serial ports also start out in a known state.
2918          */
2919         snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, 0);
2920         snd_cs46xx_pokeBA0(chip, BA0_SERMC1, 0);
2921
2922         /*
2923          *  If we are in AC97 mode, then we must set the part to a host controlled
2924          *  AC-link.  Otherwise, we won't be able to bring up the link.
2925          */
2926 #ifdef CONFIG_SND_CS46XX_NEW_DSP
2927         snd_cs46xx_pokeBA0(chip, BA0_SERACC, SERACC_HSP | SERACC_CHIP_TYPE_2_0 |
2928                            SERACC_TWO_CODECS);  /* 2.00 dual codecs */
2929         /* snd_cs46xx_pokeBA0(chip, BA0_SERACC, SERACC_HSP | SERACC_CHIP_TYPE_2_0); */ /* 2.00 codec */
2930 #else
2931         snd_cs46xx_pokeBA0(chip, BA0_SERACC, SERACC_HSP | SERACC_CHIP_TYPE_1_03); /* 1.03 codec */
2932 #endif
2933
2934         /*
2935          *  Drive the ARST# pin low for a minimum of 1uS (as defined in the AC97
2936          *  spec) and then drive it high.  This is done for non AC97 modes since
2937          *  there might be logic external to the CS461x that uses the ARST# line
2938          *  for a reset.
2939          */
2940         snd_cs46xx_pokeBA0(chip, BA0_ACCTL, 0);
2941 #ifdef CONFIG_SND_CS46XX_NEW_DSP
2942         snd_cs46xx_pokeBA0(chip, BA0_ACCTL2, 0);
2943 #endif
2944         udelay(50);
2945         snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_RSTN);
2946 #ifdef CONFIG_SND_CS46XX_NEW_DSP
2947         snd_cs46xx_pokeBA0(chip, BA0_ACCTL2, ACCTL_RSTN);
2948 #endif
2949
2950         /*
2951          *  The first thing we do here is to enable sync generation.  As soon
2952          *  as we start receiving bit clock, we'll start producing the SYNC
2953          *  signal.
2954          */
2955         snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_ESYN | ACCTL_RSTN);
2956 #ifdef CONFIG_SND_CS46XX_NEW_DSP
2957         snd_cs46xx_pokeBA0(chip, BA0_ACCTL2, ACCTL_ESYN | ACCTL_RSTN);
2958 #endif
2959
2960         /*
2961          *  Now wait for a short while to allow the AC97 part to start
2962          *  generating bit clock (so we don't try to start the PLL without an
2963          *  input clock).
2964          */
2965         mdelay(10);
2966
2967         /*
2968          *  Set the serial port timing configuration, so that
2969          *  the clock control circuit gets its clock from the correct place.
2970          */
2971         snd_cs46xx_pokeBA0(chip, BA0_SERMC1, SERMC1_PTC_AC97);
2972
2973         /*
2974          *  Write the selected clock control setup to the hardware.  Do not turn on
2975          *  SWCE yet (if requested), so that the devices clocked by the output of
2976          *  PLL are not clocked until the PLL is stable.
2977          */
2978         snd_cs46xx_pokeBA0(chip, BA0_PLLCC, PLLCC_LPF_1050_2780_KHZ | PLLCC_CDR_73_104_MHZ);
2979         snd_cs46xx_pokeBA0(chip, BA0_PLLM, 0x3a);
2980         snd_cs46xx_pokeBA0(chip, BA0_CLKCR2, CLKCR2_PDIVS_8);
2981
2982         /*
2983          *  Power up the PLL.
2984          */
2985         snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, CLKCR1_PLLP);
2986
2987         /*
2988          *  Wait until the PLL has stabilized.
2989          */
2990         msleep(100);
2991
2992         /*
2993          *  Turn on clocking of the core so that we can setup the serial ports.
2994          */
2995         snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, CLKCR1_PLLP | CLKCR1_SWCE);
2996
2997         /*
2998          * Enable FIFO  Host Bypass
2999          */
3000         snd_cs46xx_pokeBA0(chip, BA0_SERBCF, SERBCF_HBP);
3001
3002         /*
3003          *  Fill the serial port FIFOs with silence.
3004          */
3005         snd_cs46xx_clear_serial_FIFOs(chip);
3006
3007         /*
3008          *  Set the serial port FIFO pointer to the first sample in the FIFO.
3009          */
3010         /* snd_cs46xx_pokeBA0(chip, BA0_SERBSP, 0); */
3011
3012         /*
3013          *  Write the serial port configuration to the part.  The master
3014          *  enable bit is not set until all other values have been written.
3015          */
3016         snd_cs46xx_pokeBA0(chip, BA0_SERC1, SERC1_SO1F_AC97 | SERC1_SO1EN);
3017         snd_cs46xx_pokeBA0(chip, BA0_SERC2, SERC2_SI1F_AC97 | SERC1_SO1EN);
3018         snd_cs46xx_pokeBA0(chip, BA0_SERMC1, SERMC1_PTC_AC97 | SERMC1_MSPE);
3019
3020
3021 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3022         snd_cs46xx_pokeBA0(chip, BA0_SERC7, SERC7_ASDI2EN);
3023         snd_cs46xx_pokeBA0(chip, BA0_SERC3, 0);
3024         snd_cs46xx_pokeBA0(chip, BA0_SERC4, 0);
3025         snd_cs46xx_pokeBA0(chip, BA0_SERC5, 0);
3026         snd_cs46xx_pokeBA0(chip, BA0_SERC6, 1);
3027 #endif
3028
3029         mdelay(5);
3030
3031
3032         /*
3033          * Wait for the codec ready signal from the AC97 codec.
3034          */
3035         timeout = 150;
3036         while (timeout-- > 0) {
3037                 /*
3038                  *  Read the AC97 status register to see if we've seen a CODEC READY
3039                  *  signal from the AC97 codec.
3040                  */
3041                 if (snd_cs46xx_peekBA0(chip, BA0_ACSTS) & ACSTS_CRDY)
3042                         goto ok1;
3043                 msleep(10);
3044         }
3045
3046
3047         snd_printk(KERN_ERR "create - never read codec ready from AC'97\n");
3048         snd_printk(KERN_ERR "it is not probably bug, try to use CS4236 driver\n");
3049         return -EIO;
3050  ok1:
3051 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3052         {
3053                 int count;
3054                 for (count = 0; count < 150; count++) {
3055                         /* First, we want to wait for a short time. */
3056                         udelay(25);
3057
3058                         if (snd_cs46xx_peekBA0(chip, BA0_ACSTS2) & ACSTS_CRDY)
3059                                 break;
3060                 }
3061
3062                 /*
3063                  *  Make sure CODEC is READY.
3064                  */
3065                 if (!(snd_cs46xx_peekBA0(chip, BA0_ACSTS2) & ACSTS_CRDY))
3066                         snd_printdd("cs46xx: never read card ready from secondary AC'97\n");
3067         }
3068 #endif
3069
3070         /*
3071          *  Assert the vaid frame signal so that we can start sending commands
3072          *  to the AC97 codec.
3073          */
3074         snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN);
3075 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3076         snd_cs46xx_pokeBA0(chip, BA0_ACCTL2, ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN);
3077 #endif
3078
3079
3080         /*
3081          *  Wait until we've sampled input slots 3 and 4 as valid, meaning that
3082          *  the codec is pumping ADC data across the AC-link.
3083          */
3084         timeout = 150;
3085         while (timeout-- > 0) {
3086                 /*
3087                  *  Read the input slot valid register and see if input slots 3 and
3088                  *  4 are valid yet.
3089                  */
3090                 if ((snd_cs46xx_peekBA0(chip, BA0_ACISV) & (ACISV_ISV3 | ACISV_ISV4)) == (ACISV_ISV3 | ACISV_ISV4))
3091                         goto ok2;
3092                 msleep(10);
3093         }
3094
3095 #ifndef CONFIG_SND_CS46XX_NEW_DSP
3096         snd_printk(KERN_ERR "create - never read ISV3 & ISV4 from AC'97\n");
3097         return -EIO;
3098 #else
3099         /* This may happen on a cold boot with a Terratec SiXPack 5.1.
3100            Reloading the driver may help, if there's other soundcards
3101            with the same problem I would like to know. (Benny) */
3102
3103         snd_printk(KERN_ERR "ERROR: snd-cs46xx: never read ISV3 & ISV4 from AC'97\n");
3104         snd_printk(KERN_ERR "       Try reloading the ALSA driver, if you find something\n");
3105         snd_printk(KERN_ERR "       broken or not working on your soundcard upon\n");
3106         snd_printk(KERN_ERR "       this message please report to alsa-devel@alsa-project.org\n");
3107
3108         return -EIO;
3109 #endif
3110  ok2:
3111
3112         /*
3113          *  Now, assert valid frame and the slot 3 and 4 valid bits.  This will
3114          *  commense the transfer of digital audio data to the AC97 codec.
3115          */
3116
3117         snd_cs46xx_pokeBA0(chip, BA0_ACOSV, ACOSV_SLV3 | ACOSV_SLV4);
3118
3119
3120         /*
3121          *  Power down the DAC and ADC.  We will power them up (if) when we need
3122          *  them.
3123          */
3124         /* snd_cs46xx_pokeBA0(chip, BA0_AC97_POWERDOWN, 0x300); */
3125
3126         /*
3127          *  Turn off the Processor by turning off the software clock enable flag in
3128          *  the clock control register.
3129          */
3130         /* tmp = snd_cs46xx_peekBA0(chip, BA0_CLKCR1) & ~CLKCR1_SWCE; */
3131         /* snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp); */
3132
3133         return 0;
3134 }
3135
3136 /*
3137  *  start and load DSP
3138  */
3139
3140 static void cs46xx_enable_stream_irqs(struct snd_cs46xx *chip)
3141 {
3142         unsigned int tmp;
3143
3144         snd_cs46xx_pokeBA0(chip, BA0_HICR, HICR_IEV | HICR_CHGM);
3145
3146         tmp = snd_cs46xx_peek(chip, BA1_PFIE);
3147         tmp &= ~0x0000f03f;
3148         snd_cs46xx_poke(chip, BA1_PFIE, tmp);   /* playback interrupt enable */
3149
3150         tmp = snd_cs46xx_peek(chip, BA1_CIE);
3151         tmp &= ~0x0000003f;
3152         tmp |=  0x00000001;
3153         snd_cs46xx_poke(chip, BA1_CIE, tmp);    /* capture interrupt enable */
3154 }
3155
3156 int __devinit snd_cs46xx_start_dsp(struct snd_cs46xx *chip)
3157 {
3158         unsigned int tmp;
3159         /*
3160          *  Reset the processor.
3161          */
3162         snd_cs46xx_reset(chip);
3163         /*
3164          *  Download the image to the processor.
3165          */
3166 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3167 #if 0
3168         if (cs46xx_dsp_load_module(chip, &cwcemb80_module) < 0) {
3169                 snd_printk(KERN_ERR "image download error\n");
3170                 return -EIO;
3171         }
3172 #endif
3173
3174         if (cs46xx_dsp_load_module(chip, &cwc4630_module) < 0) {
3175                 snd_printk(KERN_ERR "image download error [cwc4630]\n");
3176                 return -EIO;
3177         }
3178
3179         if (cs46xx_dsp_load_module(chip, &cwcasync_module) < 0) {
3180                 snd_printk(KERN_ERR "image download error [cwcasync]\n");
3181                 return -EIO;
3182         }
3183
3184         if (cs46xx_dsp_load_module(chip, &cwcsnoop_module) < 0) {
3185                 snd_printk(KERN_ERR "image download error [cwcsnoop]\n");
3186                 return -EIO;
3187         }
3188
3189         if (cs46xx_dsp_load_module(chip, &cwcbinhack_module) < 0) {
3190                 snd_printk(KERN_ERR "image download error [cwcbinhack]\n");
3191                 return -EIO;
3192         }
3193
3194         if (cs46xx_dsp_load_module(chip, &cwcdma_module) < 0) {
3195                 snd_printk(KERN_ERR "image download error [cwcdma]\n");
3196                 return -EIO;
3197         }
3198
3199         if (cs46xx_dsp_scb_and_task_init(chip) < 0)
3200                 return -EIO;
3201 #else
3202         /* old image */
3203         if (snd_cs46xx_download_image(chip) < 0) {
3204                 snd_printk(KERN_ERR "image download error\n");
3205                 return -EIO;
3206         }
3207
3208         /*
3209          *  Stop playback DMA.
3210          */
3211         tmp = snd_cs46xx_peek(chip, BA1_PCTL);
3212         chip->play_ctl = tmp & 0xffff0000;
3213         snd_cs46xx_poke(chip, BA1_PCTL, tmp & 0x0000ffff);
3214 #endif
3215
3216         /*
3217          *  Stop capture DMA.
3218          */
3219         tmp = snd_cs46xx_peek(chip, BA1_CCTL);
3220         chip->capt.ctl = tmp & 0x0000ffff;
3221         snd_cs46xx_poke(chip, BA1_CCTL, tmp & 0xffff0000);
3222
3223         mdelay(5);
3224
3225         snd_cs46xx_set_play_sample_rate(chip, 8000);
3226         snd_cs46xx_set_capture_sample_rate(chip, 8000);
3227
3228         snd_cs46xx_proc_start(chip);
3229
3230         cs46xx_enable_stream_irqs(chip);
3231
3232 #ifndef CONFIG_SND_CS46XX_NEW_DSP
3233         /* set the attenuation to 0dB */
3234         snd_cs46xx_poke(chip, BA1_PVOL, 0x80008000);
3235         snd_cs46xx_poke(chip, BA1_CVOL, 0x80008000);
3236 #endif
3237
3238         return 0;
3239 }
3240
3241
3242 /*
3243  *      AMP control - null AMP
3244  */
3245
3246 static void amp_none(struct snd_cs46xx *chip, int change)
3247 {
3248 }
3249
3250 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3251 static int voyetra_setup_eapd_slot(struct snd_cs46xx *chip)
3252 {
3253
3254         u32 idx, valid_slots,tmp,powerdown = 0;
3255         u16 modem_power,pin_config,logic_type;
3256
3257         snd_printdd ("cs46xx: cs46xx_setup_eapd_slot()+\n");
3258
3259         /*
3260          *  See if the devices are powered down.  If so, we must power them up first
3261          *  or they will not respond.
3262          */
3263         tmp = snd_cs46xx_peekBA0(chip, BA0_CLKCR1);
3264
3265         if (!(tmp & CLKCR1_SWCE)) {
3266                 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp | CLKCR1_SWCE);
3267                 powerdown = 1;
3268         }
3269
3270         /*
3271          * Clear PRA.  The Bonzo chip will be used for GPIO not for modem
3272          * stuff.
3273          */
3274         if(chip->nr_ac97_codecs != 2) {
3275                 snd_printk (KERN_ERR "cs46xx: cs46xx_setup_eapd_slot() - no secondary codec configured\n");
3276                 return -EINVAL;
3277         }
3278
3279         modem_power = snd_cs46xx_codec_read (chip,
3280                                              AC97_EXTENDED_MSTATUS,
3281                                              CS46XX_SECONDARY_CODEC_INDEX);
3282         modem_power &=0xFEFF;
3283
3284         snd_cs46xx_codec_write(chip,
3285                                AC97_EXTENDED_MSTATUS, modem_power,
3286                                CS46XX_SECONDARY_CODEC_INDEX);
3287
3288         /*
3289          * Set GPIO pin's 7 and 8 so that they are configured for output.
3290          */
3291         pin_config = snd_cs46xx_codec_read (chip,
3292                                             AC97_GPIO_CFG,
3293                                             CS46XX_SECONDARY_CODEC_INDEX);
3294         pin_config &=0x27F;
3295
3296         snd_cs46xx_codec_write(chip,
3297                                AC97_GPIO_CFG, pin_config,
3298                                CS46XX_SECONDARY_CODEC_INDEX);
3299
3300         /*
3301          * Set GPIO pin's 7 and 8 so that they are compatible with CMOS logic.
3302          */
3303
3304         logic_type = snd_cs46xx_codec_read(chip, AC97_GPIO_POLARITY,
3305                                            CS46XX_SECONDARY_CODEC_INDEX);
3306         logic_type &=0x27F;
3307
3308         snd_cs46xx_codec_write (chip, AC97_GPIO_POLARITY, logic_type,
3309                                 CS46XX_SECONDARY_CODEC_INDEX);
3310
3311         valid_slots = snd_cs46xx_peekBA0(chip, BA0_ACOSV);
3312         valid_slots |= 0x200;
3313         snd_cs46xx_pokeBA0(chip, BA0_ACOSV, valid_slots);
3314
3315         if ( cs46xx_wait_for_fifo(chip,1) ) {
3316           snd_printdd("FIFO is busy\n");
3317
3318           return -EINVAL;
3319         }
3320
3321         /*
3322          * Fill slots 12 with the correct value for the GPIO pins.
3323          */
3324         for(idx = 0x90; idx <= 0x9F; idx++) {
3325                 /*
3326                  * Initialize the fifo so that bits 7 and 8 are on.
3327                  *
3328                  * Remember that the GPIO pins in bonzo are shifted by 4 bits to
3329                  * the left.  0x1800 corresponds to bits 7 and 8.
3330                  */
3331                 snd_cs46xx_pokeBA0(chip, BA0_SERBWP, 0x1800);
3332
3333                 /*
3334                  * Wait for command to complete
3335                  */
3336                 if ( cs46xx_wait_for_fifo(chip,200) ) {
3337                         snd_printdd("failed waiting for FIFO at addr (%02X)\n",idx);
3338
3339                         return -EINVAL;
3340                 }
3341
3342                 /*
3343                  * Write the serial port FIFO index.
3344                  */
3345                 snd_cs46xx_pokeBA0(chip, BA0_SERBAD, idx);
3346
3347                 /*
3348                  * Tell the serial port to load the new value into the FIFO location.
3349                  */
3350                 snd_cs46xx_pokeBA0(chip, BA0_SERBCM, SERBCM_WRC);
3351         }
3352
3353         /* wait for last command to complete */
3354         cs46xx_wait_for_fifo(chip,200);
3355
3356         /*
3357          *  Now, if we powered up the devices, then power them back down again.
3358          *  This is kinda ugly, but should never happen.
3359          */
3360         if (powerdown)
3361                 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp);
3362
3363         return 0;
3364 }
3365 #endif
3366
3367 /*
3368  *      Crystal EAPD mode
3369  */
3370
3371 static void amp_voyetra(struct snd_cs46xx *chip, int change)
3372 {
3373         /* Manage the EAPD bit on the Crystal 4297
3374            and the Analog AD1885 */
3375
3376 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3377         int old = chip->amplifier;
3378 #endif
3379         int oval, val;
3380
3381         chip->amplifier += change;
3382         oval = snd_cs46xx_codec_read(chip, AC97_POWERDOWN,
3383                                      CS46XX_PRIMARY_CODEC_INDEX);
3384         val = oval;
3385         if (chip->amplifier) {
3386                 /* Turn the EAPD amp on */
3387                 val |= 0x8000;
3388         } else {
3389                 /* Turn the EAPD amp off */
3390                 val &= ~0x8000;
3391         }
3392         if (val != oval) {
3393                 snd_cs46xx_codec_write(chip, AC97_POWERDOWN, val,
3394                                        CS46XX_PRIMARY_CODEC_INDEX);
3395                 if (chip->eapd_switch)
3396                         snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE,
3397                                        &chip->eapd_switch->id);
3398         }
3399
3400 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3401         if (chip->amplifier && !old) {
3402                 voyetra_setup_eapd_slot(chip);
3403         }
3404 #endif
3405 }
3406
3407 static void hercules_init(struct snd_cs46xx *chip)
3408 {
3409         /* default: AMP off, and SPDIF input optical */
3410         snd_cs46xx_pokeBA0(chip, BA0_EGPIODR, EGPIODR_GPOE0);
3411         snd_cs46xx_pokeBA0(chip, BA0_EGPIOPTR, EGPIODR_GPOE0);
3412 }
3413
3414
3415 /*
3416  *      Game Theatre XP card - EGPIO[2] is used to enable the external amp.
3417  */
3418 static void amp_hercules(struct snd_cs46xx *chip, int change)
3419 {
3420         int old = chip->amplifier;
3421         int val1 = snd_cs46xx_peekBA0(chip, BA0_EGPIODR);
3422         int val2 = snd_cs46xx_peekBA0(chip, BA0_EGPIOPTR);
3423
3424         chip->amplifier += change;
3425         if (chip->amplifier && !old) {
3426                 snd_printdd ("Hercules amplifier ON\n");
3427
3428                 snd_cs46xx_pokeBA0(chip, BA0_EGPIODR,
3429                                    EGPIODR_GPOE2 | val1);     /* enable EGPIO2 output */
3430                 snd_cs46xx_pokeBA0(chip, BA0_EGPIOPTR,
3431                                    EGPIOPTR_GPPT2 | val2);   /* open-drain on output */
3432         } else if (old && !chip->amplifier) {
3433                 snd_printdd ("Hercules amplifier OFF\n");
3434                 snd_cs46xx_pokeBA0(chip, BA0_EGPIODR,  val1 & ~EGPIODR_GPOE2); /* disable */
3435                 snd_cs46xx_pokeBA0(chip, BA0_EGPIOPTR, val2 & ~EGPIOPTR_GPPT2); /* disable */
3436         }
3437 }
3438
3439 static void voyetra_mixer_init (struct snd_cs46xx *chip)
3440 {
3441         snd_printdd ("initializing Voyetra mixer\n");
3442
3443         /* Enable SPDIF out */
3444         snd_cs46xx_pokeBA0(chip, BA0_EGPIODR, EGPIODR_GPOE0);
3445         snd_cs46xx_pokeBA0(chip, BA0_EGPIOPTR, EGPIODR_GPOE0);
3446 }
3447
3448 static void hercules_mixer_init (struct snd_cs46xx *chip)
3449 {
3450 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3451         unsigned int idx;
3452         int err;
3453         struct snd_card *card = chip->card;
3454 #endif
3455
3456         /* set EGPIO to default */
3457         hercules_init(chip);
3458
3459         snd_printdd ("initializing Hercules mixer\n");
3460
3461 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3462         if (chip->in_suspend)
3463                 return;
3464
3465         for (idx = 0 ; idx < ARRAY_SIZE(snd_hercules_controls); idx++) {
3466                 struct snd_kcontrol *kctl;
3467
3468                 kctl = snd_ctl_new1(&snd_hercules_controls[idx], chip);
3469                 if ((err = snd_ctl_add(card, kctl)) < 0) {
3470                         printk (KERN_ERR "cs46xx: failed to initialize Hercules mixer (%d)\n",err);
3471                         break;
3472                 }
3473         }
3474 #endif
3475 }
3476
3477
3478 #if 0
3479 /*
3480  *      Untested
3481  */
3482
3483 static void amp_voyetra_4294(struct snd_cs46xx *chip, int change)
3484 {
3485         chip->amplifier += change;
3486
3487         if (chip->amplifier) {
3488                 /* Switch the GPIO pins 7 and 8 to open drain */
3489                 snd_cs46xx_codec_write(chip, 0x4C,
3490                                        snd_cs46xx_codec_read(chip, 0x4C) & 0xFE7F);
3491                 snd_cs46xx_codec_write(chip, 0x4E,
3492                                        snd_cs46xx_codec_read(chip, 0x4E) | 0x0180);
3493                 /* Now wake the AMP (this might be backwards) */
3494                 snd_cs46xx_codec_write(chip, 0x54,
3495                                        snd_cs46xx_codec_read(chip, 0x54) & ~0x0180);
3496         } else {
3497                 snd_cs46xx_codec_write(chip, 0x54,
3498                                        snd_cs46xx_codec_read(chip, 0x54) | 0x0180);
3499         }
3500 }
3501 #endif
3502
3503
3504 /*
3505  *      Handle the CLKRUN on a thinkpad. We must disable CLKRUN support
3506  *      whenever we need to beat on the chip.
3507  *
3508  *      The original idea and code for this hack comes from David Kaiser at
3509  *      Linuxcare. Perhaps one day Crystal will document their chips well
3510  *      enough to make them useful.
3511  */
3512
3513 static void clkrun_hack(struct snd_cs46xx *chip, int change)
3514 {
3515         u16 control, nval;
3516
3517         if (!chip->acpi_port)
3518                 return;
3519
3520         chip->amplifier += change;
3521
3522         /* Read ACPI port */
3523         nval = control = inw(chip->acpi_port + 0x10);
3524
3525         /* Flip CLKRUN off while running */
3526         if (! chip->amplifier)
3527                 nval |= 0x2000;
3528         else
3529                 nval &= ~0x2000;
3530         if (nval != control)
3531                 outw(nval, chip->acpi_port + 0x10);
3532 }
3533
3534
3535 /*
3536  * detect intel piix4
3537  */
3538 static void clkrun_init(struct snd_cs46xx *chip)
3539 {
3540         struct pci_dev *pdev;
3541         u8 pp;
3542
3543         chip->acpi_port = 0;
3544
3545         pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
3546                 PCI_DEVICE_ID_INTEL_82371AB_3, NULL);
3547         if (pdev == NULL)
3548                 return;         /* Not a thinkpad thats for sure */
3549
3550         /* Find the control port */
3551         pci_read_config_byte(pdev, 0x41, &pp);
3552         chip->acpi_port = pp << 8;
3553         pci_dev_put(pdev);
3554 }
3555
3556
3557 /*
3558  * Card subid table
3559  */
3560
3561 struct cs_card_type
3562 {
3563         u16 vendor;
3564         u16 id;
3565         char *name;
3566         void (*init)(struct snd_cs46xx *);
3567         void (*amp)(struct snd_cs46xx *, int);
3568         void (*active)(struct snd_cs46xx *, int);
3569         void (*mixer_init)(struct snd_cs46xx *);
3570 };
3571
3572 static struct cs_card_type __devinitdata cards[] = {
3573         {
3574                 .vendor = 0x1489,
3575                 .id = 0x7001,
3576                 .name = "Genius Soundmaker 128 value",
3577                 /* nothing special */
3578         },
3579         {
3580                 .vendor = 0x5053,
3581                 .id = 0x3357,
3582                 .name = "Voyetra",
3583                 .amp = amp_voyetra,
3584                 .mixer_init = voyetra_mixer_init,
3585         },
3586         {
3587                 .vendor = 0x1071,
3588                 .id = 0x6003,
3589                 .name = "Mitac MI6020/21",
3590                 .amp = amp_voyetra,
3591         },
3592         {
3593                 .vendor = 0x14AF,
3594                 .id = 0x0050,
3595                 .name = "Hercules Game Theatre XP",
3596                 .amp = amp_hercules,
3597                 .mixer_init = hercules_mixer_init,
3598         },
3599         {
3600                 .vendor = 0x1681,
3601                 .id = 0x0050,
3602                 .name = "Hercules Game Theatre XP",
3603                 .amp = amp_hercules,
3604                 .mixer_init = hercules_mixer_init,
3605         },
3606         {
3607                 .vendor = 0x1681,
3608                 .id = 0x0051,
3609                 .name = "Hercules Game Theatre XP",
3610                 .amp = amp_hercules,
3611                 .mixer_init = hercules_mixer_init,
3612
3613         },
3614         {
3615                 .vendor = 0x1681,
3616                 .id = 0x0052,
3617                 .name = "Hercules Game Theatre XP",
3618                 .amp = amp_hercules,
3619                 .mixer_init = hercules_mixer_init,
3620         },
3621         {
3622                 .vendor = 0x1681,
3623                 .id = 0x0053,
3624                 .name = "Hercules Game Theatre XP",
3625                 .amp = amp_hercules,
3626                 .mixer_init = hercules_mixer_init,
3627         },
3628         {
3629                 .vendor = 0x1681,
3630                 .id = 0x0054,
3631                 .name = "Hercules Game Theatre XP",
3632                 .amp = amp_hercules,
3633                 .mixer_init = hercules_mixer_init,
3634         },
3635         /* Teratec */
3636         {
3637                 .vendor = 0x153b,
3638                 .id = 0x1136,
3639                 .name = "Terratec SiXPack 5.1",
3640         },
3641         /* Not sure if the 570 needs the clkrun hack */
3642         {
3643                 .vendor = PCI_VENDOR_ID_IBM,
3644                 .id = 0x0132,
3645                 .name = "Thinkpad 570",
3646                 .init = clkrun_init,
3647                 .active = clkrun_hack,
3648         },
3649         {
3650                 .vendor = PCI_VENDOR_ID_IBM,
3651                 .id = 0x0153,
3652                 .name = "Thinkpad 600X/A20/T20",
3653                 .init = clkrun_init,
3654                 .active = clkrun_hack,
3655         },
3656         {
3657                 .vendor = PCI_VENDOR_ID_IBM,
3658                 .id = 0x1010,
3659                 .name = "Thinkpad 600E (unsupported)",
3660         },
3661         {} /* terminator */
3662 };
3663
3664
3665 /*
3666  * APM support
3667  */
3668 #ifdef CONFIG_PM
3669 static unsigned int saved_regs[] = {
3670         BA0_ACOSV,
3671         BA0_ASER_FADDR,
3672         BA0_ASER_MASTER,
3673         BA1_PVOL,
3674         BA1_CVOL,
3675 };
3676
3677 int snd_cs46xx_suspend(struct pci_dev *pci, pm_message_t state)
3678 {
3679         struct snd_card *card = pci_get_drvdata(pci);
3680         struct snd_cs46xx *chip = card->private_data;
3681         int i, amp_saved;
3682
3683         snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
3684         chip->in_suspend = 1;
3685         snd_pcm_suspend_all(chip->pcm);
3686         // chip->ac97_powerdown = snd_cs46xx_codec_read(chip, AC97_POWER_CONTROL);
3687         // chip->ac97_general_purpose = snd_cs46xx_codec_read(chip, BA0_AC97_GENERAL_PURPOSE);
3688
3689         snd_ac97_suspend(chip->ac97[CS46XX_PRIMARY_CODEC_INDEX]);
3690         snd_ac97_suspend(chip->ac97[CS46XX_SECONDARY_CODEC_INDEX]);
3691
3692         /* save some registers */
3693         for (i = 0; i < ARRAY_SIZE(saved_regs); i++)
3694                 chip->saved_regs[i] = snd_cs46xx_peekBA0(chip, saved_regs[i]);
3695
3696         amp_saved = chip->amplifier;
3697         /* turn off amp */
3698         chip->amplifier_ctrl(chip, -chip->amplifier);
3699         snd_cs46xx_hw_stop(chip);
3700         /* disable CLKRUN */
3701         chip->active_ctrl(chip, -chip->amplifier);
3702         chip->amplifier = amp_saved; /* restore the status */
3703
3704         pci_disable_device(pci);
3705         pci_save_state(pci);
3706         pci_set_power_state(pci, pci_choose_state(pci, state));
3707         return 0;
3708 }
3709
3710 int snd_cs46xx_resume(struct pci_dev *pci)
3711 {
3712         struct snd_card *card = pci_get_drvdata(pci);
3713         struct snd_cs46xx *chip = card->private_data;
3714         int i, amp_saved;
3715
3716         pci_set_power_state(pci, PCI_D0);
3717         pci_restore_state(pci);
3718         if (pci_enable_device(pci) < 0) {
3719                 printk(KERN_ERR "cs46xx: pci_enable_device failed, "
3720                        "disabling device\n");
3721                 snd_card_disconnect(card);
3722                 return -EIO;
3723         }
3724         pci_set_master(pci);
3725
3726         amp_saved = chip->amplifier;
3727         chip->amplifier = 0;
3728         chip->active_ctrl(chip, 1); /* force to on */
3729
3730         snd_cs46xx_chip_init(chip);
3731
3732         snd_cs46xx_reset(chip);
3733 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3734         cs46xx_dsp_resume(chip);
3735         /* restore some registers */
3736         for (i = 0; i < ARRAY_SIZE(saved_regs); i++)
3737                 snd_cs46xx_pokeBA0(chip, saved_regs[i], chip->saved_regs[i]);
3738 #else
3739         snd_cs46xx_download_image(chip);
3740 #endif
3741
3742 #if 0
3743         snd_cs46xx_codec_write(chip, BA0_AC97_GENERAL_PURPOSE,
3744                                chip->ac97_general_purpose);
3745         snd_cs46xx_codec_write(chip, AC97_POWER_CONTROL,
3746                                chip->ac97_powerdown);
3747         mdelay(10);
3748         snd_cs46xx_codec_write(chip, BA0_AC97_POWERDOWN,
3749                                chip->ac97_powerdown);
3750         mdelay(5);
3751 #endif
3752
3753         snd_ac97_resume(chip->ac97[CS46XX_PRIMARY_CODEC_INDEX]);
3754         snd_ac97_resume(chip->ac97[CS46XX_SECONDARY_CODEC_INDEX]);
3755
3756         /* reset playback/capture */
3757         snd_cs46xx_set_play_sample_rate(chip, 8000);
3758         snd_cs46xx_set_capture_sample_rate(chip, 8000);
3759         snd_cs46xx_proc_start(chip);
3760
3761         cs46xx_enable_stream_irqs(chip);
3762
3763         if (amp_saved)
3764                 chip->amplifier_ctrl(chip, 1); /* turn amp on */
3765         else
3766                 chip->active_ctrl(chip, -1); /* disable CLKRUN */
3767         chip->amplifier = amp_saved;
3768         chip->in_suspend = 0;
3769         snd_power_change_state(card, SNDRV_CTL_POWER_D0);
3770         return 0;
3771 }
3772 #endif /* CONFIG_PM */
3773
3774
3775 /*
3776  */
3777
3778 int __devinit snd_cs46xx_create(struct snd_card *card,
3779                       struct pci_dev * pci,
3780                       int external_amp, int thinkpad,
3781                       struct snd_cs46xx ** rchip)
3782 {
3783         struct snd_cs46xx *chip;
3784         int err, idx;
3785         struct snd_cs46xx_region *region;
3786         struct cs_card_type *cp;
3787         u16 ss_card, ss_vendor;
3788         static struct snd_device_ops ops = {
3789                 .dev_free =     snd_cs46xx_dev_free,
3790         };
3791
3792         *rchip = NULL;
3793
3794         /* enable PCI device */
3795         if ((err = pci_enable_device(pci)) < 0)
3796                 return err;
3797
3798         chip = kzalloc(sizeof(*chip), GFP_KERNEL);
3799         if (chip == NULL) {
3800                 pci_disable_device(pci);
3801                 return -ENOMEM;
3802         }
3803         spin_lock_init(&chip->reg_lock);
3804 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3805         mutex_init(&chip->spos_mutex);
3806 #endif
3807         chip->card = card;
3808         chip->pci = pci;
3809         chip->irq = -1;
3810         chip->ba0_addr = pci_resource_start(pci, 0);
3811         chip->ba1_addr = pci_resource_start(pci, 1);
3812         if (chip->ba0_addr == 0 || chip->ba0_addr == (unsigned long)~0 ||
3813             chip->ba1_addr == 0 || chip->ba1_addr == (unsigned long)~0) {
3814                 snd_printk(KERN_ERR "wrong address(es) - ba0 = 0x%lx, ba1 = 0x%lx\n",
3815                            chip->ba0_addr, chip->ba1_addr);
3816                 snd_cs46xx_free(chip);
3817                 return -ENOMEM;
3818         }
3819
3820         region = &chip->region.name.ba0;
3821         strcpy(region->name, "CS46xx_BA0");
3822         region->base = chip->ba0_addr;
3823         region->size = CS46XX_BA0_SIZE;
3824
3825         region = &chip->region.name.data0;
3826         strcpy(region->name, "CS46xx_BA1_data0");
3827         region->base = chip->ba1_addr + BA1_SP_DMEM0;
3828         region->size = CS46XX_BA1_DATA0_SIZE;
3829
3830         region = &chip->region.name.data1;
3831         strcpy(region->name, "CS46xx_BA1_data1");
3832         region->base = chip->ba1_addr + BA1_SP_DMEM1;
3833         region->size = CS46XX_BA1_DATA1_SIZE;
3834
3835         region = &chip->region.name.pmem;
3836         strcpy(region->name, "CS46xx_BA1_pmem");
3837         region->base = chip->ba1_addr + BA1_SP_PMEM;
3838         region->size = CS46XX_BA1_PRG_SIZE;
3839
3840         region = &chip->region.name.reg;
3841         strcpy(region->name, "CS46xx_BA1_reg");
3842         region->base = chip->ba1_addr + BA1_SP_REG;
3843         region->size = CS46XX_BA1_REG_SIZE;
3844
3845         /* set up amp and clkrun hack */
3846         pci_read_config_word(pci, PCI_SUBSYSTEM_VENDOR_ID, &ss_vendor);
3847         pci_read_config_word(pci, PCI_SUBSYSTEM_ID, &ss_card);
3848
3849         for (cp = &cards[0]; cp->name; cp++) {
3850                 if (cp->vendor == ss_vendor && cp->id == ss_card) {
3851                         snd_printdd ("hack for %s enabled\n", cp->name);
3852
3853                         chip->amplifier_ctrl = cp->amp;
3854                         chip->active_ctrl = cp->active;
3855                         chip->mixer_init = cp->mixer_init;
3856
3857                         if (cp->init)
3858                                 cp->init(chip);
3859                         break;
3860                 }
3861         }
3862
3863         if (external_amp) {
3864                 snd_printk(KERN_INFO "Crystal EAPD support forced on.\n");
3865                 chip->amplifier_ctrl = amp_voyetra;
3866         }
3867
3868         if (thinkpad) {
3869                 snd_printk(KERN_INFO "Activating CLKRUN hack for Thinkpad.\n");
3870                 chip->active_ctrl = clkrun_hack;
3871                 clkrun_init(chip);
3872         }
3873
3874         if (chip->amplifier_ctrl == NULL)
3875                 chip->amplifier_ctrl = amp_none;
3876         if (chip->active_ctrl == NULL)
3877                 chip->active_ctrl = amp_none;
3878
3879         chip->active_ctrl(chip, 1); /* enable CLKRUN */
3880
3881         pci_set_master(pci);
3882
3883         for (idx = 0; idx < 5; idx++) {
3884                 region = &chip->region.idx[idx];
3885                 if ((region->resource = request_mem_region(region->base, region->size,
3886                                                            region->name)) == NULL) {
3887                         snd_printk(KERN_ERR "unable to request memory region 0x%lx-0x%lx\n",
3888                                    region->base, region->base + region->size - 1);
3889                         snd_cs46xx_free(chip);
3890                         return -EBUSY;
3891                 }
3892                 region->remap_addr = ioremap_nocache(region->base, region->size);
3893                 if (region->remap_addr == NULL) {
3894                         snd_printk(KERN_ERR "%s ioremap problem\n", region->name);
3895                         snd_cs46xx_free(chip);
3896                         return -ENOMEM;
3897                 }
3898         }
3899
3900         if (request_irq(pci->irq, snd_cs46xx_interrupt, IRQF_SHARED,
3901                         "CS46XX", chip)) {
3902                 snd_printk(KERN_ERR "unable to grab IRQ %d\n", pci->irq);
3903                 snd_cs46xx_free(chip);
3904                 return -EBUSY;
3905         }
3906         chip->irq = pci->irq;
3907
3908 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3909         chip->dsp_spos_instance = cs46xx_dsp_spos_create(chip);
3910         if (chip->dsp_spos_instance == NULL) {
3911                 snd_cs46xx_free(chip);
3912                 return -ENOMEM;
3913         }
3914 #endif
3915
3916         err = snd_cs46xx_chip_init(chip);
3917         if (err < 0) {
3918                 snd_cs46xx_free(chip);
3919                 return err;
3920         }
3921
3922         if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) {
3923                 snd_cs46xx_free(chip);
3924                 return err;
3925         }
3926
3927         snd_cs46xx_proc_init(card, chip);
3928
3929 #ifdef CONFIG_PM
3930         chip->saved_regs = kmalloc(sizeof(*chip->saved_regs) *
3931                                    ARRAY_SIZE(saved_regs), GFP_KERNEL);
3932         if (!chip->saved_regs) {
3933                 snd_cs46xx_free(chip);
3934                 return -ENOMEM;
3935         }
3936 #endif
3937
3938         chip->active_ctrl(chip, -1); /* disable CLKRUN */
3939
3940         snd_card_set_dev(card, &pci->dev);
3941
3942         *rchip = chip;
3943         return 0;
3944 }