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   1 /*
   2  * arch/arm/mach-at91/pm.c
   3  * AT91 Power Management
   4  *
   5  * Copyright (C) 2005 David Brownell
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  */
  12
  13 #include <linux/suspend.h>
  14 #include <linux/sched.h>
  15 #include <linux/proc_fs.h>
  16 #include <linux/interrupt.h>
  17 #include <linux/sysfs.h>
  18 #include <linux/module.h>
  19 #include <linux/platform_device.h>
  20
  21 #include <asm/io.h>
  22 #include <asm/irq.h>
  23 #include <asm/atomic.h>
  24 #include <asm/mach/time.h>
  25 #include <asm/mach/irq.h>
  26 #include <asm/mach-types.h>
  27
  28 #include <asm/arch/at91_pmc.h>
  29 #include <asm/arch/gpio.h>
  30 #include <asm/arch/cpu.h>
  31
  32 #include "generic.h"
  33
  34 #ifdef CONFIG_ARCH_AT91RM9200
  35 #include <asm/arch/at91rm9200_mc.h>
  36
  37 /*
  38  * The AT91RM9200 goes into self-refresh mode with this command, and will
  39  * terminate self-refresh automatically on the next SDRAM access.
  40  */
  41 #define sdram_selfrefresh_enable()      at91_sys_write(AT91_SDRAMC_SRR, 1)
  42 #define sdram_selfrefresh_disable()     do {} while (0)
  43
  44 #elif defined(CONFIG_ARCH_AT91CAP9)
  45 #include <asm/arch/at91cap9_ddrsdr.h>
  46
  47 static u32 saved_lpr;
  48
  49 static inline void sdram_selfrefresh_enable(void)
  50 {
  51         u32 lpr;
  52
  53         saved_lpr = at91_sys_read(AT91_DDRSDRC_LPR);
  54
  55         lpr = saved_lpr & ~AT91_DDRSDRC_LPCB;
  56         at91_sys_write(AT91_DDRSDRC_LPR, lpr | AT91_DDRSDRC_LPCB_SELF_REFRESH);
  57 }
  58
  59 #define sdram_selfrefresh_disable()     at91_sys_write(AT91_DDRSDRC_LPR, saved_lpr)
  60
  61 #else
  62 #include <asm/arch/at91sam9_sdramc.h>
  63
  64 #ifdef CONFIG_ARCH_AT91SAM9263
  65 /*
  66  * FIXME either or both the SDRAM controllers (EB0, EB1) might be in use;
  67  * handle those cases both here and in the Suspend-To-RAM support.
  68  */
  69 #define AT91_SDRAMC     AT91_SDRAMC0
  70 #warning Assuming EB1 SDRAM controller is *NOT* used
  71 #endif
  72
  73 static u32 saved_lpr;
  74
  75 static inline void sdram_selfrefresh_enable(void)
  76 {
  77         u32 lpr;
  78
  79         saved_lpr = at91_sys_read(AT91_SDRAMC_LPR);
  80
  81         lpr = saved_lpr & ~AT91_SDRAMC_LPCB;
  82         at91_sys_write(AT91_SDRAMC_LPR, lpr | AT91_SDRAMC_LPCB_SELF_REFRESH);
  83 }
  84
  85 #define sdram_selfrefresh_disable()     at91_sys_write(AT91_SDRAMC_LPR, saved_lpr)
  86
  87 #endif
  88
  89
  90 /*
  91  * Show the reason for the previous system reset.
  92  */
  93 #if defined(AT91_SHDWC)
  94
  95 #include <asm/arch/at91_rstc.h>
  96 #include <asm/arch/at91_shdwc.h>
  97
  98 static void __init show_reset_status(void)
  99 {
 100         static char reset[] __initdata = "reset";
 101
 102         static char general[] __initdata = "general";
 103         static char wakeup[] __initdata = "wakeup";
 104         static char watchdog[] __initdata = "watchdog";
 105         static char software[] __initdata = "software";
 106         static char user[] __initdata = "user";
 107         static char unknown[] __initdata = "unknown";
 108
 109         static char signal[] __initdata = "signal";
 110         static char rtc[] __initdata = "rtc";
 111         static char rtt[] __initdata = "rtt";
 112         static char restore[] __initdata = "power-restored";
 113
 114         char *reason, *r2 = reset;
 115         u32 reset_type, wake_type;
 116
 117         reset_type = at91_sys_read(AT91_RSTC_SR) & AT91_RSTC_RSTTYP;
 118         wake_type = at91_sys_read(AT91_SHDW_SR);
 119
 120         switch (reset_type) {
 121         case AT91_RSTC_RSTTYP_GENERAL:
 122                 reason = general;
 123                 break;
 124         case AT91_RSTC_RSTTYP_WAKEUP:
 125                 /* board-specific code enabled the wakeup sources */
 126                 reason = wakeup;
 127
 128                 /* "wakeup signal" */
 129                 if (wake_type & AT91_SHDW_WAKEUP0)
 130                         r2 = signal;
 131                 else {
 132                         r2 = reason;
 133                         if (wake_type & AT91_SHDW_RTTWK)        /* rtt wakeup */
 134                                 reason = rtt;
 135                         else if (wake_type & AT91_SHDW_RTCWK)   /* rtc wakeup */
 136                                 reason = rtc;
 137                         else if (wake_type == 0)        /* power-restored wakeup */
 138                                 reason = restore;
 139                         else                            /* unknown wakeup */
 140                                 reason = unknown;
 141                 }
 142                 break;
 143         case AT91_RSTC_RSTTYP_WATCHDOG:
 144                 reason = watchdog;
 145                 break;
 146         case AT91_RSTC_RSTTYP_SOFTWARE:
 147                 reason = software;
 148                 break;
 149         case AT91_RSTC_RSTTYP_USER:
 150                 reason = user;
 151                 break;
 152         default:
 153                 reason = unknown;
 154                 break;
 155         }
 156         pr_info("AT91: Starting after %s %s\n", reason, r2);
 157 }
 158 #else
 159 static void __init show_reset_status(void) {}
 160 #endif
 161
 162
 163 static int at91_pm_valid_state(suspend_state_t state)
 164 {
 165         switch (state) {
 166                 case PM_SUSPEND_ON:
 167                 case PM_SUSPEND_STANDBY:
 168                 case PM_SUSPEND_MEM:
 169                         return 1;
 170
 171                 default:
 172                         return 0;
 173         }
 174 }
 175
 176
 177 static suspend_state_t target_state;
 178
 179 /*
 180  * Called after processes are frozen, but before we shutdown devices.
 181  */
 182 static int at91_pm_begin(suspend_state_t state)
 183 {
 184         target_state = state;
 185         return 0;
 186 }
 187
 188 /*
 189  * Verify that all the clocks are correct before entering
 190  * slow-clock mode.
 191  */
 192 static int at91_pm_verify_clocks(void)
 193 {
 194         unsigned long scsr;
 195         int i;
 196
 197         scsr = at91_sys_read(AT91_PMC_SCSR);
 198
 199         /* USB must not be using PLLB */
 200         if (cpu_is_at91rm9200()) {
 201                 if ((scsr & (AT91RM9200_PMC_UHP | AT91RM9200_PMC_UDP)) != 0) {
 202                         pr_debug("AT91: PM - Suspend-to-RAM with USB still active\n");
 203                         return 0;
 204                 }
 205         } else if (cpu_is_at91sam9260() || cpu_is_at91sam9261() || cpu_is_at91sam9263()) {
 206                 if ((scsr & (AT91SAM926x_PMC_UHP | AT91SAM926x_PMC_UDP)) != 0) {
 207                         pr_debug("AT91: PM - Suspend-to-RAM with USB still active\n");
 208                         return 0;
 209                 }
 210         } else if (cpu_is_at91cap9()) {
 211                 if ((scsr & AT91CAP9_PMC_UHP) != 0) {
 212                         pr_debug("AT91: PM - Suspend-to-RAM with USB still active\n");
 213                         return 0;
 214                 }
 215         }
 216
 217 #ifdef CONFIG_AT91_PROGRAMMABLE_CLOCKS
 218         /* PCK0..PCK3 must be disabled, or configured to use clk32k */
 219         for (i = 0; i < 4; i++) {
 220                 u32 css;
 221
 222                 if ((scsr & (AT91_PMC_PCK0 << i)) == 0)
 223                         continue;
 224
 225                 css = at91_sys_read(AT91_PMC_PCKR(i)) & AT91_PMC_CSS;
 226                 if (css != AT91_PMC_CSS_SLOW) {
 227                         pr_debug("AT91: PM - Suspend-to-RAM with PCK%d src %d\n", i, css);
 228                         return 0;
 229                 }
 230         }
 231 #endif
 232
 233         return 1;
 234 }
 235
 236 /*
 237  * Call this from platform driver suspend() to see how deeply to suspend.
 238  * For example, some controllers (like OHCI) need one of the PLL clocks
 239  * in order to act as a wakeup source, and those are not available when
 240  * going into slow clock mode.
 241  *
 242  * REVISIT: generalize as clk_will_be_available(clk)?  Other platforms have
 243  * the very same problem (but not using at91 main_clk), and it'd be better
 244  * to add one generic API rather than lots of platform-specific ones.
 245  */
 246 int at91_suspend_entering_slow_clock(void)
 247 {
 248         return (target_state == PM_SUSPEND_MEM);
 249 }
 250 EXPORT_SYMBOL(at91_suspend_entering_slow_clock);
 251
 252
 253 static void (*slow_clock)(void);
 254
 255 #ifdef CONFIG_AT91_SLOW_CLOCK
 256 extern void at91_slow_clock(void);
 257 extern u32 at91_slow_clock_sz;
 258 #endif
 259
 260
 261 static int at91_pm_enter(suspend_state_t state)
 262 {
 263         at91_gpio_suspend();
 264         at91_irq_suspend();
 265
 266         pr_debug("AT91: PM - wake mask %08x, pm state %d\n",
 267                         /* remember all the always-wake irqs */
 268                         (at91_sys_read(AT91_PMC_PCSR)
 269                                         | (1 << AT91_ID_FIQ)
 270                                         | (1 << AT91_ID_SYS)
 271                                         | (at91_extern_irq))
 272                                 & at91_sys_read(AT91_AIC_IMR),
 273                         state);
 274
 275         switch (state) {
 276                 /*
 277                  * Suspend-to-RAM is like STANDBY plus slow clock mode, so
 278                  * drivers must suspend more deeply:  only the master clock
 279                  * controller may be using the main oscillator.
 280                  */
 281                 case PM_SUSPEND_MEM:
 282                         /*
 283                          * Ensure that clocks are in a valid state.
 284                          */
 285                         if (!at91_pm_verify_clocks())
 286                                 goto error;
 287
 288                         /*
 289                          * Enter slow clock mode by switching over to clk32k and
 290                          * turning off the main oscillator; reverse on wakeup.
 291                          */
 292                         if (slow_clock) {
 293 #ifdef CONFIG_AT91_SLOW_CLOCK
 294                                 /* copy slow_clock handler to SRAM, and call it */
 295                                 memcpy(slow_clock, at91_slow_clock, at91_slow_clock_sz);
 296 #endif
 297                                 slow_clock();
 298                                 break;
 299                         } else {
 300                                 pr_info("AT91: PM - no slow clock mode enabled ...\n");
 301                                 /* FALLTHROUGH leaving master clock alone */
 302                         }
 303
 304                 /*
 305                  * STANDBY mode has *all* drivers suspended; ignores irqs not
 306                  * marked as 'wakeup' event sources; and reduces DRAM power.
 307                  * But otherwise it's identical to PM_SUSPEND_ON:  cpu idle, and
 308                  * nothing fancy done with main or cpu clocks.
 309                  */
 310                 case PM_SUSPEND_STANDBY:
 311                         /*
 312                          * NOTE: the Wait-for-Interrupt instruction needs to be
 313                          * in icache so no SDRAM accesses are needed until the
 314                          * wakeup IRQ occurs and self-refresh is terminated.
 315                          */
 316                         asm("b 1f; .align 5; 1:");
 317                         asm("mcr p15, 0, r0, c7, c10, 4");      /* drain write buffer */
 318                         sdram_selfrefresh_enable();
 319                         asm("mcr p15, 0, r0, c7, c0, 4");       /* wait for interrupt */
 320                         sdram_selfrefresh_disable();
 321                         break;
 322
 323                 case PM_SUSPEND_ON:
 324                         asm("mcr p15, 0, r0, c7, c0, 4");       /* wait for interrupt */
 325                         break;
 326
 327                 default:
 328                         pr_debug("AT91: PM - bogus suspend state %d\n", state);
 329                         goto error;
 330         }
 331
 332         pr_debug("AT91: PM - wakeup %08x\n",
 333                         at91_sys_read(AT91_AIC_IPR) & at91_sys_read(AT91_AIC_IMR));
 334
 335 error:
 336         sdram_selfrefresh_disable();
 337         target_state = PM_SUSPEND_ON;
 338         at91_irq_resume();
 339         at91_gpio_resume();
 340         return 0;
 341 }
 342
 343 /*
 344  * Called right prior to thawing processes.
 345  */
 346 static void at91_pm_end(void)
 347 {
 348         target_state = PM_SUSPEND_ON;
 349 }
 350
 351
 352 static struct platform_suspend_ops at91_pm_ops ={
 353         .valid  = at91_pm_valid_state,
 354         .begin  = at91_pm_begin,
 355         .enter  = at91_pm_enter,
 356         .end    = at91_pm_end,
 357 };
 358
 359 static int __init at91_pm_init(void)
 360 {
 361 #ifdef CONFIG_AT91_SLOW_CLOCK
 362         slow_clock = (void *) (AT91_IO_VIRT_BASE - at91_slow_clock_sz);
 363 #endif
 364
 365         pr_info("AT91: Power Management%s\n", (slow_clock ? " (with slow clock mode)" : ""));
 366
 367 #ifdef CONFIG_ARCH_AT91RM9200
 368         /* AT91RM9200 SDRAM low-power mode cannot be used with self-refresh. */
 369         at91_sys_write(AT91_SDRAMC_LPR, 0);
 370 #endif
 371
 372         suspend_set_ops(&at91_pm_ops);
 373
 374         show_reset_status();
 375         return 0;
 376 }
 377 arch_initcall(at91_pm_init);