2 * MPC8xx Internal Memory Map
3 * Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
5 * The I/O on the MPC860 is comprised of blocks of special registers
6 * and the dual port ram for the Communication Processor Module.
7 * Within this space are functional units such as the SIU, memory
8 * controller, system timers, and other control functions. It is
9 * a combination that I found difficult to separate into logical
10 * functional files.....but anyone else is welcome to try. -- Dan
16 /* System configuration registers.
18 typedef struct sys_conf {
34 /* PCMCIA configuration registers.
36 typedef struct pcmcia_conf {
64 /* Memory controller registers.
66 typedef struct mem_ctlr {
95 /*-----------------------------------------------------------------------
96 * BR - Memory Controler: Base Register 16-9
98 #define BR_BA_MSK 0xffff8000 /* Base Address Mask */
99 #define BR_AT_MSK 0x00007000 /* Address Type Mask */
100 #define BR_PS_MSK 0x00000c00 /* Port Size Mask */
101 #define BR_PS_32 0x00000000 /* 32 bit port size */
102 #define BR_PS_16 0x00000800 /* 16 bit port size */
103 #define BR_PS_8 0x00000400 /* 8 bit port size */
104 #define BR_PARE 0x00000200 /* Parity Enable */
105 #define BR_WP 0x00000100 /* Write Protect */
106 #define BR_MS_MSK 0x000000c0 /* Machine Select Mask */
107 #define BR_MS_GPCM 0x00000000 /* G.P.C.M. Machine Select */
108 #define BR_MS_UPMA 0x00000080 /* U.P.M.A Machine Select */
109 #define BR_MS_UPMB 0x000000c0 /* U.P.M.B Machine Select */
110 #define BR_V 0x00000001 /* Bank Valid */
112 /*-----------------------------------------------------------------------
113 * OR - Memory Controler: Option Register 16-11
115 #define OR_AM_MSK 0xffff8000 /* Address Mask Mask */
116 #define OR_ATM_MSK 0x00007000 /* Address Type Mask Mask */
117 #define OR_CSNT_SAM 0x00000800 /* Chip Select Negation Time/ Start */
118 /* Address Multiplex */
119 #define OR_ACS_MSK 0x00000600 /* Address to Chip Select Setup mask */
120 #define OR_ACS_DIV1 0x00000000 /* CS is output at the same time */
121 #define OR_ACS_DIV4 0x00000400 /* CS is output 1/4 a clock later */
122 #define OR_ACS_DIV2 0x00000600 /* CS is output 1/2 a clock later */
123 #define OR_G5LA 0x00000400 /* Output #GPL5 on #GPL_A5 */
124 #define OR_G5LS 0x00000200 /* Drive #GPL high on falling edge of...*/
125 #define OR_BI 0x00000100 /* Burst inhibit */
126 #define OR_SCY_MSK 0x000000f0 /* Cycle Length in Clocks */
127 #define OR_SCY_0_CLK 0x00000000 /* 0 clock cycles wait states */
128 #define OR_SCY_1_CLK 0x00000010 /* 1 clock cycles wait states */
129 #define OR_SCY_2_CLK 0x00000020 /* 2 clock cycles wait states */
130 #define OR_SCY_3_CLK 0x00000030 /* 3 clock cycles wait states */
131 #define OR_SCY_4_CLK 0x00000040 /* 4 clock cycles wait states */
132 #define OR_SCY_5_CLK 0x00000050 /* 5 clock cycles wait states */
133 #define OR_SCY_6_CLK 0x00000060 /* 6 clock cycles wait states */
134 #define OR_SCY_7_CLK 0x00000070 /* 7 clock cycles wait states */
135 #define OR_SCY_8_CLK 0x00000080 /* 8 clock cycles wait states */
136 #define OR_SCY_9_CLK 0x00000090 /* 9 clock cycles wait states */
137 #define OR_SCY_10_CLK 0x000000a0 /* 10 clock cycles wait states */
138 #define OR_SCY_11_CLK 0x000000b0 /* 11 clock cycles wait states */
139 #define OR_SCY_12_CLK 0x000000c0 /* 12 clock cycles wait states */
140 #define OR_SCY_13_CLK 0x000000d0 /* 13 clock cycles wait states */
141 #define OR_SCY_14_CLK 0x000000e0 /* 14 clock cycles wait states */
142 #define OR_SCY_15_CLK 0x000000f0 /* 15 clock cycles wait states */
143 #define OR_SETA 0x00000008 /* External Transfer Acknowledge */
144 #define OR_TRLX 0x00000004 /* Timing Relaxed */
145 #define OR_EHTR 0x00000002 /* Extended Hold Time on Read */
147 /* System Integration Timers.
149 typedef struct sys_int_timers {
168 #define TBSCR_TBIRQ_MASK ((ushort)0xff00)
169 #define TBSCR_REFA ((ushort)0x0080)
170 #define TBSCR_REFB ((ushort)0x0040)
171 #define TBSCR_REFAE ((ushort)0x0008)
172 #define TBSCR_REFBE ((ushort)0x0004)
173 #define TBSCR_TBF ((ushort)0x0002)
174 #define TBSCR_TBE ((ushort)0x0001)
176 #define RTCSC_RTCIRQ_MASK ((ushort)0xff00)
177 #define RTCSC_SEC ((ushort)0x0080)
178 #define RTCSC_ALR ((ushort)0x0040)
179 #define RTCSC_38K ((ushort)0x0010)
180 #define RTCSC_SIE ((ushort)0x0008)
181 #define RTCSC_ALE ((ushort)0x0004)
182 #define RTCSC_RTF ((ushort)0x0002)
183 #define RTCSC_RTE ((ushort)0x0001)
185 #define PISCR_PIRQ_MASK ((ushort)0xff00)
186 #define PISCR_PS ((ushort)0x0080)
187 #define PISCR_PIE ((ushort)0x0004)
188 #define PISCR_PTF ((ushort)0x0002)
189 #define PISCR_PTE ((ushort)0x0001)
193 typedef struct clk_and_reset {
197 char res[0x74]; /* Reserved area */
200 /* System Integration Timers keys.
202 typedef struct sitk {
218 /* Clocks and reset keys.
220 typedef struct cark {
227 /* The key to unlock registers maintained by keep-alive power.
229 #define KAPWR_KEY ((unsigned int)0x55ccaa33)
231 /* Video interface. MPC823 Only.
233 typedef struct vid823 {
251 /* LCD interface. 823 Only.
281 /* DMA control/status registers.
283 typedef struct sdma_csr {
300 /* Communication Processor Module Interrupt Controller.
302 typedef struct cpm_ic {
311 /* Input/Output Port control/status registers.
313 typedef struct io_port {
333 /* Communication Processor Module Timers
335 typedef struct cpm_timers {
361 /* Finally, the Communication Processor stuff.....
363 typedef struct scc { /* Serial communication channels */
378 typedef struct smc { /* Serial management channels */
388 /* MPC860T Fast Ethernet Controller. It isn't part of the CPM, but
389 * it fits within the address space.
393 uint fec_addr_low; /* lower 32 bits of station address */
394 ushort fec_addr_high; /* upper 16 bits of station address */
395 ushort res1; /* reserved */
396 uint fec_hash_table_high; /* upper 32-bits of hash table */
397 uint fec_hash_table_low; /* lower 32-bits of hash table */
398 uint fec_r_des_start; /* beginning of Rx descriptor ring */
399 uint fec_x_des_start; /* beginning of Tx descriptor ring */
400 uint fec_r_buff_size; /* Rx buffer size */
401 uint res2[9]; /* reserved */
402 uint fec_ecntrl; /* ethernet control register */
403 uint fec_ievent; /* interrupt event register */
404 uint fec_imask; /* interrupt mask register */
405 uint fec_ivec; /* interrupt level and vector status */
406 uint fec_r_des_active; /* Rx ring updated flag */
407 uint fec_x_des_active; /* Tx ring updated flag */
408 uint res3[10]; /* reserved */
409 uint fec_mii_data; /* MII data register */
410 uint fec_mii_speed; /* MII speed control register */
411 uint res4[17]; /* reserved */
412 uint fec_r_bound; /* end of RAM (read-only) */
413 uint fec_r_fstart; /* Rx FIFO start address */
414 uint res5[6]; /* reserved */
415 uint fec_x_fstart; /* Tx FIFO start address */
416 uint res6[17]; /* reserved */
417 uint fec_fun_code; /* fec SDMA function code */
418 uint res7[3]; /* reserved */
419 uint fec_r_cntrl; /* Rx control register */
420 uint fec_r_hash; /* Rx hash register */
421 uint res8[14]; /* reserved */
422 uint fec_x_cntrl; /* Tx control register */
423 uint res9[0x1e]; /* reserved */
426 /* The FEC and LCD color map share the same address space....
427 * I guess we will never see an 823T :-).
431 u_char fl_un_cmap[0x200];
434 typedef struct comm_proc {
435 /* General control and status registers.
453 /* Baud rate generators.
460 /* Serial Communication Channels.
464 /* Serial Management Channels.
468 /* Serial Peripheral Interface.
479 /* Parallel Interface Port.
491 /* Port E - MPC87x/88x only.
499 /* Communications Processor Timing Register -
500 Contains RMII Timing for the FECs on MPC87x/88x only.
504 /* Serial Interface and Time Slot Assignment.
516 /* 256 bytes of MPC823 video controller RAM array.
518 u_char cp_vcram[0x100];
519 u_char cp_siram[0x200];
521 /* The fast ethernet controller is not really part of the CPM,
522 * but it resides in the address space.
523 * The LCD color map is also here.
526 #define cp_fec fl_un.fl_un_fec
527 #define lcd_cmap fl_un.fl_un_cmap
530 /* The DUET family has a second FEC here */
532 #define cp_fec1 cp_fec /* consistency macro */
534 /* Dual Ported RAM follows.
535 * There are many different formats for this memory area
536 * depending upon the devices used and options chosen.
537 * Some processors don't have all of it populated.
539 u_char cp_dpmem[0x1C00]; /* BD / Data / ucode */
540 u_char cp_dparam[0x400]; /* Parameter RAM */
543 /* Internal memory map.
545 typedef struct immap {
546 sysconf8xx_t im_siu_conf; /* SIU Configuration */
547 pcmconf8xx_t im_pcmcia; /* PCMCIA Configuration */
548 memctl8xx_t im_memctl; /* Memory Controller */
549 sit8xx_t im_sit; /* System integration timers */
550 car8xx_t im_clkrst; /* Clocks and reset */
551 sitk8xx_t im_sitk; /* Sys int timer keys */
552 cark8xx_t im_clkrstk; /* Clocks and reset keys */
553 vid823_t im_vid; /* Video (823 only) */
554 lcd823_t im_lcd; /* LCD (823 only) */
555 i2c8xx_t im_i2c; /* I2C control/status */
556 sdma8xx_t im_sdma; /* SDMA control/status */
557 cpic8xx_t im_cpic; /* CPM Interrupt Controller */
558 iop8xx_t im_ioport; /* IO Port control/status */
559 cpmtimer8xx_t im_cpmtimer; /* CPM timers */
560 cpm8xx_t im_cpm; /* Communication processor */
563 #endif /* __IMMAP_8XX__ */
564 #endif /* __KERNEL__ */