Merge branches 'release', 'acpica', 'bugzilla-10224', 'bugzilla-9772', 'bugzilla...
[linux-2.6] / arch / arm / mach-s3c2410 / mach-vr1000.c
1 /* linux/arch/arm/mach-s3c2410/mach-vr1000.c
2  *
3  * Copyright (c) 2003-2005 Simtec Electronics
4  *   Ben Dooks <ben@simtec.co.uk>
5  *
6  * Machine support for Thorcom VR1000 board. Designed for Thorcom by
7  * Simtec Electronics, http://www.simtec.co.uk/
8  *
9  * This program is free software; you can redistribute it and/or modify
10  * it under the terms of the GNU General Public License version 2 as
11  * published by the Free Software Foundation.
12  *
13 */
14
15 #include <linux/kernel.h>
16 #include <linux/types.h>
17 #include <linux/interrupt.h>
18 #include <linux/list.h>
19 #include <linux/timer.h>
20 #include <linux/init.h>
21 #include <linux/dm9000.h>
22
23 #include <linux/serial.h>
24 #include <linux/tty.h>
25 #include <linux/serial_8250.h>
26 #include <linux/serial_reg.h>
27
28 #include <asm/mach/arch.h>
29 #include <asm/mach/map.h>
30 #include <asm/mach/irq.h>
31
32 #include <asm/arch/bast-map.h>
33 #include <asm/arch/vr1000-map.h>
34 #include <asm/arch/vr1000-irq.h>
35 #include <asm/arch/vr1000-cpld.h>
36
37 #include <asm/hardware.h>
38 #include <asm/io.h>
39 #include <asm/irq.h>
40 #include <asm/mach-types.h>
41
42 #include <asm/plat-s3c/regs-serial.h>
43 #include <asm/arch/regs-gpio.h>
44 #include <asm/arch/leds-gpio.h>
45
46 #include <asm/plat-s3c24xx/clock.h>
47 #include <asm/plat-s3c24xx/devs.h>
48 #include <asm/plat-s3c24xx/cpu.h>
49 #include "usb-simtec.h"
50
51 /* macros for virtual address mods for the io space entries */
52 #define VA_C5(item) ((unsigned long)(item) + BAST_VAM_CS5)
53 #define VA_C4(item) ((unsigned long)(item) + BAST_VAM_CS4)
54 #define VA_C3(item) ((unsigned long)(item) + BAST_VAM_CS3)
55 #define VA_C2(item) ((unsigned long)(item) + BAST_VAM_CS2)
56
57 /* macros to modify the physical addresses for io space */
58
59 #define PA_CS2(item) (__phys_to_pfn((item) + S3C2410_CS2))
60 #define PA_CS3(item) (__phys_to_pfn((item) + S3C2410_CS3))
61 #define PA_CS4(item) (__phys_to_pfn((item) + S3C2410_CS4))
62 #define PA_CS5(item) (__phys_to_pfn((item) + S3C2410_CS5))
63
64 static struct map_desc vr1000_iodesc[] __initdata = {
65   /* ISA IO areas */
66   {
67           .virtual      = (u32)S3C24XX_VA_ISA_BYTE,
68           .pfn          = PA_CS2(BAST_PA_ISAIO),
69           .length       = SZ_16M,
70           .type         = MT_DEVICE,
71   }, {
72           .virtual      = (u32)S3C24XX_VA_ISA_WORD,
73           .pfn          = PA_CS3(BAST_PA_ISAIO),
74           .length       = SZ_16M,
75           .type         = MT_DEVICE,
76   },
77
78   /*  CPLD control registers, and external interrupt controls */
79   {
80           .virtual      = (u32)VR1000_VA_CTRL1,
81           .pfn          = __phys_to_pfn(VR1000_PA_CTRL1),
82           .length       = SZ_1M,
83           .type         = MT_DEVICE,
84   }, {
85           .virtual      = (u32)VR1000_VA_CTRL2,
86           .pfn          = __phys_to_pfn(VR1000_PA_CTRL2),
87           .length       = SZ_1M,
88           .type         = MT_DEVICE,
89   }, {
90           .virtual      = (u32)VR1000_VA_CTRL3,
91           .pfn          = __phys_to_pfn(VR1000_PA_CTRL3),
92           .length       = SZ_1M,
93           .type         = MT_DEVICE,
94   }, {
95           .virtual      = (u32)VR1000_VA_CTRL4,
96           .pfn          = __phys_to_pfn(VR1000_PA_CTRL4),
97           .length       = SZ_1M,
98           .type         = MT_DEVICE,
99   },
100
101   /* peripheral space... one for each of fast/slow/byte/16bit */
102   /* note, ide is only decoded in word space, even though some registers
103    * are only 8bit */
104
105   /* slow, byte */
106   { VA_C2(VR1000_VA_IDEPRI),  PA_CS3(VR1000_PA_IDEPRI),   SZ_1M,  MT_DEVICE },
107   { VA_C2(VR1000_VA_IDESEC),  PA_CS3(VR1000_PA_IDESEC),   SZ_1M,  MT_DEVICE },
108   { VA_C2(VR1000_VA_IDEPRIAUX), PA_CS3(VR1000_PA_IDEPRIAUX), SZ_1M, MT_DEVICE },
109   { VA_C2(VR1000_VA_IDESECAUX), PA_CS3(VR1000_PA_IDESECAUX), SZ_1M, MT_DEVICE },
110
111   /* slow, word */
112   { VA_C3(VR1000_VA_IDEPRI),  PA_CS3(VR1000_PA_IDEPRI),   SZ_1M,  MT_DEVICE },
113   { VA_C3(VR1000_VA_IDESEC),  PA_CS3(VR1000_PA_IDESEC),   SZ_1M,  MT_DEVICE },
114   { VA_C3(VR1000_VA_IDEPRIAUX), PA_CS3(VR1000_PA_IDEPRIAUX), SZ_1M, MT_DEVICE },
115   { VA_C3(VR1000_VA_IDESECAUX), PA_CS3(VR1000_PA_IDESECAUX), SZ_1M, MT_DEVICE },
116
117   /* fast, byte */
118   { VA_C4(VR1000_VA_IDEPRI),  PA_CS5(VR1000_PA_IDEPRI),   SZ_1M,  MT_DEVICE },
119   { VA_C4(VR1000_VA_IDESEC),  PA_CS5(VR1000_PA_IDESEC),   SZ_1M,  MT_DEVICE },
120   { VA_C4(VR1000_VA_IDEPRIAUX), PA_CS5(VR1000_PA_IDEPRIAUX), SZ_1M, MT_DEVICE },
121   { VA_C4(VR1000_VA_IDESECAUX), PA_CS5(VR1000_PA_IDESECAUX), SZ_1M, MT_DEVICE },
122
123   /* fast, word */
124   { VA_C5(VR1000_VA_IDEPRI),  PA_CS5(VR1000_PA_IDEPRI),   SZ_1M,  MT_DEVICE },
125   { VA_C5(VR1000_VA_IDESEC),  PA_CS5(VR1000_PA_IDESEC),   SZ_1M,  MT_DEVICE },
126   { VA_C5(VR1000_VA_IDEPRIAUX), PA_CS5(VR1000_PA_IDEPRIAUX), SZ_1M, MT_DEVICE },
127   { VA_C5(VR1000_VA_IDESECAUX), PA_CS5(VR1000_PA_IDESECAUX), SZ_1M, MT_DEVICE },
128 };
129
130 #define UCON S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK
131 #define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
132 #define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE
133
134 /* uart clock source(s) */
135
136 static struct s3c24xx_uart_clksrc vr1000_serial_clocks[] = {
137         [0] = {
138                 .name           = "uclk",
139                 .divisor        = 1,
140                 .min_baud       = 0,
141                 .max_baud       = 0,
142         },
143         [1] = {
144                 .name           = "pclk",
145                 .divisor        = 1,
146                 .min_baud       = 0,
147                 .max_baud       = 0.
148         }
149 };
150
151 static struct s3c2410_uartcfg vr1000_uartcfgs[] __initdata = {
152         [0] = {
153                 .hwport      = 0,
154                 .flags       = 0,
155                 .ucon        = UCON,
156                 .ulcon       = ULCON,
157                 .ufcon       = UFCON,
158                 .clocks      = vr1000_serial_clocks,
159                 .clocks_size = ARRAY_SIZE(vr1000_serial_clocks),
160         },
161         [1] = {
162                 .hwport      = 1,
163                 .flags       = 0,
164                 .ucon        = UCON,
165                 .ulcon       = ULCON,
166                 .ufcon       = UFCON,
167                 .clocks      = vr1000_serial_clocks,
168                 .clocks_size = ARRAY_SIZE(vr1000_serial_clocks),
169         },
170         /* port 2 is not actually used */
171         [2] = {
172                 .hwport      = 2,
173                 .flags       = 0,
174                 .ucon        = UCON,
175                 .ulcon       = ULCON,
176                 .ufcon       = UFCON,
177                 .clocks      = vr1000_serial_clocks,
178                 .clocks_size = ARRAY_SIZE(vr1000_serial_clocks),
179
180         }
181 };
182
183 /* definitions for the vr1000 extra 16550 serial ports */
184
185 #define VR1000_BAUDBASE (3692307)
186
187 #define VR1000_SERIAL_MAPBASE(x) (VR1000_PA_SERIAL + 0x80 + ((x) << 5))
188
189 static struct plat_serial8250_port serial_platform_data[] = {
190         [0] = {
191                 .mapbase        = VR1000_SERIAL_MAPBASE(0),
192                 .irq            = IRQ_VR1000_SERIAL + 0,
193                 .flags          = UPF_BOOT_AUTOCONF | UPF_IOREMAP,
194                 .iotype         = UPIO_MEM,
195                 .regshift       = 0,
196                 .uartclk        = VR1000_BAUDBASE,
197         },
198         [1] = {
199                 .mapbase        = VR1000_SERIAL_MAPBASE(1),
200                 .irq            = IRQ_VR1000_SERIAL + 1,
201                 .flags          = UPF_BOOT_AUTOCONF | UPF_IOREMAP,
202                 .iotype         = UPIO_MEM,
203                 .regshift       = 0,
204                 .uartclk        = VR1000_BAUDBASE,
205         },
206         [2] = {
207                 .mapbase        = VR1000_SERIAL_MAPBASE(2),
208                 .irq            = IRQ_VR1000_SERIAL + 2,
209                 .flags          = UPF_BOOT_AUTOCONF | UPF_IOREMAP,
210                 .iotype         = UPIO_MEM,
211                 .regshift       = 0,
212                 .uartclk        = VR1000_BAUDBASE,
213         },
214         [3] = {
215                 .mapbase        = VR1000_SERIAL_MAPBASE(3),
216                 .irq            = IRQ_VR1000_SERIAL + 3,
217                 .flags          = UPF_BOOT_AUTOCONF | UPF_IOREMAP,
218                 .iotype         = UPIO_MEM,
219                 .regshift       = 0,
220                 .uartclk        = VR1000_BAUDBASE,
221         },
222         { },
223 };
224
225 static struct platform_device serial_device = {
226         .name                   = "serial8250",
227         .id                     = PLAT8250_DEV_PLATFORM,
228         .dev                    = {
229                 .platform_data  = serial_platform_data,
230         },
231 };
232
233 /* MTD NOR Flash */
234
235 static struct resource vr1000_nor_resource[] = {
236         [0] = {
237                 .start  = S3C2410_CS1 + 0x4000000,
238                 .end    = S3C2410_CS1 + 0x4000000 + SZ_16M - 1,
239                 .flags  = IORESOURCE_MEM,
240         }
241 };
242
243 static struct platform_device vr1000_nor = {
244         .name           = "bast-nor",
245         .id             = -1,
246         .num_resources  = ARRAY_SIZE(vr1000_nor_resource),
247         .resource       = vr1000_nor_resource,
248 };
249
250 /* DM9000 ethernet devices */
251
252 static struct resource vr1000_dm9k0_resource[] = {
253         [0] = {
254                 .start = S3C2410_CS5 + VR1000_PA_DM9000,
255                 .end   = S3C2410_CS5 + VR1000_PA_DM9000 + 3,
256                 .flags = IORESOURCE_MEM
257         },
258         [1] = {
259                 .start = S3C2410_CS5 + VR1000_PA_DM9000 + 0x40,
260                 .end   = S3C2410_CS5 + VR1000_PA_DM9000 + 0x7f,
261                 .flags = IORESOURCE_MEM
262         },
263         [2] = {
264                 .start = IRQ_VR1000_DM9000A,
265                 .end   = IRQ_VR1000_DM9000A,
266                 .flags = IORESOURCE_IRQ
267         }
268
269 };
270
271 static struct resource vr1000_dm9k1_resource[] = {
272         [0] = {
273                 .start = S3C2410_CS5 + VR1000_PA_DM9000 + 0x80,
274                 .end   = S3C2410_CS5 + VR1000_PA_DM9000 + 0x83,
275                 .flags = IORESOURCE_MEM
276         },
277         [1] = {
278                 .start = S3C2410_CS5 + VR1000_PA_DM9000 + 0xC0,
279                 .end   = S3C2410_CS5 + VR1000_PA_DM9000 + 0xFF,
280                 .flags = IORESOURCE_MEM
281         },
282         [2] = {
283                 .start = IRQ_VR1000_DM9000N,
284                 .end   = IRQ_VR1000_DM9000N,
285                 .flags = IORESOURCE_IRQ
286         }
287 };
288
289 /* for the moment we limit ourselves to 16bit IO until some
290  * better IO routines can be written and tested
291 */
292
293 static struct dm9000_plat_data vr1000_dm9k_platdata = {
294         .flags          = DM9000_PLATF_16BITONLY,
295 };
296
297 static struct platform_device vr1000_dm9k0 = {
298         .name           = "dm9000",
299         .id             = 0,
300         .num_resources  = ARRAY_SIZE(vr1000_dm9k0_resource),
301         .resource       = vr1000_dm9k0_resource,
302         .dev            = {
303                 .platform_data = &vr1000_dm9k_platdata,
304         }
305 };
306
307 static struct platform_device vr1000_dm9k1 = {
308         .name           = "dm9000",
309         .id             = 1,
310         .num_resources  = ARRAY_SIZE(vr1000_dm9k1_resource),
311         .resource       = vr1000_dm9k1_resource,
312         .dev            = {
313                 .platform_data = &vr1000_dm9k_platdata,
314         }
315 };
316
317 /* LEDS */
318
319 static struct s3c24xx_led_platdata vr1000_led1_pdata = {
320         .name           = "led1",
321         .gpio           = S3C2410_GPB0,
322         .def_trigger    = "",
323 };
324
325 static struct s3c24xx_led_platdata vr1000_led2_pdata = {
326         .name           = "led2",
327         .gpio           = S3C2410_GPB1,
328         .def_trigger    = "",
329 };
330
331 static struct s3c24xx_led_platdata vr1000_led3_pdata = {
332         .name           = "led3",
333         .gpio           = S3C2410_GPB2,
334         .def_trigger    = "",
335 };
336
337 static struct platform_device vr1000_led1 = {
338         .name           = "s3c24xx_led",
339         .id             = 1,
340         .dev            = {
341                 .platform_data  = &vr1000_led1_pdata,
342         },
343 };
344
345 static struct platform_device vr1000_led2 = {
346         .name           = "s3c24xx_led",
347         .id             = 2,
348         .dev            = {
349                 .platform_data  = &vr1000_led2_pdata,
350         },
351 };
352
353 static struct platform_device vr1000_led3 = {
354         .name           = "s3c24xx_led",
355         .id             = 3,
356         .dev            = {
357                 .platform_data  = &vr1000_led3_pdata,
358         },
359 };
360
361 /* devices for this board */
362
363 static struct platform_device *vr1000_devices[] __initdata = {
364         &s3c_device_usb,
365         &s3c_device_lcd,
366         &s3c_device_wdt,
367         &s3c_device_i2c,
368         &s3c_device_adc,
369         &serial_device,
370         &vr1000_nor,
371         &vr1000_dm9k0,
372         &vr1000_dm9k1,
373         &vr1000_led1,
374         &vr1000_led2,
375         &vr1000_led3,
376 };
377
378 static struct clk *vr1000_clocks[] = {
379         &s3c24xx_dclk0,
380         &s3c24xx_dclk1,
381         &s3c24xx_clkout0,
382         &s3c24xx_clkout1,
383         &s3c24xx_uclk,
384 };
385
386 static void vr1000_power_off(void)
387 {
388         s3c2410_gpio_cfgpin(S3C2410_GPB9, S3C2410_GPB9_OUTP);
389         s3c2410_gpio_setpin(S3C2410_GPB9, 1);
390 }
391
392 static void __init vr1000_map_io(void)
393 {
394         /* initialise clock sources */
395
396         s3c24xx_dclk0.parent = &clk_upll;
397         s3c24xx_dclk0.rate   = 12*1000*1000;
398
399         s3c24xx_dclk1.parent = NULL;
400         s3c24xx_dclk1.rate   = 3692307;
401
402         s3c24xx_clkout0.parent  = &s3c24xx_dclk0;
403         s3c24xx_clkout1.parent  = &s3c24xx_dclk1;
404
405         s3c24xx_uclk.parent  = &s3c24xx_clkout1;
406
407         s3c24xx_register_clocks(vr1000_clocks, ARRAY_SIZE(vr1000_clocks));
408
409         pm_power_off = vr1000_power_off;
410
411         s3c24xx_init_io(vr1000_iodesc, ARRAY_SIZE(vr1000_iodesc));
412         s3c24xx_init_clocks(0);
413         s3c24xx_init_uarts(vr1000_uartcfgs, ARRAY_SIZE(vr1000_uartcfgs));
414 }
415
416 static void __init vr1000_init(void)
417 {
418         platform_add_devices(vr1000_devices, ARRAY_SIZE(vr1000_devices));
419 }
420
421 MACHINE_START(VR1000, "Thorcom-VR1000")
422         /* Maintainer: Ben Dooks <ben@simtec.co.uk> */
423         .phys_io        = S3C2410_PA_UART,
424         .io_pg_offst    = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc,
425         .boot_params    = S3C2410_SDRAM_PA + 0x100,
426         .map_io         = vr1000_map_io,
427         .init_machine   = vr1000_init,
428         .init_irq       = s3c24xx_init_irq,
429         .timer          = &s3c24xx_timer,
430 MACHINE_END