[WATCHDOG] Merge code clean-up's from Alan Cox.
[linux-2.6] / drivers / mtd / nand / cafe_nand.c
1 /*
2  * Driver for One Laptop Per Child ‘CAFÉ’ controller, aka Marvell 88ALP01
3  *
4  * Copyright © 2006 Red Hat, Inc.
5  * Copyright © 2006 David Woodhouse <dwmw2@infradead.org>
6  */
7
8 #define DEBUG
9
10 #include <linux/device.h>
11 #undef DEBUG
12 #include <linux/mtd/mtd.h>
13 #include <linux/mtd/nand.h>
14 #include <linux/mtd/partitions.h>
15 #include <linux/rslib.h>
16 #include <linux/pci.h>
17 #include <linux/delay.h>
18 #include <linux/interrupt.h>
19 #include <linux/dma-mapping.h>
20 #include <asm/io.h>
21
22 #define CAFE_NAND_CTRL1         0x00
23 #define CAFE_NAND_CTRL2         0x04
24 #define CAFE_NAND_CTRL3         0x08
25 #define CAFE_NAND_STATUS        0x0c
26 #define CAFE_NAND_IRQ           0x10
27 #define CAFE_NAND_IRQ_MASK      0x14
28 #define CAFE_NAND_DATA_LEN      0x18
29 #define CAFE_NAND_ADDR1         0x1c
30 #define CAFE_NAND_ADDR2         0x20
31 #define CAFE_NAND_TIMING1       0x24
32 #define CAFE_NAND_TIMING2       0x28
33 #define CAFE_NAND_TIMING3       0x2c
34 #define CAFE_NAND_NONMEM        0x30
35 #define CAFE_NAND_ECC_RESULT    0x3C
36 #define CAFE_NAND_DMA_CTRL      0x40
37 #define CAFE_NAND_DMA_ADDR0     0x44
38 #define CAFE_NAND_DMA_ADDR1     0x48
39 #define CAFE_NAND_ECC_SYN01     0x50
40 #define CAFE_NAND_ECC_SYN23     0x54
41 #define CAFE_NAND_ECC_SYN45     0x58
42 #define CAFE_NAND_ECC_SYN67     0x5c
43 #define CAFE_NAND_READ_DATA     0x1000
44 #define CAFE_NAND_WRITE_DATA    0x2000
45
46 #define CAFE_GLOBAL_CTRL        0x3004
47 #define CAFE_GLOBAL_IRQ         0x3008
48 #define CAFE_GLOBAL_IRQ_MASK    0x300c
49 #define CAFE_NAND_RESET         0x3034
50
51 /* Missing from the datasheet: bit 19 of CTRL1 sets CE0 vs. CE1 */
52 #define CTRL1_CHIPSELECT        (1<<19)
53
54 struct cafe_priv {
55         struct nand_chip nand;
56         struct mtd_partition *parts;
57         struct pci_dev *pdev;
58         void __iomem *mmio;
59         struct rs_control *rs;
60         uint32_t ctl1;
61         uint32_t ctl2;
62         int datalen;
63         int nr_data;
64         int data_pos;
65         int page_addr;
66         dma_addr_t dmaaddr;
67         unsigned char *dmabuf;
68 };
69
70 static int usedma = 1;
71 module_param(usedma, int, 0644);
72
73 static int skipbbt = 0;
74 module_param(skipbbt, int, 0644);
75
76 static int debug = 0;
77 module_param(debug, int, 0644);
78
79 static int regdebug = 0;
80 module_param(regdebug, int, 0644);
81
82 static int checkecc = 1;
83 module_param(checkecc, int, 0644);
84
85 static unsigned int numtimings;
86 static int timing[3];
87 module_param_array(timing, int, &numtimings, 0644);
88
89 #ifdef CONFIG_MTD_PARTITIONS
90 static const char *part_probes[] = { "RedBoot", NULL };
91 #endif
92
93 /* Hrm. Why isn't this already conditional on something in the struct device? */
94 #define cafe_dev_dbg(dev, args...) do { if (debug) dev_dbg(dev, ##args); } while(0)
95
96 /* Make it easier to switch to PIO if we need to */
97 #define cafe_readl(cafe, addr)                  readl((cafe)->mmio + CAFE_##addr)
98 #define cafe_writel(cafe, datum, addr)          writel(datum, (cafe)->mmio + CAFE_##addr)
99
100 static int cafe_device_ready(struct mtd_info *mtd)
101 {
102         struct cafe_priv *cafe = mtd->priv;
103         int result = !!(cafe_readl(cafe, NAND_STATUS) | 0x40000000);
104         uint32_t irqs = cafe_readl(cafe, NAND_IRQ);
105
106         cafe_writel(cafe, irqs, NAND_IRQ);
107
108         cafe_dev_dbg(&cafe->pdev->dev, "NAND device is%s ready, IRQ %x (%x) (%x,%x)\n",
109                 result?"":" not", irqs, cafe_readl(cafe, NAND_IRQ),
110                 cafe_readl(cafe, GLOBAL_IRQ), cafe_readl(cafe, GLOBAL_IRQ_MASK));
111
112         return result;
113 }
114
115
116 static void cafe_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
117 {
118         struct cafe_priv *cafe = mtd->priv;
119
120         if (usedma)
121                 memcpy(cafe->dmabuf + cafe->datalen, buf, len);
122         else
123                 memcpy_toio(cafe->mmio + CAFE_NAND_WRITE_DATA + cafe->datalen, buf, len);
124
125         cafe->datalen += len;
126
127         cafe_dev_dbg(&cafe->pdev->dev, "Copy 0x%x bytes to write buffer. datalen 0x%x\n",
128                 len, cafe->datalen);
129 }
130
131 static void cafe_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
132 {
133         struct cafe_priv *cafe = mtd->priv;
134
135         if (usedma)
136                 memcpy(buf, cafe->dmabuf + cafe->datalen, len);
137         else
138                 memcpy_fromio(buf, cafe->mmio + CAFE_NAND_READ_DATA + cafe->datalen, len);
139
140         cafe_dev_dbg(&cafe->pdev->dev, "Copy 0x%x bytes from position 0x%x in read buffer.\n",
141                   len, cafe->datalen);
142         cafe->datalen += len;
143 }
144
145 static uint8_t cafe_read_byte(struct mtd_info *mtd)
146 {
147         struct cafe_priv *cafe = mtd->priv;
148         uint8_t d;
149
150         cafe_read_buf(mtd, &d, 1);
151         cafe_dev_dbg(&cafe->pdev->dev, "Read %02x\n", d);
152
153         return d;
154 }
155
156 static void cafe_nand_cmdfunc(struct mtd_info *mtd, unsigned command,
157                               int column, int page_addr)
158 {
159         struct cafe_priv *cafe = mtd->priv;
160         int adrbytes = 0;
161         uint32_t ctl1;
162         uint32_t doneint = 0x80000000;
163
164         cafe_dev_dbg(&cafe->pdev->dev, "cmdfunc %02x, 0x%x, 0x%x\n",
165                 command, column, page_addr);
166
167         if (command == NAND_CMD_ERASE2 || command == NAND_CMD_PAGEPROG) {
168                 /* Second half of a command we already calculated */
169                 cafe_writel(cafe, cafe->ctl2 | 0x100 | command, NAND_CTRL2);
170                 ctl1 = cafe->ctl1;
171                 cafe->ctl2 &= ~(1<<30);
172                 cafe_dev_dbg(&cafe->pdev->dev, "Continue command, ctl1 %08x, #data %d\n",
173                           cafe->ctl1, cafe->nr_data);
174                 goto do_command;
175         }
176         /* Reset ECC engine */
177         cafe_writel(cafe, 0, NAND_CTRL2);
178
179         /* Emulate NAND_CMD_READOOB on large-page chips */
180         if (mtd->writesize > 512 &&
181             command == NAND_CMD_READOOB) {
182                 column += mtd->writesize;
183                 command = NAND_CMD_READ0;
184         }
185
186         /* FIXME: Do we need to send read command before sending data
187            for small-page chips, to position the buffer correctly? */
188
189         if (column != -1) {
190                 cafe_writel(cafe, column, NAND_ADDR1);
191                 adrbytes = 2;
192                 if (page_addr != -1)
193                         goto write_adr2;
194         } else if (page_addr != -1) {
195                 cafe_writel(cafe, page_addr & 0xffff, NAND_ADDR1);
196                 page_addr >>= 16;
197         write_adr2:
198                 cafe_writel(cafe, page_addr, NAND_ADDR2);
199                 adrbytes += 2;
200                 if (mtd->size > mtd->writesize << 16)
201                         adrbytes++;
202         }
203
204         cafe->data_pos = cafe->datalen = 0;
205
206         /* Set command valid bit, mask in the chip select bit  */
207         ctl1 = 0x80000000 | command | (cafe->ctl1 & CTRL1_CHIPSELECT);
208
209         /* Set RD or WR bits as appropriate */
210         if (command == NAND_CMD_READID || command == NAND_CMD_STATUS) {
211                 ctl1 |= (1<<26); /* rd */
212                 /* Always 5 bytes, for now */
213                 cafe->datalen = 4;
214                 /* And one address cycle -- even for STATUS, since the controller doesn't work without */
215                 adrbytes = 1;
216         } else if (command == NAND_CMD_READ0 || command == NAND_CMD_READ1 ||
217                    command == NAND_CMD_READOOB || command == NAND_CMD_RNDOUT) {
218                 ctl1 |= 1<<26; /* rd */
219                 /* For now, assume just read to end of page */
220                 cafe->datalen = mtd->writesize + mtd->oobsize - column;
221         } else if (command == NAND_CMD_SEQIN)
222                 ctl1 |= 1<<25; /* wr */
223
224         /* Set number of address bytes */
225         if (adrbytes)
226                 ctl1 |= ((adrbytes-1)|8) << 27;
227
228         if (command == NAND_CMD_SEQIN || command == NAND_CMD_ERASE1) {
229                 /* Ignore the first command of a pair; the hardware
230                    deals with them both at once, later */
231                 cafe->ctl1 = ctl1;
232                 cafe_dev_dbg(&cafe->pdev->dev, "Setup for delayed command, ctl1 %08x, dlen %x\n",
233                           cafe->ctl1, cafe->datalen);
234                 return;
235         }
236         /* RNDOUT and READ0 commands need a following byte */
237         if (command == NAND_CMD_RNDOUT)
238                 cafe_writel(cafe, cafe->ctl2 | 0x100 | NAND_CMD_RNDOUTSTART, NAND_CTRL2);
239         else if (command == NAND_CMD_READ0 && mtd->writesize > 512)
240                 cafe_writel(cafe, cafe->ctl2 | 0x100 | NAND_CMD_READSTART, NAND_CTRL2);
241
242  do_command:
243         cafe_dev_dbg(&cafe->pdev->dev, "dlen %x, ctl1 %x, ctl2 %x\n",
244                 cafe->datalen, ctl1, cafe_readl(cafe, NAND_CTRL2));
245
246         /* NB: The datasheet lies -- we really should be subtracting 1 here */
247         cafe_writel(cafe, cafe->datalen, NAND_DATA_LEN);
248         cafe_writel(cafe, 0x90000000, NAND_IRQ);
249         if (usedma && (ctl1 & (3<<25))) {
250                 uint32_t dmactl = 0xc0000000 + cafe->datalen;
251                 /* If WR or RD bits set, set up DMA */
252                 if (ctl1 & (1<<26)) {
253                         /* It's a read */
254                         dmactl |= (1<<29);
255                         /* ... so it's done when the DMA is done, not just
256                            the command. */
257                         doneint = 0x10000000;
258                 }
259                 cafe_writel(cafe, dmactl, NAND_DMA_CTRL);
260         }
261         cafe->datalen = 0;
262
263         if (unlikely(regdebug)) {
264                 int i;
265                 printk("About to write command %08x to register 0\n", ctl1);
266                 for (i=4; i< 0x5c; i+=4)
267                         printk("Register %x: %08x\n", i, readl(cafe->mmio + i));
268         }
269
270         cafe_writel(cafe, ctl1, NAND_CTRL1);
271         /* Apply this short delay always to ensure that we do wait tWB in
272          * any case on any machine. */
273         ndelay(100);
274
275         if (1) {
276                 int c;
277                 uint32_t irqs;
278
279                 for (c = 500000; c != 0; c--) {
280                         irqs = cafe_readl(cafe, NAND_IRQ);
281                         if (irqs & doneint)
282                                 break;
283                         udelay(1);
284                         if (!(c % 100000))
285                                 cafe_dev_dbg(&cafe->pdev->dev, "Wait for ready, IRQ %x\n", irqs);
286                         cpu_relax();
287                 }
288                 cafe_writel(cafe, doneint, NAND_IRQ);
289                 cafe_dev_dbg(&cafe->pdev->dev, "Command %x completed after %d usec, irqs %x (%x)\n",
290                              command, 500000-c, irqs, cafe_readl(cafe, NAND_IRQ));
291         }
292
293         WARN_ON(cafe->ctl2 & (1<<30));
294
295         switch (command) {
296
297         case NAND_CMD_CACHEDPROG:
298         case NAND_CMD_PAGEPROG:
299         case NAND_CMD_ERASE1:
300         case NAND_CMD_ERASE2:
301         case NAND_CMD_SEQIN:
302         case NAND_CMD_RNDIN:
303         case NAND_CMD_STATUS:
304         case NAND_CMD_DEPLETE1:
305         case NAND_CMD_RNDOUT:
306         case NAND_CMD_STATUS_ERROR:
307         case NAND_CMD_STATUS_ERROR0:
308         case NAND_CMD_STATUS_ERROR1:
309         case NAND_CMD_STATUS_ERROR2:
310         case NAND_CMD_STATUS_ERROR3:
311                 cafe_writel(cafe, cafe->ctl2, NAND_CTRL2);
312                 return;
313         }
314         nand_wait_ready(mtd);
315         cafe_writel(cafe, cafe->ctl2, NAND_CTRL2);
316 }
317
318 static void cafe_select_chip(struct mtd_info *mtd, int chipnr)
319 {
320         struct cafe_priv *cafe = mtd->priv;
321
322         cafe_dev_dbg(&cafe->pdev->dev, "select_chip %d\n", chipnr);
323
324         /* Mask the appropriate bit into the stored value of ctl1
325            which will be used by cafe_nand_cmdfunc() */
326         if (chipnr)
327                 cafe->ctl1 |= CTRL1_CHIPSELECT;
328         else
329                 cafe->ctl1 &= ~CTRL1_CHIPSELECT;
330 }
331
332 static int cafe_nand_interrupt(int irq, void *id)
333 {
334         struct mtd_info *mtd = id;
335         struct cafe_priv *cafe = mtd->priv;
336         uint32_t irqs = cafe_readl(cafe, NAND_IRQ);
337         cafe_writel(cafe, irqs & ~0x90000000, NAND_IRQ);
338         if (!irqs)
339                 return IRQ_NONE;
340
341         cafe_dev_dbg(&cafe->pdev->dev, "irq, bits %x (%x)\n", irqs, cafe_readl(cafe, NAND_IRQ));
342         return IRQ_HANDLED;
343 }
344
345 static void cafe_nand_bug(struct mtd_info *mtd)
346 {
347         BUG();
348 }
349
350 static int cafe_nand_write_oob(struct mtd_info *mtd,
351                                struct nand_chip *chip, int page)
352 {
353         int status = 0;
354
355         chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
356         chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
357         chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
358         status = chip->waitfunc(mtd, chip);
359
360         return status & NAND_STATUS_FAIL ? -EIO : 0;
361 }
362
363 /* Don't use -- use nand_read_oob_std for now */
364 static int cafe_nand_read_oob(struct mtd_info *mtd, struct nand_chip *chip,
365                               int page, int sndcmd)
366 {
367         chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
368         chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
369         return 1;
370 }
371 /**
372  * cafe_nand_read_page_syndrome - {REPLACABLE] hardware ecc syndrom based page read
373  * @mtd:        mtd info structure
374  * @chip:       nand chip info structure
375  * @buf:        buffer to store read data
376  *
377  * The hw generator calculates the error syndrome automatically. Therefor
378  * we need a special oob layout and handling.
379  */
380 static int cafe_nand_read_page(struct mtd_info *mtd, struct nand_chip *chip,
381                                uint8_t *buf)
382 {
383         struct cafe_priv *cafe = mtd->priv;
384
385         cafe_dev_dbg(&cafe->pdev->dev, "ECC result %08x SYN1,2 %08x\n",
386                      cafe_readl(cafe, NAND_ECC_RESULT),
387                      cafe_readl(cafe, NAND_ECC_SYN01));
388
389         chip->read_buf(mtd, buf, mtd->writesize);
390         chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
391
392         if (checkecc && cafe_readl(cafe, NAND_ECC_RESULT) & (1<<18)) {
393                 unsigned short syn[8], pat[4];
394                 int pos[4];
395                 u8 *oob = chip->oob_poi;
396                 int i, n;
397
398                 for (i=0; i<8; i+=2) {
399                         uint32_t tmp = cafe_readl(cafe, NAND_ECC_SYN01 + (i*2));
400                         syn[i] = cafe->rs->index_of[tmp & 0xfff];
401                         syn[i+1] = cafe->rs->index_of[(tmp >> 16) & 0xfff];
402                 }
403
404                 n = decode_rs16(cafe->rs, NULL, NULL, 1367, syn, 0, pos, 0,
405                                 pat);
406
407                 for (i = 0; i < n; i++) {
408                         int p = pos[i];
409
410                         /* The 12-bit symbols are mapped to bytes here */
411
412                         if (p > 1374) {
413                                 /* out of range */
414                                 n = -1374;
415                         } else if (p == 0) {
416                                 /* high four bits do not correspond to data */
417                                 if (pat[i] > 0xff)
418                                         n = -2048;
419                                 else
420                                         buf[0] ^= pat[i];
421                         } else if (p == 1365) {
422                                 buf[2047] ^= pat[i] >> 4;
423                                 oob[0] ^= pat[i] << 4;
424                         } else if (p > 1365) {
425                                 if ((p & 1) == 1) {
426                                         oob[3*p/2 - 2048] ^= pat[i] >> 4;
427                                         oob[3*p/2 - 2047] ^= pat[i] << 4;
428                                 } else {
429                                         oob[3*p/2 - 2049] ^= pat[i] >> 8;
430                                         oob[3*p/2 - 2048] ^= pat[i];
431                                 }
432                         } else if ((p & 1) == 1) {
433                                 buf[3*p/2] ^= pat[i] >> 4;
434                                 buf[3*p/2 + 1] ^= pat[i] << 4;
435                         } else {
436                                 buf[3*p/2 - 1] ^= pat[i] >> 8;
437                                 buf[3*p/2] ^= pat[i];
438                         }
439                 }
440
441                 if (n < 0) {
442                         dev_dbg(&cafe->pdev->dev, "Failed to correct ECC at %08x\n",
443                                 cafe_readl(cafe, NAND_ADDR2) * 2048);
444                         for (i = 0; i < 0x5c; i += 4)
445                                 printk("Register %x: %08x\n", i, readl(cafe->mmio + i));
446                         mtd->ecc_stats.failed++;
447                 } else {
448                         dev_dbg(&cafe->pdev->dev, "Corrected %d symbol errors\n", n);
449                         mtd->ecc_stats.corrected += n;
450                 }
451         }
452
453         return 0;
454 }
455
456 static struct nand_ecclayout cafe_oobinfo_2048 = {
457         .eccbytes = 14,
458         .eccpos = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13},
459         .oobfree = {{14, 50}}
460 };
461
462 /* Ick. The BBT code really ought to be able to work this bit out
463    for itself from the above, at least for the 2KiB case */
464 static uint8_t cafe_bbt_pattern_2048[] = { 'B', 'b', 't', '0' };
465 static uint8_t cafe_mirror_pattern_2048[] = { '1', 't', 'b', 'B' };
466
467 static uint8_t cafe_bbt_pattern_512[] = { 0xBB };
468 static uint8_t cafe_mirror_pattern_512[] = { 0xBC };
469
470
471 static struct nand_bbt_descr cafe_bbt_main_descr_2048 = {
472         .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
473                 | NAND_BBT_2BIT | NAND_BBT_VERSION,
474         .offs = 14,
475         .len = 4,
476         .veroffs = 18,
477         .maxblocks = 4,
478         .pattern = cafe_bbt_pattern_2048
479 };
480
481 static struct nand_bbt_descr cafe_bbt_mirror_descr_2048 = {
482         .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
483                 | NAND_BBT_2BIT | NAND_BBT_VERSION,
484         .offs = 14,
485         .len = 4,
486         .veroffs = 18,
487         .maxblocks = 4,
488         .pattern = cafe_mirror_pattern_2048
489 };
490
491 static struct nand_ecclayout cafe_oobinfo_512 = {
492         .eccbytes = 14,
493         .eccpos = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13},
494         .oobfree = {{14, 2}}
495 };
496
497 static struct nand_bbt_descr cafe_bbt_main_descr_512 = {
498         .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
499                 | NAND_BBT_2BIT | NAND_BBT_VERSION,
500         .offs = 14,
501         .len = 1,
502         .veroffs = 15,
503         .maxblocks = 4,
504         .pattern = cafe_bbt_pattern_512
505 };
506
507 static struct nand_bbt_descr cafe_bbt_mirror_descr_512 = {
508         .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
509                 | NAND_BBT_2BIT | NAND_BBT_VERSION,
510         .offs = 14,
511         .len = 1,
512         .veroffs = 15,
513         .maxblocks = 4,
514         .pattern = cafe_mirror_pattern_512
515 };
516
517
518 static void cafe_nand_write_page_lowlevel(struct mtd_info *mtd,
519                                           struct nand_chip *chip, const uint8_t *buf)
520 {
521         struct cafe_priv *cafe = mtd->priv;
522
523         chip->write_buf(mtd, buf, mtd->writesize);
524         chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
525
526         /* Set up ECC autogeneration */
527         cafe->ctl2 |= (1<<30);
528 }
529
530 static int cafe_nand_write_page(struct mtd_info *mtd, struct nand_chip *chip,
531                                 const uint8_t *buf, int page, int cached, int raw)
532 {
533         int status;
534
535         chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page);
536
537         if (unlikely(raw))
538                 chip->ecc.write_page_raw(mtd, chip, buf);
539         else
540                 chip->ecc.write_page(mtd, chip, buf);
541
542         /*
543          * Cached progamming disabled for now, Not sure if its worth the
544          * trouble. The speed gain is not very impressive. (2.3->2.6Mib/s)
545          */
546         cached = 0;
547
548         if (!cached || !(chip->options & NAND_CACHEPRG)) {
549
550                 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
551                 status = chip->waitfunc(mtd, chip);
552                 /*
553                  * See if operation failed and additional status checks are
554                  * available
555                  */
556                 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
557                         status = chip->errstat(mtd, chip, FL_WRITING, status,
558                                                page);
559
560                 if (status & NAND_STATUS_FAIL)
561                         return -EIO;
562         } else {
563                 chip->cmdfunc(mtd, NAND_CMD_CACHEDPROG, -1, -1);
564                 status = chip->waitfunc(mtd, chip);
565         }
566
567 #ifdef CONFIG_MTD_NAND_VERIFY_WRITE
568         /* Send command to read back the data */
569         chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
570
571         if (chip->verify_buf(mtd, buf, mtd->writesize))
572                 return -EIO;
573 #endif
574         return 0;
575 }
576
577 static int cafe_nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip)
578 {
579         return 0;
580 }
581
582 /* F_2[X]/(X**6+X+1)  */
583 static unsigned short __devinit gf64_mul(u8 a, u8 b)
584 {
585         u8 c;
586         unsigned int i;
587
588         c = 0;
589         for (i = 0; i < 6; i++) {
590                 if (a & 1)
591                         c ^= b;
592                 a >>= 1;
593                 b <<= 1;
594                 if ((b & 0x40) != 0)
595                         b ^= 0x43;
596         }
597
598         return c;
599 }
600
601 /* F_64[X]/(X**2+X+A**-1) with A the generator of F_64[X]  */
602 static u16 __devinit gf4096_mul(u16 a, u16 b)
603 {
604         u8 ah, al, bh, bl, ch, cl;
605
606         ah = a >> 6;
607         al = a & 0x3f;
608         bh = b >> 6;
609         bl = b & 0x3f;
610
611         ch = gf64_mul(ah ^ al, bh ^ bl) ^ gf64_mul(al, bl);
612         cl = gf64_mul(gf64_mul(ah, bh), 0x21) ^ gf64_mul(al, bl);
613
614         return (ch << 6) ^ cl;
615 }
616
617 static int __devinit cafe_mul(int x)
618 {
619         if (x == 0)
620                 return 1;
621         return gf4096_mul(x, 0xe01);
622 }
623
624 static int __devinit cafe_nand_probe(struct pci_dev *pdev,
625                                      const struct pci_device_id *ent)
626 {
627         struct mtd_info *mtd;
628         struct cafe_priv *cafe;
629         uint32_t ctrl;
630         int err = 0;
631 #ifdef CONFIG_MTD_PARTITIONS
632         struct mtd_partition *parts;
633         int nr_parts;
634 #endif
635
636         /* Very old versions shared the same PCI ident for all three
637            functions on the chip. Verify the class too... */
638         if ((pdev->class >> 8) != PCI_CLASS_MEMORY_FLASH)
639                 return -ENODEV;
640
641         err = pci_enable_device(pdev);
642         if (err)
643                 return err;
644
645         pci_set_master(pdev);
646
647         mtd = kzalloc(sizeof(*mtd) + sizeof(struct cafe_priv), GFP_KERNEL);
648         if (!mtd) {
649                 dev_warn(&pdev->dev, "failed to alloc mtd_info\n");
650                 return  -ENOMEM;
651         }
652         cafe = (void *)(&mtd[1]);
653
654         mtd->priv = cafe;
655         mtd->owner = THIS_MODULE;
656
657         cafe->pdev = pdev;
658         cafe->mmio = pci_iomap(pdev, 0, 0);
659         if (!cafe->mmio) {
660                 dev_warn(&pdev->dev, "failed to iomap\n");
661                 err = -ENOMEM;
662                 goto out_free_mtd;
663         }
664         cafe->dmabuf = dma_alloc_coherent(&cafe->pdev->dev, 2112 + sizeof(struct nand_buffers),
665                                           &cafe->dmaaddr, GFP_KERNEL);
666         if (!cafe->dmabuf) {
667                 err = -ENOMEM;
668                 goto out_ior;
669         }
670         cafe->nand.buffers = (void *)cafe->dmabuf + 2112;
671
672         cafe->rs = init_rs_non_canonical(12, &cafe_mul, 0, 1, 8);
673         if (!cafe->rs) {
674                 err = -ENOMEM;
675                 goto out_ior;
676         }
677
678         cafe->nand.cmdfunc = cafe_nand_cmdfunc;
679         cafe->nand.dev_ready = cafe_device_ready;
680         cafe->nand.read_byte = cafe_read_byte;
681         cafe->nand.read_buf = cafe_read_buf;
682         cafe->nand.write_buf = cafe_write_buf;
683         cafe->nand.select_chip = cafe_select_chip;
684
685         cafe->nand.chip_delay = 0;
686
687         /* Enable the following for a flash based bad block table */
688         cafe->nand.options = NAND_USE_FLASH_BBT | NAND_NO_AUTOINCR | NAND_OWN_BUFFERS;
689
690         if (skipbbt) {
691                 cafe->nand.options |= NAND_SKIP_BBTSCAN;
692                 cafe->nand.block_bad = cafe_nand_block_bad;
693         }
694
695         if (numtimings && numtimings != 3) {
696                 dev_warn(&cafe->pdev->dev, "%d timing register values ignored; precisely three are required\n", numtimings);
697         }
698
699         if (numtimings == 3) {
700                 cafe_dev_dbg(&cafe->pdev->dev, "Using provided timings (%08x %08x %08x)\n",
701                              timing[0], timing[1], timing[2]);
702         } else {
703                 timing[0] = cafe_readl(cafe, NAND_TIMING1);
704                 timing[1] = cafe_readl(cafe, NAND_TIMING2);
705                 timing[2] = cafe_readl(cafe, NAND_TIMING3);
706
707                 if (timing[0] | timing[1] | timing[2]) {
708                         cafe_dev_dbg(&cafe->pdev->dev, "Timing registers already set (%08x %08x %08x)\n",
709                                      timing[0], timing[1], timing[2]);
710                 } else {
711                         dev_warn(&cafe->pdev->dev, "Timing registers unset; using most conservative defaults\n");
712                         timing[0] = timing[1] = timing[2] = 0xffffffff;
713                 }
714         }
715
716         /* Start off by resetting the NAND controller completely */
717         cafe_writel(cafe, 1, NAND_RESET);
718         cafe_writel(cafe, 0, NAND_RESET);
719
720         cafe_writel(cafe, timing[0], NAND_TIMING1);
721         cafe_writel(cafe, timing[1], NAND_TIMING2);
722         cafe_writel(cafe, timing[2], NAND_TIMING3);
723
724         cafe_writel(cafe, 0xffffffff, NAND_IRQ_MASK);
725         err = request_irq(pdev->irq, &cafe_nand_interrupt, IRQF_SHARED,
726                           "CAFE NAND", mtd);
727         if (err) {
728                 dev_warn(&pdev->dev, "Could not register IRQ %d\n", pdev->irq);
729                 goto out_free_dma;
730         }
731
732         /* Disable master reset, enable NAND clock */
733         ctrl = cafe_readl(cafe, GLOBAL_CTRL);
734         ctrl &= 0xffffeff0;
735         ctrl |= 0x00007000;
736         cafe_writel(cafe, ctrl | 0x05, GLOBAL_CTRL);
737         cafe_writel(cafe, ctrl | 0x0a, GLOBAL_CTRL);
738         cafe_writel(cafe, 0, NAND_DMA_CTRL);
739
740         cafe_writel(cafe, 0x7006, GLOBAL_CTRL);
741         cafe_writel(cafe, 0x700a, GLOBAL_CTRL);
742
743         /* Set up DMA address */
744         cafe_writel(cafe, cafe->dmaaddr & 0xffffffff, NAND_DMA_ADDR0);
745         if (sizeof(cafe->dmaaddr) > 4)
746                 /* Shift in two parts to shut the compiler up */
747                 cafe_writel(cafe, (cafe->dmaaddr >> 16) >> 16, NAND_DMA_ADDR1);
748         else
749                 cafe_writel(cafe, 0, NAND_DMA_ADDR1);
750
751         cafe_dev_dbg(&cafe->pdev->dev, "Set DMA address to %x (virt %p)\n",
752                 cafe_readl(cafe, NAND_DMA_ADDR0), cafe->dmabuf);
753
754         /* Enable NAND IRQ in global IRQ mask register */
755         cafe_writel(cafe, 0x80000007, GLOBAL_IRQ_MASK);
756         cafe_dev_dbg(&cafe->pdev->dev, "Control %x, IRQ mask %x\n",
757                 cafe_readl(cafe, GLOBAL_CTRL), cafe_readl(cafe, GLOBAL_IRQ_MASK));
758
759         /* Scan to find existence of the device */
760         if (nand_scan_ident(mtd, 2)) {
761                 err = -ENXIO;
762                 goto out_irq;
763         }
764
765         cafe->ctl2 = 1<<27; /* Reed-Solomon ECC */
766         if (mtd->writesize == 2048)
767                 cafe->ctl2 |= 1<<29; /* 2KiB page size */
768
769         /* Set up ECC according to the type of chip we found */
770         if (mtd->writesize == 2048) {
771                 cafe->nand.ecc.layout = &cafe_oobinfo_2048;
772                 cafe->nand.bbt_td = &cafe_bbt_main_descr_2048;
773                 cafe->nand.bbt_md = &cafe_bbt_mirror_descr_2048;
774         } else if (mtd->writesize == 512) {
775                 cafe->nand.ecc.layout = &cafe_oobinfo_512;
776                 cafe->nand.bbt_td = &cafe_bbt_main_descr_512;
777                 cafe->nand.bbt_md = &cafe_bbt_mirror_descr_512;
778         } else {
779                 printk(KERN_WARNING "Unexpected NAND flash writesize %d. Aborting\n",
780                        mtd->writesize);
781                 goto out_irq;
782         }
783         cafe->nand.ecc.mode = NAND_ECC_HW_SYNDROME;
784         cafe->nand.ecc.size = mtd->writesize;
785         cafe->nand.ecc.bytes = 14;
786         cafe->nand.ecc.hwctl  = (void *)cafe_nand_bug;
787         cafe->nand.ecc.calculate = (void *)cafe_nand_bug;
788         cafe->nand.ecc.correct  = (void *)cafe_nand_bug;
789         cafe->nand.write_page = cafe_nand_write_page;
790         cafe->nand.ecc.write_page = cafe_nand_write_page_lowlevel;
791         cafe->nand.ecc.write_oob = cafe_nand_write_oob;
792         cafe->nand.ecc.read_page = cafe_nand_read_page;
793         cafe->nand.ecc.read_oob = cafe_nand_read_oob;
794
795         err = nand_scan_tail(mtd);
796         if (err)
797                 goto out_irq;
798
799         pci_set_drvdata(pdev, mtd);
800
801         /* We register the whole device first, separate from the partitions */
802         add_mtd_device(mtd);
803
804 #ifdef CONFIG_MTD_PARTITIONS
805         nr_parts = parse_mtd_partitions(mtd, part_probes, &parts, 0);
806         if (nr_parts > 0) {
807                 cafe->parts = parts;
808                 dev_info(&cafe->pdev->dev, "%d RedBoot partitions found\n", nr_parts);
809                 add_mtd_partitions(mtd, parts, nr_parts);
810         }
811 #endif
812         goto out;
813
814  out_irq:
815         /* Disable NAND IRQ in global IRQ mask register */
816         cafe_writel(cafe, ~1 & cafe_readl(cafe, GLOBAL_IRQ_MASK), GLOBAL_IRQ_MASK);
817         free_irq(pdev->irq, mtd);
818  out_free_dma:
819         dma_free_coherent(&cafe->pdev->dev, 2112, cafe->dmabuf, cafe->dmaaddr);
820  out_ior:
821         pci_iounmap(pdev, cafe->mmio);
822  out_free_mtd:
823         kfree(mtd);
824  out:
825         return err;
826 }
827
828 static void __devexit cafe_nand_remove(struct pci_dev *pdev)
829 {
830         struct mtd_info *mtd = pci_get_drvdata(pdev);
831         struct cafe_priv *cafe = mtd->priv;
832
833         del_mtd_device(mtd);
834         /* Disable NAND IRQ in global IRQ mask register */
835         cafe_writel(cafe, ~1 & cafe_readl(cafe, GLOBAL_IRQ_MASK), GLOBAL_IRQ_MASK);
836         free_irq(pdev->irq, mtd);
837         nand_release(mtd);
838         free_rs(cafe->rs);
839         pci_iounmap(pdev, cafe->mmio);
840         dma_free_coherent(&cafe->pdev->dev, 2112, cafe->dmabuf, cafe->dmaaddr);
841         kfree(mtd);
842 }
843
844 static struct pci_device_id cafe_nand_tbl[] = {
845         { 0x11ab, 0x4100, PCI_ANY_ID, PCI_ANY_ID },
846         { }
847 };
848
849 MODULE_DEVICE_TABLE(pci, cafe_nand_tbl);
850
851 static int cafe_nand_resume(struct pci_dev *pdev)
852 {
853         uint32_t ctrl;
854         struct mtd_info *mtd = pci_get_drvdata(pdev);
855         struct cafe_priv *cafe = mtd->priv;
856
857        /* Start off by resetting the NAND controller completely */
858         cafe_writel(cafe, 1, NAND_RESET);
859         cafe_writel(cafe, 0, NAND_RESET);
860         cafe_writel(cafe, 0xffffffff, NAND_IRQ_MASK);
861
862         /* Restore timing configuration */
863         cafe_writel(cafe, timing[0], NAND_TIMING1);
864         cafe_writel(cafe, timing[1], NAND_TIMING2);
865         cafe_writel(cafe, timing[2], NAND_TIMING3);
866
867         /* Disable master reset, enable NAND clock */
868         ctrl = cafe_readl(cafe, GLOBAL_CTRL);
869         ctrl &= 0xffffeff0;
870         ctrl |= 0x00007000;
871         cafe_writel(cafe, ctrl | 0x05, GLOBAL_CTRL);
872         cafe_writel(cafe, ctrl | 0x0a, GLOBAL_CTRL);
873         cafe_writel(cafe, 0, NAND_DMA_CTRL);
874         cafe_writel(cafe, 0x7006, GLOBAL_CTRL);
875         cafe_writel(cafe, 0x700a, GLOBAL_CTRL);
876
877         /* Set up DMA address */
878         cafe_writel(cafe, cafe->dmaaddr & 0xffffffff, NAND_DMA_ADDR0);
879         if (sizeof(cafe->dmaaddr) > 4)
880         /* Shift in two parts to shut the compiler up */
881                 cafe_writel(cafe, (cafe->dmaaddr >> 16) >> 16, NAND_DMA_ADDR1);
882         else
883                 cafe_writel(cafe, 0, NAND_DMA_ADDR1);
884
885         /* Enable NAND IRQ in global IRQ mask register */
886         cafe_writel(cafe, 0x80000007, GLOBAL_IRQ_MASK);
887         return 0;
888 }
889
890 static struct pci_driver cafe_nand_pci_driver = {
891         .name = "CAFÉ NAND",
892         .id_table = cafe_nand_tbl,
893         .probe = cafe_nand_probe,
894         .remove = __devexit_p(cafe_nand_remove),
895         .resume = cafe_nand_resume,
896 };
897
898 static int cafe_nand_init(void)
899 {
900         return pci_register_driver(&cafe_nand_pci_driver);
901 }
902
903 static void cafe_nand_exit(void)
904 {
905         pci_unregister_driver(&cafe_nand_pci_driver);
906 }
907 module_init(cafe_nand_init);
908 module_exit(cafe_nand_exit);
909
910 MODULE_LICENSE("GPL");
911 MODULE_AUTHOR("David Woodhouse <dwmw2@infradead.org>");
912 MODULE_DESCRIPTION("NAND flash driver for OLPC CAFÉ chip");