Merge branch 'master' into devel
[linux-2.6] / sound / pci / oxygen / oxygen_lib.c
1 /*
2  * C-Media CMI8788 driver - main driver module
3  *
4  * Copyright (c) Clemens Ladisch <clemens@ladisch.de>
5  *
6  *
7  *  This driver is free software; you can redistribute it and/or modify
8  *  it under the terms of the GNU General Public License, version 2.
9  *
10  *  This driver is distributed in the hope that it will be useful,
11  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
12  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13  *  GNU General Public License for more details.
14  *
15  *  You should have received a copy of the GNU General Public License
16  *  along with this driver; if not, write to the Free Software
17  *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
18  */
19
20 #include <linux/delay.h>
21 #include <linux/interrupt.h>
22 #include <linux/mutex.h>
23 #include <linux/pci.h>
24 #include <sound/ac97_codec.h>
25 #include <sound/asoundef.h>
26 #include <sound/core.h>
27 #include <sound/info.h>
28 #include <sound/mpu401.h>
29 #include <sound/pcm.h>
30 #include "oxygen.h"
31 #include "cm9780.h"
32
33 MODULE_AUTHOR("Clemens Ladisch <clemens@ladisch.de>");
34 MODULE_DESCRIPTION("C-Media CMI8788 helper library");
35 MODULE_LICENSE("GPL v2");
36
37 #define DRIVER "oxygen"
38
39 static inline int oxygen_uart_input_ready(struct oxygen *chip)
40 {
41         return !(oxygen_read8(chip, OXYGEN_MPU401 + 1) & MPU401_RX_EMPTY);
42 }
43
44 static void oxygen_read_uart(struct oxygen *chip)
45 {
46         if (unlikely(!oxygen_uart_input_ready(chip))) {
47                 /* no data, but read it anyway to clear the interrupt */
48                 oxygen_read8(chip, OXYGEN_MPU401);
49                 return;
50         }
51         do {
52                 u8 data = oxygen_read8(chip, OXYGEN_MPU401);
53                 if (data == MPU401_ACK)
54                         continue;
55                 if (chip->uart_input_count >= ARRAY_SIZE(chip->uart_input))
56                         chip->uart_input_count = 0;
57                 chip->uart_input[chip->uart_input_count++] = data;
58         } while (oxygen_uart_input_ready(chip));
59         if (chip->model.uart_input)
60                 chip->model.uart_input(chip);
61 }
62
63 static irqreturn_t oxygen_interrupt(int dummy, void *dev_id)
64 {
65         struct oxygen *chip = dev_id;
66         unsigned int status, clear, elapsed_streams, i;
67
68         status = oxygen_read16(chip, OXYGEN_INTERRUPT_STATUS);
69         if (!status)
70                 return IRQ_NONE;
71
72         spin_lock(&chip->reg_lock);
73
74         clear = status & (OXYGEN_CHANNEL_A |
75                           OXYGEN_CHANNEL_B |
76                           OXYGEN_CHANNEL_C |
77                           OXYGEN_CHANNEL_SPDIF |
78                           OXYGEN_CHANNEL_MULTICH |
79                           OXYGEN_CHANNEL_AC97 |
80                           OXYGEN_INT_SPDIF_IN_DETECT |
81                           OXYGEN_INT_GPIO |
82                           OXYGEN_INT_AC97);
83         if (clear) {
84                 if (clear & OXYGEN_INT_SPDIF_IN_DETECT)
85                         chip->interrupt_mask &= ~OXYGEN_INT_SPDIF_IN_DETECT;
86                 oxygen_write16(chip, OXYGEN_INTERRUPT_MASK,
87                                chip->interrupt_mask & ~clear);
88                 oxygen_write16(chip, OXYGEN_INTERRUPT_MASK,
89                                chip->interrupt_mask);
90         }
91
92         elapsed_streams = status & chip->pcm_running;
93
94         spin_unlock(&chip->reg_lock);
95
96         for (i = 0; i < PCM_COUNT; ++i)
97                 if ((elapsed_streams & (1 << i)) && chip->streams[i])
98                         snd_pcm_period_elapsed(chip->streams[i]);
99
100         if (status & OXYGEN_INT_SPDIF_IN_DETECT) {
101                 spin_lock(&chip->reg_lock);
102                 i = oxygen_read32(chip, OXYGEN_SPDIF_CONTROL);
103                 if (i & (OXYGEN_SPDIF_SENSE_INT | OXYGEN_SPDIF_LOCK_INT |
104                          OXYGEN_SPDIF_RATE_INT)) {
105                         /* write the interrupt bit(s) to clear */
106                         oxygen_write32(chip, OXYGEN_SPDIF_CONTROL, i);
107                         schedule_work(&chip->spdif_input_bits_work);
108                 }
109                 spin_unlock(&chip->reg_lock);
110         }
111
112         if (status & OXYGEN_INT_GPIO)
113                 schedule_work(&chip->gpio_work);
114
115         if (status & OXYGEN_INT_MIDI) {
116                 if (chip->midi)
117                         snd_mpu401_uart_interrupt(0, chip->midi->private_data);
118                 else
119                         oxygen_read_uart(chip);
120         }
121
122         if (status & OXYGEN_INT_AC97)
123                 wake_up(&chip->ac97_waitqueue);
124
125         return IRQ_HANDLED;
126 }
127
128 static void oxygen_spdif_input_bits_changed(struct work_struct *work)
129 {
130         struct oxygen *chip = container_of(work, struct oxygen,
131                                            spdif_input_bits_work);
132         u32 reg;
133
134         /*
135          * This function gets called when there is new activity on the SPDIF
136          * input, or when we lose lock on the input signal, or when the rate
137          * changes.
138          */
139         msleep(1);
140         spin_lock_irq(&chip->reg_lock);
141         reg = oxygen_read32(chip, OXYGEN_SPDIF_CONTROL);
142         if ((reg & (OXYGEN_SPDIF_SENSE_STATUS |
143                     OXYGEN_SPDIF_LOCK_STATUS))
144             == OXYGEN_SPDIF_SENSE_STATUS) {
145                 /*
146                  * If we detect activity on the SPDIF input but cannot lock to
147                  * a signal, the clock bit is likely to be wrong.
148                  */
149                 reg ^= OXYGEN_SPDIF_IN_CLOCK_MASK;
150                 oxygen_write32(chip, OXYGEN_SPDIF_CONTROL, reg);
151                 spin_unlock_irq(&chip->reg_lock);
152                 msleep(1);
153                 spin_lock_irq(&chip->reg_lock);
154                 reg = oxygen_read32(chip, OXYGEN_SPDIF_CONTROL);
155                 if ((reg & (OXYGEN_SPDIF_SENSE_STATUS |
156                             OXYGEN_SPDIF_LOCK_STATUS))
157                     == OXYGEN_SPDIF_SENSE_STATUS) {
158                         /* nothing detected with either clock; give up */
159                         if ((reg & OXYGEN_SPDIF_IN_CLOCK_MASK)
160                             == OXYGEN_SPDIF_IN_CLOCK_192) {
161                                 /*
162                                  * Reset clock to <= 96 kHz because this is
163                                  * more likely to be received next time.
164                                  */
165                                 reg &= ~OXYGEN_SPDIF_IN_CLOCK_MASK;
166                                 reg |= OXYGEN_SPDIF_IN_CLOCK_96;
167                                 oxygen_write32(chip, OXYGEN_SPDIF_CONTROL, reg);
168                         }
169                 }
170         }
171         spin_unlock_irq(&chip->reg_lock);
172
173         if (chip->controls[CONTROL_SPDIF_INPUT_BITS]) {
174                 spin_lock_irq(&chip->reg_lock);
175                 chip->interrupt_mask |= OXYGEN_INT_SPDIF_IN_DETECT;
176                 oxygen_write16(chip, OXYGEN_INTERRUPT_MASK,
177                                chip->interrupt_mask);
178                 spin_unlock_irq(&chip->reg_lock);
179
180                 /*
181                  * We don't actually know that any channel status bits have
182                  * changed, but let's send a notification just to be sure.
183                  */
184                 snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE,
185                                &chip->controls[CONTROL_SPDIF_INPUT_BITS]->id);
186         }
187 }
188
189 static void oxygen_gpio_changed(struct work_struct *work)
190 {
191         struct oxygen *chip = container_of(work, struct oxygen, gpio_work);
192
193         if (chip->model.gpio_changed)
194                 chip->model.gpio_changed(chip);
195 }
196
197 #ifdef CONFIG_PROC_FS
198 static void oxygen_proc_read(struct snd_info_entry *entry,
199                              struct snd_info_buffer *buffer)
200 {
201         struct oxygen *chip = entry->private_data;
202         int i, j;
203
204         snd_iprintf(buffer, "CMI8788\n\n");
205         for (i = 0; i < OXYGEN_IO_SIZE; i += 0x10) {
206                 snd_iprintf(buffer, "%02x:", i);
207                 for (j = 0; j < 0x10; ++j)
208                         snd_iprintf(buffer, " %02x", oxygen_read8(chip, i + j));
209                 snd_iprintf(buffer, "\n");
210         }
211         if (mutex_lock_interruptible(&chip->mutex) < 0)
212                 return;
213         if (chip->has_ac97_0) {
214                 snd_iprintf(buffer, "\nAC97\n");
215                 for (i = 0; i < 0x80; i += 0x10) {
216                         snd_iprintf(buffer, "%02x:", i);
217                         for (j = 0; j < 0x10; j += 2)
218                                 snd_iprintf(buffer, " %04x",
219                                             oxygen_read_ac97(chip, 0, i + j));
220                         snd_iprintf(buffer, "\n");
221                 }
222         }
223         if (chip->has_ac97_1) {
224                 snd_iprintf(buffer, "\nAC97 2\n");
225                 for (i = 0; i < 0x80; i += 0x10) {
226                         snd_iprintf(buffer, "%02x:", i);
227                         for (j = 0; j < 0x10; j += 2)
228                                 snd_iprintf(buffer, " %04x",
229                                             oxygen_read_ac97(chip, 1, i + j));
230                         snd_iprintf(buffer, "\n");
231                 }
232         }
233         mutex_unlock(&chip->mutex);
234 }
235
236 static void oxygen_proc_init(struct oxygen *chip)
237 {
238         struct snd_info_entry *entry;
239
240         if (!snd_card_proc_new(chip->card, "cmi8788", &entry))
241                 snd_info_set_text_ops(entry, chip, oxygen_proc_read);
242 }
243 #else
244 #define oxygen_proc_init(chip)
245 #endif
246
247 static const struct pci_device_id *
248 oxygen_search_pci_id(struct oxygen *chip, const struct pci_device_id ids[])
249 {
250         u16 subdevice;
251
252         /*
253          * Make sure the EEPROM pins are available, i.e., not used for SPI.
254          * (This function is called before we initialize or use SPI.)
255          */
256         oxygen_clear_bits8(chip, OXYGEN_FUNCTION,
257                            OXYGEN_FUNCTION_ENABLE_SPI_4_5);
258         /*
259          * Read the subsystem device ID directly from the EEPROM, because the
260          * chip didn't if the first EEPROM word was overwritten.
261          */
262         subdevice = oxygen_read_eeprom(chip, 2);
263         /*
264          * We use only the subsystem device ID for searching because it is
265          * unique even without the subsystem vendor ID, which may have been
266          * overwritten in the EEPROM.
267          */
268         for (; ids->vendor; ++ids)
269                 if (ids->subdevice == subdevice &&
270                     ids->driver_data != BROKEN_EEPROM_DRIVER_DATA)
271                         return ids;
272         return NULL;
273 }
274
275 static void oxygen_restore_eeprom(struct oxygen *chip,
276                                   const struct pci_device_id *id)
277 {
278         if (oxygen_read_eeprom(chip, 0) != OXYGEN_EEPROM_ID) {
279                 /*
280                  * This function gets called only when a known card model has
281                  * been detected, i.e., we know there is a valid subsystem
282                  * product ID at index 2 in the EEPROM.  Therefore, we have
283                  * been able to deduce the correct subsystem vendor ID, and
284                  * this is enough information to restore the original EEPROM
285                  * contents.
286                  */
287                 oxygen_write_eeprom(chip, 1, id->subvendor);
288                 oxygen_write_eeprom(chip, 0, OXYGEN_EEPROM_ID);
289
290                 oxygen_set_bits8(chip, OXYGEN_MISC,
291                                  OXYGEN_MISC_WRITE_PCI_SUBID);
292                 pci_write_config_word(chip->pci, PCI_SUBSYSTEM_VENDOR_ID,
293                                       id->subvendor);
294                 pci_write_config_word(chip->pci, PCI_SUBSYSTEM_ID,
295                                       id->subdevice);
296                 oxygen_clear_bits8(chip, OXYGEN_MISC,
297                                    OXYGEN_MISC_WRITE_PCI_SUBID);
298
299                 snd_printk(KERN_INFO "EEPROM ID restored\n");
300         }
301 }
302
303 static void oxygen_init(struct oxygen *chip)
304 {
305         unsigned int i;
306
307         chip->dac_routing = 1;
308         for (i = 0; i < 8; ++i)
309                 chip->dac_volume[i] = chip->model.dac_volume_min;
310         chip->dac_mute = 1;
311         chip->spdif_playback_enable = 1;
312         chip->spdif_bits = OXYGEN_SPDIF_C | OXYGEN_SPDIF_ORIGINAL |
313                 (IEC958_AES1_CON_PCM_CODER << OXYGEN_SPDIF_CATEGORY_SHIFT);
314         chip->spdif_pcm_bits = chip->spdif_bits;
315
316         if (oxygen_read8(chip, OXYGEN_REVISION) & OXYGEN_REVISION_2)
317                 chip->revision = 2;
318         else
319                 chip->revision = 1;
320
321         if (chip->revision == 1)
322                 oxygen_set_bits8(chip, OXYGEN_MISC,
323                                  OXYGEN_MISC_PCI_MEM_W_1_CLOCK);
324
325         i = oxygen_read16(chip, OXYGEN_AC97_CONTROL);
326         chip->has_ac97_0 = (i & OXYGEN_AC97_CODEC_0) != 0;
327         chip->has_ac97_1 = (i & OXYGEN_AC97_CODEC_1) != 0;
328
329         oxygen_write8_masked(chip, OXYGEN_FUNCTION,
330                              OXYGEN_FUNCTION_RESET_CODEC |
331                              chip->model.function_flags,
332                              OXYGEN_FUNCTION_RESET_CODEC |
333                              OXYGEN_FUNCTION_2WIRE_SPI_MASK |
334                              OXYGEN_FUNCTION_ENABLE_SPI_4_5);
335         oxygen_write8(chip, OXYGEN_DMA_STATUS, 0);
336         oxygen_write8(chip, OXYGEN_DMA_PAUSE, 0);
337         oxygen_write8(chip, OXYGEN_PLAY_CHANNELS,
338                       OXYGEN_PLAY_CHANNELS_2 |
339                       OXYGEN_DMA_A_BURST_8 |
340                       OXYGEN_DMA_MULTICH_BURST_8);
341         oxygen_write16(chip, OXYGEN_INTERRUPT_MASK, 0);
342         oxygen_write8_masked(chip, OXYGEN_MISC,
343                              chip->model.misc_flags,
344                              OXYGEN_MISC_WRITE_PCI_SUBID |
345                              OXYGEN_MISC_REC_C_FROM_SPDIF |
346                              OXYGEN_MISC_REC_B_FROM_AC97 |
347                              OXYGEN_MISC_REC_A_FROM_MULTICH |
348                              OXYGEN_MISC_MIDI);
349         oxygen_write8(chip, OXYGEN_REC_FORMAT,
350                       (OXYGEN_FORMAT_16 << OXYGEN_REC_FORMAT_A_SHIFT) |
351                       (OXYGEN_FORMAT_16 << OXYGEN_REC_FORMAT_B_SHIFT) |
352                       (OXYGEN_FORMAT_16 << OXYGEN_REC_FORMAT_C_SHIFT));
353         oxygen_write8(chip, OXYGEN_PLAY_FORMAT,
354                       (OXYGEN_FORMAT_16 << OXYGEN_SPDIF_FORMAT_SHIFT) |
355                       (OXYGEN_FORMAT_16 << OXYGEN_MULTICH_FORMAT_SHIFT));
356         oxygen_write8(chip, OXYGEN_REC_CHANNELS, OXYGEN_REC_CHANNELS_2_2_2);
357         oxygen_write16(chip, OXYGEN_I2S_MULTICH_FORMAT,
358                        OXYGEN_RATE_48000 | chip->model.dac_i2s_format |
359                        OXYGEN_I2S_MCLK_256 | OXYGEN_I2S_BITS_16 |
360                        OXYGEN_I2S_MASTER | OXYGEN_I2S_BCLK_64);
361         if (chip->model.device_config & CAPTURE_0_FROM_I2S_1)
362                 oxygen_write16(chip, OXYGEN_I2S_A_FORMAT,
363                                OXYGEN_RATE_48000 | chip->model.adc_i2s_format |
364                                OXYGEN_I2S_MCLK_256 | OXYGEN_I2S_BITS_16 |
365                                OXYGEN_I2S_MASTER | OXYGEN_I2S_BCLK_64);
366         else
367                 oxygen_write16(chip, OXYGEN_I2S_A_FORMAT,
368                                OXYGEN_I2S_MASTER | OXYGEN_I2S_MUTE_MCLK);
369         if (chip->model.device_config & (CAPTURE_0_FROM_I2S_2 |
370                                          CAPTURE_2_FROM_I2S_2))
371                 oxygen_write16(chip, OXYGEN_I2S_B_FORMAT,
372                                OXYGEN_RATE_48000 | chip->model.adc_i2s_format |
373                                OXYGEN_I2S_MCLK_256 | OXYGEN_I2S_BITS_16 |
374                                OXYGEN_I2S_MASTER | OXYGEN_I2S_BCLK_64);
375         else
376                 oxygen_write16(chip, OXYGEN_I2S_B_FORMAT,
377                                OXYGEN_I2S_MASTER | OXYGEN_I2S_MUTE_MCLK);
378         oxygen_write16(chip, OXYGEN_I2S_C_FORMAT,
379                        OXYGEN_I2S_MASTER | OXYGEN_I2S_MUTE_MCLK);
380         oxygen_clear_bits32(chip, OXYGEN_SPDIF_CONTROL,
381                             OXYGEN_SPDIF_OUT_ENABLE |
382                             OXYGEN_SPDIF_LOOPBACK);
383         if (chip->model.device_config & CAPTURE_1_FROM_SPDIF)
384                 oxygen_write32_masked(chip, OXYGEN_SPDIF_CONTROL,
385                                       OXYGEN_SPDIF_SENSE_MASK |
386                                       OXYGEN_SPDIF_LOCK_MASK |
387                                       OXYGEN_SPDIF_RATE_MASK |
388                                       OXYGEN_SPDIF_LOCK_PAR |
389                                       OXYGEN_SPDIF_IN_CLOCK_96,
390                                       OXYGEN_SPDIF_SENSE_MASK |
391                                       OXYGEN_SPDIF_LOCK_MASK |
392                                       OXYGEN_SPDIF_RATE_MASK |
393                                       OXYGEN_SPDIF_SENSE_PAR |
394                                       OXYGEN_SPDIF_LOCK_PAR |
395                                       OXYGEN_SPDIF_IN_CLOCK_MASK);
396         else
397                 oxygen_clear_bits32(chip, OXYGEN_SPDIF_CONTROL,
398                                     OXYGEN_SPDIF_SENSE_MASK |
399                                     OXYGEN_SPDIF_LOCK_MASK |
400                                     OXYGEN_SPDIF_RATE_MASK);
401         oxygen_write32(chip, OXYGEN_SPDIF_OUTPUT_BITS, chip->spdif_bits);
402         oxygen_write16(chip, OXYGEN_2WIRE_BUS_STATUS,
403                        OXYGEN_2WIRE_LENGTH_8 |
404                        OXYGEN_2WIRE_INTERRUPT_MASK |
405                        OXYGEN_2WIRE_SPEED_STANDARD);
406         oxygen_clear_bits8(chip, OXYGEN_MPU401_CONTROL, OXYGEN_MPU401_LOOPBACK);
407         oxygen_write8(chip, OXYGEN_GPI_INTERRUPT_MASK, 0);
408         oxygen_write16(chip, OXYGEN_GPIO_INTERRUPT_MASK, 0);
409         oxygen_write16(chip, OXYGEN_PLAY_ROUTING,
410                        OXYGEN_PLAY_MULTICH_I2S_DAC |
411                        OXYGEN_PLAY_SPDIF_SPDIF |
412                        (0 << OXYGEN_PLAY_DAC0_SOURCE_SHIFT) |
413                        (1 << OXYGEN_PLAY_DAC1_SOURCE_SHIFT) |
414                        (2 << OXYGEN_PLAY_DAC2_SOURCE_SHIFT) |
415                        (3 << OXYGEN_PLAY_DAC3_SOURCE_SHIFT));
416         oxygen_write8(chip, OXYGEN_REC_ROUTING,
417                       OXYGEN_REC_A_ROUTE_I2S_ADC_1 |
418                       OXYGEN_REC_B_ROUTE_I2S_ADC_2 |
419                       OXYGEN_REC_C_ROUTE_SPDIF);
420         oxygen_write8(chip, OXYGEN_ADC_MONITOR, 0);
421         oxygen_write8(chip, OXYGEN_A_MONITOR_ROUTING,
422                       (0 << OXYGEN_A_MONITOR_ROUTE_0_SHIFT) |
423                       (1 << OXYGEN_A_MONITOR_ROUTE_1_SHIFT) |
424                       (2 << OXYGEN_A_MONITOR_ROUTE_2_SHIFT) |
425                       (3 << OXYGEN_A_MONITOR_ROUTE_3_SHIFT));
426
427         if (chip->has_ac97_0 | chip->has_ac97_1)
428                 oxygen_write8(chip, OXYGEN_AC97_INTERRUPT_MASK,
429                               OXYGEN_AC97_INT_READ_DONE |
430                               OXYGEN_AC97_INT_WRITE_DONE);
431         else
432                 oxygen_write8(chip, OXYGEN_AC97_INTERRUPT_MASK, 0);
433         oxygen_write32(chip, OXYGEN_AC97_OUT_CONFIG, 0);
434         oxygen_write32(chip, OXYGEN_AC97_IN_CONFIG, 0);
435         if (!(chip->has_ac97_0 | chip->has_ac97_1))
436                 oxygen_set_bits16(chip, OXYGEN_AC97_CONTROL,
437                                   OXYGEN_AC97_CLOCK_DISABLE);
438         if (!chip->has_ac97_0) {
439                 oxygen_set_bits16(chip, OXYGEN_AC97_CONTROL,
440                                   OXYGEN_AC97_NO_CODEC_0);
441         } else {
442                 oxygen_write_ac97(chip, 0, AC97_RESET, 0);
443                 msleep(1);
444                 oxygen_ac97_set_bits(chip, 0, CM9780_GPIO_SETUP,
445                                      CM9780_GPIO0IO | CM9780_GPIO1IO);
446                 oxygen_ac97_set_bits(chip, 0, CM9780_MIXER,
447                                      CM9780_BSTSEL | CM9780_STRO_MIC |
448                                      CM9780_MIX2FR | CM9780_PCBSW);
449                 oxygen_ac97_set_bits(chip, 0, CM9780_JACK,
450                                      CM9780_RSOE | CM9780_CBOE |
451                                      CM9780_SSOE | CM9780_FROE |
452                                      CM9780_MIC2MIC | CM9780_LI2LI);
453                 oxygen_write_ac97(chip, 0, AC97_MASTER, 0x0000);
454                 oxygen_write_ac97(chip, 0, AC97_PC_BEEP, 0x8000);
455                 oxygen_write_ac97(chip, 0, AC97_MIC, 0x8808);
456                 oxygen_write_ac97(chip, 0, AC97_LINE, 0x0808);
457                 oxygen_write_ac97(chip, 0, AC97_CD, 0x8808);
458                 oxygen_write_ac97(chip, 0, AC97_VIDEO, 0x8808);
459                 oxygen_write_ac97(chip, 0, AC97_AUX, 0x8808);
460                 oxygen_write_ac97(chip, 0, AC97_REC_GAIN, 0x8000);
461                 oxygen_write_ac97(chip, 0, AC97_CENTER_LFE_MASTER, 0x8080);
462                 oxygen_write_ac97(chip, 0, AC97_SURROUND_MASTER, 0x8080);
463                 oxygen_ac97_clear_bits(chip, 0, CM9780_GPIO_STATUS,
464                                        CM9780_GPO0);
465                 /* power down unused ADCs and DACs */
466                 oxygen_ac97_set_bits(chip, 0, AC97_POWERDOWN,
467                                      AC97_PD_PR0 | AC97_PD_PR1);
468                 oxygen_ac97_set_bits(chip, 0, AC97_EXTENDED_STATUS,
469                                      AC97_EA_PRI | AC97_EA_PRJ | AC97_EA_PRK);
470         }
471         if (chip->has_ac97_1) {
472                 oxygen_set_bits32(chip, OXYGEN_AC97_OUT_CONFIG,
473                                   OXYGEN_AC97_CODEC1_SLOT3 |
474                                   OXYGEN_AC97_CODEC1_SLOT4);
475                 oxygen_write_ac97(chip, 1, AC97_RESET, 0);
476                 msleep(1);
477                 oxygen_write_ac97(chip, 1, AC97_MASTER, 0x0000);
478                 oxygen_write_ac97(chip, 1, AC97_HEADPHONE, 0x8000);
479                 oxygen_write_ac97(chip, 1, AC97_PC_BEEP, 0x8000);
480                 oxygen_write_ac97(chip, 1, AC97_MIC, 0x8808);
481                 oxygen_write_ac97(chip, 1, AC97_LINE, 0x8808);
482                 oxygen_write_ac97(chip, 1, AC97_CD, 0x8808);
483                 oxygen_write_ac97(chip, 1, AC97_VIDEO, 0x8808);
484                 oxygen_write_ac97(chip, 1, AC97_AUX, 0x8808);
485                 oxygen_write_ac97(chip, 1, AC97_PCM, 0x0808);
486                 oxygen_write_ac97(chip, 1, AC97_REC_SEL, 0x0000);
487                 oxygen_write_ac97(chip, 1, AC97_REC_GAIN, 0x0000);
488                 oxygen_ac97_set_bits(chip, 1, 0x6a, 0x0040);
489         }
490 }
491
492 static void oxygen_card_free(struct snd_card *card)
493 {
494         struct oxygen *chip = card->private_data;
495
496         spin_lock_irq(&chip->reg_lock);
497         chip->interrupt_mask = 0;
498         chip->pcm_running = 0;
499         oxygen_write16(chip, OXYGEN_DMA_STATUS, 0);
500         oxygen_write16(chip, OXYGEN_INTERRUPT_MASK, 0);
501         spin_unlock_irq(&chip->reg_lock);
502         if (chip->irq >= 0)
503                 free_irq(chip->irq, chip);
504         flush_scheduled_work();
505         chip->model.cleanup(chip);
506         kfree(chip->model_data);
507         mutex_destroy(&chip->mutex);
508         pci_release_regions(chip->pci);
509         pci_disable_device(chip->pci);
510 }
511
512 int oxygen_pci_probe(struct pci_dev *pci, int index, char *id,
513                      struct module *owner,
514                      const struct pci_device_id *ids,
515                      int (*get_model)(struct oxygen *chip,
516                                       const struct pci_device_id *id
517                                      )
518                     )
519 {
520         struct snd_card *card;
521         struct oxygen *chip;
522         const struct pci_device_id *pci_id;
523         int err;
524
525         err = snd_card_create(index, id, owner, sizeof(*chip), &card);
526         if (err < 0)
527                 return err;
528
529         chip = card->private_data;
530         chip->card = card;
531         chip->pci = pci;
532         chip->irq = -1;
533         spin_lock_init(&chip->reg_lock);
534         mutex_init(&chip->mutex);
535         INIT_WORK(&chip->spdif_input_bits_work,
536                   oxygen_spdif_input_bits_changed);
537         INIT_WORK(&chip->gpio_work, oxygen_gpio_changed);
538         init_waitqueue_head(&chip->ac97_waitqueue);
539
540         err = pci_enable_device(pci);
541         if (err < 0)
542                 goto err_card;
543
544         err = pci_request_regions(pci, DRIVER);
545         if (err < 0) {
546                 snd_printk(KERN_ERR "cannot reserve PCI resources\n");
547                 goto err_pci_enable;
548         }
549
550         if (!(pci_resource_flags(pci, 0) & IORESOURCE_IO) ||
551             pci_resource_len(pci, 0) < OXYGEN_IO_SIZE) {
552                 snd_printk(KERN_ERR "invalid PCI I/O range\n");
553                 err = -ENXIO;
554                 goto err_pci_regions;
555         }
556         chip->addr = pci_resource_start(pci, 0);
557
558         pci_id = oxygen_search_pci_id(chip, ids);
559         if (!pci_id) {
560                 err = -ENODEV;
561                 goto err_pci_regions;
562         }
563         oxygen_restore_eeprom(chip, pci_id);
564         err = get_model(chip, pci_id);
565         if (err < 0)
566                 goto err_pci_regions;
567
568         if (chip->model.model_data_size) {
569                 chip->model_data = kzalloc(chip->model.model_data_size,
570                                            GFP_KERNEL);
571                 if (!chip->model_data) {
572                         err = -ENOMEM;
573                         goto err_pci_regions;
574                 }
575         }
576
577         pci_set_master(pci);
578         snd_card_set_dev(card, &pci->dev);
579         card->private_free = oxygen_card_free;
580
581         oxygen_init(chip);
582         chip->model.init(chip);
583
584         err = request_irq(pci->irq, oxygen_interrupt, IRQF_SHARED,
585                           DRIVER, chip);
586         if (err < 0) {
587                 snd_printk(KERN_ERR "cannot grab interrupt %d\n", pci->irq);
588                 goto err_card;
589         }
590         chip->irq = pci->irq;
591
592         strcpy(card->driver, chip->model.chip);
593         strcpy(card->shortname, chip->model.shortname);
594         sprintf(card->longname, "%s (rev %u) at %#lx, irq %i",
595                 chip->model.longname, chip->revision, chip->addr, chip->irq);
596         strcpy(card->mixername, chip->model.chip);
597         snd_component_add(card, chip->model.chip);
598
599         err = oxygen_pcm_init(chip);
600         if (err < 0)
601                 goto err_card;
602
603         err = oxygen_mixer_init(chip);
604         if (err < 0)
605                 goto err_card;
606
607         if (chip->model.device_config & (MIDI_OUTPUT | MIDI_INPUT)) {
608                 unsigned int info_flags = MPU401_INFO_INTEGRATED;
609                 if (chip->model.device_config & MIDI_OUTPUT)
610                         info_flags |= MPU401_INFO_OUTPUT;
611                 if (chip->model.device_config & MIDI_INPUT)
612                         info_flags |= MPU401_INFO_INPUT;
613                 err = snd_mpu401_uart_new(card, 0, MPU401_HW_CMIPCI,
614                                           chip->addr + OXYGEN_MPU401,
615                                           info_flags, 0, 0,
616                                           &chip->midi);
617                 if (err < 0)
618                         goto err_card;
619         }
620
621         oxygen_proc_init(chip);
622
623         spin_lock_irq(&chip->reg_lock);
624         if (chip->model.device_config & CAPTURE_1_FROM_SPDIF)
625                 chip->interrupt_mask |= OXYGEN_INT_SPDIF_IN_DETECT;
626         if (chip->has_ac97_0 | chip->has_ac97_1)
627                 chip->interrupt_mask |= OXYGEN_INT_AC97;
628         oxygen_write16(chip, OXYGEN_INTERRUPT_MASK, chip->interrupt_mask);
629         spin_unlock_irq(&chip->reg_lock);
630
631         err = snd_card_register(card);
632         if (err < 0)
633                 goto err_card;
634
635         pci_set_drvdata(pci, card);
636         return 0;
637
638 err_pci_regions:
639         pci_release_regions(pci);
640 err_pci_enable:
641         pci_disable_device(pci);
642 err_card:
643         snd_card_free(card);
644         return err;
645 }
646 EXPORT_SYMBOL(oxygen_pci_probe);
647
648 void oxygen_pci_remove(struct pci_dev *pci)
649 {
650         snd_card_free(pci_get_drvdata(pci));
651         pci_set_drvdata(pci, NULL);
652 }
653 EXPORT_SYMBOL(oxygen_pci_remove);
654
655 #ifdef CONFIG_PM
656 int oxygen_pci_suspend(struct pci_dev *pci, pm_message_t state)
657 {
658         struct snd_card *card = pci_get_drvdata(pci);
659         struct oxygen *chip = card->private_data;
660         unsigned int i, saved_interrupt_mask;
661
662         snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
663
664         for (i = 0; i < PCM_COUNT; ++i)
665                 if (chip->streams[i])
666                         snd_pcm_suspend(chip->streams[i]);
667
668         if (chip->model.suspend)
669                 chip->model.suspend(chip);
670
671         spin_lock_irq(&chip->reg_lock);
672         saved_interrupt_mask = chip->interrupt_mask;
673         chip->interrupt_mask = 0;
674         oxygen_write16(chip, OXYGEN_DMA_STATUS, 0);
675         oxygen_write16(chip, OXYGEN_INTERRUPT_MASK, 0);
676         spin_unlock_irq(&chip->reg_lock);
677
678         synchronize_irq(chip->irq);
679         flush_scheduled_work();
680         chip->interrupt_mask = saved_interrupt_mask;
681
682         pci_disable_device(pci);
683         pci_save_state(pci);
684         pci_set_power_state(pci, pci_choose_state(pci, state));
685         return 0;
686 }
687 EXPORT_SYMBOL(oxygen_pci_suspend);
688
689 static const u32 registers_to_restore[OXYGEN_IO_SIZE / 32] = {
690         0xffffffff, 0x00ff077f, 0x00011d08, 0x007f00ff,
691         0x00300000, 0x00000fe4, 0x0ff7001f, 0x00000000
692 };
693 static const u32 ac97_registers_to_restore[2][0x40 / 32] = {
694         { 0x18284fa2, 0x03060000 },
695         { 0x00007fa6, 0x00200000 }
696 };
697
698 static inline int is_bit_set(const u32 *bitmap, unsigned int bit)
699 {
700         return bitmap[bit / 32] & (1 << (bit & 31));
701 }
702
703 static void oxygen_restore_ac97(struct oxygen *chip, unsigned int codec)
704 {
705         unsigned int i;
706
707         oxygen_write_ac97(chip, codec, AC97_RESET, 0);
708         msleep(1);
709         for (i = 1; i < 0x40; ++i)
710                 if (is_bit_set(ac97_registers_to_restore[codec], i))
711                         oxygen_write_ac97(chip, codec, i * 2,
712                                           chip->saved_ac97_registers[codec][i]);
713 }
714
715 int oxygen_pci_resume(struct pci_dev *pci)
716 {
717         struct snd_card *card = pci_get_drvdata(pci);
718         struct oxygen *chip = card->private_data;
719         unsigned int i;
720
721         pci_set_power_state(pci, PCI_D0);
722         pci_restore_state(pci);
723         if (pci_enable_device(pci) < 0) {
724                 snd_printk(KERN_ERR "cannot reenable device");
725                 snd_card_disconnect(card);
726                 return -EIO;
727         }
728         pci_set_master(pci);
729
730         oxygen_write16(chip, OXYGEN_DMA_STATUS, 0);
731         oxygen_write16(chip, OXYGEN_INTERRUPT_MASK, 0);
732         for (i = 0; i < OXYGEN_IO_SIZE; ++i)
733                 if (is_bit_set(registers_to_restore, i))
734                         oxygen_write8(chip, i, chip->saved_registers._8[i]);
735         if (chip->has_ac97_0)
736                 oxygen_restore_ac97(chip, 0);
737         if (chip->has_ac97_1)
738                 oxygen_restore_ac97(chip, 1);
739
740         if (chip->model.resume)
741                 chip->model.resume(chip);
742
743         oxygen_write16(chip, OXYGEN_INTERRUPT_MASK, chip->interrupt_mask);
744
745         snd_power_change_state(card, SNDRV_CTL_POWER_D0);
746         return 0;
747 }
748 EXPORT_SYMBOL(oxygen_pci_resume);
749 #endif /* CONFIG_PM */