2 * linux/arch/arm/kernel/entry-armv.S
4 * Copyright (C) 1996,1997,1998 Russell King.
5 * ARM700 fix by Matthew Godbolt (linux-user@willothewisp.demon.co.uk)
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
11 * Low-level vector interface routines
13 * Note: there is a StrongARM bug in the STMIA rn, {regs}^ instruction that causes
14 * it to save wrong values... Be aware!
16 #include <linux/config.h>
18 #include <asm/memory.h>
20 #include <asm/vfpmacros.h>
21 #include <asm/arch/entry-macro.S>
23 #include "entry-header.S"
26 * Interrupt handling. Preserves r7, r8, r9
29 1: get_irqnr_and_base r0, r6, r5, lr
32 @ routine called with r0 = irq number, r1 = struct pt_regs *
41 * this macro assumes that irqstat (r6) and base (r5) are
42 * preserved from get_irqnr_and_base above
44 test_for_ipi r0, r6, r5, lr
49 #ifdef CONFIG_LOCAL_TIMERS
50 test_for_ltirq r0, r6, r5, lr
60 * Invalid mode handlers
62 .macro inv_entry, reason
63 sub sp, sp, #S_FRAME_SIZE
69 inv_entry BAD_PREFETCH
81 inv_entry BAD_UNDEFINSTR
84 @ XXX fall through to common_invalid
88 @ common_invalid - generic code for failed exception (re-entrant version of handlers)
94 add r0, sp, #S_PC @ here for interlock avoidance
95 mov r7, #-1 @ "" "" "" ""
96 str r4, [sp] @ save preserved r0
97 stmia r0, {r5 - r7} @ lr_<exception>,
98 @ cpsr_<exception>, "old_r0"
108 sub sp, sp, #S_FRAME_SIZE
112 add r5, sp, #S_SP @ here for interlock avoidance
113 mov r4, #-1 @ "" "" "" ""
114 add r0, sp, #S_FRAME_SIZE @ "" "" "" ""
115 str r1, [sp] @ save the "real" r0 copied
116 @ from the exception stack
121 @ We are now ready to fill in the remaining blanks on the stack:
125 @ r2 - lr_<exception>, already fixed up for correct return/restart
126 @ r3 - spsr_<exception>
127 @ r4 - orig_r0 (see pt_regs definition in ptrace.h)
137 @ get ready to re-enable interrupts if appropriate
141 biceq r9, r9, #PSR_I_BIT
144 @ Call the processor-specific abort handler:
146 @ r2 - aborted context pc
147 @ r3 - aborted context cpsr
149 @ The abort handler must return the aborted address in r0, and
150 @ the fault status register in r1. r9 must be preserved.
161 @ set desired IRQ state, then call main handler
168 @ IRQs off again before pulling preserved data off the stack
173 @ restore SPSR and restart the instruction
177 ldmia sp, {r0 - pc}^ @ load r0 - pc, cpsr
183 #ifdef CONFIG_PREEMPT
185 ldr r8, [tsk, #TI_PREEMPT] @ get preempt count
186 add r7, r8, #1 @ increment it
187 str r7, [tsk, #TI_PREEMPT]
191 #ifdef CONFIG_PREEMPT
192 ldr r0, [tsk, #TI_FLAGS] @ get flags
193 tst r0, #_TIF_NEED_RESCHED
196 ldr r0, [tsk, #TI_PREEMPT] @ read preempt value
197 str r8, [tsk, #TI_PREEMPT] @ restore preempt count
199 strne r0, [r0, -r0] @ bug()
201 ldr r0, [sp, #S_PSR] @ irqs are already disabled
203 ldmia sp, {r0 - pc}^ @ load r0 - pc, cpsr
207 #ifdef CONFIG_PREEMPT
209 teq r8, #0 @ was preempt count = 0
210 ldreq r6, .LCirq_stat
212 ldr r0, [r6, #4] @ local_irq_count
213 ldr r1, [r6, #8] @ local_bh_count
216 mov r7, #0 @ preempt_schedule_irq
217 str r7, [tsk, #TI_PREEMPT] @ expects preempt_count == 0
218 1: bl preempt_schedule_irq @ irq en/disable is done inside
219 ldr r0, [tsk, #TI_FLAGS] @ get new tasks TI_FLAGS
220 tst r0, #_TIF_NEED_RESCHED
221 beq preempt_return @ go again
230 @ call emulation code, which returns using r9 if it has emulated
231 @ the instruction, or the more conventional lr if we are to treat
232 @ this as a real undefined instruction
240 mov r0, sp @ struct pt_regs *regs
244 @ IRQs off again before pulling preserved data off the stack
249 @ restore SPSR and restart the instruction
251 ldr lr, [sp, #S_PSR] @ Get SVC cpsr
253 ldmia sp, {r0 - pc}^ @ Restore SVC registers
260 @ re-enable interrupts if appropriate
264 biceq r9, r9, #PSR_I_BIT
268 @ set args, then call main handler
270 @ r0 - address of faulting instruction
271 @ r1 - pointer to registers on stack
273 mov r0, r2 @ address (pc)
275 bl do_PrefetchAbort @ call abort handler
278 @ IRQs off again before pulling preserved data off the stack
283 @ restore SPSR and restart the instruction
287 ldmia sp, {r0 - pc}^ @ load r0 - pc, cpsr
298 #ifdef CONFIG_PREEMPT
307 sub sp, sp, #S_FRAME_SIZE
311 add r0, sp, #S_PC @ here for interlock avoidance
312 mov r4, #-1 @ "" "" "" ""
314 str r1, [sp] @ save the "real" r0 copied
315 @ from the exception stack
317 #if __LINUX_ARM_ARCH__ < 6 && !defined(CONFIG_NEEDS_SYSCALL_FOR_CMPXCHG)
318 @ make sure our user space atomic helper is aborted
320 bichs r3, r3, #PSR_Z_BIT
324 @ We are now ready to fill in the remaining blanks on the stack:
326 @ r2 - lr_<exception>, already fixed up for correct return/restart
327 @ r3 - spsr_<exception>
328 @ r4 - orig_r0 (see pt_regs definition in ptrace.h)
330 @ Also, separately save sp_usr and lr_usr
336 @ Enable the alignment trap while in kernel mode
341 @ Clear FP to mark the first stack frame
351 @ Call the processor-specific abort handler:
353 @ r2 - aborted context pc
354 @ r3 - aborted context cpsr
356 @ The abort handler must return the aborted address in r0, and
357 @ the fault status register in r1.
368 @ IRQs on, then call the main handler
372 adr lr, ret_from_exception
380 #ifdef CONFIG_PREEMPT
381 ldr r8, [tsk, #TI_PREEMPT] @ get preempt count
382 add r7, r8, #1 @ increment it
383 str r7, [tsk, #TI_PREEMPT]
387 #ifdef CONFIG_PREEMPT
388 ldr r0, [tsk, #TI_PREEMPT]
389 str r8, [tsk, #TI_PREEMPT]
403 tst r3, #PSR_T_BIT @ Thumb mode?
404 bne fpundefinstr @ ignore FP
408 @ fall through to the emulation code, which returns using r9 if
409 @ it has emulated the instruction, or the more conventional lr
410 @ if we are to treat this as a real undefined instruction
415 adr r9, ret_from_exception
418 @ fallthrough to call_fpe
422 * The out of line fixup for the ldrt above.
424 .section .fixup, "ax"
427 .section __ex_table,"a"
432 * Check whether the instruction is a co-processor instruction.
433 * If yes, we need to call the relevant co-processor handler.
435 * Note that we don't do a full check here for the co-processor
436 * instructions; all instructions with bit 27 set are well
437 * defined. The only instructions that should fault are the
438 * co-processor instructions. However, we have to watch out
439 * for the ARM6/ARM7 SWI bug.
441 * Emulators may wish to make use of the following registers:
442 * r0 = instruction opcode.
444 * r10 = this threads thread_info structure.
447 tst r0, #0x08000000 @ only CDP/CPRT/LDC/STC have bit 27
448 #if defined(CONFIG_CPU_ARM610) || defined(CONFIG_CPU_ARM710)
449 and r8, r0, #0x0f000000 @ mask out op-code bits
450 teqne r8, #0x0f000000 @ SWI (ARM6/7 bug)?
453 get_thread_info r10 @ get current thread
454 and r8, r0, #0x00000f00 @ mask out CP number
456 add r6, r10, #TI_USED_CP
457 strb r7, [r6, r8, lsr #8] @ set appropriate used_cp[]
459 @ Test if we need to give access to iWMMXt coprocessors
460 ldr r5, [r10, #TI_FLAGS]
461 rsbs r7, r8, #(1 << 8) @ CP 0 or 1 only
462 movcss r7, r5, lsr #(TIF_USING_IWMMXT + 1)
463 bcs iwmmxt_task_enable
466 add pc, pc, r8, lsr #6
470 b do_fpe @ CP#1 (FPE)
471 b do_fpe @ CP#2 (FPE)
480 b do_vfp @ CP#10 (VFP)
481 b do_vfp @ CP#11 (VFP)
483 mov pc, lr @ CP#10 (VFP)
484 mov pc, lr @ CP#11 (VFP)
488 mov pc, lr @ CP#14 (Debug)
489 mov pc, lr @ CP#15 (Control)
493 add r10, r10, #TI_FPSTATE @ r10 = workspace
494 ldr pc, [r4] @ Call FP module USR entry point
497 * The FP module is called with these registers set:
500 * r9 = normal "successful" return address
502 * lr = unrecognised FP instruction return address
512 adr lr, ret_from_exception
519 enable_irq @ Enable interrupts
520 mov r0, r2 @ address (pc)
522 bl do_PrefetchAbort @ call abort handler
525 * This is the return code to user mode for abort handlers
527 ENTRY(ret_from_exception)
533 * Register switch for ARMv3 and ARMv4 processors
534 * r0 = previous task_struct, r1 = previous thread_info, r2 = next thread_info
535 * previous and next are guaranteed not to be the same.
538 add ip, r1, #TI_CPU_SAVE
539 ldr r3, [r2, #TI_TP_VALUE]
540 stmia ip!, {r4 - sl, fp, sp, lr} @ Store most regs on stack
541 ldr r6, [r2, #TI_CPU_DOMAIN]!
542 #if __LINUX_ARM_ARCH__ >= 6
543 #ifdef CONFIG_CPU_MPCORE
546 strex r5, r4, [ip] @ Clear exclusive monitor
549 #if defined(CONFIG_CPU_XSCALE) && !defined(CONFIG_IWMMXT)
553 #if defined(CONFIG_HAS_TLS_REG)
554 mcr p15, 0, r3, c13, c0, 3 @ set TLS register
555 #elif !defined(CONFIG_TLS_REG_EMUL)
557 str r3, [r4, #-15] @ TLS val at 0xffff0ff0
559 mcr p15, 0, r6, c3, c0, 0 @ Set domain register
561 @ Always disable VFP so we can lazily save/restore the old
562 @ state. This occurs in the context of the previous thread.
564 bic r4, r4, #FPEXC_ENABLE
567 #if defined(CONFIG_IWMMXT)
568 bl iwmmxt_task_switch
569 #elif defined(CONFIG_CPU_XSCALE)
570 add r4, r2, #40 @ cpu_context_save->extra
574 ldmib r2, {r4 - sl, fp, sp, pc} @ Load all regs saved previously
581 * These are segment of kernel provided user code reachable from user space
582 * at a fixed address in kernel memory. This is used to provide user space
583 * with some operations which require kernel help because of unimplemented
584 * native feature and/or instructions in many ARM CPUs. The idea is for
585 * this code to be executed directly in user mode for best efficiency but
586 * which is too intimate with the kernel counter part to be left to user
587 * libraries. In fact this code might even differ from one CPU to another
588 * depending on the available instruction set and restrictions like on
589 * SMP systems. In other words, the kernel reserves the right to change
590 * this code as needed without warning. Only the entry points and their
591 * results are guaranteed to be stable.
593 * Each segment is 32-byte aligned and will be moved to the top of the high
594 * vector page. New segments (if ever needed) must be added in front of
595 * existing ones. This mechanism should be used only for things that are
596 * really small and justified, and not be abused freely.
598 * User space is expected to implement those things inline when optimizing
599 * for a processor that has the necessary native support, but only if such
600 * resulting binaries are already to be incompatible with earlier ARM
601 * processors due to the use of unsupported instructions other than what
602 * is provided here. In other words don't make binaries unable to run on
603 * earlier processors just for the sake of not using these kernel helpers
604 * if your compiled code is not going to use the new instructions for other
609 .globl __kuser_helper_start
610 __kuser_helper_start:
613 * Reference prototype:
615 * void __kernel_memory_barrier(void)
619 * lr = return address
627 * the Z flag might be lost
629 * Definition and user space usage example:
631 * typedef void (__kernel_dmb_t)(void);
632 * #define __kernel_dmb (*(__kernel_dmb_t *)0xffff0fa0)
634 * Apply any needed memory barrier to preserve consistency with data modified
635 * manually and __kuser_cmpxchg usage.
637 * This could be used as follows:
639 * #define __kernel_dmb() \
640 * asm volatile ( "mov r0, #0xffff0fff; mov lr, pc; sub pc, r0, #95" \
644 __kuser_memory_barrier: @ 0xffff0fa0
646 #if __LINUX_ARM_ARCH__ >= 6 && defined(CONFIG_SMP)
647 mcr p15, 0, r0, c7, c10, 5 @ dmb
654 * Reference prototype:
656 * int __kernel_cmpxchg(int oldval, int newval, int *ptr)
663 * lr = return address
667 * r0 = returned value (zero or non-zero)
668 * C flag = set if r0 == 0, clear if r0 != 0
674 * Definition and user space usage example:
676 * typedef int (__kernel_cmpxchg_t)(int oldval, int newval, int *ptr);
677 * #define __kernel_cmpxchg (*(__kernel_cmpxchg_t *)0xffff0fc0)
679 * Atomically store newval in *ptr if *ptr is equal to oldval for user space.
680 * Return zero if *ptr was changed or non-zero if no exchange happened.
681 * The C flag is also set if *ptr was changed to allow for assembly
682 * optimization in the calling code.
684 * Note: this routine already includes memory barriers as needed.
686 * For example, a user space atomic_add implementation could look like this:
688 * #define atomic_add(ptr, val) \
689 * ({ register unsigned int *__ptr asm("r2") = (ptr); \
690 * register unsigned int __result asm("r1"); \
692 * "1: @ atomic_add\n\t" \
693 * "ldr r0, [r2]\n\t" \
694 * "mov r3, #0xffff0fff\n\t" \
695 * "add lr, pc, #4\n\t" \
696 * "add r1, r0, %2\n\t" \
697 * "add pc, r3, #(0xffff0fc0 - 0xffff0fff)\n\t" \
699 * : "=&r" (__result) \
700 * : "r" (__ptr), "rIL" (val) \
701 * : "r0","r3","ip","lr","cc","memory" ); \
705 __kuser_cmpxchg: @ 0xffff0fc0
707 #if defined(CONFIG_NEEDS_SYSCALL_FOR_CMPXCHG)
710 * Poor you. No fast solution possible...
711 * The kernel itself must perform the operation.
712 * A special ghost syscall is used for that (see traps.c).
717 #elif __LINUX_ARM_ARCH__ < 6
720 * Theory of operation:
722 * We set the Z flag before loading oldval. If ever an exception
723 * occurs we can not be sure the loaded value will still be the same
724 * when the exception returns, therefore the user exception handler
725 * will clear the Z flag whenever the interrupted user code was
726 * actually from the kernel address space (see the usr_entry macro).
728 * The post-increment on the str is used to prevent a race with an
729 * exception happening just after the str instruction which would
730 * clear the Z flag although the exchange was done.
732 teq ip, ip @ set Z flag
733 ldr ip, [r2] @ load current val
734 add r3, r2, #1 @ prepare store ptr
735 teqeq ip, r0 @ compare with oldval if still allowed
736 streq r1, [r3, #-1]! @ store newval if still allowed
737 subs r0, r2, r3 @ if r2 == r3 the str occured
743 mcr p15, 0, r0, c7, c10, 5 @ dmb
750 mcr p15, 0, r0, c7, c10, 5 @ dmb
759 * Reference prototype:
761 * int __kernel_get_tls(void)
765 * lr = return address
773 * the Z flag might be lost
775 * Definition and user space usage example:
777 * typedef int (__kernel_get_tls_t)(void);
778 * #define __kernel_get_tls (*(__kernel_get_tls_t *)0xffff0fe0)
780 * Get the TLS value as previously set via the __ARM_NR_set_tls syscall.
782 * This could be used as follows:
784 * #define __kernel_get_tls() \
785 * ({ register unsigned int __val asm("r0"); \
786 * asm( "mov r0, #0xffff0fff; mov lr, pc; sub pc, r0, #31" \
787 * : "=r" (__val) : : "lr","cc" ); \
791 __kuser_get_tls: @ 0xffff0fe0
793 #if !defined(CONFIG_HAS_TLS_REG) && !defined(CONFIG_TLS_REG_EMUL)
795 ldr r0, [pc, #(16 - 8)] @ TLS stored at 0xffff0ff0
800 mrc p15, 0, r0, c13, c0, 3 @ read TLS register
806 .word 0 @ pad up to __kuser_helper_version
810 * Reference declaration:
812 * extern unsigned int __kernel_helper_version;
814 * Definition and user space usage example:
816 * #define __kernel_helper_version (*(unsigned int *)0xffff0ffc)
818 * User space may read this to determine the curent number of helpers
822 __kuser_helper_version: @ 0xffff0ffc
823 .word ((__kuser_helper_end - __kuser_helper_start) >> 5)
825 .globl __kuser_helper_end
832 * This code is copied to 0xffff0200 so we can use branches in the
833 * vectors, rather than ldr's. Note that this code must not
834 * exceed 0x300 bytes.
836 * Common stub entry macro:
837 * Enter in IRQ mode, spsr = SVC/USR CPSR, lr = SVC/USR PC
839 * SP points to a minimal amount of processor-private memory, the address
840 * of which is copied into r0 for the mode specific abort handler.
842 .macro vector_stub, name, mode, correction=0
847 sub lr, lr, #\correction
851 @ Save r0, lr_<exception> (parent PC) and spsr_<exception>
854 stmia sp, {r0, lr} @ save r0, lr
856 str lr, [sp, #8] @ save spsr
859 @ Prepare for SVC32 mode. IRQs remain disabled.
862 eor r0, r0, #(\mode ^ SVC_MODE)
866 @ the branch table must immediately follow this code
870 ldr lr, [pc, lr, lsl #2]
871 movs pc, lr @ branch to handler in SVC mode
877 * Interrupt dispatcher
879 vector_stub irq, IRQ_MODE, 4
881 .long __irq_usr @ 0 (USR_26 / USR_32)
882 .long __irq_invalid @ 1 (FIQ_26 / FIQ_32)
883 .long __irq_invalid @ 2 (IRQ_26 / IRQ_32)
884 .long __irq_svc @ 3 (SVC_26 / SVC_32)
885 .long __irq_invalid @ 4
886 .long __irq_invalid @ 5
887 .long __irq_invalid @ 6
888 .long __irq_invalid @ 7
889 .long __irq_invalid @ 8
890 .long __irq_invalid @ 9
891 .long __irq_invalid @ a
892 .long __irq_invalid @ b
893 .long __irq_invalid @ c
894 .long __irq_invalid @ d
895 .long __irq_invalid @ e
896 .long __irq_invalid @ f
899 * Data abort dispatcher
900 * Enter in ABT mode, spsr = USR CPSR, lr = USR PC
902 vector_stub dabt, ABT_MODE, 8
904 .long __dabt_usr @ 0 (USR_26 / USR_32)
905 .long __dabt_invalid @ 1 (FIQ_26 / FIQ_32)
906 .long __dabt_invalid @ 2 (IRQ_26 / IRQ_32)
907 .long __dabt_svc @ 3 (SVC_26 / SVC_32)
908 .long __dabt_invalid @ 4
909 .long __dabt_invalid @ 5
910 .long __dabt_invalid @ 6
911 .long __dabt_invalid @ 7
912 .long __dabt_invalid @ 8
913 .long __dabt_invalid @ 9
914 .long __dabt_invalid @ a
915 .long __dabt_invalid @ b
916 .long __dabt_invalid @ c
917 .long __dabt_invalid @ d
918 .long __dabt_invalid @ e
919 .long __dabt_invalid @ f
922 * Prefetch abort dispatcher
923 * Enter in ABT mode, spsr = USR CPSR, lr = USR PC
925 vector_stub pabt, ABT_MODE, 4
927 .long __pabt_usr @ 0 (USR_26 / USR_32)
928 .long __pabt_invalid @ 1 (FIQ_26 / FIQ_32)
929 .long __pabt_invalid @ 2 (IRQ_26 / IRQ_32)
930 .long __pabt_svc @ 3 (SVC_26 / SVC_32)
931 .long __pabt_invalid @ 4
932 .long __pabt_invalid @ 5
933 .long __pabt_invalid @ 6
934 .long __pabt_invalid @ 7
935 .long __pabt_invalid @ 8
936 .long __pabt_invalid @ 9
937 .long __pabt_invalid @ a
938 .long __pabt_invalid @ b
939 .long __pabt_invalid @ c
940 .long __pabt_invalid @ d
941 .long __pabt_invalid @ e
942 .long __pabt_invalid @ f
945 * Undef instr entry dispatcher
946 * Enter in UND mode, spsr = SVC/USR CPSR, lr = SVC/USR PC
948 vector_stub und, UND_MODE
950 .long __und_usr @ 0 (USR_26 / USR_32)
951 .long __und_invalid @ 1 (FIQ_26 / FIQ_32)
952 .long __und_invalid @ 2 (IRQ_26 / IRQ_32)
953 .long __und_svc @ 3 (SVC_26 / SVC_32)
954 .long __und_invalid @ 4
955 .long __und_invalid @ 5
956 .long __und_invalid @ 6
957 .long __und_invalid @ 7
958 .long __und_invalid @ 8
959 .long __und_invalid @ 9
960 .long __und_invalid @ a
961 .long __und_invalid @ b
962 .long __und_invalid @ c
963 .long __und_invalid @ d
964 .long __und_invalid @ e
965 .long __und_invalid @ f
969 /*=============================================================================
971 *-----------------------------------------------------------------------------
972 * Enter in FIQ mode, spsr = ANY CPSR, lr = ANY PC
973 * MUST PRESERVE SVC SPSR, but need to switch to SVC mode to show our msg.
974 * Basically to switch modes, we *HAVE* to clobber one register... brain
975 * damage alert! I don't think that we can execute any code in here in any
976 * other mode than FIQ... Ok you can switch to another mode, but you can't
977 * get out of that mode without clobbering one register.
983 /*=============================================================================
984 * Address exception handler
985 *-----------------------------------------------------------------------------
986 * These aren't too critical.
987 * (they're not supposed to happen, and won't happen in 32-bit data mode).
994 * We group all the following data together to optimise
995 * for CPUs with separate I & D caches.
1005 .equ stubs_offset, __vectors_start + 0x200 - __stubs_start
1007 .globl __vectors_start
1010 b vector_und + stubs_offset
1011 ldr pc, .LCvswi + stubs_offset
1012 b vector_pabt + stubs_offset
1013 b vector_dabt + stubs_offset
1014 b vector_addrexcptn + stubs_offset
1015 b vector_irq + stubs_offset
1016 b vector_fiq + stubs_offset
1018 .globl __vectors_end
1024 .globl cr_no_alignment
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