2 * sata_nv.c - NVIDIA nForce SATA
4 * Copyright 2004 NVIDIA Corp. All rights reserved.
5 * Copyright 2004 Andrew Chew
7 * The contents of this file are subject to the Open
8 * Software License version 1.1 that can be found at
9 * http://www.opensource.org/licenses/osl-1.1.txt and is included herein
12 * Alternatively, the contents of this file may be used under the terms
13 * of the GNU General Public License version 2 (the "GPL") as distributed
14 * in the kernel source COPYING file, in which case the provisions of
15 * the GPL are applicable instead of the above. If you wish to allow
16 * the use of your version of this file only under the terms of the
17 * GPL and not to allow others to use your version of this file under
18 * the OSL, indicate your decision by deleting the provisions above and
19 * replace them with the notice and other provisions required by the GPL.
20 * If you do not delete the provisions above, a recipient may use your
21 * version of this file under either the OSL or the GPL.
24 * - Added support for MCP51 and MCP55.
27 * - Added support for RAID class code.
30 * - Added generic SATA support by using a pci_device_id that filters on
31 * the IDE storage class code.
34 * - Fixed a bug where the hotplug handlers for non-CK804/MCP04 were using
35 * mmio_base, which is only set for the CK804/MCP04 case.
38 * - Added support for CK804 SATA controller.
44 #include <linux/config.h>
45 #include <linux/kernel.h>
46 #include <linux/module.h>
47 #include <linux/pci.h>
48 #include <linux/init.h>
49 #include <linux/blkdev.h>
50 #include <linux/delay.h>
51 #include <linux/interrupt.h>
53 #include <scsi/scsi_host.h>
54 #include <linux/libata.h>
56 #define DRV_NAME "sata_nv"
57 #define DRV_VERSION "0.8"
60 #define NV_PIO_MASK 0x1f
61 #define NV_MWDMA_MASK 0x07
62 #define NV_UDMA_MASK 0x7f
63 #define NV_PORT0_SCR_REG_OFFSET 0x00
64 #define NV_PORT1_SCR_REG_OFFSET 0x40
66 #define NV_INT_STATUS 0x10
67 #define NV_INT_STATUS_CK804 0x440
68 #define NV_INT_STATUS_PDEV_INT 0x01
69 #define NV_INT_STATUS_PDEV_PM 0x02
70 #define NV_INT_STATUS_PDEV_ADDED 0x04
71 #define NV_INT_STATUS_PDEV_REMOVED 0x08
72 #define NV_INT_STATUS_SDEV_INT 0x10
73 #define NV_INT_STATUS_SDEV_PM 0x20
74 #define NV_INT_STATUS_SDEV_ADDED 0x40
75 #define NV_INT_STATUS_SDEV_REMOVED 0x80
76 #define NV_INT_STATUS_PDEV_HOTPLUG (NV_INT_STATUS_PDEV_ADDED | \
77 NV_INT_STATUS_PDEV_REMOVED)
78 #define NV_INT_STATUS_SDEV_HOTPLUG (NV_INT_STATUS_SDEV_ADDED | \
79 NV_INT_STATUS_SDEV_REMOVED)
80 #define NV_INT_STATUS_HOTPLUG (NV_INT_STATUS_PDEV_HOTPLUG | \
81 NV_INT_STATUS_SDEV_HOTPLUG)
83 #define NV_INT_ENABLE 0x11
84 #define NV_INT_ENABLE_CK804 0x441
85 #define NV_INT_ENABLE_PDEV_MASK 0x01
86 #define NV_INT_ENABLE_PDEV_PM 0x02
87 #define NV_INT_ENABLE_PDEV_ADDED 0x04
88 #define NV_INT_ENABLE_PDEV_REMOVED 0x08
89 #define NV_INT_ENABLE_SDEV_MASK 0x10
90 #define NV_INT_ENABLE_SDEV_PM 0x20
91 #define NV_INT_ENABLE_SDEV_ADDED 0x40
92 #define NV_INT_ENABLE_SDEV_REMOVED 0x80
93 #define NV_INT_ENABLE_PDEV_HOTPLUG (NV_INT_ENABLE_PDEV_ADDED | \
94 NV_INT_ENABLE_PDEV_REMOVED)
95 #define NV_INT_ENABLE_SDEV_HOTPLUG (NV_INT_ENABLE_SDEV_ADDED | \
96 NV_INT_ENABLE_SDEV_REMOVED)
97 #define NV_INT_ENABLE_HOTPLUG (NV_INT_ENABLE_PDEV_HOTPLUG | \
98 NV_INT_ENABLE_SDEV_HOTPLUG)
100 #define NV_INT_CONFIG 0x12
101 #define NV_INT_CONFIG_METHD 0x01 // 0 = INT, 1 = SMI
103 // For PCI config register 20
104 #define NV_MCP_SATA_CFG_20 0x50
105 #define NV_MCP_SATA_CFG_20_SATA_SPACE_EN 0x04
107 static int nv_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
108 static irqreturn_t nv_interrupt (int irq, void *dev_instance,
109 struct pt_regs *regs);
110 static u32 nv_scr_read (struct ata_port *ap, unsigned int sc_reg);
111 static void nv_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val);
112 static void nv_host_stop (struct ata_host_set *host_set);
113 static void nv_enable_hotplug(struct ata_probe_ent *probe_ent);
114 static void nv_disable_hotplug(struct ata_host_set *host_set);
115 static void nv_check_hotplug(struct ata_host_set *host_set);
116 static void nv_enable_hotplug_ck804(struct ata_probe_ent *probe_ent);
117 static void nv_disable_hotplug_ck804(struct ata_host_set *host_set);
118 static void nv_check_hotplug_ck804(struct ata_host_set *host_set);
130 static struct pci_device_id nv_pci_tbl[] = {
131 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2S_SATA,
132 PCI_ANY_ID, PCI_ANY_ID, 0, 0, NFORCE2 },
133 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3S_SATA,
134 PCI_ANY_ID, PCI_ANY_ID, 0, 0, NFORCE3 },
135 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3S_SATA2,
136 PCI_ANY_ID, PCI_ANY_ID, 0, 0, NFORCE3 },
137 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_CK804_SATA,
138 PCI_ANY_ID, PCI_ANY_ID, 0, 0, CK804 },
139 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_CK804_SATA2,
140 PCI_ANY_ID, PCI_ANY_ID, 0, 0, CK804 },
141 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_SATA,
142 PCI_ANY_ID, PCI_ANY_ID, 0, 0, CK804 },
143 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_SATA2,
144 PCI_ANY_ID, PCI_ANY_ID, 0, 0, CK804 },
145 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_SATA,
146 PCI_ANY_ID, PCI_ANY_ID, 0, 0, MCP51 },
147 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_SATA2,
148 PCI_ANY_ID, PCI_ANY_ID, 0, 0, MCP51 },
149 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_SATA,
150 PCI_ANY_ID, PCI_ANY_ID, 0, 0, MCP55 },
151 { PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID,
152 PCI_ANY_ID, PCI_ANY_ID,
153 PCI_CLASS_STORAGE_IDE<<8, 0xffff00, GENERIC },
154 { PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID,
155 PCI_ANY_ID, PCI_ANY_ID,
156 PCI_CLASS_STORAGE_RAID<<8, 0xffff00, GENERIC },
157 { 0, } /* terminate list */
160 #define NV_HOST_FLAGS_SCR_MMIO 0x00000001
164 enum nv_host_type host_type;
165 void (*enable_hotplug)(struct ata_probe_ent *probe_ent);
166 void (*disable_hotplug)(struct ata_host_set *host_set);
167 void (*check_hotplug)(struct ata_host_set *host_set);
170 static struct nv_host_desc nv_device_tbl[] = {
172 .host_type = GENERIC,
173 .enable_hotplug = NULL,
174 .disable_hotplug= NULL,
175 .check_hotplug = NULL,
178 .host_type = NFORCE2,
179 .enable_hotplug = nv_enable_hotplug,
180 .disable_hotplug= nv_disable_hotplug,
181 .check_hotplug = nv_check_hotplug,
184 .host_type = NFORCE3,
185 .enable_hotplug = nv_enable_hotplug,
186 .disable_hotplug= nv_disable_hotplug,
187 .check_hotplug = nv_check_hotplug,
189 { .host_type = CK804,
190 .enable_hotplug = nv_enable_hotplug_ck804,
191 .disable_hotplug= nv_disable_hotplug_ck804,
192 .check_hotplug = nv_check_hotplug_ck804,
198 struct nv_host_desc *host_desc;
199 unsigned long host_flags;
202 static struct pci_driver nv_pci_driver = {
204 .id_table = nv_pci_tbl,
205 .probe = nv_init_one,
206 .remove = ata_pci_remove_one,
209 static Scsi_Host_Template nv_sht = {
210 .module = THIS_MODULE,
212 .ioctl = ata_scsi_ioctl,
213 .queuecommand = ata_scsi_queuecmd,
214 .eh_strategy_handler = ata_scsi_error,
215 .can_queue = ATA_DEF_QUEUE,
216 .this_id = ATA_SHT_THIS_ID,
217 .sg_tablesize = LIBATA_MAX_PRD,
218 .max_sectors = ATA_MAX_SECTORS,
219 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
220 .emulated = ATA_SHT_EMULATED,
221 .use_clustering = ATA_SHT_USE_CLUSTERING,
222 .proc_name = DRV_NAME,
223 .dma_boundary = ATA_DMA_BOUNDARY,
224 .slave_configure = ata_scsi_slave_config,
225 .bios_param = ata_std_bios_param,
229 static struct ata_port_operations nv_ops = {
230 .port_disable = ata_port_disable,
231 .tf_load = ata_tf_load,
232 .tf_read = ata_tf_read,
233 .exec_command = ata_exec_command,
234 .check_status = ata_check_status,
235 .dev_select = ata_std_dev_select,
236 .phy_reset = sata_phy_reset,
237 .bmdma_setup = ata_bmdma_setup,
238 .bmdma_start = ata_bmdma_start,
239 .bmdma_stop = ata_bmdma_stop,
240 .bmdma_status = ata_bmdma_status,
241 .qc_prep = ata_qc_prep,
242 .qc_issue = ata_qc_issue_prot,
243 .eng_timeout = ata_eng_timeout,
244 .irq_handler = nv_interrupt,
245 .irq_clear = ata_bmdma_irq_clear,
246 .scr_read = nv_scr_read,
247 .scr_write = nv_scr_write,
248 .port_start = ata_port_start,
249 .port_stop = ata_port_stop,
250 .host_stop = nv_host_stop,
253 /* FIXME: The hardware provides the necessary SATA PHY controls
254 * to support ATA_FLAG_SATA_RESET. However, it is currently
255 * necessary to disable that flag, to solve misdetection problems.
256 * See http://bugme.osdl.org/show_bug.cgi?id=3352 for more info.
258 * This problem really needs to be investigated further. But in the
259 * meantime, we avoid ATA_FLAG_SATA_RESET to get people working.
261 static struct ata_port_info nv_port_info = {
263 .host_flags = ATA_FLAG_SATA |
264 /* ATA_FLAG_SATA_RESET | */
267 .pio_mask = NV_PIO_MASK,
268 .mwdma_mask = NV_MWDMA_MASK,
269 .udma_mask = NV_UDMA_MASK,
273 MODULE_AUTHOR("NVIDIA");
274 MODULE_DESCRIPTION("low-level driver for NVIDIA nForce SATA controller");
275 MODULE_LICENSE("GPL");
276 MODULE_DEVICE_TABLE(pci, nv_pci_tbl);
277 MODULE_VERSION(DRV_VERSION);
279 static irqreturn_t nv_interrupt (int irq, void *dev_instance,
280 struct pt_regs *regs)
282 struct ata_host_set *host_set = dev_instance;
283 struct nv_host *host = host_set->private_data;
285 unsigned int handled = 0;
288 spin_lock_irqsave(&host_set->lock, flags);
290 for (i = 0; i < host_set->n_ports; i++) {
293 ap = host_set->ports[i];
295 !(ap->flags & (ATA_FLAG_PORT_DISABLED | ATA_FLAG_NOINTR))) {
296 struct ata_queued_cmd *qc;
298 qc = ata_qc_from_tag(ap, ap->active_tag);
299 if (qc && (!(qc->tf.ctl & ATA_NIEN)))
300 handled += ata_host_intr(ap, qc);
305 if (host->host_desc->check_hotplug)
306 host->host_desc->check_hotplug(host_set);
308 spin_unlock_irqrestore(&host_set->lock, flags);
310 return IRQ_RETVAL(handled);
313 static u32 nv_scr_read (struct ata_port *ap, unsigned int sc_reg)
315 struct ata_host_set *host_set = ap->host_set;
316 struct nv_host *host = host_set->private_data;
318 if (sc_reg > SCR_CONTROL)
321 if (host->host_flags & NV_HOST_FLAGS_SCR_MMIO)
322 return readl((void*)ap->ioaddr.scr_addr + (sc_reg * 4));
324 return inl(ap->ioaddr.scr_addr + (sc_reg * 4));
327 static void nv_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val)
329 struct ata_host_set *host_set = ap->host_set;
330 struct nv_host *host = host_set->private_data;
332 if (sc_reg > SCR_CONTROL)
335 if (host->host_flags & NV_HOST_FLAGS_SCR_MMIO)
336 writel(val, (void*)ap->ioaddr.scr_addr + (sc_reg * 4));
338 outl(val, ap->ioaddr.scr_addr + (sc_reg * 4));
341 static void nv_host_stop (struct ata_host_set *host_set)
343 struct nv_host *host = host_set->private_data;
345 // Disable hotplug event interrupts.
346 if (host->host_desc->disable_hotplug)
347 host->host_desc->disable_hotplug(host_set);
351 ata_host_stop(host_set);
354 static int nv_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
356 static int printed_version = 0;
357 struct nv_host *host;
358 struct ata_port_info *ppi;
359 struct ata_probe_ent *probe_ent;
360 int pci_dev_busy = 0;
364 // Make sure this is a SATA controller by counting the number of bars
365 // (NVIDIA SATA controllers will always have six bars). Otherwise,
366 // it's an IDE controller and we ignore it.
367 for (bar=0; bar<6; bar++)
368 if (pci_resource_start(pdev, bar) == 0)
371 if (!printed_version++)
372 printk(KERN_DEBUG DRV_NAME " version " DRV_VERSION "\n");
374 rc = pci_enable_device(pdev);
378 rc = pci_request_regions(pdev, DRV_NAME);
381 goto err_out_disable;
384 rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
386 goto err_out_regions;
387 rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
389 goto err_out_regions;
394 probe_ent = ata_pci_init_native_mode(pdev, &ppi);
396 goto err_out_regions;
398 host = kmalloc(sizeof(struct nv_host), GFP_KERNEL);
400 goto err_out_free_ent;
402 memset(host, 0, sizeof(struct nv_host));
403 host->host_desc = &nv_device_tbl[ent->driver_data];
405 probe_ent->private_data = host;
407 if (pci_resource_flags(pdev, 5) & IORESOURCE_MEM)
408 host->host_flags |= NV_HOST_FLAGS_SCR_MMIO;
410 if (host->host_flags & NV_HOST_FLAGS_SCR_MMIO) {
413 probe_ent->mmio_base = ioremap(pci_resource_start(pdev, 5),
414 pci_resource_len(pdev, 5));
415 if (probe_ent->mmio_base == NULL) {
417 goto err_out_free_host;
420 base = (unsigned long)probe_ent->mmio_base;
422 probe_ent->port[0].scr_addr =
423 base + NV_PORT0_SCR_REG_OFFSET;
424 probe_ent->port[1].scr_addr =
425 base + NV_PORT1_SCR_REG_OFFSET;
428 probe_ent->port[0].scr_addr =
429 pci_resource_start(pdev, 5) | NV_PORT0_SCR_REG_OFFSET;
430 probe_ent->port[1].scr_addr =
431 pci_resource_start(pdev, 5) | NV_PORT1_SCR_REG_OFFSET;
434 pci_set_master(pdev);
436 rc = ata_device_add(probe_ent);
438 goto err_out_iounmap;
440 // Enable hotplug event interrupts.
441 if (host->host_desc->enable_hotplug)
442 host->host_desc->enable_hotplug(probe_ent);
449 if (host->host_flags & NV_HOST_FLAGS_SCR_MMIO)
450 iounmap(probe_ent->mmio_base);
456 pci_release_regions(pdev);
459 pci_disable_device(pdev);
464 static void nv_enable_hotplug(struct ata_probe_ent *probe_ent)
468 outb(NV_INT_STATUS_HOTPLUG,
469 probe_ent->port[0].scr_addr + NV_INT_STATUS);
471 intr_mask = inb(probe_ent->port[0].scr_addr + NV_INT_ENABLE);
472 intr_mask |= NV_INT_ENABLE_HOTPLUG;
474 outb(intr_mask, probe_ent->port[0].scr_addr + NV_INT_ENABLE);
477 static void nv_disable_hotplug(struct ata_host_set *host_set)
481 intr_mask = inb(host_set->ports[0]->ioaddr.scr_addr + NV_INT_ENABLE);
483 intr_mask &= ~(NV_INT_ENABLE_HOTPLUG);
485 outb(intr_mask, host_set->ports[0]->ioaddr.scr_addr + NV_INT_ENABLE);
488 static void nv_check_hotplug(struct ata_host_set *host_set)
492 intr_status = inb(host_set->ports[0]->ioaddr.scr_addr + NV_INT_STATUS);
494 // Clear interrupt status.
495 outb(0xff, host_set->ports[0]->ioaddr.scr_addr + NV_INT_STATUS);
497 if (intr_status & NV_INT_STATUS_HOTPLUG) {
498 if (intr_status & NV_INT_STATUS_PDEV_ADDED)
499 printk(KERN_WARNING "nv_sata: "
500 "Primary device added\n");
502 if (intr_status & NV_INT_STATUS_PDEV_REMOVED)
503 printk(KERN_WARNING "nv_sata: "
504 "Primary device removed\n");
506 if (intr_status & NV_INT_STATUS_SDEV_ADDED)
507 printk(KERN_WARNING "nv_sata: "
508 "Secondary device added\n");
510 if (intr_status & NV_INT_STATUS_SDEV_REMOVED)
511 printk(KERN_WARNING "nv_sata: "
512 "Secondary device removed\n");
516 static void nv_enable_hotplug_ck804(struct ata_probe_ent *probe_ent)
518 struct pci_dev *pdev = to_pci_dev(probe_ent->dev);
522 pci_read_config_byte(pdev, NV_MCP_SATA_CFG_20, ®val);
523 regval |= NV_MCP_SATA_CFG_20_SATA_SPACE_EN;
524 pci_write_config_byte(pdev, NV_MCP_SATA_CFG_20, regval);
526 writeb(NV_INT_STATUS_HOTPLUG, probe_ent->mmio_base + NV_INT_STATUS_CK804);
528 intr_mask = readb(probe_ent->mmio_base + NV_INT_ENABLE_CK804);
529 intr_mask |= NV_INT_ENABLE_HOTPLUG;
531 writeb(intr_mask, probe_ent->mmio_base + NV_INT_ENABLE_CK804);
534 static void nv_disable_hotplug_ck804(struct ata_host_set *host_set)
536 struct pci_dev *pdev = to_pci_dev(host_set->dev);
540 intr_mask = readb(host_set->mmio_base + NV_INT_ENABLE_CK804);
542 intr_mask &= ~(NV_INT_ENABLE_HOTPLUG);
544 writeb(intr_mask, host_set->mmio_base + NV_INT_ENABLE_CK804);
546 pci_read_config_byte(pdev, NV_MCP_SATA_CFG_20, ®val);
547 regval &= ~NV_MCP_SATA_CFG_20_SATA_SPACE_EN;
548 pci_write_config_byte(pdev, NV_MCP_SATA_CFG_20, regval);
551 static void nv_check_hotplug_ck804(struct ata_host_set *host_set)
555 intr_status = readb(host_set->mmio_base + NV_INT_STATUS_CK804);
557 // Clear interrupt status.
558 writeb(0xff, host_set->mmio_base + NV_INT_STATUS_CK804);
560 if (intr_status & NV_INT_STATUS_HOTPLUG) {
561 if (intr_status & NV_INT_STATUS_PDEV_ADDED)
562 printk(KERN_WARNING "nv_sata: "
563 "Primary device added\n");
565 if (intr_status & NV_INT_STATUS_PDEV_REMOVED)
566 printk(KERN_WARNING "nv_sata: "
567 "Primary device removed\n");
569 if (intr_status & NV_INT_STATUS_SDEV_ADDED)
570 printk(KERN_WARNING "nv_sata: "
571 "Secondary device added\n");
573 if (intr_status & NV_INT_STATUS_SDEV_REMOVED)
574 printk(KERN_WARNING "nv_sata: "
575 "Secondary device removed\n");
579 static int __init nv_init(void)
581 return pci_module_init(&nv_pci_driver);
584 static void __exit nv_exit(void)
586 pci_unregister_driver(&nv_pci_driver);
589 module_init(nv_init);
590 module_exit(nv_exit);