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   1 #ifndef _MVME147HW_H_
   2 #define _MVME147HW_H_
   3
   4 typedef struct {
   5         unsigned char
   6                 ctrl,
   7                 bcd_sec,
   8                 bcd_min,
   9                 bcd_hr,
  10                 bcd_dow,
  11                 bcd_dom,
  12                 bcd_mth,
  13                 bcd_year;
  14 } MK48T02;
  15
  16 #define RTC_WRITE       0x80
  17 #define RTC_READ        0x40
  18 #define RTC_STOP        0x20
  19
  20 #define m147_rtc ((MK48T02 * volatile)0xfffe07f8)
  21
  22
  23 struct pcc_regs {
  24    volatile u_long      dma_tadr;
  25    volatile u_long      dma_dadr;
  26    volatile u_long      dma_bcr;
  27    volatile u_long      dma_hr;
  28    volatile u_short     t1_preload;
  29    volatile u_short     t1_count;
  30    volatile u_short     t2_preload;
  31    volatile u_short     t2_count;
  32    volatile u_char      t1_int_cntrl;
  33    volatile u_char      t1_cntrl;
  34    volatile u_char      t2_int_cntrl;
  35    volatile u_char      t2_cntrl;
  36    volatile u_char      ac_fail;
  37    volatile u_char      watchdog;
  38    volatile u_char      lpt_intr;
  39    volatile u_char      lpt_cntrl;
  40    volatile u_char      dma_intr;
  41    volatile u_char      dma_cntrl;
  42    volatile u_char      bus_error;
  43    volatile u_char      dma_status;
  44    volatile u_char      abort;
  45    volatile u_char      ta_fnctl;
  46    volatile u_char      serial_cntrl;
  47    volatile u_char      general_cntrl;
  48    volatile u_char      lan_cntrl;
  49    volatile u_char      general_status;
  50    volatile u_char      scsi_interrupt;
  51    volatile u_char      slave;
  52    volatile u_char      soft1_cntrl;
  53    volatile u_char      int_base;
  54    volatile u_char      soft2_cntrl;
  55    volatile u_char      revision_level;
  56    volatile u_char      lpt_data;
  57    volatile u_char      lpt_status;
  58    };
  59
  60 #define m147_pcc ((struct pcc_regs * volatile)0xfffe1000)
  61
  62
  63 #define PCC_INT_ENAB            0x08
  64
  65 #define PCC_TIMER_INT_CLR       0x80
  66 #define PCC_TIMER_PRELOAD       63936l
  67
  68 #define PCC_LEVEL_ABORT         0x07
  69 #define PCC_LEVEL_SERIAL        0x04
  70 #define PCC_LEVEL_ETH           0x04
  71 #define PCC_LEVEL_TIMER1        0x04
  72 #define PCC_LEVEL_SCSI_PORT     0x04
  73 #define PCC_LEVEL_SCSI_DMA      0x04
  74
  75 #define PCC_IRQ_AC_FAIL         0x40
  76 #define PCC_IRQ_BERR            0x41
  77 #define PCC_IRQ_ABORT           0x42
  78 /* #define PCC_IRQ_SERIAL       0x43 */
  79 #define PCC_IRQ_PRINTER         0x47
  80 #define PCC_IRQ_TIMER1          0x48
  81 #define PCC_IRQ_TIMER2          0x49
  82 #define PCC_IRQ_SOFTWARE1       0x4a
  83 #define PCC_IRQ_SOFTWARE2       0x4b
  84
  85
  86 #define M147_SCC_A_ADDR         0xfffe3002
  87 #define M147_SCC_B_ADDR         0xfffe3000
  88 #define M147_SCC_PCLK           5000000
  89
  90 #define MVME147_IRQ_SCSI_PORT   0x45
  91 #define MVME147_IRQ_SCSI_DMA    0x46
  92
  93 /* SCC interrupts, for MVME147 */
  94
  95 #define MVME147_IRQ_TYPE_PRIO   0
  96 #define MVME147_IRQ_SCC_BASE            0x60
  97 #define MVME147_IRQ_SCCB_TX             0x60
  98 #define MVME147_IRQ_SCCB_STAT           0x62
  99 #define MVME147_IRQ_SCCB_RX             0x64
 100 #define MVME147_IRQ_SCCB_SPCOND         0x66
 101 #define MVME147_IRQ_SCCA_TX             0x68
 102 #define MVME147_IRQ_SCCA_STAT           0x6a
 103 #define MVME147_IRQ_SCCA_RX             0x6c
 104 #define MVME147_IRQ_SCCA_SPCOND         0x6e
 105
 106 #define MVME147_LANCE_BASE      0xfffe1800
 107 #define MVME147_LANCE_IRQ       0x44
 108
 109 #define ETHERNET_ADDRESS 0xfffe0778
 110
 111 #endif