git.oblomov.eu Git - linux-2.6/blob - drivers/ide/pci/sis5513.c

   1 /*
   2  * linux/drivers/ide/pci/sis5513.c      Version 0.16ac+vp       Jun 18, 2003
   3  *
   4  * Copyright (C) 1999-2000      Andre Hedrick <andre@linux-ide.org>
   5  * Copyright (C) 2002           Lionel Bouton <Lionel.Bouton@inet6.fr>, Maintainer
   6  * Copyright (C) 2003           Vojtech Pavlik <vojtech@suse.cz>
   7  * May be copied or modified under the terms of the GNU General Public License
   8  *
   9  *
  10  * Thanks :
  11  *
  12  * SiS Taiwan           : for direct support and hardware.
  13  * Daniela Engert       : for initial ATA100 advices and numerous others.
  14  * John Fremlin, Manfred Spraul, Dave Morgan, Peter Kjellerstedt        :
  15  *                        for checking code correctness, providing patches.
  16  *
  17  *
  18  * Original tests and design on the SiS620 chipset.
  19  * ATA100 tests and design on the SiS735 chipset.
  20  * ATA16/33 support from specs
  21  * ATA133 support for SiS961/962 by L.C. Chang <lcchang@sis.com.tw>
  22  * ATA133 961/962/963 fixes by Vojtech Pavlik <vojtech@suse.cz>
  23  *
  24  * Documentation:
  25  *      SiS chipset documentation available under NDA to companies only
  26  *      (not to individuals).
  27  */
  28
  29 /*
  30  * The original SiS5513 comes from a SiS5511/55112/5513 chipset. The original
  31  * SiS5513 was also used in the SiS5596/5513 chipset. Thus if we see a SiS5511
  32  * or SiS5596, we can assume we see the first MWDMA-16 capable SiS5513 chip.
  33  *
  34  * Later SiS chipsets integrated the 5513 functionality into the NorthBridge,
  35  * starting with SiS5571 and up to SiS745. The PCI ID didn't change, though. We
  36  * can figure out that we have a more modern and more capable 5513 by looking
  37  * for the respective NorthBridge IDs.
  38  *
  39  * Even later (96x family) SiS chipsets use the MuTIOL link and place the 5513
  40  * into the SouthBrige. Here we cannot rely on looking up the NorthBridge PCI
  41  * ID, while the now ATA-133 capable 5513 still has the same PCI ID.
  42  * Fortunately the 5513 can be 'unmasked' by fiddling with some config space
  43  * bits, changing its device id to the true one - 5517 for 961 and 5518 for
  44  * 962/963.
  45  */
  46
  47 #include <linux/config.h>
  48 #include <linux/types.h>
  49 #include <linux/module.h>
  50 #include <linux/kernel.h>
  51 #include <linux/delay.h>
  52 #include <linux/timer.h>
  53 #include <linux/mm.h>
  54 #include <linux/ioport.h>
  55 #include <linux/blkdev.h>
  56 #include <linux/hdreg.h>
  57
  58 #include <linux/interrupt.h>
  59 #include <linux/pci.h>
  60 #include <linux/init.h>
  61 #include <linux/ide.h>
  62
  63 #include <asm/irq.h>
  64
  65 #include "ide-timing.h"
  66
  67 #define DISPLAY_SIS_TIMINGS
  68
  69 /* registers layout and init values are chipset family dependant */
  70
  71 #define ATA_16          0x01
  72 #define ATA_33          0x02
  73 #define ATA_66          0x03
  74 #define ATA_100a        0x04 // SiS730/SiS550 is ATA100 with ATA66 layout
  75 #define ATA_100         0x05
  76 #define ATA_133a        0x06 // SiS961b with 133 support
  77 #define ATA_133         0x07 // SiS962/963
  78
  79 static u8 chipset_family;
  80
  81 /*
  82  * Devices supported
  83  */
  84 static const struct {
  85         const char *name;
  86         u16 host_id;
  87         u8 chipset_family;
  88         u8 flags;
  89 } SiSHostChipInfo[] = {
  90         { "SiS965",     PCI_DEVICE_ID_SI_965,   ATA_133  },
  91         { "SiS745",     PCI_DEVICE_ID_SI_745,   ATA_100  },
  92         { "SiS735",     PCI_DEVICE_ID_SI_735,   ATA_100  },
  93         { "SiS733",     PCI_DEVICE_ID_SI_733,   ATA_100  },
  94         { "SiS635",     PCI_DEVICE_ID_SI_635,   ATA_100  },
  95         { "SiS633",     PCI_DEVICE_ID_SI_633,   ATA_100  },
  96
  97         { "SiS730",     PCI_DEVICE_ID_SI_730,   ATA_100a },
  98         { "SiS550",     PCI_DEVICE_ID_SI_550,   ATA_100a },
  99
 100         { "SiS640",     PCI_DEVICE_ID_SI_640,   ATA_66   },
 101         { "SiS630",     PCI_DEVICE_ID_SI_630,   ATA_66   },
 102         { "SiS620",     PCI_DEVICE_ID_SI_620,   ATA_66   },
 103         { "SiS540",     PCI_DEVICE_ID_SI_540,   ATA_66   },
 104         { "SiS530",     PCI_DEVICE_ID_SI_530,   ATA_66   },
 105
 106         { "SiS5600",    PCI_DEVICE_ID_SI_5600,  ATA_33   },
 107         { "SiS5598",    PCI_DEVICE_ID_SI_5598,  ATA_33   },
 108         { "SiS5597",    PCI_DEVICE_ID_SI_5597,  ATA_33   },
 109         { "SiS5591/2",  PCI_DEVICE_ID_SI_5591,  ATA_33   },
 110         { "SiS5582",    PCI_DEVICE_ID_SI_5582,  ATA_33   },
 111         { "SiS5581",    PCI_DEVICE_ID_SI_5581,  ATA_33   },
 112
 113         { "SiS5596",    PCI_DEVICE_ID_SI_5596,  ATA_16   },
 114         { "SiS5571",    PCI_DEVICE_ID_SI_5571,  ATA_16   },
 115         { "SiS551x",    PCI_DEVICE_ID_SI_5511,  ATA_16   },
 116 };
 117
 118 /* Cycle time bits and values vary across chip dma capabilities
 119    These three arrays hold the register layout and the values to set.
 120    Indexed by chipset_family and (dma_mode - XFER_UDMA_0) */
 121
 122 /* {0, ATA_16, ATA_33, ATA_66, ATA_100a, ATA_100, ATA_133} */
 123 static u8 cycle_time_offset[] = {0,0,5,4,4,0,0};
 124 static u8 cycle_time_range[] = {0,0,2,3,3,4,4};
 125 static u8 cycle_time_value[][XFER_UDMA_6 - XFER_UDMA_0 + 1] = {
 126         {0,0,0,0,0,0,0}, /* no udma */
 127         {0,0,0,0,0,0,0}, /* no udma */
 128         {3,2,1,0,0,0,0}, /* ATA_33 */
 129         {7,5,3,2,1,0,0}, /* ATA_66 */
 130         {7,5,3,2,1,0,0}, /* ATA_100a (730 specific), differences are on cycle_time range and offset */
 131         {11,7,5,4,2,1,0}, /* ATA_100 */
 132         {15,10,7,5,3,2,1}, /* ATA_133a (earliest 691 southbridges) */
 133         {15,10,7,5,3,2,1}, /* ATA_133 */
 134 };
 135 /* CRC Valid Setup Time vary across IDE clock setting 33/66/100/133
 136    See SiS962 data sheet for more detail */
 137 static u8 cvs_time_value[][XFER_UDMA_6 - XFER_UDMA_0 + 1] = {
 138         {0,0,0,0,0,0,0}, /* no udma */
 139         {0,0,0,0,0,0,0}, /* no udma */
 140         {2,1,1,0,0,0,0},
 141         {4,3,2,1,0,0,0},
 142         {4,3,2,1,0,0,0},
 143         {6,4,3,1,1,1,0},
 144         {9,6,4,2,2,2,2},
 145         {9,6,4,2,2,2,2},
 146 };
 147 /* Initialize time, Active time, Recovery time vary across
 148    IDE clock settings. These 3 arrays hold the register value
 149    for PIO0/1/2/3/4 and DMA0/1/2 mode in order */
 150 static u8 ini_time_value[][8] = {
 151         {0,0,0,0,0,0,0,0},
 152         {0,0,0,0,0,0,0,0},
 153         {2,1,0,0,0,1,0,0},
 154         {4,3,1,1,1,3,1,1},
 155         {4,3,1,1,1,3,1,1},
 156         {6,4,2,2,2,4,2,2},
 157         {9,6,3,3,3,6,3,3},
 158         {9,6,3,3,3,6,3,3},
 159 };
 160 static u8 act_time_value[][8] = {
 161         {0,0,0,0,0,0,0,0},
 162         {0,0,0,0,0,0,0,0},
 163         {9,9,9,2,2,7,2,2},
 164         {19,19,19,5,4,14,5,4},
 165         {19,19,19,5,4,14,5,4},
 166         {28,28,28,7,6,21,7,6},
 167         {38,38,38,10,9,28,10,9},
 168         {38,38,38,10,9,28,10,9},
 169 };
 170 static u8 rco_time_value[][8] = {
 171         {0,0,0,0,0,0,0,0},
 172         {0,0,0,0,0,0,0,0},
 173         {9,2,0,2,0,7,1,1},
 174         {19,5,1,5,2,16,3,2},
 175         {19,5,1,5,2,16,3,2},
 176         {30,9,3,9,4,25,6,4},
 177         {40,12,4,12,5,34,12,5},
 178         {40,12,4,12,5,34,12,5},
 179 };
 180
 181 /*
 182  * Printing configuration
 183  */
 184 /* Used for chipset type printing at boot time */
 185 static char* chipset_capability[] = {
 186         "ATA", "ATA 16",
 187         "ATA 33", "ATA 66",
 188         "ATA 100 (1st gen)", "ATA 100 (2nd gen)",
 189         "ATA 133 (1st gen)", "ATA 133 (2nd gen)"
 190 };
 191
 192 #if defined(DISPLAY_SIS_TIMINGS) && defined(CONFIG_PROC_FS)
 193 #include <linux/stat.h>
 194 #include <linux/proc_fs.h>
 195
 196 static u8 sis_proc = 0;
 197
 198 static struct pci_dev *bmide_dev;
 199
 200 static char* cable_type[] = {
 201         "80 pins",
 202         "40 pins"
 203 };
 204
 205 static char* recovery_time[] ={
 206         "12 PCICLK", "1 PCICLK",
 207         "2 PCICLK", "3 PCICLK",
 208         "4 PCICLK", "5 PCICLCK",
 209         "6 PCICLK", "7 PCICLCK",
 210         "8 PCICLK", "9 PCICLCK",
 211         "10 PCICLK", "11 PCICLK",
 212         "13 PCICLK", "14 PCICLK",
 213         "15 PCICLK", "15 PCICLK"
 214 };
 215
 216 static char* active_time[] = {
 217         "8 PCICLK", "1 PCICLCK",
 218         "2 PCICLK", "3 PCICLK",
 219         "4 PCICLK", "5 PCICLK",
 220         "6 PCICLK", "12 PCICLK"
 221 };
 222
 223 static char* cycle_time[] = {
 224         "Reserved", "2 CLK",
 225         "3 CLK", "4 CLK",
 226         "5 CLK", "6 CLK",
 227         "7 CLK", "8 CLK",
 228         "9 CLK", "10 CLK",
 229         "11 CLK", "12 CLK",
 230         "13 CLK", "14 CLK",
 231         "15 CLK", "16 CLK"
 232 };
 233
 234 /* Generic add master or slave info function */
 235 static char* get_drives_info (char *buffer, u8 pos)
 236 {
 237         u8 reg00, reg01, reg10, reg11; /* timing registers */
 238         u32 regdw0, regdw1;
 239         char* p = buffer;
 240
 241 /* Postwrite/Prefetch */
 242         if (chipset_family < ATA_133) {
 243                 pci_read_config_byte(bmide_dev, 0x4b, &reg00);
 244                 p += sprintf(p, "Drive %d:        Postwrite %s \t \t Postwrite %s\n",
 245                              pos, (reg00 & (0x10 << pos)) ? "Enabled" : "Disabled",
 246                              (reg00 & (0x40 << pos)) ? "Enabled" : "Disabled");
 247                 p += sprintf(p, "                Prefetch  %s \t \t Prefetch  %s\n",
 248                              (reg00 & (0x01 << pos)) ? "Enabled" : "Disabled",
 249                              (reg00 & (0x04 << pos)) ? "Enabled" : "Disabled");
 250                 pci_read_config_byte(bmide_dev, 0x40+2*pos, &reg00);
 251                 pci_read_config_byte(bmide_dev, 0x41+2*pos, &reg01);
 252                 pci_read_config_byte(bmide_dev, 0x44+2*pos, &reg10);
 253                 pci_read_config_byte(bmide_dev, 0x45+2*pos, &reg11);
 254         } else {
 255                 u32 reg54h;
 256                 u8 drive_pci = 0x40;
 257                 pci_read_config_dword(bmide_dev, 0x54, &reg54h);
 258                 if (reg54h & 0x40000000) {
 259                         // Configuration space remapped to 0x70
 260                         drive_pci = 0x70;
 261                 }
 262                 pci_read_config_dword(bmide_dev, (unsigned long)drive_pci+4*pos, &regdw0);
 263                 pci_read_config_dword(bmide_dev, (unsigned long)drive_pci+4*pos+8, &regdw1);
 264
 265                 p += sprintf(p, "Drive %d:\n", pos);
 266         }
 267
 268
 269 /* UDMA */
 270         if (chipset_family >= ATA_133) {
 271                 p += sprintf(p, "                UDMA %s \t \t \t UDMA %s\n",
 272                              (regdw0 & 0x04) ? "Enabled" : "Disabled",
 273                              (regdw1 & 0x04) ? "Enabled" : "Disabled");
 274                 p += sprintf(p, "                UDMA Cycle Time    %s \t UDMA Cycle Time    %s\n",
 275                              cycle_time[(regdw0 & 0xF0) >> 4],
 276                              cycle_time[(regdw1 & 0xF0) >> 4]);
 277         } else if (chipset_family >= ATA_33) {
 278                 p += sprintf(p, "                UDMA %s \t \t \t UDMA %s\n",
 279                              (reg01 & 0x80) ? "Enabled" : "Disabled",
 280                              (reg11 & 0x80) ? "Enabled" : "Disabled");
 281
 282                 p += sprintf(p, "                UDMA Cycle Time    ");
 283                 switch(chipset_family) {
 284                         case ATA_33:    p += sprintf(p, cycle_time[(reg01 & 0x60) >> 5]); break;
 285                         case ATA_66:
 286                         case ATA_100a:  p += sprintf(p, cycle_time[(reg01 & 0x70) >> 4]); break;
 287                         case ATA_100:
 288                         case ATA_133a:  p += sprintf(p, cycle_time[reg01 & 0x0F]); break;
 289                         default:        p += sprintf(p, "?"); break;
 290                 }
 291                 p += sprintf(p, " \t UDMA Cycle Time    ");
 292                 switch(chipset_family) {
 293                         case ATA_33:    p += sprintf(p, cycle_time[(reg11 & 0x60) >> 5]); break;
 294                         case ATA_66:
 295                         case ATA_100a:  p += sprintf(p, cycle_time[(reg11 & 0x70) >> 4]); break;
 296                         case ATA_100:
 297                         case ATA_133a:  p += sprintf(p, cycle_time[reg11 & 0x0F]); break;
 298                         default:        p += sprintf(p, "?"); break;
 299                 }
 300                 p += sprintf(p, "\n");
 301         }
 302
 303
 304         if (chipset_family < ATA_133) { /* else case TODO */
 305
 306 /* Data Active */
 307                 p += sprintf(p, "                Data Active Time   ");
 308                 switch(chipset_family) {
 309                         case ATA_16: /* confirmed */
 310                         case ATA_33:
 311                         case ATA_66:
 312                         case ATA_100a: p += sprintf(p, active_time[reg01 & 0x07]); break;
 313                         case ATA_100:
 314                         case ATA_133a: p += sprintf(p, active_time[(reg00 & 0x70) >> 4]); break;
 315                         default: p += sprintf(p, "?"); break;
 316                 }
 317                 p += sprintf(p, " \t Data Active Time   ");
 318                 switch(chipset_family) {
 319                         case ATA_16:
 320                         case ATA_33:
 321                         case ATA_66:
 322                         case ATA_100a: p += sprintf(p, active_time[reg11 & 0x07]); break;
 323                         case ATA_100:
 324                         case ATA_133a: p += sprintf(p, active_time[(reg10 & 0x70) >> 4]); break;
 325                         default: p += sprintf(p, "?"); break;
 326                 }
 327                 p += sprintf(p, "\n");
 328
 329 /* Data Recovery */
 330         /* warning: may need (reg&0x07) for pre ATA66 chips */
 331                 p += sprintf(p, "                Data Recovery Time %s \t Data Recovery Time %s\n",
 332                              recovery_time[reg00 & 0x0f], recovery_time[reg10 & 0x0f]);
 333         }
 334
 335         return p;
 336 }
 337
 338 static char* get_masters_info(char* buffer)
 339 {
 340         return get_drives_info(buffer, 0);
 341 }
 342
 343 static char* get_slaves_info(char* buffer)
 344 {
 345         return get_drives_info(buffer, 1);
 346 }
 347
 348 /* Main get_info, called on /proc/ide/sis reads */
 349 static int sis_get_info (char *buffer, char **addr, off_t offset, int count)
 350 {
 351         char *p = buffer;
 352         int len;
 353         u8 reg;
 354         u16 reg2, reg3;
 355
 356         p += sprintf(p, "\nSiS 5513 ");
 357         switch(chipset_family) {
 358                 case ATA_16: p += sprintf(p, "DMA 16"); break;
 359                 case ATA_33: p += sprintf(p, "Ultra 33"); break;
 360                 case ATA_66: p += sprintf(p, "Ultra 66"); break;
 361                 case ATA_100a:
 362                 case ATA_100: p += sprintf(p, "Ultra 100"); break;
 363                 case ATA_133a:
 364                 case ATA_133: p += sprintf(p, "Ultra 133"); break;
 365                 default: p+= sprintf(p, "Unknown???"); break;
 366         }
 367         p += sprintf(p, " chipset\n");
 368         p += sprintf(p, "--------------- Primary Channel "
 369                      "---------------- Secondary Channel "
 370                      "-------------\n");
 371
 372 /* Status */
 373         pci_read_config_byte(bmide_dev, 0x4a, &reg);
 374         if (chipset_family == ATA_133) {
 375                 pci_read_config_word(bmide_dev, 0x50, &reg2);
 376                 pci_read_config_word(bmide_dev, 0x52, &reg3);
 377         }
 378         p += sprintf(p, "Channel Status: ");
 379         if (chipset_family < ATA_66) {
 380                 p += sprintf(p, "%s \t \t \t \t %s\n",
 381                              (reg & 0x04) ? "On" : "Off",
 382                              (reg & 0x02) ? "On" : "Off");
 383         } else if (chipset_family < ATA_133) {
 384                 p += sprintf(p, "%s \t \t \t \t %s \n",
 385                              (reg & 0x02) ? "On" : "Off",
 386                              (reg & 0x04) ? "On" : "Off");
 387         } else { /* ATA_133 */
 388                 p += sprintf(p, "%s \t \t \t \t %s \n",
 389                              (reg2 & 0x02) ? "On" : "Off",
 390                              (reg3 & 0x02) ? "On" : "Off");
 391         }
 392
 393 /* Operation Mode */
 394         pci_read_config_byte(bmide_dev, 0x09, &reg);
 395         p += sprintf(p, "Operation Mode: %s \t \t \t %s \n",
 396                      (reg & 0x01) ? "Native" : "Compatible",
 397                      (reg & 0x04) ? "Native" : "Compatible");
 398
 399 /* 80-pin cable ? */
 400         if (chipset_family >= ATA_133) {
 401                 p += sprintf(p, "Cable Type:     %s \t \t \t %s\n",
 402                              (reg2 & 0x01) ? cable_type[1] : cable_type[0],
 403                              (reg3 & 0x01) ? cable_type[1] : cable_type[0]);
 404         } else if (chipset_family > ATA_33) {
 405                 pci_read_config_byte(bmide_dev, 0x48, &reg);
 406                 p += sprintf(p, "Cable Type:     %s \t \t \t %s\n",
 407                              (reg & 0x10) ? cable_type[1] : cable_type[0],
 408                              (reg & 0x20) ? cable_type[1] : cable_type[0]);
 409         }
 410
 411 /* Prefetch Count */
 412         if (chipset_family < ATA_133) {
 413                 pci_read_config_word(bmide_dev, 0x4c, &reg2);
 414                 pci_read_config_word(bmide_dev, 0x4e, &reg3);
 415                 p += sprintf(p, "Prefetch Count: %d \t \t \t \t %d\n",
 416                              reg2, reg3);
 417         }
 418
 419         p = get_masters_info(p);
 420         p = get_slaves_info(p);
 421
 422         len = (p - buffer) - offset;
 423         *addr = buffer + offset;
 424
 425         return len > count ? count : len;
 426 }
 427 #endif /* defined(DISPLAY_SIS_TIMINGS) && defined(CONFIG_PROC_FS) */
 428
 429 static u8 sis5513_ratemask (ide_drive_t *drive)
 430 {
 431         u8 rates[] = { 0, 0, 1, 2, 3, 3, 4, 4 };
 432         u8 mode = rates[chipset_family];
 433
 434         if (!eighty_ninty_three(drive))
 435                 mode = min(mode, (u8)1);
 436         return mode;
 437 }
 438
 439 /*
 440  * Configuration functions
 441  */
 442 /* Enables per-drive prefetch and postwrite */
 443 static void config_drive_art_rwp (ide_drive_t *drive)
 444 {
 445         ide_hwif_t *hwif        = HWIF(drive);
 446         struct pci_dev *dev     = hwif->pci_dev;
 447
 448         u8 reg4bh               = 0;
 449         u8 rw_prefetch          = (0x11 << drive->dn);
 450
 451         if (drive->media != ide_disk)
 452                 return;
 453         pci_read_config_byte(dev, 0x4b, &reg4bh);
 454
 455         if ((reg4bh & rw_prefetch) != rw_prefetch)
 456                 pci_write_config_byte(dev, 0x4b, reg4bh|rw_prefetch);
 457 }
 458
 459
 460 /* Set per-drive active and recovery time */
 461 static void config_art_rwp_pio (ide_drive_t *drive, u8 pio)
 462 {
 463         ide_hwif_t *hwif        = HWIF(drive);
 464         struct pci_dev *dev     = hwif->pci_dev;
 465
 466         u8                      timing, drive_pci, test1, test2;
 467
 468         u16 eide_pio_timing[6] = {600, 390, 240, 180, 120, 90};
 469         u16 xfer_pio = drive->id->eide_pio_modes;
 470
 471         config_drive_art_rwp(drive);
 472         pio = ide_get_best_pio_mode(drive, 255, pio, NULL);
 473
 474         if (xfer_pio> 4)
 475                 xfer_pio = 0;
 476
 477         if (drive->id->eide_pio_iordy > 0) {
 478                 for (xfer_pio = 5;
 479                         (xfer_pio > 0) &&
 480                         (drive->id->eide_pio_iordy > eide_pio_timing[xfer_pio]);
 481                         xfer_pio--);
 482         } else {
 483                 xfer_pio = (drive->id->eide_pio_modes & 4) ? 0x05 :
 484                            (drive->id->eide_pio_modes & 2) ? 0x04 :
 485                            (drive->id->eide_pio_modes & 1) ? 0x03 : xfer_pio;
 486         }
 487
 488         timing = (xfer_pio >= pio) ? xfer_pio : pio;
 489
 490         /* In pre ATA_133 case, drives sit at 0x40 + 4*drive->dn */
 491         drive_pci = 0x40;
 492         /* In SiS962 case drives sit at (0x40 or 0x70) + 8*drive->dn) */
 493         if (chipset_family >= ATA_133) {
 494                 u32 reg54h;
 495                 pci_read_config_dword(dev, 0x54, &reg54h);
 496                 if (reg54h & 0x40000000) drive_pci = 0x70;
 497                 drive_pci += ((drive->dn)*0x4);
 498         } else {
 499                 drive_pci += ((drive->dn)*0x2);
 500         }
 501
 502         /* register layout changed with newer ATA100 chips */
 503         if (chipset_family < ATA_100) {
 504                 pci_read_config_byte(dev, drive_pci, &test1);
 505                 pci_read_config_byte(dev, drive_pci+1, &test2);
 506
 507                 /* Clear active and recovery timings */
 508                 test1 &= ~0x0F;
 509                 test2 &= ~0x07;
 510
 511                 switch(timing) {
 512                         case 4:         test1 |= 0x01; test2 |= 0x03; break;
 513                         case 3:         test1 |= 0x03; test2 |= 0x03; break;
 514                         case 2:         test1 |= 0x04; test2 |= 0x04; break;
 515                         case 1:         test1 |= 0x07; test2 |= 0x06; break;
 516                         default:        break;
 517                 }
 518                 pci_write_config_byte(dev, drive_pci, test1);
 519                 pci_write_config_byte(dev, drive_pci+1, test2);
 520         } else if (chipset_family < ATA_133) {
 521                 switch(timing) { /*             active  recovery
 522                                                   v     v */
 523                         case 4:         test1 = 0x30|0x01; break;
 524                         case 3:         test1 = 0x30|0x03; break;
 525                         case 2:         test1 = 0x40|0x04; break;
 526                         case 1:         test1 = 0x60|0x07; break;
 527                         default:        break;
 528                 }
 529                 pci_write_config_byte(dev, drive_pci, test1);
 530         } else { /* ATA_133 */
 531                 u32 test3;
 532                 pci_read_config_dword(dev, drive_pci, &test3);
 533                 test3 &= 0xc0c00fff;
 534                 if (test3 & 0x08) {
 535                         test3 |= (unsigned long)ini_time_value[ATA_133][timing] << 12;
 536                         test3 |= (unsigned long)act_time_value[ATA_133][timing] << 16;
 537                         test3 |= (unsigned long)rco_time_value[ATA_133][timing] << 24;
 538                 } else {
 539                         test3 |= (unsigned long)ini_time_value[ATA_100][timing] << 12;
 540                         test3 |= (unsigned long)act_time_value[ATA_100][timing] << 16;
 541                         test3 |= (unsigned long)rco_time_value[ATA_100][timing] << 24;
 542                 }
 543                 pci_write_config_dword(dev, drive_pci, test3);
 544         }
 545 }
 546
 547 static int config_chipset_for_pio (ide_drive_t *drive, u8 pio)
 548 {
 549         if (pio == 255)
 550                 pio = ide_find_best_mode(drive, XFER_PIO | XFER_EPIO) - XFER_PIO_0;
 551         config_art_rwp_pio(drive, pio);
 552         return ide_config_drive_speed(drive, XFER_PIO_0 + min_t(u8, pio, 4));
 553 }
 554
 555 static int sis5513_tune_chipset (ide_drive_t *drive, u8 xferspeed)
 556 {
 557         ide_hwif_t *hwif        = HWIF(drive);
 558         struct pci_dev *dev     = hwif->pci_dev;
 559
 560         u8 drive_pci, reg, speed;
 561         u32 regdw;
 562
 563         speed = ide_rate_filter(sis5513_ratemask(drive), xferspeed);
 564
 565         /* See config_art_rwp_pio for drive pci config registers */
 566         drive_pci = 0x40;
 567         if (chipset_family >= ATA_133) {
 568                 u32 reg54h;
 569                 pci_read_config_dword(dev, 0x54, &reg54h);
 570                 if (reg54h & 0x40000000) drive_pci = 0x70;
 571                 drive_pci += ((drive->dn)*0x4);
 572                 pci_read_config_dword(dev, (unsigned long)drive_pci, &regdw);
 573                 /* Disable UDMA bit for non UDMA modes on UDMA chips */
 574                 if (speed < XFER_UDMA_0) {
 575                         regdw &= 0xfffffffb;
 576                         pci_write_config_dword(dev, (unsigned long)drive_pci, regdw);
 577                 }
 578
 579         } else {
 580                 drive_pci += ((drive->dn)*0x2);
 581                 pci_read_config_byte(dev, drive_pci+1, &reg);
 582                 /* Disable UDMA bit for non UDMA modes on UDMA chips */
 583                 if ((speed < XFER_UDMA_0) && (chipset_family > ATA_16)) {
 584                         reg &= 0x7F;
 585                         pci_write_config_byte(dev, drive_pci+1, reg);
 586                 }
 587         }
 588
 589         /* Config chip for mode */
 590         switch(speed) {
 591                 case XFER_UDMA_6:
 592                 case XFER_UDMA_5:
 593                 case XFER_UDMA_4:
 594                 case XFER_UDMA_3:
 595                 case XFER_UDMA_2:
 596                 case XFER_UDMA_1:
 597                 case XFER_UDMA_0:
 598                         if (chipset_family >= ATA_133) {
 599                                 regdw |= 0x04;
 600                                 regdw &= 0xfffff00f;
 601                                 /* check if ATA133 enable */
 602                                 if (regdw & 0x08) {
 603                                         regdw |= (unsigned long)cycle_time_value[ATA_133][speed-XFER_UDMA_0] << 4;
 604                                         regdw |= (unsigned long)cvs_time_value[ATA_133][speed-XFER_UDMA_0] << 8;
 605                                 } else {
 606                                 /* if ATA133 disable, we should not set speed above UDMA5 */
 607                                         if (speed > XFER_UDMA_5)
 608                                                 speed = XFER_UDMA_5;
 609                                         regdw |= (unsigned long)cycle_time_value[ATA_100][speed-XFER_UDMA_0] << 4;
 610                                         regdw |= (unsigned long)cvs_time_value[ATA_100][speed-XFER_UDMA_0] << 8;
 611                                 }
 612                                 pci_write_config_dword(dev, (unsigned long)drive_pci, regdw);
 613                         } else {
 614                                 /* Force the UDMA bit on if we want to use UDMA */
 615                                 reg |= 0x80;
 616                                 /* clean reg cycle time bits */
 617                                 reg &= ~((0xFF >> (8 - cycle_time_range[chipset_family]))
 618                                          << cycle_time_offset[chipset_family]);
 619                                 /* set reg cycle time bits */
 620                                 reg |= cycle_time_value[chipset_family][speed-XFER_UDMA_0]
 621                                         << cycle_time_offset[chipset_family];
 622                                 pci_write_config_byte(dev, drive_pci+1, reg);
 623                         }
 624                         break;
 625                 case XFER_MW_DMA_2:
 626                 case XFER_MW_DMA_1:
 627                 case XFER_MW_DMA_0:
 628                 case XFER_SW_DMA_2:
 629                 case XFER_SW_DMA_1:
 630                 case XFER_SW_DMA_0:
 631                         break;
 632                 case XFER_PIO_4: return((int) config_chipset_for_pio(drive, 4));
 633                 case XFER_PIO_3: return((int) config_chipset_for_pio(drive, 3));
 634                 case XFER_PIO_2: return((int) config_chipset_for_pio(drive, 2));
 635                 case XFER_PIO_1: return((int) config_chipset_for_pio(drive, 1));
 636                 case XFER_PIO_0:
 637                 default:         return((int) config_chipset_for_pio(drive, 0));
 638         }
 639
 640         return ((int) ide_config_drive_speed(drive, speed));
 641 }
 642
 643 static void sis5513_tune_drive (ide_drive_t *drive, u8 pio)
 644 {
 645         (void) config_chipset_for_pio(drive, pio);
 646 }
 647
 648 /*
 649  * ((id->hw_config & 0x4000|0x2000) && (HWIF(drive)->udma_four))
 650  */
 651 static int config_chipset_for_dma (ide_drive_t *drive)
 652 {
 653         u8 speed        = ide_dma_speed(drive, sis5513_ratemask(drive));
 654
 655 #ifdef DEBUG
 656         printk("SIS5513: config_chipset_for_dma, drive %d, ultra %x\n",
 657                drive->dn, drive->id->dma_ultra);
 658 #endif
 659
 660         if (!(speed))
 661                 return 0;
 662
 663         sis5513_tune_chipset(drive, speed);
 664         return ide_dma_enable(drive);
 665 }
 666
 667 static int sis5513_config_drive_xfer_rate (ide_drive_t *drive)
 668 {
 669         ide_hwif_t *hwif        = HWIF(drive);
 670         struct hd_driveid *id   = drive->id;
 671
 672         drive->init_speed = 0;
 673
 674         if (id && (id->capability & 1) && drive->autodma) {
 675
 676                 if (ide_use_dma(drive)) {
 677                         if (config_chipset_for_dma(drive))
 678                                 return hwif->ide_dma_on(drive);
 679                 }
 680
 681                 goto fast_ata_pio;
 682
 683         } else if ((id->capability & 8) || (id->field_valid & 2)) {
 684 fast_ata_pio:
 685                 sis5513_tune_drive(drive, 5);
 686                 return hwif->ide_dma_off_quietly(drive);
 687         }
 688         /* IORDY not supported */
 689         return 0;
 690 }
 691
 692 /* initiates/aborts (U)DMA read/write operations on a drive. */
 693 static int sis5513_config_xfer_rate (ide_drive_t *drive)
 694 {
 695         config_drive_art_rwp(drive);
 696         config_art_rwp_pio(drive, 5);
 697         return sis5513_config_drive_xfer_rate(drive);
 698 }
 699
 700 /*
 701   Future simpler config_xfer_rate :
 702    When ide_find_best_mode is made bad-drive aware
 703    - remove config_drive_xfer_rate and config_chipset_for_dma,
 704    - replace config_xfer_rate with the following
 705
 706 static int sis5513_config_xfer_rate (ide_drive_t *drive)
 707 {
 708         u16 w80 = HWIF(drive)->udma_four;
 709         u16 speed;
 710
 711         config_drive_art_rwp(drive);
 712         config_art_rwp_pio(drive, 5);
 713
 714         speed = ide_find_best_mode(drive,
 715                 XFER_PIO | XFER_EPIO | XFER_SWDMA | XFER_MWDMA |
 716                 (chipset_family >= ATA_33 ? XFER_UDMA : 0) |
 717                 (w80 && chipset_family >= ATA_66 ? XFER_UDMA_66 : 0) |
 718                 (w80 && chipset_family >= ATA_100a ? XFER_UDMA_100 : 0) |
 719                 (w80 && chipset_family >= ATA_133a ? XFER_UDMA_133 : 0));
 720
 721         sis5513_tune_chipset(drive, speed);
 722
 723         if (drive->autodma && (speed & XFER_MODE) != XFER_PIO)
 724                 return HWIF(drive)->ide_dma_on(drive);
 725         return HWIF(drive)->ide_dma_off_quietly(drive);
 726 }
 727 */
 728
 729 /* Chip detection and general config */
 730 static unsigned int __devinit init_chipset_sis5513 (struct pci_dev *dev, const char *name)
 731 {
 732         struct pci_dev *host;
 733         int i = 0;
 734
 735         chipset_family = 0;
 736
 737         for (i = 0; i < ARRAY_SIZE(SiSHostChipInfo) && !chipset_family; i++) {
 738
 739                 host = pci_find_device(PCI_VENDOR_ID_SI, SiSHostChipInfo[i].host_id, NULL);
 740
 741                 if (!host)
 742                         continue;
 743
 744                 chipset_family = SiSHostChipInfo[i].chipset_family;
 745
 746                 /* Special case for SiS630 : 630S/ET is ATA_100a */
 747                 if (SiSHostChipInfo[i].host_id == PCI_DEVICE_ID_SI_630) {
 748                         u8 hostrev;
 749                         pci_read_config_byte(host, PCI_REVISION_ID, &hostrev);
 750                         if (hostrev >= 0x30)
 751                                 chipset_family = ATA_100a;
 752                 }
 753
 754                 printk(KERN_INFO "SIS5513: %s %s controller\n",
 755                          SiSHostChipInfo[i].name, chipset_capability[chipset_family]);
 756         }
 757
 758         if (!chipset_family) { /* Belongs to pci-quirks */
 759
 760                         u32 idemisc;
 761                         u16 trueid;
 762
 763                         /* Disable ID masking and register remapping */
 764                         pci_read_config_dword(dev, 0x54, &idemisc);
 765                         pci_write_config_dword(dev, 0x54, (idemisc & 0x7fffffff));
 766                         pci_read_config_word(dev, PCI_DEVICE_ID, &trueid);
 767                         pci_write_config_dword(dev, 0x54, idemisc);
 768
 769                         if (trueid == 0x5518) {
 770                                 printk(KERN_INFO "SIS5513: SiS 962/963 MuTIOL IDE UDMA133 controller\n");
 771                                 chipset_family = ATA_133;
 772
 773                                 /* Check for 5513 compability mapping
 774                                  * We must use this, else the port enabled code will fail,
 775                                  * as it expects the enablebits at 0x4a.
 776                                  */
 777                                 if ((idemisc & 0x40000000) == 0) {
 778                                         pci_write_config_dword(dev, 0x54, idemisc | 0x40000000);
 779                                         printk(KERN_INFO "SIS5513: Switching to 5513 register mapping\n");
 780                                 }
 781                         }
 782         }
 783
 784         if (!chipset_family) { /* Belongs to pci-quirks */
 785
 786                         struct pci_dev *lpc_bridge;
 787                         u16 trueid;
 788                         u8 prefctl;
 789                         u8 idecfg;
 790                         u8 sbrev;
 791
 792                         pci_read_config_byte(dev, 0x4a, &idecfg);
 793                         pci_write_config_byte(dev, 0x4a, idecfg | 0x10);
 794                         pci_read_config_word(dev, PCI_DEVICE_ID, &trueid);
 795                         pci_write_config_byte(dev, 0x4a, idecfg);
 796
 797                         if (trueid == 0x5517) { /* SiS 961/961B */
 798
 799                                 lpc_bridge = pci_find_slot(0x00, 0x10); /* Bus 0, Dev 2, Fn 0 */
 800                                 pci_read_config_byte(lpc_bridge, PCI_REVISION_ID, &sbrev);
 801                                 pci_read_config_byte(dev, 0x49, &prefctl);
 802
 803                                 if (sbrev == 0x10 && (prefctl & 0x80)) {
 804                                         printk(KERN_INFO "SIS5513: SiS 961B MuTIOL IDE UDMA133 controller\n");
 805                                         chipset_family = ATA_133a;
 806                                 } else {
 807                                         printk(KERN_INFO "SIS5513: SiS 961 MuTIOL IDE UDMA100 controller\n");
 808                                         chipset_family = ATA_100;
 809                                 }
 810                         }
 811         }
 812
 813         if (!chipset_family)
 814                 return -1;
 815
 816         /* Make general config ops here
 817            1/ tell IDE channels to operate in Compatibility mode only
 818            2/ tell old chips to allow per drive IDE timings */
 819
 820         {
 821                 u8 reg;
 822                 u16 regw;
 823
 824                 switch(chipset_family) {
 825                         case ATA_133:
 826                                 /* SiS962 operation mode */
 827                                 pci_read_config_word(dev, 0x50, &regw);
 828                                 if (regw & 0x08)
 829                                         pci_write_config_word(dev, 0x50, regw&0xfff7);
 830                                 pci_read_config_word(dev, 0x52, &regw);
 831                                 if (regw & 0x08)
 832                                         pci_write_config_word(dev, 0x52, regw&0xfff7);
 833                                 break;
 834                         case ATA_133a:
 835                         case ATA_100:
 836                                 /* Fixup latency */
 837                                 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x80);
 838                                 /* Set compatibility bit */
 839                                 pci_read_config_byte(dev, 0x49, &reg);
 840                                 if (!(reg & 0x01)) {
 841                                         pci_write_config_byte(dev, 0x49, reg|0x01);
 842                                 }
 843                                 break;
 844                         case ATA_100a:
 845                         case ATA_66:
 846                                 /* Fixup latency */
 847                                 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x10);
 848
 849                                 /* On ATA_66 chips the bit was elsewhere */
 850                                 pci_read_config_byte(dev, 0x52, &reg);
 851                                 if (!(reg & 0x04)) {
 852                                         pci_write_config_byte(dev, 0x52, reg|0x04);
 853                                 }
 854                                 break;
 855                         case ATA_33:
 856                                 /* On ATA_33 we didn't have a single bit to set */
 857                                 pci_read_config_byte(dev, 0x09, &reg);
 858                                 if ((reg & 0x0f) != 0x00) {
 859                                         pci_write_config_byte(dev, 0x09, reg&0xf0);
 860                                 }
 861                         case ATA_16:
 862                                 /* force per drive recovery and active timings
 863                                    needed on ATA_33 and below chips */
 864                                 pci_read_config_byte(dev, 0x52, &reg);
 865                                 if (!(reg & 0x08)) {
 866                                         pci_write_config_byte(dev, 0x52, reg|0x08);
 867                                 }
 868                                 break;
 869                 }
 870
 871 #if defined(DISPLAY_SIS_TIMINGS) && defined(CONFIG_PROC_FS)
 872                 if (!sis_proc) {
 873                         sis_proc = 1;
 874                         bmide_dev = dev;
 875                         ide_pci_create_host_proc("sis", sis_get_info);
 876                 }
 877 #endif
 878         }
 879
 880         return 0;
 881 }
 882
 883 static unsigned int __devinit ata66_sis5513 (ide_hwif_t *hwif)
 884 {
 885         u8 ata66 = 0;
 886
 887         if (chipset_family >= ATA_133) {
 888                 u16 regw = 0;
 889                 u16 reg_addr = hwif->channel ? 0x52: 0x50;
 890                 pci_read_config_word(hwif->pci_dev, reg_addr, &regw);
 891                 ata66 = (regw & 0x8000) ? 0 : 1;
 892         } else if (chipset_family >= ATA_66) {
 893                 u8 reg48h = 0;
 894                 u8 mask = hwif->channel ? 0x20 : 0x10;
 895                 pci_read_config_byte(hwif->pci_dev, 0x48, &reg48h);
 896                 ata66 = (reg48h & mask) ? 0 : 1;
 897         }
 898         return ata66;
 899 }
 900
 901 static void __devinit init_hwif_sis5513 (ide_hwif_t *hwif)
 902 {
 903         hwif->autodma = 0;
 904
 905         if (!hwif->irq)
 906                 hwif->irq = hwif->channel ? 15 : 14;
 907
 908         hwif->tuneproc = &sis5513_tune_drive;
 909         hwif->speedproc = &sis5513_tune_chipset;
 910
 911         if (!(hwif->dma_base)) {
 912                 hwif->drives[0].autotune = 1;
 913                 hwif->drives[1].autotune = 1;
 914                 return;
 915         }
 916
 917         hwif->atapi_dma = 1;
 918         hwif->ultra_mask = 0x7f;
 919         hwif->mwdma_mask = 0x07;
 920         hwif->swdma_mask = 0x07;
 921
 922         if (!chipset_family)
 923                 return;
 924
 925         if (!(hwif->udma_four))
 926                 hwif->udma_four = ata66_sis5513(hwif);
 927
 928         if (chipset_family > ATA_16) {
 929                 hwif->ide_dma_check = &sis5513_config_xfer_rate;
 930                 if (!noautodma)
 931                         hwif->autodma = 1;
 932         }
 933         hwif->drives[0].autodma = hwif->autodma;
 934         hwif->drives[1].autodma = hwif->autodma;
 935         return;
 936 }
 937
 938 static ide_pci_device_t sis5513_chipset __devinitdata = {
 939         .name           = "SIS5513",
 940         .init_chipset   = init_chipset_sis5513,
 941         .init_hwif      = init_hwif_sis5513,
 942         .channels       = 2,
 943         .autodma        = NOAUTODMA,
 944         .enablebits     = {{0x4a,0x02,0x02}, {0x4a,0x04,0x04}},
 945         .bootable       = ON_BOARD,
 946 };
 947
 948 static int __devinit sis5513_init_one(struct pci_dev *dev, const struct pci_device_id *id)
 949 {
 950         return ide_setup_pci_device(dev, &sis5513_chipset);
 951 }
 952
 953 static struct pci_device_id sis5513_pci_tbl[] = {
 954         { PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5513, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
 955         { PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5518, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
 956         { 0, },
 957 };
 958 MODULE_DEVICE_TABLE(pci, sis5513_pci_tbl);
 959
 960 static struct pci_driver driver = {
 961         .name           = "SIS_IDE",
 962         .id_table       = sis5513_pci_tbl,
 963         .probe          = sis5513_init_one,
 964 };
 965
 966 static int sis5513_ide_init(void)
 967 {
 968         return ide_pci_register_driver(&driver);
 969 }
 970
 971 module_init(sis5513_ide_init);
 972
 973 MODULE_AUTHOR("Lionel Bouton, L C Chang, Andre Hedrick, Vojtech Pavlik");
 974 MODULE_DESCRIPTION("PCI driver module for SIS IDE");
 975 MODULE_LICENSE("GPL");
 976
 977 /*
 978  * TODO:
 979  *      - CLEANUP
 980  *      - Use drivers/ide/ide-timing.h !
 981  *      - More checks in the config registers (force values instead of
 982  *        relying on the BIOS setting them correctly).
 983  *      - Further optimisations ?
 984  *        . for example ATA66+ regs 0x48 & 0x4A
 985  */