Merge changes from linux-2.6 by hand
[linux-2.6] / arch / ppc / syslib / pci_auto.c
1 /*
2  * arch/ppc/syslib/pci_auto.c
3  *
4  * PCI autoconfiguration library
5  *
6  * Author: Matt Porter <mporter@mvista.com>
7  *
8  * 2001 (c) MontaVista, Software, Inc.  This file is licensed under
9  * the terms of the GNU General Public License version 2.  This program
10  * is licensed "as is" without any warranty of any kind, whether express
11  * or implied.
12  */
13
14 /*
15  * The CardBus support is very preliminary.  Preallocating space is
16  * the way to go but will require some change in card services to
17  * make it useful.  Eventually this will ensure that we can put
18  * multiple CB bridges behind multiple P2P bridges.  For now, at
19  * least it ensures that we place the CB bridge BAR and assigned
20  * initial bus numbers.  I definitely need to do something about
21  * the lack of 16-bit I/O support. -MDP
22  */
23
24 #include <linux/kernel.h>
25 #include <linux/init.h>
26 #include <linux/pci.h>
27
28 #include <asm/pci-bridge.h>
29
30 #define PCIAUTO_IDE_MODE_MASK           0x05
31
32 #undef DEBUG
33
34 #ifdef DEBUG
35 #define DBG(x...) printk(x)
36 #else
37 #define DBG(x...)
38 #endif /* DEBUG */
39
40 static int pciauto_upper_iospc;
41 static int pciauto_upper_memspc;
42
43 void __init pciauto_setup_bars(struct pci_controller *hose,
44                 int current_bus,
45                 int pci_devfn,
46                 int bar_limit)
47 {
48         int bar_response, bar_size, bar_value;
49         int bar, addr_mask;
50         int * upper_limit;
51         int found_mem64 = 0;
52
53         DBG("PCI Autoconfig: Found Bus %d, Device %d, Function %d\n",
54                 current_bus, PCI_SLOT(pci_devfn), PCI_FUNC(pci_devfn) );
55
56         for (bar = PCI_BASE_ADDRESS_0; bar <= bar_limit; bar+=4) {
57                 /* Tickle the BAR and get the response */
58                 early_write_config_dword(hose,
59                                 current_bus,
60                                 pci_devfn,
61                                 bar,
62                                 0xffffffff);
63                 early_read_config_dword(hose,
64                                 current_bus,
65                                 pci_devfn,
66                                 bar,
67                                 &bar_response);
68
69                 /* If BAR is not implemented go to the next BAR */
70                 if (!bar_response)
71                         continue;
72
73                 /* Check the BAR type and set our address mask */
74                 if (bar_response & PCI_BASE_ADDRESS_SPACE) {
75                         addr_mask = PCI_BASE_ADDRESS_IO_MASK;
76                         upper_limit = &pciauto_upper_iospc;
77                         DBG("PCI Autoconfig: BAR 0x%x, I/O, ", bar);
78                 } else {
79                         if ( (bar_response & PCI_BASE_ADDRESS_MEM_TYPE_MASK) ==
80                         PCI_BASE_ADDRESS_MEM_TYPE_64)
81                                 found_mem64 = 1;
82
83                         addr_mask = PCI_BASE_ADDRESS_MEM_MASK;  
84                         upper_limit = &pciauto_upper_memspc;
85                         DBG("PCI Autoconfig: BAR 0x%x, Mem ", bar);
86                 }
87
88                 /* Calculate requested size */
89                 bar_size = ~(bar_response & addr_mask) + 1;
90
91                 /* Allocate a base address */
92                 bar_value = (*upper_limit - bar_size) & ~(bar_size - 1);
93
94                 /* Write it out and update our limit */
95                 early_write_config_dword(hose,
96                                 current_bus,
97                                 pci_devfn,
98                                 bar,
99                                 bar_value);
100
101                 *upper_limit = bar_value;
102
103                 /*
104                  * If we are a 64-bit decoder then increment to the
105                  * upper 32 bits of the bar and force it to locate
106                  * in the lower 4GB of memory.
107                  */
108                 if (found_mem64) {
109                         bar += 4;
110                         early_write_config_dword(hose,
111                                         current_bus,
112                                         pci_devfn,
113                                         bar,
114                                         0x00000000);
115                         found_mem64 = 0;
116                 }
117
118                 DBG("size=0x%x, address=0x%x\n",
119                         bar_size, bar_value);
120         }
121
122 }
123
124 void __init pciauto_prescan_setup_bridge(struct pci_controller *hose,
125                 int current_bus,
126                 int pci_devfn,
127                 int sub_bus,
128                 int *iosave,
129                 int *memsave)
130 {
131         /* Configure bus number registers */
132         early_write_config_byte(hose,
133                         current_bus,
134                         pci_devfn,
135                         PCI_PRIMARY_BUS,
136                         current_bus);
137         early_write_config_byte(hose,
138                         current_bus,
139                         pci_devfn,
140                         PCI_SECONDARY_BUS,
141                         sub_bus + 1);
142         early_write_config_byte(hose,
143                         current_bus,
144                         pci_devfn,
145                         PCI_SUBORDINATE_BUS,
146                         0xff);
147
148         /* Round memory allocator to 1MB boundary */
149         pciauto_upper_memspc &= ~(0x100000 - 1);
150         *memsave = pciauto_upper_memspc;
151
152         /* Round I/O allocator to 4KB boundary */
153         pciauto_upper_iospc &= ~(0x1000 - 1);
154         *iosave = pciauto_upper_iospc;
155
156         /* Set up memory and I/O filter limits, assume 32-bit I/O space */
157         early_write_config_word(hose,
158                         current_bus,
159                         pci_devfn,
160                         PCI_MEMORY_LIMIT,
161                         ((pciauto_upper_memspc - 1) & 0xfff00000) >> 16);
162         early_write_config_byte(hose,
163                         current_bus,
164                         pci_devfn,
165                         PCI_IO_LIMIT,
166                         ((pciauto_upper_iospc - 1) & 0x0000f000) >> 8);
167         early_write_config_word(hose,
168                         current_bus,
169                         pci_devfn,
170                         PCI_IO_LIMIT_UPPER16,
171                         ((pciauto_upper_iospc - 1) & 0xffff0000) >> 16);
172
173         /* Zero upper 32 bits of prefetchable base/limit */
174         early_write_config_dword(hose,
175                         current_bus,
176                         pci_devfn,
177                         PCI_PREF_BASE_UPPER32,
178                         0);
179         early_write_config_dword(hose,
180                         current_bus,
181                         pci_devfn,
182                         PCI_PREF_LIMIT_UPPER32,
183                         0);
184 }
185
186 void __init pciauto_postscan_setup_bridge(struct pci_controller *hose,
187                 int current_bus,
188                 int pci_devfn,
189                 int sub_bus,
190                 int *iosave,
191                 int *memsave)
192 {
193         int cmdstat;
194
195         /* Configure bus number registers */
196         early_write_config_byte(hose,
197                         current_bus,
198                         pci_devfn,
199                         PCI_SUBORDINATE_BUS,
200                         sub_bus);
201
202         /*
203          * Round memory allocator to 1MB boundary.
204          * If no space used, allocate minimum.
205          */
206         pciauto_upper_memspc &= ~(0x100000 - 1);
207         if (*memsave == pciauto_upper_memspc)
208                 pciauto_upper_memspc -= 0x00100000;
209
210         early_write_config_word(hose,
211                         current_bus,
212                         pci_devfn,
213                         PCI_MEMORY_BASE,
214                         pciauto_upper_memspc >> 16);
215
216         /* Allocate 1MB for pre-fretch */
217         early_write_config_word(hose,
218                         current_bus,
219                         pci_devfn,
220                         PCI_PREF_MEMORY_LIMIT,
221                         ((pciauto_upper_memspc - 1) & 0xfff00000) >> 16);
222
223         pciauto_upper_memspc -= 0x100000;
224
225         early_write_config_word(hose,
226                         current_bus,
227                         pci_devfn,
228                         PCI_PREF_MEMORY_BASE,
229                         pciauto_upper_memspc >> 16);
230
231         /* Round I/O allocator to 4KB boundary */
232         pciauto_upper_iospc &= ~(0x1000 - 1);
233         if (*iosave == pciauto_upper_iospc)
234                 pciauto_upper_iospc -= 0x1000;
235
236         early_write_config_byte(hose,
237                         current_bus,
238                         pci_devfn,
239                         PCI_IO_BASE,
240                         (pciauto_upper_iospc & 0x0000f000) >> 8);
241         early_write_config_word(hose,
242                         current_bus,
243                         pci_devfn,
244                         PCI_IO_BASE_UPPER16,
245                         pciauto_upper_iospc >> 16);
246
247         /* Enable memory and I/O accesses, enable bus master */
248         early_read_config_dword(hose,
249                         current_bus,
250                         pci_devfn,
251                         PCI_COMMAND,
252                         &cmdstat);
253         early_write_config_dword(hose,
254                         current_bus,
255                         pci_devfn,
256                         PCI_COMMAND,
257                         cmdstat |
258                         PCI_COMMAND_IO |
259                         PCI_COMMAND_MEMORY |
260                         PCI_COMMAND_MASTER);
261 }
262
263 void __init pciauto_prescan_setup_cardbus_bridge(struct pci_controller *hose,
264                 int current_bus,
265                 int pci_devfn,
266                 int sub_bus,
267                 int *iosave,
268                 int *memsave)
269 {
270         /* Configure bus number registers */
271         early_write_config_byte(hose,
272                         current_bus,
273                         pci_devfn,
274                         PCI_PRIMARY_BUS,
275                         current_bus);
276         early_write_config_byte(hose,
277                         current_bus,
278                         pci_devfn,
279                         PCI_SECONDARY_BUS,
280                         sub_bus + 1);
281         early_write_config_byte(hose,
282                         current_bus,
283                         pci_devfn,
284                         PCI_SUBORDINATE_BUS,
285                         0xff);
286
287         /* Round memory allocator to 4KB boundary */
288         pciauto_upper_memspc &= ~(0x1000 - 1);
289         *memsave = pciauto_upper_memspc;
290
291         /* Round I/O allocator to 4 byte boundary */
292         pciauto_upper_iospc &= ~(0x4 - 1);
293         *iosave = pciauto_upper_iospc;
294
295         /* Set up memory and I/O filter limits, assume 32-bit I/O space */
296         early_write_config_dword(hose,
297                         current_bus,
298                         pci_devfn,
299                         0x20,
300                         pciauto_upper_memspc - 1);
301         early_write_config_dword(hose,
302                         current_bus,
303                         pci_devfn,
304                         0x30,
305                         pciauto_upper_iospc - 1);
306 }
307
308 void __init pciauto_postscan_setup_cardbus_bridge(struct pci_controller *hose,
309                 int current_bus,
310                 int pci_devfn,
311                 int sub_bus,
312                 int *iosave,
313                 int *memsave)
314 {
315         int cmdstat;
316
317         /*
318          * Configure subordinate bus number.  The PCI subsystem
319          * bus scan will renumber buses (reserving three additional
320          * for this PCI<->CardBus bridge for the case where a CardBus
321          * adapter contains a P2P or CB2CB bridge.
322          */
323         early_write_config_byte(hose,
324                         current_bus,
325                         pci_devfn,
326                         PCI_SUBORDINATE_BUS,
327                         sub_bus);
328
329         /*
330          * Reserve an additional 4MB for mem space and 16KB for
331          * I/O space.  This should cover any additional space
332          * requirement of unusual CardBus devices with
333          * additional bridges that can consume more address space.
334          *
335          * Although pcmcia-cs currently will reprogram bridge
336          * windows, the goal is to add an option to leave them
337          * alone and use the bridge window ranges as the regions
338          * that are searched for free resources upon hot-insertion
339          * of a device.  This will allow a PCI<->CardBus bridge
340          * configured by this routine to happily live behind a
341          * P2P bridge in a system.
342          */
343         pciauto_upper_memspc -= 0x00400000;
344         pciauto_upper_iospc -= 0x00004000;
345
346         /* Round memory allocator to 4KB boundary */
347         pciauto_upper_memspc &= ~(0x1000 - 1);
348
349         early_write_config_dword(hose,
350                         current_bus,
351                         pci_devfn,
352                         0x1c,
353                         pciauto_upper_memspc);
354
355         /* Round I/O allocator to 4 byte boundary */
356         pciauto_upper_iospc &= ~(0x4 - 1);
357         early_write_config_dword(hose,
358                         current_bus,
359                         pci_devfn,
360                         0x2c,
361                         pciauto_upper_iospc);
362
363         /* Enable memory and I/O accesses, enable bus master */
364         early_read_config_dword(hose,
365                         current_bus,
366                         pci_devfn,
367                         PCI_COMMAND,
368                         &cmdstat);
369         early_write_config_dword(hose,
370                         current_bus,
371                         pci_devfn,
372                         PCI_COMMAND,
373                         cmdstat |
374                         PCI_COMMAND_IO |
375                         PCI_COMMAND_MEMORY |
376                         PCI_COMMAND_MASTER);
377 }
378
379 int __init pciauto_bus_scan(struct pci_controller *hose, int current_bus)
380 {
381         int sub_bus, pci_devfn, pci_class, cmdstat, found_multi = 0;
382         unsigned short vid;
383         unsigned char header_type;
384
385         /*
386          * Fetch our I/O and memory space upper boundaries used
387          * to allocated base addresses on this hose.
388          */
389         if (current_bus == hose->first_busno) {
390                 pciauto_upper_iospc = hose->io_space.end + 1;
391                 pciauto_upper_memspc = hose->mem_space.end + 1;
392         }
393
394         sub_bus = current_bus;
395
396         for (pci_devfn = 0; pci_devfn < 0xff; pci_devfn++) {
397                 /* Skip our host bridge */
398                 if ( (current_bus == hose->first_busno) && (pci_devfn == 0) )
399                         continue;
400
401                 if (PCI_FUNC(pci_devfn) && !found_multi)
402                         continue;
403
404                 /* If config space read fails from this device, move on */
405                 if (early_read_config_byte(hose,
406                                 current_bus,
407                                 pci_devfn,
408                                 PCI_HEADER_TYPE,
409                                 &header_type))
410                         continue;
411
412                 if (!PCI_FUNC(pci_devfn))
413                         found_multi = header_type & 0x80;
414
415                 early_read_config_word(hose,
416                                 current_bus,
417                                 pci_devfn,
418                                 PCI_VENDOR_ID,
419                                 &vid);
420
421                 if (vid != 0xffff) {
422                         early_read_config_dword(hose,
423                                         current_bus,
424                                         pci_devfn,
425                                         PCI_CLASS_REVISION, &pci_class);
426                         if ( (pci_class >> 16) == PCI_CLASS_BRIDGE_PCI ) {
427                                 int iosave, memsave;
428
429                                 DBG("PCI Autoconfig: Found P2P bridge, device %d\n", PCI_SLOT(pci_devfn));
430                                 /* Allocate PCI I/O and/or memory space */
431                                 pciauto_setup_bars(hose,
432                                                 current_bus,
433                                                 pci_devfn,
434                                                 PCI_BASE_ADDRESS_1);
435
436                                 pciauto_prescan_setup_bridge(hose,
437                                                 current_bus,
438                                                 pci_devfn,
439                                                 sub_bus,
440                                                 &iosave,
441                                                 &memsave);
442                                 sub_bus = pciauto_bus_scan(hose, sub_bus+1);
443                                 pciauto_postscan_setup_bridge(hose,
444                                                 current_bus,
445                                                 pci_devfn,
446                                                 sub_bus,
447                                                 &iosave,
448                                                 &memsave);
449                         } else if ((pci_class >> 16) == PCI_CLASS_BRIDGE_CARDBUS) {
450                                 int iosave, memsave;
451
452                                 DBG("PCI Autoconfig: Found CardBus bridge, device %d function %d\n", PCI_SLOT(pci_devfn), PCI_FUNC(pci_devfn));
453                                 /* Place CardBus Socket/ExCA registers */
454                                 pciauto_setup_bars(hose,
455                                                 current_bus,
456                                                 pci_devfn,
457                                                 PCI_BASE_ADDRESS_0);
458
459                                 pciauto_prescan_setup_cardbus_bridge(hose,
460                                                 current_bus,
461                                                 pci_devfn,
462                                                 sub_bus,
463                                                 &iosave,
464                                                 &memsave);
465                                 sub_bus = pciauto_bus_scan(hose, sub_bus+1);
466                                 pciauto_postscan_setup_cardbus_bridge(hose,
467                                                 current_bus,
468                                                 pci_devfn,
469                                                 sub_bus,
470                                                 &iosave,
471                                                 &memsave);
472                         } else {
473                                 if ((pci_class >> 16) == PCI_CLASS_STORAGE_IDE) {
474                                         unsigned char prg_iface;
475
476                                         early_read_config_byte(hose,
477                                                         current_bus,
478                                                         pci_devfn,
479                                                         PCI_CLASS_PROG,
480                                                         &prg_iface);
481                                         if (!(prg_iface & PCIAUTO_IDE_MODE_MASK)) {
482                                                 DBG("PCI Autoconfig: Skipping legacy mode IDE controller\n");
483                                                 continue;
484                                         }
485                                 }
486                                 /* Allocate PCI I/O and/or memory space */
487                                 pciauto_setup_bars(hose,
488                                                 current_bus,
489                                                 pci_devfn,
490                                                 PCI_BASE_ADDRESS_5);
491
492                                 /*
493                                  * Enable some standard settings
494                                  */
495                                 early_read_config_dword(hose,
496                                                 current_bus,
497                                                 pci_devfn,
498                                                 PCI_COMMAND,
499                                                 &cmdstat);
500                                 early_write_config_dword(hose,
501                                                 current_bus,
502                                                 pci_devfn,
503                                                 PCI_COMMAND,
504                                                 cmdstat |
505                                                 PCI_COMMAND_IO |
506                                                 PCI_COMMAND_MEMORY |
507                                                 PCI_COMMAND_MASTER);
508                                 early_write_config_byte(hose,
509                                                 current_bus,
510                                                 pci_devfn,
511                                                 PCI_LATENCY_TIMER,
512                                                 0x80);
513                         }
514                 }
515         }
516         return sub_bus;
517 }