git.oblomov.eu Git - linux-2.6/blob - arch/sparc/mm/srmmu.c

   1 /*
   2  * srmmu.c:  SRMMU specific routines for memory management.
   3  *
   4  * Copyright (C) 1995 David S. Miller  (davem@caip.rutgers.edu)
   5  * Copyright (C) 1995,2002 Pete Zaitcev (zaitcev@yahoo.com)
   6  * Copyright (C) 1996 Eddie C. Dost    (ecd@skynet.be)
   7  * Copyright (C) 1997,1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
   8  * Copyright (C) 1999,2000 Anton Blanchard (anton@samba.org)
   9  */
  10
  11 #include <linux/kernel.h>
  12 #include <linux/mm.h>
  13 #include <linux/slab.h>
  14 #include <linux/vmalloc.h>
  15 #include <linux/pagemap.h>
  16 #include <linux/init.h>
  17 #include <linux/spinlock.h>
  18 #include <linux/bootmem.h>
  19 #include <linux/fs.h>
  20 #include <linux/seq_file.h>
  21 #include <linux/kdebug.h>
  22 #include <linux/log2.h>
  23
  24 #include <asm/bitext.h>
  25 #include <asm/page.h>
  26 #include <asm/pgalloc.h>
  27 #include <asm/pgtable.h>
  28 #include <asm/io.h>
  29 #include <asm/vaddrs.h>
  30 #include <asm/traps.h>
  31 #include <asm/smp.h>
  32 #include <asm/mbus.h>
  33 #include <asm/cache.h>
  34 #include <asm/oplib.h>
  35 #include <asm/asi.h>
  36 #include <asm/msi.h>
  37 #include <asm/mmu_context.h>
  38 #include <asm/io-unit.h>
  39 #include <asm/cacheflush.h>
  40 #include <asm/tlbflush.h>
  41
  42 /* Now the cpu specific definitions. */
  43 #include <asm/viking.h>
  44 #include <asm/mxcc.h>
  45 #include <asm/ross.h>
  46 #include <asm/tsunami.h>
  47 #include <asm/swift.h>
  48 #include <asm/turbosparc.h>
  49
  50 #include <asm/btfixup.h>
  51
  52 enum mbus_module srmmu_modtype;
  53 static unsigned int hwbug_bitmask;
  54 int vac_cache_size;
  55 int vac_line_size;
  56
  57 extern struct resource sparc_iomap;
  58
  59 extern unsigned long last_valid_pfn;
  60
  61 extern unsigned long page_kernel;
  62
  63 static pgd_t *srmmu_swapper_pg_dir;
  64
  65 #ifdef CONFIG_SMP
  66 #define FLUSH_BEGIN(mm)
  67 #define FLUSH_END
  68 #else
  69 #define FLUSH_BEGIN(mm) if((mm)->context != NO_CONTEXT) {
  70 #define FLUSH_END       }
  71 #endif
  72
  73 BTFIXUPDEF_CALL(void, flush_page_for_dma, unsigned long)
  74 #define flush_page_for_dma(page) BTFIXUP_CALL(flush_page_for_dma)(page)
  75
  76 int flush_page_for_dma_global = 1;
  77
  78 #ifdef CONFIG_SMP
  79 BTFIXUPDEF_CALL(void, local_flush_page_for_dma, unsigned long)
  80 #define local_flush_page_for_dma(page) BTFIXUP_CALL(local_flush_page_for_dma)(page)
  81 #endif
  82
  83 char *srmmu_name;
  84
  85 ctxd_t *srmmu_ctx_table_phys;
  86 static ctxd_t *srmmu_context_table;
  87
  88 int viking_mxcc_present;
  89 static DEFINE_SPINLOCK(srmmu_context_spinlock);
  90
  91 static int is_hypersparc;
  92
  93 /*
  94  * In general all page table modifications should use the V8 atomic
  95  * swap instruction.  This insures the mmu and the cpu are in sync
  96  * with respect to ref/mod bits in the page tables.
  97  */
  98 static inline unsigned long srmmu_swap(unsigned long *addr, unsigned long value)
  99 {
 100         __asm__ __volatile__("swap [%2], %0" : "=&r" (value) : "0" (value), "r" (addr));
 101         return value;
 102 }
 103
 104 static inline void srmmu_set_pte(pte_t *ptep, pte_t pteval)
 105 {
 106         srmmu_swap((unsigned long *)ptep, pte_val(pteval));
 107 }
 108
 109 /* The very generic SRMMU page table operations. */
 110 static inline int srmmu_device_memory(unsigned long x)
 111 {
 112         return ((x & 0xF0000000) != 0);
 113 }
 114
 115 static int srmmu_cache_pagetables;
 116
 117 /* these will be initialized in srmmu_nocache_calcsize() */
 118 static unsigned long srmmu_nocache_size;
 119 static unsigned long srmmu_nocache_end;
 120
 121 /* 1 bit <=> 256 bytes of nocache <=> 64 PTEs */
 122 #define SRMMU_NOCACHE_BITMAP_SHIFT (PAGE_SHIFT - 4)
 123
 124 /* The context table is a nocache user with the biggest alignment needs. */
 125 #define SRMMU_NOCACHE_ALIGN_MAX (sizeof(ctxd_t)*SRMMU_MAX_CONTEXTS)
 126
 127 void *srmmu_nocache_pool;
 128 void *srmmu_nocache_bitmap;
 129 static struct bit_map srmmu_nocache_map;
 130
 131 static unsigned long srmmu_pte_pfn(pte_t pte)
 132 {
 133         if (srmmu_device_memory(pte_val(pte))) {
 134                 /* Just return something that will cause
 135                  * pfn_valid() to return false.  This makes
 136                  * copy_one_pte() to just directly copy to
 137                  * PTE over.
 138                  */
 139                 return ~0UL;
 140         }
 141         return (pte_val(pte) & SRMMU_PTE_PMASK) >> (PAGE_SHIFT-4);
 142 }
 143
 144 static struct page *srmmu_pmd_page(pmd_t pmd)
 145 {
 146
 147         if (srmmu_device_memory(pmd_val(pmd)))
 148                 BUG();
 149         return pfn_to_page((pmd_val(pmd) & SRMMU_PTD_PMASK) >> (PAGE_SHIFT-4));
 150 }
 151
 152 static inline unsigned long srmmu_pgd_page(pgd_t pgd)
 153 { return srmmu_device_memory(pgd_val(pgd))?~0:(unsigned long)__nocache_va((pgd_val(pgd) & SRMMU_PTD_PMASK) << 4); }
 154
 155
 156 static inline int srmmu_pte_none(pte_t pte)
 157 { return !(pte_val(pte) & 0xFFFFFFF); }
 158
 159 static inline int srmmu_pte_present(pte_t pte)
 160 { return ((pte_val(pte) & SRMMU_ET_MASK) == SRMMU_ET_PTE); }
 161
 162 static inline void srmmu_pte_clear(pte_t *ptep)
 163 { srmmu_set_pte(ptep, __pte(0)); }
 164
 165 static inline int srmmu_pmd_none(pmd_t pmd)
 166 { return !(pmd_val(pmd) & 0xFFFFFFF); }
 167
 168 static inline int srmmu_pmd_bad(pmd_t pmd)
 169 { return (pmd_val(pmd) & SRMMU_ET_MASK) != SRMMU_ET_PTD; }
 170
 171 static inline int srmmu_pmd_present(pmd_t pmd)
 172 { return ((pmd_val(pmd) & SRMMU_ET_MASK) == SRMMU_ET_PTD); }
 173
 174 static inline void srmmu_pmd_clear(pmd_t *pmdp) {
 175         int i;
 176         for (i = 0; i < PTRS_PER_PTE/SRMMU_REAL_PTRS_PER_PTE; i++)
 177                 srmmu_set_pte((pte_t *)&pmdp->pmdv[i], __pte(0));
 178 }
 179
 180 static inline int srmmu_pgd_none(pgd_t pgd)
 181 { return !(pgd_val(pgd) & 0xFFFFFFF); }
 182
 183 static inline int srmmu_pgd_bad(pgd_t pgd)
 184 { return (pgd_val(pgd) & SRMMU_ET_MASK) != SRMMU_ET_PTD; }
 185
 186 static inline int srmmu_pgd_present(pgd_t pgd)
 187 { return ((pgd_val(pgd) & SRMMU_ET_MASK) == SRMMU_ET_PTD); }
 188
 189 static inline void srmmu_pgd_clear(pgd_t * pgdp)
 190 { srmmu_set_pte((pte_t *)pgdp, __pte(0)); }
 191
 192 static inline pte_t srmmu_pte_wrprotect(pte_t pte)
 193 { return __pte(pte_val(pte) & ~SRMMU_WRITE);}
 194
 195 static inline pte_t srmmu_pte_mkclean(pte_t pte)
 196 { return __pte(pte_val(pte) & ~SRMMU_DIRTY);}
 197
 198 static inline pte_t srmmu_pte_mkold(pte_t pte)
 199 { return __pte(pte_val(pte) & ~SRMMU_REF);}
 200
 201 static inline pte_t srmmu_pte_mkwrite(pte_t pte)
 202 { return __pte(pte_val(pte) | SRMMU_WRITE);}
 203
 204 static inline pte_t srmmu_pte_mkdirty(pte_t pte)
 205 { return __pte(pte_val(pte) | SRMMU_DIRTY);}
 206
 207 static inline pte_t srmmu_pte_mkyoung(pte_t pte)
 208 { return __pte(pte_val(pte) | SRMMU_REF);}
 209
 210 /*
 211  * Conversion functions: convert a page and protection to a page entry,
 212  * and a page entry and page directory to the page they refer to.
 213  */
 214 static pte_t srmmu_mk_pte(struct page *page, pgprot_t pgprot)
 215 { return __pte((page_to_pfn(page) << (PAGE_SHIFT-4)) | pgprot_val(pgprot)); }
 216
 217 static pte_t srmmu_mk_pte_phys(unsigned long page, pgprot_t pgprot)
 218 { return __pte(((page) >> 4) | pgprot_val(pgprot)); }
 219
 220 static pte_t srmmu_mk_pte_io(unsigned long page, pgprot_t pgprot, int space)
 221 { return __pte(((page) >> 4) | (space << 28) | pgprot_val(pgprot)); }
 222
 223 /* XXX should we hyper_flush_whole_icache here - Anton */
 224 static inline void srmmu_ctxd_set(ctxd_t *ctxp, pgd_t *pgdp)
 225 { srmmu_set_pte((pte_t *)ctxp, (SRMMU_ET_PTD | (__nocache_pa((unsigned long) pgdp) >> 4))); }
 226
 227 static inline void srmmu_pgd_set(pgd_t * pgdp, pmd_t * pmdp)
 228 { srmmu_set_pte((pte_t *)pgdp, (SRMMU_ET_PTD | (__nocache_pa((unsigned long) pmdp) >> 4))); }
 229
 230 static void srmmu_pmd_set(pmd_t *pmdp, pte_t *ptep)
 231 {
 232         unsigned long ptp;      /* Physical address, shifted right by 4 */
 233         int i;
 234
 235         ptp = __nocache_pa((unsigned long) ptep) >> 4;
 236         for (i = 0; i < PTRS_PER_PTE/SRMMU_REAL_PTRS_PER_PTE; i++) {
 237                 srmmu_set_pte((pte_t *)&pmdp->pmdv[i], SRMMU_ET_PTD | ptp);
 238                 ptp += (SRMMU_REAL_PTRS_PER_PTE*sizeof(pte_t) >> 4);
 239         }
 240 }
 241
 242 static void srmmu_pmd_populate(pmd_t *pmdp, struct page *ptep)
 243 {
 244         unsigned long ptp;      /* Physical address, shifted right by 4 */
 245         int i;
 246
 247         ptp = page_to_pfn(ptep) << (PAGE_SHIFT-4);      /* watch for overflow */
 248         for (i = 0; i < PTRS_PER_PTE/SRMMU_REAL_PTRS_PER_PTE; i++) {
 249                 srmmu_set_pte((pte_t *)&pmdp->pmdv[i], SRMMU_ET_PTD | ptp);
 250                 ptp += (SRMMU_REAL_PTRS_PER_PTE*sizeof(pte_t) >> 4);
 251         }
 252 }
 253
 254 static inline pte_t srmmu_pte_modify(pte_t pte, pgprot_t newprot)
 255 { return __pte((pte_val(pte) & SRMMU_CHG_MASK) | pgprot_val(newprot)); }
 256
 257 /* to find an entry in a top-level page table... */
 258 static inline pgd_t *srmmu_pgd_offset(struct mm_struct * mm, unsigned long address)
 259 { return mm->pgd + (address >> SRMMU_PGDIR_SHIFT); }
 260
 261 /* Find an entry in the second-level page table.. */
 262 static inline pmd_t *srmmu_pmd_offset(pgd_t * dir, unsigned long address)
 263 {
 264         return (pmd_t *) srmmu_pgd_page(*dir) +
 265             ((address >> PMD_SHIFT) & (PTRS_PER_PMD - 1));
 266 }
 267
 268 /* Find an entry in the third-level page table.. */
 269 static inline pte_t *srmmu_pte_offset(pmd_t * dir, unsigned long address)
 270 {
 271         void *pte;
 272
 273         pte = __nocache_va((dir->pmdv[0] & SRMMU_PTD_PMASK) << 4);
 274         return (pte_t *) pte +
 275             ((address >> PAGE_SHIFT) & (PTRS_PER_PTE - 1));
 276 }
 277
 278 static unsigned long srmmu_swp_type(swp_entry_t entry)
 279 {
 280         return (entry.val >> SRMMU_SWP_TYPE_SHIFT) & SRMMU_SWP_TYPE_MASK;
 281 }
 282
 283 static unsigned long srmmu_swp_offset(swp_entry_t entry)
 284 {
 285         return (entry.val >> SRMMU_SWP_OFF_SHIFT) & SRMMU_SWP_OFF_MASK;
 286 }
 287
 288 static swp_entry_t srmmu_swp_entry(unsigned long type, unsigned long offset)
 289 {
 290         return (swp_entry_t) {
 291                   (type & SRMMU_SWP_TYPE_MASK) << SRMMU_SWP_TYPE_SHIFT
 292                 | (offset & SRMMU_SWP_OFF_MASK) << SRMMU_SWP_OFF_SHIFT };
 293 }
 294
 295 /*
 296  * size: bytes to allocate in the nocache area.
 297  * align: bytes, number to align at.
 298  * Returns the virtual address of the allocated area.
 299  */
 300 static unsigned long __srmmu_get_nocache(int size, int align)
 301 {
 302         int offset;
 303
 304         if (size < SRMMU_NOCACHE_BITMAP_SHIFT) {
 305                 printk("Size 0x%x too small for nocache request\n", size);
 306                 size = SRMMU_NOCACHE_BITMAP_SHIFT;
 307         }
 308         if (size & (SRMMU_NOCACHE_BITMAP_SHIFT-1)) {
 309                 printk("Size 0x%x unaligned int nocache request\n", size);
 310                 size += SRMMU_NOCACHE_BITMAP_SHIFT-1;
 311         }
 312         BUG_ON(align > SRMMU_NOCACHE_ALIGN_MAX);
 313
 314         offset = bit_map_string_get(&srmmu_nocache_map,
 315                                         size >> SRMMU_NOCACHE_BITMAP_SHIFT,
 316                                         align >> SRMMU_NOCACHE_BITMAP_SHIFT);
 317         if (offset == -1) {
 318                 printk("srmmu: out of nocache %d: %d/%d\n",
 319                     size, (int) srmmu_nocache_size,
 320                     srmmu_nocache_map.used << SRMMU_NOCACHE_BITMAP_SHIFT);
 321                 return 0;
 322         }
 323
 324         return (SRMMU_NOCACHE_VADDR + (offset << SRMMU_NOCACHE_BITMAP_SHIFT));
 325 }
 326
 327 static unsigned long srmmu_get_nocache(int size, int align)
 328 {
 329         unsigned long tmp;
 330
 331         tmp = __srmmu_get_nocache(size, align);
 332
 333         if (tmp)
 334                 memset((void *)tmp, 0, size);
 335
 336         return tmp;
 337 }
 338
 339 static void srmmu_free_nocache(unsigned long vaddr, int size)
 340 {
 341         int offset;
 342
 343         if (vaddr < SRMMU_NOCACHE_VADDR) {
 344                 printk("Vaddr %lx is smaller than nocache base 0x%lx\n",
 345                     vaddr, (unsigned long)SRMMU_NOCACHE_VADDR);
 346                 BUG();
 347         }
 348         if (vaddr+size > srmmu_nocache_end) {
 349                 printk("Vaddr %lx is bigger than nocache end 0x%lx\n",
 350                     vaddr, srmmu_nocache_end);
 351                 BUG();
 352         }
 353         if (!is_power_of_2(size)) {
 354                 printk("Size 0x%x is not a power of 2\n", size);
 355                 BUG();
 356         }
 357         if (size < SRMMU_NOCACHE_BITMAP_SHIFT) {
 358                 printk("Size 0x%x is too small\n", size);
 359                 BUG();
 360         }
 361         if (vaddr & (size-1)) {
 362                 printk("Vaddr %lx is not aligned to size 0x%x\n", vaddr, size);
 363                 BUG();
 364         }
 365
 366         offset = (vaddr - SRMMU_NOCACHE_VADDR) >> SRMMU_NOCACHE_BITMAP_SHIFT;
 367         size = size >> SRMMU_NOCACHE_BITMAP_SHIFT;
 368
 369         bit_map_clear(&srmmu_nocache_map, offset, size);
 370 }
 371
 372 static void srmmu_early_allocate_ptable_skeleton(unsigned long start,
 373                                                  unsigned long end);
 374
 375 extern unsigned long probe_memory(void);        /* in fault.c */
 376
 377 /*
 378  * Reserve nocache dynamically proportionally to the amount of
 379  * system RAM. -- Tomas Szepe <szepe@pinerecords.com>, June 2002
 380  */
 381 static void srmmu_nocache_calcsize(void)
 382 {
 383         unsigned long sysmemavail = probe_memory() / 1024;
 384         int srmmu_nocache_npages;
 385
 386         srmmu_nocache_npages =
 387                 sysmemavail / SRMMU_NOCACHE_ALCRATIO / 1024 * 256;
 388
 389  /* P3 XXX The 4x overuse: corroborated by /proc/meminfo. */
 390         // if (srmmu_nocache_npages < 256) srmmu_nocache_npages = 256;
 391         if (srmmu_nocache_npages < SRMMU_MIN_NOCACHE_PAGES)
 392                 srmmu_nocache_npages = SRMMU_MIN_NOCACHE_PAGES;
 393
 394         /* anything above 1280 blows up */
 395         if (srmmu_nocache_npages > SRMMU_MAX_NOCACHE_PAGES)
 396                 srmmu_nocache_npages = SRMMU_MAX_NOCACHE_PAGES;
 397
 398         srmmu_nocache_size = srmmu_nocache_npages * PAGE_SIZE;
 399         srmmu_nocache_end = SRMMU_NOCACHE_VADDR + srmmu_nocache_size;
 400 }
 401
 402 static void __init srmmu_nocache_init(void)
 403 {
 404         unsigned int bitmap_bits;
 405         pgd_t *pgd;
 406         pmd_t *pmd;
 407         pte_t *pte;
 408         unsigned long paddr, vaddr;
 409         unsigned long pteval;
 410
 411         bitmap_bits = srmmu_nocache_size >> SRMMU_NOCACHE_BITMAP_SHIFT;
 412
 413         srmmu_nocache_pool = __alloc_bootmem(srmmu_nocache_size,
 414                 SRMMU_NOCACHE_ALIGN_MAX, 0UL);
 415         memset(srmmu_nocache_pool, 0, srmmu_nocache_size);
 416
 417         srmmu_nocache_bitmap = __alloc_bootmem(bitmap_bits >> 3, SMP_CACHE_BYTES, 0UL);
 418         bit_map_init(&srmmu_nocache_map, srmmu_nocache_bitmap, bitmap_bits);
 419
 420         srmmu_swapper_pg_dir = (pgd_t *)__srmmu_get_nocache(SRMMU_PGD_TABLE_SIZE, SRMMU_PGD_TABLE_SIZE);
 421         memset(__nocache_fix(srmmu_swapper_pg_dir), 0, SRMMU_PGD_TABLE_SIZE);
 422         init_mm.pgd = srmmu_swapper_pg_dir;
 423
 424         srmmu_early_allocate_ptable_skeleton(SRMMU_NOCACHE_VADDR, srmmu_nocache_end);
 425
 426         paddr = __pa((unsigned long)srmmu_nocache_pool);
 427         vaddr = SRMMU_NOCACHE_VADDR;
 428
 429         while (vaddr < srmmu_nocache_end) {
 430                 pgd = pgd_offset_k(vaddr);
 431                 pmd = srmmu_pmd_offset(__nocache_fix(pgd), vaddr);
 432                 pte = srmmu_pte_offset(__nocache_fix(pmd), vaddr);
 433
 434                 pteval = ((paddr >> 4) | SRMMU_ET_PTE | SRMMU_PRIV);
 435
 436                 if (srmmu_cache_pagetables)
 437                         pteval |= SRMMU_CACHE;
 438
 439                 srmmu_set_pte(__nocache_fix(pte), __pte(pteval));
 440
 441                 vaddr += PAGE_SIZE;
 442                 paddr += PAGE_SIZE;
 443         }
 444
 445         flush_cache_all();
 446         flush_tlb_all();
 447 }
 448
 449 static inline pgd_t *srmmu_get_pgd_fast(void)
 450 {
 451         pgd_t *pgd = NULL;
 452
 453         pgd = (pgd_t *)__srmmu_get_nocache(SRMMU_PGD_TABLE_SIZE, SRMMU_PGD_TABLE_SIZE);
 454         if (pgd) {
 455                 pgd_t *init = pgd_offset_k(0);
 456                 memset(pgd, 0, USER_PTRS_PER_PGD * sizeof(pgd_t));
 457                 memcpy(pgd + USER_PTRS_PER_PGD, init + USER_PTRS_PER_PGD,
 458                                                 (PTRS_PER_PGD - USER_PTRS_PER_PGD) * sizeof(pgd_t));
 459         }
 460
 461         return pgd;
 462 }
 463
 464 static void srmmu_free_pgd_fast(pgd_t *pgd)
 465 {
 466         srmmu_free_nocache((unsigned long)pgd, SRMMU_PGD_TABLE_SIZE);
 467 }
 468
 469 static pmd_t *srmmu_pmd_alloc_one(struct mm_struct *mm, unsigned long address)
 470 {
 471         return (pmd_t *)srmmu_get_nocache(SRMMU_PMD_TABLE_SIZE, SRMMU_PMD_TABLE_SIZE);
 472 }
 473
 474 static void srmmu_pmd_free(pmd_t * pmd)
 475 {
 476         srmmu_free_nocache((unsigned long)pmd, SRMMU_PMD_TABLE_SIZE);
 477 }
 478
 479 /*
 480  * Hardware needs alignment to 256 only, but we align to whole page size
 481  * to reduce fragmentation problems due to the buddy principle.
 482  * XXX Provide actual fragmentation statistics in /proc.
 483  *
 484  * Alignments up to the page size are the same for physical and virtual
 485  * addresses of the nocache area.
 486  */
 487 static pte_t *
 488 srmmu_pte_alloc_one_kernel(struct mm_struct *mm, unsigned long address)
 489 {
 490         return (pte_t *)srmmu_get_nocache(PTE_SIZE, PTE_SIZE);
 491 }
 492
 493 static pgtable_t
 494 srmmu_pte_alloc_one(struct mm_struct *mm, unsigned long address)
 495 {
 496         unsigned long pte;
 497         struct page *page;
 498
 499         if ((pte = (unsigned long)srmmu_pte_alloc_one_kernel(mm, address)) == 0)
 500                 return NULL;
 501         page = pfn_to_page( __nocache_pa(pte) >> PAGE_SHIFT );
 502         pgtable_page_ctor(page);
 503         return page;
 504 }
 505
 506 static void srmmu_free_pte_fast(pte_t *pte)
 507 {
 508         srmmu_free_nocache((unsigned long)pte, PTE_SIZE);
 509 }
 510
 511 static void srmmu_pte_free(pgtable_t pte)
 512 {
 513         unsigned long p;
 514
 515         pgtable_page_dtor(pte);
 516         p = (unsigned long)page_address(pte);   /* Cached address (for test) */
 517         if (p == 0)
 518                 BUG();
 519         p = page_to_pfn(pte) << PAGE_SHIFT;     /* Physical address */
 520         p = (unsigned long) __nocache_va(p);    /* Nocached virtual */
 521         srmmu_free_nocache(p, PTE_SIZE);
 522 }
 523
 524 /*
 525  */
 526 static inline void alloc_context(struct mm_struct *old_mm, struct mm_struct *mm)
 527 {
 528         struct ctx_list *ctxp;
 529
 530         ctxp = ctx_free.next;
 531         if(ctxp != &ctx_free) {
 532                 remove_from_ctx_list(ctxp);
 533                 add_to_used_ctxlist(ctxp);
 534                 mm->context = ctxp->ctx_number;
 535                 ctxp->ctx_mm = mm;
 536                 return;
 537         }
 538         ctxp = ctx_used.next;
 539         if(ctxp->ctx_mm == old_mm)
 540                 ctxp = ctxp->next;
 541         if(ctxp == &ctx_used)
 542                 panic("out of mmu contexts");
 543         flush_cache_mm(ctxp->ctx_mm);
 544         flush_tlb_mm(ctxp->ctx_mm);
 545         remove_from_ctx_list(ctxp);
 546         add_to_used_ctxlist(ctxp);
 547         ctxp->ctx_mm->context = NO_CONTEXT;
 548         ctxp->ctx_mm = mm;
 549         mm->context = ctxp->ctx_number;
 550 }
 551
 552 static inline void free_context(int context)
 553 {
 554         struct ctx_list *ctx_old;
 555
 556         ctx_old = ctx_list_pool + context;
 557         remove_from_ctx_list(ctx_old);
 558         add_to_free_ctxlist(ctx_old);
 559 }
 560
 561
 562 static void srmmu_switch_mm(struct mm_struct *old_mm, struct mm_struct *mm,
 563     struct task_struct *tsk, int cpu)
 564 {
 565         if(mm->context == NO_CONTEXT) {
 566                 spin_lock(&srmmu_context_spinlock);
 567                 alloc_context(old_mm, mm);
 568                 spin_unlock(&srmmu_context_spinlock);
 569                 srmmu_ctxd_set(&srmmu_context_table[mm->context], mm->pgd);
 570         }
 571
 572         if (is_hypersparc)
 573                 hyper_flush_whole_icache();
 574
 575         srmmu_set_context(mm->context);
 576 }
 577
 578 /* Low level IO area allocation on the SRMMU. */
 579 static inline void srmmu_mapioaddr(unsigned long physaddr,
 580     unsigned long virt_addr, int bus_type)
 581 {
 582         pgd_t *pgdp;
 583         pmd_t *pmdp;
 584         pte_t *ptep;
 585         unsigned long tmp;
 586
 587         physaddr &= PAGE_MASK;
 588         pgdp = pgd_offset_k(virt_addr);
 589         pmdp = srmmu_pmd_offset(pgdp, virt_addr);
 590         ptep = srmmu_pte_offset(pmdp, virt_addr);
 591         tmp = (physaddr >> 4) | SRMMU_ET_PTE;
 592
 593         /*
 594          * I need to test whether this is consistent over all
 595          * sun4m's.  The bus_type represents the upper 4 bits of
 596          * 36-bit physical address on the I/O space lines...
 597          */
 598         tmp |= (bus_type << 28);
 599         tmp |= SRMMU_PRIV;
 600         __flush_page_to_ram(virt_addr);
 601         srmmu_set_pte(ptep, __pte(tmp));
 602 }
 603
 604 static void srmmu_mapiorange(unsigned int bus, unsigned long xpa,
 605     unsigned long xva, unsigned int len)
 606 {
 607         while (len != 0) {
 608                 len -= PAGE_SIZE;
 609                 srmmu_mapioaddr(xpa, xva, bus);
 610                 xva += PAGE_SIZE;
 611                 xpa += PAGE_SIZE;
 612         }
 613         flush_tlb_all();
 614 }
 615
 616 static inline void srmmu_unmapioaddr(unsigned long virt_addr)
 617 {
 618         pgd_t *pgdp;
 619         pmd_t *pmdp;
 620         pte_t *ptep;
 621
 622         pgdp = pgd_offset_k(virt_addr);
 623         pmdp = srmmu_pmd_offset(pgdp, virt_addr);
 624         ptep = srmmu_pte_offset(pmdp, virt_addr);
 625
 626         /* No need to flush uncacheable page. */
 627         srmmu_pte_clear(ptep);
 628 }
 629
 630 static void srmmu_unmapiorange(unsigned long virt_addr, unsigned int len)
 631 {
 632         while (len != 0) {
 633                 len -= PAGE_SIZE;
 634                 srmmu_unmapioaddr(virt_addr);
 635                 virt_addr += PAGE_SIZE;
 636         }
 637         flush_tlb_all();
 638 }
 639
 640 /*
 641  * On the SRMMU we do not have the problems with limited tlb entries
 642  * for mapping kernel pages, so we just take things from the free page
 643  * pool.  As a side effect we are putting a little too much pressure
 644  * on the gfp() subsystem.  This setup also makes the logic of the
 645  * iommu mapping code a lot easier as we can transparently handle
 646  * mappings on the kernel stack without any special code as we did
 647  * need on the sun4c.
 648  */
 649 static struct thread_info *srmmu_alloc_thread_info(void)
 650 {
 651         struct thread_info *ret;
 652
 653         ret = (struct thread_info *)__get_free_pages(GFP_KERNEL,
 654                                                      THREAD_INFO_ORDER);
 655 #ifdef CONFIG_DEBUG_STACK_USAGE
 656         if (ret)
 657                 memset(ret, 0, PAGE_SIZE << THREAD_INFO_ORDER);
 658 #endif /* DEBUG_STACK_USAGE */
 659
 660         return ret;
 661 }
 662
 663 static void srmmu_free_thread_info(struct thread_info *ti)
 664 {
 665         free_pages((unsigned long)ti, THREAD_INFO_ORDER);
 666 }
 667
 668 /* tsunami.S */
 669 extern void tsunami_flush_cache_all(void);
 670 extern void tsunami_flush_cache_mm(struct mm_struct *mm);
 671 extern void tsunami_flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end);
 672 extern void tsunami_flush_cache_page(struct vm_area_struct *vma, unsigned long page);
 673 extern void tsunami_flush_page_to_ram(unsigned long page);
 674 extern void tsunami_flush_page_for_dma(unsigned long page);
 675 extern void tsunami_flush_sig_insns(struct mm_struct *mm, unsigned long insn_addr);
 676 extern void tsunami_flush_tlb_all(void);
 677 extern void tsunami_flush_tlb_mm(struct mm_struct *mm);
 678 extern void tsunami_flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end);
 679 extern void tsunami_flush_tlb_page(struct vm_area_struct *vma, unsigned long page);
 680 extern void tsunami_setup_blockops(void);
 681
 682 /*
 683  * Workaround, until we find what's going on with Swift. When low on memory,
 684  * it sometimes loops in fault/handle_mm_fault incl. flush_tlb_page to find
 685  * out it is already in page tables/ fault again on the same instruction.
 686  * I really don't understand it, have checked it and contexts
 687  * are right, flush_tlb_all is done as well, and it faults again...
 688  * Strange. -jj
 689  *
 690  * The following code is a deadwood that may be necessary when
 691  * we start to make precise page flushes again. --zaitcev
 692  */
 693 static void swift_update_mmu_cache(struct vm_area_struct * vma, unsigned long address, pte_t pte)
 694 {
 695 #if 0
 696         static unsigned long last;
 697         unsigned int val;
 698         /* unsigned int n; */
 699
 700         if (address == last) {
 701                 val = srmmu_hwprobe(address);
 702                 if (val != 0 && pte_val(pte) != val) {
 703                         printk("swift_update_mmu_cache: "
 704                             "addr %lx put %08x probed %08x from %p\n",
 705                             address, pte_val(pte), val,
 706                             __builtin_return_address(0));
 707                         srmmu_flush_whole_tlb();
 708                 }
 709         }
 710         last = address;
 711 #endif
 712 }
 713
 714 /* swift.S */
 715 extern void swift_flush_cache_all(void);
 716 extern void swift_flush_cache_mm(struct mm_struct *mm);
 717 extern void swift_flush_cache_range(struct vm_area_struct *vma,
 718                                     unsigned long start, unsigned long end);
 719 extern void swift_flush_cache_page(struct vm_area_struct *vma, unsigned long page);
 720 extern void swift_flush_page_to_ram(unsigned long page);
 721 extern void swift_flush_page_for_dma(unsigned long page);
 722 extern void swift_flush_sig_insns(struct mm_struct *mm, unsigned long insn_addr);
 723 extern void swift_flush_tlb_all(void);
 724 extern void swift_flush_tlb_mm(struct mm_struct *mm);
 725 extern void swift_flush_tlb_range(struct vm_area_struct *vma,
 726                                   unsigned long start, unsigned long end);
 727 extern void swift_flush_tlb_page(struct vm_area_struct *vma, unsigned long page);
 728
 729 #if 0  /* P3: deadwood to debug precise flushes on Swift. */
 730 void swift_flush_tlb_page(struct vm_area_struct *vma, unsigned long page)
 731 {
 732         int cctx, ctx1;
 733
 734         page &= PAGE_MASK;
 735         if ((ctx1 = vma->vm_mm->context) != -1) {
 736                 cctx = srmmu_get_context();
 737 /* Is context # ever different from current context? P3 */
 738                 if (cctx != ctx1) {
 739                         printk("flush ctx %02x curr %02x\n", ctx1, cctx);
 740                         srmmu_set_context(ctx1);
 741                         swift_flush_page(page);
 742                         __asm__ __volatile__("sta %%g0, [%0] %1\n\t" : :
 743                                         "r" (page), "i" (ASI_M_FLUSH_PROBE));
 744                         srmmu_set_context(cctx);
 745                 } else {
 746                          /* Rm. prot. bits from virt. c. */
 747                         /* swift_flush_cache_all(); */
 748                         /* swift_flush_cache_page(vma, page); */
 749                         swift_flush_page(page);
 750
 751                         __asm__ __volatile__("sta %%g0, [%0] %1\n\t" : :
 752                                 "r" (page), "i" (ASI_M_FLUSH_PROBE));
 753                         /* same as above: srmmu_flush_tlb_page() */
 754                 }
 755         }
 756 }
 757 #endif
 758
 759 /*
 760  * The following are all MBUS based SRMMU modules, and therefore could
 761  * be found in a multiprocessor configuration.  On the whole, these
 762  * chips seems to be much more touchy about DVMA and page tables
 763  * with respect to cache coherency.
 764  */
 765
 766 /* Cypress flushes. */
 767 static void cypress_flush_cache_all(void)
 768 {
 769         volatile unsigned long cypress_sucks;
 770         unsigned long faddr, tagval;
 771
 772         flush_user_windows();
 773         for(faddr = 0; faddr < 0x10000; faddr += 0x20) {
 774                 __asm__ __volatile__("lda [%1 + %2] %3, %0\n\t" :
 775                                      "=r" (tagval) :
 776                                      "r" (faddr), "r" (0x40000),
 777                                      "i" (ASI_M_DATAC_TAG));
 778
 779                 /* If modified and valid, kick it. */
 780                 if((tagval & 0x60) == 0x60)
 781                         cypress_sucks = *(unsigned long *)(0xf0020000 + faddr);
 782         }
 783 }
 784
 785 static void cypress_flush_cache_mm(struct mm_struct *mm)
 786 {
 787         register unsigned long a, b, c, d, e, f, g;
 788         unsigned long flags, faddr;
 789         int octx;
 790
 791         FLUSH_BEGIN(mm)
 792         flush_user_windows();
 793         local_irq_save(flags);
 794         octx = srmmu_get_context();
 795         srmmu_set_context(mm->context);
 796         a = 0x20; b = 0x40; c = 0x60;
 797         d = 0x80; e = 0xa0; f = 0xc0; g = 0xe0;
 798
 799         faddr = (0x10000 - 0x100);
 800         goto inside;
 801         do {
 802                 faddr -= 0x100;
 803         inside:
 804                 __asm__ __volatile__("sta %%g0, [%0] %1\n\t"
 805                                      "sta %%g0, [%0 + %2] %1\n\t"
 806                                      "sta %%g0, [%0 + %3] %1\n\t"
 807                                      "sta %%g0, [%0 + %4] %1\n\t"
 808                                      "sta %%g0, [%0 + %5] %1\n\t"
 809                                      "sta %%g0, [%0 + %6] %1\n\t"
 810                                      "sta %%g0, [%0 + %7] %1\n\t"
 811                                      "sta %%g0, [%0 + %8] %1\n\t" : :
 812                                      "r" (faddr), "i" (ASI_M_FLUSH_CTX),
 813                                      "r" (a), "r" (b), "r" (c), "r" (d),
 814                                      "r" (e), "r" (f), "r" (g));
 815         } while(faddr);
 816         srmmu_set_context(octx);
 817         local_irq_restore(flags);
 818         FLUSH_END
 819 }
 820
 821 static void cypress_flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end)
 822 {
 823         struct mm_struct *mm = vma->vm_mm;
 824         register unsigned long a, b, c, d, e, f, g;
 825         unsigned long flags, faddr;
 826         int octx;
 827
 828         FLUSH_BEGIN(mm)
 829         flush_user_windows();
 830         local_irq_save(flags);
 831         octx = srmmu_get_context();
 832         srmmu_set_context(mm->context);
 833         a = 0x20; b = 0x40; c = 0x60;
 834         d = 0x80; e = 0xa0; f = 0xc0; g = 0xe0;
 835
 836         start &= SRMMU_REAL_PMD_MASK;
 837         while(start < end) {
 838                 faddr = (start + (0x10000 - 0x100));
 839                 goto inside;
 840                 do {
 841                         faddr -= 0x100;
 842                 inside:
 843                         __asm__ __volatile__("sta %%g0, [%0] %1\n\t"
 844                                              "sta %%g0, [%0 + %2] %1\n\t"
 845                                              "sta %%g0, [%0 + %3] %1\n\t"
 846                                              "sta %%g0, [%0 + %4] %1\n\t"
 847                                              "sta %%g0, [%0 + %5] %1\n\t"
 848                                              "sta %%g0, [%0 + %6] %1\n\t"
 849                                              "sta %%g0, [%0 + %7] %1\n\t"
 850                                              "sta %%g0, [%0 + %8] %1\n\t" : :
 851                                              "r" (faddr),
 852                                              "i" (ASI_M_FLUSH_SEG),
 853                                              "r" (a), "r" (b), "r" (c), "r" (d),
 854                                              "r" (e), "r" (f), "r" (g));
 855                 } while (faddr != start);
 856                 start += SRMMU_REAL_PMD_SIZE;
 857         }
 858         srmmu_set_context(octx);
 859         local_irq_restore(flags);
 860         FLUSH_END
 861 }
 862
 863 static void cypress_flush_cache_page(struct vm_area_struct *vma, unsigned long page)
 864 {
 865         register unsigned long a, b, c, d, e, f, g;
 866         struct mm_struct *mm = vma->vm_mm;
 867         unsigned long flags, line;
 868         int octx;
 869
 870         FLUSH_BEGIN(mm)
 871         flush_user_windows();
 872         local_irq_save(flags);
 873         octx = srmmu_get_context();
 874         srmmu_set_context(mm->context);
 875         a = 0x20; b = 0x40; c = 0x60;
 876         d = 0x80; e = 0xa0; f = 0xc0; g = 0xe0;
 877
 878         page &= PAGE_MASK;
 879         line = (page + PAGE_SIZE) - 0x100;
 880         goto inside;
 881         do {
 882                 line -= 0x100;
 883         inside:
 884                         __asm__ __volatile__("sta %%g0, [%0] %1\n\t"
 885                                              "sta %%g0, [%0 + %2] %1\n\t"
 886                                              "sta %%g0, [%0 + %3] %1\n\t"
 887                                              "sta %%g0, [%0 + %4] %1\n\t"
 888                                              "sta %%g0, [%0 + %5] %1\n\t"
 889                                              "sta %%g0, [%0 + %6] %1\n\t"
 890                                              "sta %%g0, [%0 + %7] %1\n\t"
 891                                              "sta %%g0, [%0 + %8] %1\n\t" : :
 892                                              "r" (line),
 893                                              "i" (ASI_M_FLUSH_PAGE),
 894                                              "r" (a), "r" (b), "r" (c), "r" (d),
 895                                              "r" (e), "r" (f), "r" (g));
 896         } while(line != page);
 897         srmmu_set_context(octx);
 898         local_irq_restore(flags);
 899         FLUSH_END
 900 }
 901
 902 /* Cypress is copy-back, at least that is how we configure it. */
 903 static void cypress_flush_page_to_ram(unsigned long page)
 904 {
 905         register unsigned long a, b, c, d, e, f, g;
 906         unsigned long line;
 907
 908         a = 0x20; b = 0x40; c = 0x60; d = 0x80; e = 0xa0; f = 0xc0; g = 0xe0;
 909         page &= PAGE_MASK;
 910         line = (page + PAGE_SIZE) - 0x100;
 911         goto inside;
 912         do {
 913                 line -= 0x100;
 914         inside:
 915                 __asm__ __volatile__("sta %%g0, [%0] %1\n\t"
 916                                      "sta %%g0, [%0 + %2] %1\n\t"
 917                                      "sta %%g0, [%0 + %3] %1\n\t"
 918                                      "sta %%g0, [%0 + %4] %1\n\t"
 919                                      "sta %%g0, [%0 + %5] %1\n\t"
 920                                      "sta %%g0, [%0 + %6] %1\n\t"
 921                                      "sta %%g0, [%0 + %7] %1\n\t"
 922                                      "sta %%g0, [%0 + %8] %1\n\t" : :
 923                                      "r" (line),
 924                                      "i" (ASI_M_FLUSH_PAGE),
 925                                      "r" (a), "r" (b), "r" (c), "r" (d),
 926                                      "r" (e), "r" (f), "r" (g));
 927         } while(line != page);
 928 }
 929
 930 /* Cypress is also IO cache coherent. */
 931 static void cypress_flush_page_for_dma(unsigned long page)
 932 {
 933 }
 934
 935 /* Cypress has unified L2 VIPT, from which both instructions and data
 936  * are stored.  It does not have an onboard icache of any sort, therefore
 937  * no flush is necessary.
 938  */
 939 static void cypress_flush_sig_insns(struct mm_struct *mm, unsigned long insn_addr)
 940 {
 941 }
 942
 943 static void cypress_flush_tlb_all(void)
 944 {
 945         srmmu_flush_whole_tlb();
 946 }
 947
 948 static void cypress_flush_tlb_mm(struct mm_struct *mm)
 949 {
 950         FLUSH_BEGIN(mm)
 951         __asm__ __volatile__(
 952         "lda    [%0] %3, %%g5\n\t"
 953         "sta    %2, [%0] %3\n\t"
 954         "sta    %%g0, [%1] %4\n\t"
 955         "sta    %%g5, [%0] %3\n"
 956         : /* no outputs */
 957         : "r" (SRMMU_CTX_REG), "r" (0x300), "r" (mm->context),
 958           "i" (ASI_M_MMUREGS), "i" (ASI_M_FLUSH_PROBE)
 959         : "g5");
 960         FLUSH_END
 961 }
 962
 963 static void cypress_flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end)
 964 {
 965         struct mm_struct *mm = vma->vm_mm;
 966         unsigned long size;
 967
 968         FLUSH_BEGIN(mm)
 969         start &= SRMMU_PGDIR_MASK;
 970         size = SRMMU_PGDIR_ALIGN(end) - start;
 971         __asm__ __volatile__(
 972                 "lda    [%0] %5, %%g5\n\t"
 973                 "sta    %1, [%0] %5\n"
 974                 "1:\n\t"
 975                 "subcc  %3, %4, %3\n\t"
 976                 "bne    1b\n\t"
 977                 " sta   %%g0, [%2 + %3] %6\n\t"
 978                 "sta    %%g5, [%0] %5\n"
 979         : /* no outputs */
 980         : "r" (SRMMU_CTX_REG), "r" (mm->context), "r" (start | 0x200),
 981           "r" (size), "r" (SRMMU_PGDIR_SIZE), "i" (ASI_M_MMUREGS),
 982           "i" (ASI_M_FLUSH_PROBE)
 983         : "g5", "cc");
 984         FLUSH_END
 985 }
 986
 987 static void cypress_flush_tlb_page(struct vm_area_struct *vma, unsigned long page)
 988 {
 989         struct mm_struct *mm = vma->vm_mm;
 990
 991         FLUSH_BEGIN(mm)
 992         __asm__ __volatile__(
 993         "lda    [%0] %3, %%g5\n\t"
 994         "sta    %1, [%0] %3\n\t"
 995         "sta    %%g0, [%2] %4\n\t"
 996         "sta    %%g5, [%0] %3\n"
 997         : /* no outputs */
 998         : "r" (SRMMU_CTX_REG), "r" (mm->context), "r" (page & PAGE_MASK),
 999           "i" (ASI_M_MMUREGS), "i" (ASI_M_FLUSH_PROBE)
1000         : "g5");
1001         FLUSH_END
1002 }
1003
1004 /* viking.S */
1005 extern void viking_flush_cache_all(void);
1006 extern void viking_flush_cache_mm(struct mm_struct *mm);
1007 extern void viking_flush_cache_range(struct vm_area_struct *vma, unsigned long start,
1008                                      unsigned long end);
1009 extern void viking_flush_cache_page(struct vm_area_struct *vma, unsigned long page);
1010 extern void viking_flush_page_to_ram(unsigned long page);
1011 extern void viking_flush_page_for_dma(unsigned long page);
1012 extern void viking_flush_sig_insns(struct mm_struct *mm, unsigned long addr);
1013 extern void viking_flush_page(unsigned long page);
1014 extern void viking_mxcc_flush_page(unsigned long page);
1015 extern void viking_flush_tlb_all(void);
1016 extern void viking_flush_tlb_mm(struct mm_struct *mm);
1017 extern void viking_flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
1018                                    unsigned long end);
1019 extern void viking_flush_tlb_page(struct vm_area_struct *vma,
1020                                   unsigned long page);
1021 extern void sun4dsmp_flush_tlb_all(void);
1022 extern void sun4dsmp_flush_tlb_mm(struct mm_struct *mm);
1023 extern void sun4dsmp_flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
1024                                    unsigned long end);
1025 extern void sun4dsmp_flush_tlb_page(struct vm_area_struct *vma,
1026                                   unsigned long page);
1027
1028 /* hypersparc.S */
1029 extern void hypersparc_flush_cache_all(void);
1030 extern void hypersparc_flush_cache_mm(struct mm_struct *mm);
1031 extern void hypersparc_flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end);
1032 extern void hypersparc_flush_cache_page(struct vm_area_struct *vma, unsigned long page);
1033 extern void hypersparc_flush_page_to_ram(unsigned long page);
1034 extern void hypersparc_flush_page_for_dma(unsigned long page);
1035 extern void hypersparc_flush_sig_insns(struct mm_struct *mm, unsigned long insn_addr);
1036 extern void hypersparc_flush_tlb_all(void);
1037 extern void hypersparc_flush_tlb_mm(struct mm_struct *mm);
1038 extern void hypersparc_flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end);
1039 extern void hypersparc_flush_tlb_page(struct vm_area_struct *vma, unsigned long page);
1040 extern void hypersparc_setup_blockops(void);
1041
1042 /*
1043  * NOTE: All of this startup code assumes the low 16mb (approx.) of
1044  *       kernel mappings are done with one single contiguous chunk of
1045  *       ram.  On small ram machines (classics mainly) we only get
1046  *       around 8mb mapped for us.
1047  */
1048
1049 static void __init early_pgtable_allocfail(char *type)
1050 {
1051         prom_printf("inherit_prom_mappings: Cannot alloc kernel %s.\n", type);
1052         prom_halt();
1053 }
1054
1055 static void __init srmmu_early_allocate_ptable_skeleton(unsigned long start,
1056                                                         unsigned long end)
1057 {
1058         pgd_t *pgdp;
1059         pmd_t *pmdp;
1060         pte_t *ptep;
1061
1062         while(start < end) {
1063                 pgdp = pgd_offset_k(start);
1064                 if(srmmu_pgd_none(*(pgd_t *)__nocache_fix(pgdp))) {
1065                         pmdp = (pmd_t *) __srmmu_get_nocache(
1066                             SRMMU_PMD_TABLE_SIZE, SRMMU_PMD_TABLE_SIZE);
1067                         if (pmdp == NULL)
1068                                 early_pgtable_allocfail("pmd");
1069                         memset(__nocache_fix(pmdp), 0, SRMMU_PMD_TABLE_SIZE);
1070                         srmmu_pgd_set(__nocache_fix(pgdp), pmdp);
1071                 }
1072                 pmdp = srmmu_pmd_offset(__nocache_fix(pgdp), start);
1073                 if(srmmu_pmd_none(*(pmd_t *)__nocache_fix(pmdp))) {
1074                         ptep = (pte_t *)__srmmu_get_nocache(PTE_SIZE, PTE_SIZE);
1075                         if (ptep == NULL)
1076                                 early_pgtable_allocfail("pte");
1077                         memset(__nocache_fix(ptep), 0, PTE_SIZE);
1078                         srmmu_pmd_set(__nocache_fix(pmdp), ptep);
1079                 }
1080                 if (start > (0xffffffffUL - PMD_SIZE))
1081                         break;
1082                 start = (start + PMD_SIZE) & PMD_MASK;
1083         }
1084 }
1085
1086 static void __init srmmu_allocate_ptable_skeleton(unsigned long start,
1087                                                   unsigned long end)
1088 {
1089         pgd_t *pgdp;
1090         pmd_t *pmdp;
1091         pte_t *ptep;
1092
1093         while(start < end) {
1094                 pgdp = pgd_offset_k(start);
1095                 if(srmmu_pgd_none(*pgdp)) {
1096                         pmdp = (pmd_t *)__srmmu_get_nocache(SRMMU_PMD_TABLE_SIZE, SRMMU_PMD_TABLE_SIZE);
1097                         if (pmdp == NULL)
1098                                 early_pgtable_allocfail("pmd");
1099                         memset(pmdp, 0, SRMMU_PMD_TABLE_SIZE);
1100                         srmmu_pgd_set(pgdp, pmdp);
1101                 }
1102                 pmdp = srmmu_pmd_offset(pgdp, start);
1103                 if(srmmu_pmd_none(*pmdp)) {
1104                         ptep = (pte_t *) __srmmu_get_nocache(PTE_SIZE,
1105                                                              PTE_SIZE);
1106                         if (ptep == NULL)
1107                                 early_pgtable_allocfail("pte");
1108                         memset(ptep, 0, PTE_SIZE);
1109                         srmmu_pmd_set(pmdp, ptep);
1110                 }
1111                 if (start > (0xffffffffUL - PMD_SIZE))
1112                         break;
1113                 start = (start + PMD_SIZE) & PMD_MASK;
1114         }
1115 }
1116
1117 /*
1118  * This is much cleaner than poking around physical address space
1119  * looking at the prom's page table directly which is what most
1120  * other OS's do.  Yuck... this is much better.
1121  */
1122 static void __init srmmu_inherit_prom_mappings(unsigned long start,
1123                                                unsigned long end)
1124 {
1125         pgd_t *pgdp;
1126         pmd_t *pmdp;
1127         pte_t *ptep;
1128         int what = 0; /* 0 = normal-pte, 1 = pmd-level pte, 2 = pgd-level pte */
1129         unsigned long prompte;
1130
1131         while(start <= end) {
1132                 if (start == 0)
1133                         break; /* probably wrap around */
1134                 if(start == 0xfef00000)
1135                         start = KADB_DEBUGGER_BEGVM;
1136                 if(!(prompte = srmmu_hwprobe(start))) {
1137                         start += PAGE_SIZE;
1138                         continue;
1139                 }
1140
1141                 /* A red snapper, see what it really is. */
1142                 what = 0;
1143
1144                 if(!(start & ~(SRMMU_REAL_PMD_MASK))) {
1145                         if(srmmu_hwprobe((start-PAGE_SIZE) + SRMMU_REAL_PMD_SIZE) == prompte)
1146                                 what = 1;
1147                 }
1148
1149                 if(!(start & ~(SRMMU_PGDIR_MASK))) {
1150                         if(srmmu_hwprobe((start-PAGE_SIZE) + SRMMU_PGDIR_SIZE) ==
1151                            prompte)
1152                                 what = 2;
1153                 }
1154
1155                 pgdp = pgd_offset_k(start);
1156                 if(what == 2) {
1157                         *(pgd_t *)__nocache_fix(pgdp) = __pgd(prompte);
1158                         start += SRMMU_PGDIR_SIZE;
1159                         continue;
1160                 }
1161                 if(srmmu_pgd_none(*(pgd_t *)__nocache_fix(pgdp))) {
1162                         pmdp = (pmd_t *)__srmmu_get_nocache(SRMMU_PMD_TABLE_SIZE, SRMMU_PMD_TABLE_SIZE);
1163                         if (pmdp == NULL)
1164                                 early_pgtable_allocfail("pmd");
1165                         memset(__nocache_fix(pmdp), 0, SRMMU_PMD_TABLE_SIZE);
1166                         srmmu_pgd_set(__nocache_fix(pgdp), pmdp);
1167                 }
1168                 pmdp = srmmu_pmd_offset(__nocache_fix(pgdp), start);
1169                 if(srmmu_pmd_none(*(pmd_t *)__nocache_fix(pmdp))) {
1170                         ptep = (pte_t *) __srmmu_get_nocache(PTE_SIZE,
1171                                                              PTE_SIZE);
1172                         if (ptep == NULL)
1173                                 early_pgtable_allocfail("pte");
1174                         memset(__nocache_fix(ptep), 0, PTE_SIZE);
1175                         srmmu_pmd_set(__nocache_fix(pmdp), ptep);
1176                 }
1177                 if(what == 1) {
1178                         /*
1179                          * We bend the rule where all 16 PTPs in a pmd_t point
1180                          * inside the same PTE page, and we leak a perfectly
1181                          * good hardware PTE piece. Alternatives seem worse.
1182                          */
1183                         unsigned int x; /* Index of HW PMD in soft cluster */
1184                         x = (start >> PMD_SHIFT) & 15;
1185                         *(unsigned long *)__nocache_fix(&pmdp->pmdv[x]) = prompte;
1186                         start += SRMMU_REAL_PMD_SIZE;
1187                         continue;
1188                 }
1189                 ptep = srmmu_pte_offset(__nocache_fix(pmdp), start);
1190                 *(pte_t *)__nocache_fix(ptep) = __pte(prompte);
1191                 start += PAGE_SIZE;
1192         }
1193 }
1194
1195 #define KERNEL_PTE(page_shifted) ((page_shifted)|SRMMU_CACHE|SRMMU_PRIV|SRMMU_VALID)
1196
1197 /* Create a third-level SRMMU 16MB page mapping. */
1198 static void __init do_large_mapping(unsigned long vaddr, unsigned long phys_base)
1199 {
1200         pgd_t *pgdp = pgd_offset_k(vaddr);
1201         unsigned long big_pte;
1202
1203         big_pte = KERNEL_PTE(phys_base >> 4);
1204         *(pgd_t *)__nocache_fix(pgdp) = __pgd(big_pte);
1205 }
1206
1207 /* Map sp_bank entry SP_ENTRY, starting at virtual address VBASE. */
1208 static unsigned long __init map_spbank(unsigned long vbase, int sp_entry)
1209 {
1210         unsigned long pstart = (sp_banks[sp_entry].base_addr & SRMMU_PGDIR_MASK);
1211         unsigned long vstart = (vbase & SRMMU_PGDIR_MASK);
1212         unsigned long vend = SRMMU_PGDIR_ALIGN(vbase + sp_banks[sp_entry].num_bytes);
1213         /* Map "low" memory only */
1214         const unsigned long min_vaddr = PAGE_OFFSET;
1215         const unsigned long max_vaddr = PAGE_OFFSET + SRMMU_MAXMEM;
1216
1217         if (vstart < min_vaddr || vstart >= max_vaddr)
1218                 return vstart;
1219
1220         if (vend > max_vaddr || vend < min_vaddr)
1221                 vend = max_vaddr;
1222
1223         while(vstart < vend) {
1224                 do_large_mapping(vstart, pstart);
1225                 vstart += SRMMU_PGDIR_SIZE; pstart += SRMMU_PGDIR_SIZE;
1226         }
1227         return vstart;
1228 }
1229
1230 static inline void memprobe_error(char *msg)
1231 {
1232         prom_printf(msg);
1233         prom_printf("Halting now...\n");
1234         prom_halt();
1235 }
1236
1237 static inline void map_kernel(void)
1238 {
1239         int i;
1240
1241         if (phys_base > 0) {
1242                 do_large_mapping(PAGE_OFFSET, phys_base);
1243         }
1244
1245         for (i = 0; sp_banks[i].num_bytes != 0; i++) {
1246                 map_spbank((unsigned long)__va(sp_banks[i].base_addr), i);
1247         }
1248
1249         BTFIXUPSET_SIMM13(user_ptrs_per_pgd, PAGE_OFFSET / SRMMU_PGDIR_SIZE);
1250 }
1251
1252 /* Paging initialization on the Sparc Reference MMU. */
1253 extern void sparc_context_init(int);
1254
1255 void (*poke_srmmu)(void) __cpuinitdata = NULL;
1256
1257 extern unsigned long bootmem_init(unsigned long *pages_avail);
1258
1259 void __init srmmu_paging_init(void)
1260 {
1261         int i, cpunode;
1262         char node_str[128];
1263         pgd_t *pgd;
1264         pmd_t *pmd;
1265         pte_t *pte;
1266         unsigned long pages_avail;
1267
1268         sparc_iomap.start = SUN4M_IOBASE_VADDR; /* 16MB of IOSPACE on all sun4m's. */
1269
1270         if (sparc_cpu_model == sun4d)
1271                 num_contexts = 65536; /* We know it is Viking */
1272         else {
1273                 /* Find the number of contexts on the srmmu. */
1274                 cpunode = prom_getchild(prom_root_node);
1275                 num_contexts = 0;
1276                 while(cpunode != 0) {
1277                         prom_getstring(cpunode, "device_type", node_str, sizeof(node_str));
1278                         if(!strcmp(node_str, "cpu")) {
1279                                 num_contexts = prom_getintdefault(cpunode, "mmu-nctx", 0x8);
1280                                 break;
1281                         }
1282                         cpunode = prom_getsibling(cpunode);
1283                 }
1284         }
1285
1286         if(!num_contexts) {
1287                 prom_printf("Something wrong, can't find cpu node in paging_init.\n");
1288                 prom_halt();
1289         }
1290
1291         pages_avail = 0;
1292         last_valid_pfn = bootmem_init(&pages_avail);
1293
1294         srmmu_nocache_calcsize();
1295         srmmu_nocache_init();
1296         srmmu_inherit_prom_mappings(0xfe400000,(LINUX_OPPROM_ENDVM-PAGE_SIZE));
1297         map_kernel();
1298
1299         /* ctx table has to be physically aligned to its size */
1300         srmmu_context_table = (ctxd_t *)__srmmu_get_nocache(num_contexts*sizeof(ctxd_t), num_contexts*sizeof(ctxd_t));
1301         srmmu_ctx_table_phys = (ctxd_t *)__nocache_pa((unsigned long)srmmu_context_table);
1302
1303         for(i = 0; i < num_contexts; i++)
1304                 srmmu_ctxd_set((ctxd_t *)__nocache_fix(&srmmu_context_table[i]), srmmu_swapper_pg_dir);
1305
1306         flush_cache_all();
1307         srmmu_set_ctable_ptr((unsigned long)srmmu_ctx_table_phys);
1308 #ifdef CONFIG_SMP
1309         /* Stop from hanging here... */
1310         local_flush_tlb_all();
1311 #else
1312         flush_tlb_all();
1313 #endif
1314         poke_srmmu();
1315
1316         srmmu_allocate_ptable_skeleton(sparc_iomap.start, IOBASE_END);
1317         srmmu_allocate_ptable_skeleton(DVMA_VADDR, DVMA_END);
1318
1319         srmmu_allocate_ptable_skeleton(
1320                 __fix_to_virt(__end_of_fixed_addresses - 1), FIXADDR_TOP);
1321         srmmu_allocate_ptable_skeleton(PKMAP_BASE, PKMAP_END);
1322
1323         pgd = pgd_offset_k(PKMAP_BASE);
1324         pmd = srmmu_pmd_offset(pgd, PKMAP_BASE);
1325         pte = srmmu_pte_offset(pmd, PKMAP_BASE);
1326         pkmap_page_table = pte;
1327
1328         flush_cache_all();
1329         flush_tlb_all();
1330
1331         sparc_context_init(num_contexts);
1332
1333         kmap_init();
1334
1335         {
1336                 unsigned long zones_size[MAX_NR_ZONES];
1337                 unsigned long zholes_size[MAX_NR_ZONES];
1338                 unsigned long npages;
1339                 int znum;
1340
1341                 for (znum = 0; znum < MAX_NR_ZONES; znum++)
1342                         zones_size[znum] = zholes_size[znum] = 0;
1343
1344                 npages = max_low_pfn - pfn_base;
1345
1346                 zones_size[ZONE_DMA] = npages;
1347                 zholes_size[ZONE_DMA] = npages - pages_avail;
1348
1349                 npages = highend_pfn - max_low_pfn;
1350                 zones_size[ZONE_HIGHMEM] = npages;
1351                 zholes_size[ZONE_HIGHMEM] = npages - calc_highpages();
1352
1353                 free_area_init_node(0, zones_size, pfn_base, zholes_size);
1354         }
1355 }
1356
1357 static void srmmu_mmu_info(struct seq_file *m)
1358 {
1359         seq_printf(m,
1360                    "MMU type\t: %s\n"
1361                    "contexts\t: %d\n"
1362                    "nocache total\t: %ld\n"
1363                    "nocache used\t: %d\n",
1364                    srmmu_name,
1365                    num_contexts,
1366                    srmmu_nocache_size,
1367                    srmmu_nocache_map.used << SRMMU_NOCACHE_BITMAP_SHIFT);
1368 }
1369
1370 static void srmmu_update_mmu_cache(struct vm_area_struct * vma, unsigned long address, pte_t pte)
1371 {
1372 }
1373
1374 static void srmmu_destroy_context(struct mm_struct *mm)
1375 {
1376
1377         if(mm->context != NO_CONTEXT) {
1378                 flush_cache_mm(mm);
1379                 srmmu_ctxd_set(&srmmu_context_table[mm->context], srmmu_swapper_pg_dir);
1380                 flush_tlb_mm(mm);
1381                 spin_lock(&srmmu_context_spinlock);
1382                 free_context(mm->context);
1383                 spin_unlock(&srmmu_context_spinlock);
1384                 mm->context = NO_CONTEXT;
1385         }
1386 }
1387
1388 /* Init various srmmu chip types. */
1389 static void __init srmmu_is_bad(void)
1390 {
1391         prom_printf("Could not determine SRMMU chip type.\n");
1392         prom_halt();
1393 }
1394
1395 static void __init init_vac_layout(void)
1396 {
1397         int nd, cache_lines;
1398         char node_str[128];
1399 #ifdef CONFIG_SMP
1400         int cpu = 0;
1401         unsigned long max_size = 0;
1402         unsigned long min_line_size = 0x10000000;
1403 #endif
1404
1405         nd = prom_getchild(prom_root_node);
1406         while((nd = prom_getsibling(nd)) != 0) {
1407                 prom_getstring(nd, "device_type", node_str, sizeof(node_str));
1408                 if(!strcmp(node_str, "cpu")) {
1409                         vac_line_size = prom_getint(nd, "cache-line-size");
1410                         if (vac_line_size == -1) {
1411                                 prom_printf("can't determine cache-line-size, "
1412                                             "halting.\n");
1413                                 prom_halt();
1414                         }
1415                         cache_lines = prom_getint(nd, "cache-nlines");
1416                         if (cache_lines == -1) {
1417                                 prom_printf("can't determine cache-nlines, halting.\n");
1418                                 prom_halt();
1419                         }
1420
1421                         vac_cache_size = cache_lines * vac_line_size;
1422 #ifdef CONFIG_SMP
1423                         if(vac_cache_size > max_size)
1424                                 max_size = vac_cache_size;
1425                         if(vac_line_size < min_line_size)
1426                                 min_line_size = vac_line_size;
1427                         //FIXME: cpus not contiguous!!
1428                         cpu++;
1429                         if (cpu >= nr_cpu_ids || !cpu_online(cpu))
1430                                 break;
1431 #else
1432                         break;
1433 #endif
1434                 }
1435         }
1436         if(nd == 0) {
1437                 prom_printf("No CPU nodes found, halting.\n");
1438                 prom_halt();
1439         }
1440 #ifdef CONFIG_SMP
1441         vac_cache_size = max_size;
1442         vac_line_size = min_line_size;
1443 #endif
1444         printk("SRMMU: Using VAC size of %d bytes, line size %d bytes.\n",
1445                (int)vac_cache_size, (int)vac_line_size);
1446 }
1447
1448 static void __cpuinit poke_hypersparc(void)
1449 {
1450         volatile unsigned long clear;
1451         unsigned long mreg = srmmu_get_mmureg();
1452
1453         hyper_flush_unconditional_combined();
1454
1455         mreg &= ~(HYPERSPARC_CWENABLE);
1456         mreg |= (HYPERSPARC_CENABLE | HYPERSPARC_WBENABLE);
1457         mreg |= (HYPERSPARC_CMODE);
1458
1459         srmmu_set_mmureg(mreg);
1460
1461 #if 0 /* XXX I think this is bad news... -DaveM */
1462         hyper_clear_all_tags();
1463 #endif
1464
1465         put_ross_icr(HYPERSPARC_ICCR_FTD | HYPERSPARC_ICCR_ICE);
1466         hyper_flush_whole_icache();
1467         clear = srmmu_get_faddr();
1468         clear = srmmu_get_fstatus();
1469 }
1470
1471 static void __init init_hypersparc(void)
1472 {
1473         srmmu_name = "ROSS HyperSparc";
1474         srmmu_modtype = HyperSparc;
1475
1476         init_vac_layout();
1477
1478         is_hypersparc = 1;
1479
1480         BTFIXUPSET_CALL(pte_clear, srmmu_pte_clear, BTFIXUPCALL_NORM);
1481         BTFIXUPSET_CALL(pmd_clear, srmmu_pmd_clear, BTFIXUPCALL_NORM);
1482         BTFIXUPSET_CALL(pgd_clear, srmmu_pgd_clear, BTFIXUPCALL_NORM);
1483         BTFIXUPSET_CALL(flush_cache_all, hypersparc_flush_cache_all, BTFIXUPCALL_NORM);
1484         BTFIXUPSET_CALL(flush_cache_mm, hypersparc_flush_cache_mm, BTFIXUPCALL_NORM);
1485         BTFIXUPSET_CALL(flush_cache_range, hypersparc_flush_cache_range, BTFIXUPCALL_NORM);
1486         BTFIXUPSET_CALL(flush_cache_page, hypersparc_flush_cache_page, BTFIXUPCALL_NORM);
1487
1488         BTFIXUPSET_CALL(flush_tlb_all, hypersparc_flush_tlb_all, BTFIXUPCALL_NORM);
1489         BTFIXUPSET_CALL(flush_tlb_mm, hypersparc_flush_tlb_mm, BTFIXUPCALL_NORM);
1490         BTFIXUPSET_CALL(flush_tlb_range, hypersparc_flush_tlb_range, BTFIXUPCALL_NORM);
1491         BTFIXUPSET_CALL(flush_tlb_page, hypersparc_flush_tlb_page, BTFIXUPCALL_NORM);
1492
1493         BTFIXUPSET_CALL(__flush_page_to_ram, hypersparc_flush_page_to_ram, BTFIXUPCALL_NORM);
1494         BTFIXUPSET_CALL(flush_sig_insns, hypersparc_flush_sig_insns, BTFIXUPCALL_NORM);
1495         BTFIXUPSET_CALL(flush_page_for_dma, hypersparc_flush_page_for_dma, BTFIXUPCALL_NOP);
1496
1497
1498         poke_srmmu = poke_hypersparc;
1499
1500         hypersparc_setup_blockops();
1501 }
1502
1503 static void __cpuinit poke_cypress(void)
1504 {
1505         unsigned long mreg = srmmu_get_mmureg();
1506         unsigned long faddr, tagval;
1507         volatile unsigned long cypress_sucks;
1508         volatile unsigned long clear;
1509
1510         clear = srmmu_get_faddr();
1511         clear = srmmu_get_fstatus();
1512
1513         if (!(mreg & CYPRESS_CENABLE)) {
1514                 for(faddr = 0x0; faddr < 0x10000; faddr += 20) {
1515                         __asm__ __volatile__("sta %%g0, [%0 + %1] %2\n\t"
1516                                              "sta %%g0, [%0] %2\n\t" : :
1517                                              "r" (faddr), "r" (0x40000),
1518                                              "i" (ASI_M_DATAC_TAG));
1519                 }
1520         } else {
1521                 for(faddr = 0; faddr < 0x10000; faddr += 0x20) {
1522                         __asm__ __volatile__("lda [%1 + %2] %3, %0\n\t" :
1523                                              "=r" (tagval) :
1524                                              "r" (faddr), "r" (0x40000),
1525                                              "i" (ASI_M_DATAC_TAG));
1526
1527                         /* If modified and valid, kick it. */
1528                         if((tagval & 0x60) == 0x60)
1529                                 cypress_sucks = *(unsigned long *)
1530                                                         (0xf0020000 + faddr);
1531                 }
1532         }
1533
1534         /* And one more, for our good neighbor, Mr. Broken Cypress. */
1535         clear = srmmu_get_faddr();
1536         clear = srmmu_get_fstatus();
1537
1538         mreg |= (CYPRESS_CENABLE | CYPRESS_CMODE);
1539         srmmu_set_mmureg(mreg);
1540 }
1541
1542 static void __init init_cypress_common(void)
1543 {
1544         init_vac_layout();
1545
1546         BTFIXUPSET_CALL(pte_clear, srmmu_pte_clear, BTFIXUPCALL_NORM);
1547         BTFIXUPSET_CALL(pmd_clear, srmmu_pmd_clear, BTFIXUPCALL_NORM);
1548         BTFIXUPSET_CALL(pgd_clear, srmmu_pgd_clear, BTFIXUPCALL_NORM);
1549         BTFIXUPSET_CALL(flush_cache_all, cypress_flush_cache_all, BTFIXUPCALL_NORM);
1550         BTFIXUPSET_CALL(flush_cache_mm, cypress_flush_cache_mm, BTFIXUPCALL_NORM);
1551         BTFIXUPSET_CALL(flush_cache_range, cypress_flush_cache_range, BTFIXUPCALL_NORM);
1552         BTFIXUPSET_CALL(flush_cache_page, cypress_flush_cache_page, BTFIXUPCALL_NORM);
1553
1554         BTFIXUPSET_CALL(flush_tlb_all, cypress_flush_tlb_all, BTFIXUPCALL_NORM);
1555         BTFIXUPSET_CALL(flush_tlb_mm, cypress_flush_tlb_mm, BTFIXUPCALL_NORM);
1556         BTFIXUPSET_CALL(flush_tlb_page, cypress_flush_tlb_page, BTFIXUPCALL_NORM);
1557         BTFIXUPSET_CALL(flush_tlb_range, cypress_flush_tlb_range, BTFIXUPCALL_NORM);
1558
1559
1560         BTFIXUPSET_CALL(__flush_page_to_ram, cypress_flush_page_to_ram, BTFIXUPCALL_NORM);
1561         BTFIXUPSET_CALL(flush_sig_insns, cypress_flush_sig_insns, BTFIXUPCALL_NOP);
1562         BTFIXUPSET_CALL(flush_page_for_dma, cypress_flush_page_for_dma, BTFIXUPCALL_NOP);
1563
1564         poke_srmmu = poke_cypress;
1565 }
1566
1567 static void __init init_cypress_604(void)
1568 {
1569         srmmu_name = "ROSS Cypress-604(UP)";
1570         srmmu_modtype = Cypress;
1571         init_cypress_common();
1572 }
1573
1574 static void __init init_cypress_605(unsigned long mrev)
1575 {
1576         srmmu_name = "ROSS Cypress-605(MP)";
1577         if(mrev == 0xe) {
1578                 srmmu_modtype = Cypress_vE;
1579                 hwbug_bitmask |= HWBUG_COPYBACK_BROKEN;
1580         } else {
1581                 if(mrev == 0xd) {
1582                         srmmu_modtype = Cypress_vD;
1583                         hwbug_bitmask |= HWBUG_ASIFLUSH_BROKEN;
1584                 } else {
1585                         srmmu_modtype = Cypress;
1586                 }
1587         }
1588         init_cypress_common();
1589 }
1590
1591 static void __cpuinit poke_swift(void)
1592 {
1593         unsigned long mreg;
1594
1595         /* Clear any crap from the cache or else... */
1596         swift_flush_cache_all();
1597
1598         /* Enable I & D caches */
1599         mreg = srmmu_get_mmureg();
1600         mreg |= (SWIFT_IE | SWIFT_DE);
1601         /*
1602          * The Swift branch folding logic is completely broken.  At
1603          * trap time, if things are just right, if can mistakenly
1604          * think that a trap is coming from kernel mode when in fact
1605          * it is coming from user mode (it mis-executes the branch in
1606          * the trap code).  So you see things like crashme completely
1607          * hosing your machine which is completely unacceptable.  Turn
1608          * this shit off... nice job Fujitsu.
1609          */
1610         mreg &= ~(SWIFT_BF);
1611         srmmu_set_mmureg(mreg);
1612 }
1613
1614 #define SWIFT_MASKID_ADDR  0x10003018
1615 static void __init init_swift(void)
1616 {
1617         unsigned long swift_rev;
1618
1619         __asm__ __volatile__("lda [%1] %2, %0\n\t"
1620                              "srl %0, 0x18, %0\n\t" :
1621                              "=r" (swift_rev) :
1622                              "r" (SWIFT_MASKID_ADDR), "i" (ASI_M_BYPASS));
1623         srmmu_name = "Fujitsu Swift";
1624         switch(swift_rev) {
1625         case 0x11:
1626         case 0x20:
1627         case 0x23:
1628         case 0x30:
1629                 srmmu_modtype = Swift_lots_o_bugs;
1630                 hwbug_bitmask |= (HWBUG_KERN_ACCBROKEN | HWBUG_KERN_CBITBROKEN);
1631                 /*
1632                  * Gee george, I wonder why Sun is so hush hush about
1633                  * this hardware bug... really braindamage stuff going
1634                  * on here.  However I think we can find a way to avoid
1635                  * all of the workaround overhead under Linux.  Basically,
1636                  * any page fault can cause kernel pages to become user
1637                  * accessible (the mmu gets confused and clears some of
1638                  * the ACC bits in kernel ptes).  Aha, sounds pretty
1639                  * horrible eh?  But wait, after extensive testing it appears
1640                  * that if you use pgd_t level large kernel pte's (like the
1641                  * 4MB pages on the Pentium) the bug does not get tripped
1642                  * at all.  This avoids almost all of the major overhead.
1643                  * Welcome to a world where your vendor tells you to,
1644                  * "apply this kernel patch" instead of "sorry for the
1645                  * broken hardware, send it back and we'll give you
1646                  * properly functioning parts"
1647                  */
1648                 break;
1649         case 0x25:
1650         case 0x31:
1651                 srmmu_modtype = Swift_bad_c;
1652                 hwbug_bitmask |= HWBUG_KERN_CBITBROKEN;
1653                 /*
1654                  * You see Sun allude to this hardware bug but never
1655                  * admit things directly, they'll say things like,
1656                  * "the Swift chip cache problems" or similar.
1657                  */
1658                 break;
1659         default:
1660                 srmmu_modtype = Swift_ok;
1661                 break;
1662         };
1663
1664         BTFIXUPSET_CALL(flush_cache_all, swift_flush_cache_all, BTFIXUPCALL_NORM);
1665         BTFIXUPSET_CALL(flush_cache_mm, swift_flush_cache_mm, BTFIXUPCALL_NORM);
1666         BTFIXUPSET_CALL(flush_cache_page, swift_flush_cache_page, BTFIXUPCALL_NORM);
1667         BTFIXUPSET_CALL(flush_cache_range, swift_flush_cache_range, BTFIXUPCALL_NORM);
1668
1669
1670         BTFIXUPSET_CALL(flush_tlb_all, swift_flush_tlb_all, BTFIXUPCALL_NORM);
1671         BTFIXUPSET_CALL(flush_tlb_mm, swift_flush_tlb_mm, BTFIXUPCALL_NORM);
1672         BTFIXUPSET_CALL(flush_tlb_page, swift_flush_tlb_page, BTFIXUPCALL_NORM);
1673         BTFIXUPSET_CALL(flush_tlb_range, swift_flush_tlb_range, BTFIXUPCALL_NORM);
1674
1675         BTFIXUPSET_CALL(__flush_page_to_ram, swift_flush_page_to_ram, BTFIXUPCALL_NORM);
1676         BTFIXUPSET_CALL(flush_sig_insns, swift_flush_sig_insns, BTFIXUPCALL_NORM);
1677         BTFIXUPSET_CALL(flush_page_for_dma, swift_flush_page_for_dma, BTFIXUPCALL_NORM);
1678
1679         BTFIXUPSET_CALL(update_mmu_cache, swift_update_mmu_cache, BTFIXUPCALL_NORM);
1680
1681         flush_page_for_dma_global = 0;
1682
1683         /*
1684          * Are you now convinced that the Swift is one of the
1685          * biggest VLSI abortions of all time?  Bravo Fujitsu!
1686          * Fujitsu, the !#?!%$'d up processor people.  I bet if
1687          * you examined the microcode of the Swift you'd find
1688          * XXX's all over the place.
1689          */
1690         poke_srmmu = poke_swift;
1691 }
1692
1693 static void turbosparc_flush_cache_all(void)
1694 {
1695         flush_user_windows();
1696         turbosparc_idflash_clear();
1697 }
1698
1699 static void turbosparc_flush_cache_mm(struct mm_struct *mm)
1700 {
1701         FLUSH_BEGIN(mm)
1702         flush_user_windows();
1703         turbosparc_idflash_clear();
1704         FLUSH_END
1705 }
1706
1707 static void turbosparc_flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end)
1708 {
1709         FLUSH_BEGIN(vma->vm_mm)
1710         flush_user_windows();
1711         turbosparc_idflash_clear();
1712         FLUSH_END
1713 }
1714
1715 static void turbosparc_flush_cache_page(struct vm_area_struct *vma, unsigned long page)
1716 {
1717         FLUSH_BEGIN(vma->vm_mm)
1718         flush_user_windows();
1719         if (vma->vm_flags & VM_EXEC)
1720                 turbosparc_flush_icache();
1721         turbosparc_flush_dcache();
1722         FLUSH_END
1723 }
1724
1725 /* TurboSparc is copy-back, if we turn it on, but this does not work. */
1726 static void turbosparc_flush_page_to_ram(unsigned long page)
1727 {
1728 #ifdef TURBOSPARC_WRITEBACK
1729         volatile unsigned long clear;
1730
1731         if (srmmu_hwprobe(page))
1732                 turbosparc_flush_page_cache(page);
1733         clear = srmmu_get_fstatus();
1734 #endif
1735 }
1736
1737 static void turbosparc_flush_sig_insns(struct mm_struct *mm, unsigned long insn_addr)
1738 {
1739 }
1740
1741 static void turbosparc_flush_page_for_dma(unsigned long page)
1742 {
1743         turbosparc_flush_dcache();
1744 }
1745
1746 static void turbosparc_flush_tlb_all(void)
1747 {
1748         srmmu_flush_whole_tlb();
1749 }
1750
1751 static void turbosparc_flush_tlb_mm(struct mm_struct *mm)
1752 {
1753         FLUSH_BEGIN(mm)
1754         srmmu_flush_whole_tlb();
1755         FLUSH_END
1756 }
1757
1758 static void turbosparc_flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end)
1759 {
1760         FLUSH_BEGIN(vma->vm_mm)
1761         srmmu_flush_whole_tlb();
1762         FLUSH_END
1763 }
1764
1765 static void turbosparc_flush_tlb_page(struct vm_area_struct *vma, unsigned long page)
1766 {
1767         FLUSH_BEGIN(vma->vm_mm)
1768         srmmu_flush_whole_tlb();
1769         FLUSH_END
1770 }
1771
1772
1773 static void __cpuinit poke_turbosparc(void)
1774 {
1775         unsigned long mreg = srmmu_get_mmureg();
1776         unsigned long ccreg;
1777
1778         /* Clear any crap from the cache or else... */
1779         turbosparc_flush_cache_all();
1780         mreg &= ~(TURBOSPARC_ICENABLE | TURBOSPARC_DCENABLE); /* Temporarily disable I & D caches */
1781         mreg &= ~(TURBOSPARC_PCENABLE);         /* Don't check parity */
1782         srmmu_set_mmureg(mreg);
1783
1784         ccreg = turbosparc_get_ccreg();
1785
1786 #ifdef TURBOSPARC_WRITEBACK
1787         ccreg |= (TURBOSPARC_SNENABLE);         /* Do DVMA snooping in Dcache */
1788         ccreg &= ~(TURBOSPARC_uS2 | TURBOSPARC_WTENABLE);
1789                         /* Write-back D-cache, emulate VLSI
1790                          * abortion number three, not number one */
1791 #else
1792         /* For now let's play safe, optimize later */
1793         ccreg |= (TURBOSPARC_SNENABLE | TURBOSPARC_WTENABLE);
1794                         /* Do DVMA snooping in Dcache, Write-thru D-cache */
1795         ccreg &= ~(TURBOSPARC_uS2);
1796                         /* Emulate VLSI abortion number three, not number one */
1797 #endif
1798
1799         switch (ccreg & 7) {
1800         case 0: /* No SE cache */
1801         case 7: /* Test mode */
1802                 break;
1803         default:
1804                 ccreg |= (TURBOSPARC_SCENABLE);
1805         }
1806         turbosparc_set_ccreg (ccreg);
1807
1808         mreg |= (TURBOSPARC_ICENABLE | TURBOSPARC_DCENABLE); /* I & D caches on */
1809         mreg |= (TURBOSPARC_ICSNOOP);           /* Icache snooping on */
1810         srmmu_set_mmureg(mreg);
1811 }
1812
1813 static void __init init_turbosparc(void)
1814 {
1815         srmmu_name = "Fujitsu TurboSparc";
1816         srmmu_modtype = TurboSparc;
1817
1818         BTFIXUPSET_CALL(flush_cache_all, turbosparc_flush_cache_all, BTFIXUPCALL_NORM);
1819         BTFIXUPSET_CALL(flush_cache_mm, turbosparc_flush_cache_mm, BTFIXUPCALL_NORM);
1820         BTFIXUPSET_CALL(flush_cache_page, turbosparc_flush_cache_page, BTFIXUPCALL_NORM);
1821         BTFIXUPSET_CALL(flush_cache_range, turbosparc_flush_cache_range, BTFIXUPCALL_NORM);
1822
1823         BTFIXUPSET_CALL(flush_tlb_all, turbosparc_flush_tlb_all, BTFIXUPCALL_NORM);
1824         BTFIXUPSET_CALL(flush_tlb_mm, turbosparc_flush_tlb_mm, BTFIXUPCALL_NORM);
1825         BTFIXUPSET_CALL(flush_tlb_page, turbosparc_flush_tlb_page, BTFIXUPCALL_NORM);
1826         BTFIXUPSET_CALL(flush_tlb_range, turbosparc_flush_tlb_range, BTFIXUPCALL_NORM);
1827
1828         BTFIXUPSET_CALL(__flush_page_to_ram, turbosparc_flush_page_to_ram, BTFIXUPCALL_NORM);
1829
1830         BTFIXUPSET_CALL(flush_sig_insns, turbosparc_flush_sig_insns, BTFIXUPCALL_NOP);
1831         BTFIXUPSET_CALL(flush_page_for_dma, turbosparc_flush_page_for_dma, BTFIXUPCALL_NORM);
1832
1833         poke_srmmu = poke_turbosparc;
1834 }
1835
1836 static void __cpuinit poke_tsunami(void)
1837 {
1838         unsigned long mreg = srmmu_get_mmureg();
1839
1840         tsunami_flush_icache();
1841         tsunami_flush_dcache();
1842         mreg &= ~TSUNAMI_ITD;
1843         mreg |= (TSUNAMI_IENAB | TSUNAMI_DENAB);
1844         srmmu_set_mmureg(mreg);
1845 }
1846
1847 static void __init init_tsunami(void)
1848 {
1849         /*
1850          * Tsunami's pretty sane, Sun and TI actually got it
1851          * somewhat right this time.  Fujitsu should have
1852          * taken some lessons from them.
1853          */
1854
1855         srmmu_name = "TI Tsunami";
1856         srmmu_modtype = Tsunami;
1857
1858         BTFIXUPSET_CALL(flush_cache_all, tsunami_flush_cache_all, BTFIXUPCALL_NORM);
1859         BTFIXUPSET_CALL(flush_cache_mm, tsunami_flush_cache_mm, BTFIXUPCALL_NORM);
1860         BTFIXUPSET_CALL(flush_cache_page, tsunami_flush_cache_page, BTFIXUPCALL_NORM);
1861         BTFIXUPSET_CALL(flush_cache_range, tsunami_flush_cache_range, BTFIXUPCALL_NORM);
1862
1863
1864         BTFIXUPSET_CALL(flush_tlb_all, tsunami_flush_tlb_all, BTFIXUPCALL_NORM);
1865         BTFIXUPSET_CALL(flush_tlb_mm, tsunami_flush_tlb_mm, BTFIXUPCALL_NORM);
1866         BTFIXUPSET_CALL(flush_tlb_page, tsunami_flush_tlb_page, BTFIXUPCALL_NORM);
1867         BTFIXUPSET_CALL(flush_tlb_range, tsunami_flush_tlb_range, BTFIXUPCALL_NORM);
1868
1869         BTFIXUPSET_CALL(__flush_page_to_ram, tsunami_flush_page_to_ram, BTFIXUPCALL_NOP);
1870         BTFIXUPSET_CALL(flush_sig_insns, tsunami_flush_sig_insns, BTFIXUPCALL_NORM);
1871         BTFIXUPSET_CALL(flush_page_for_dma, tsunami_flush_page_for_dma, BTFIXUPCALL_NORM);
1872
1873         poke_srmmu = poke_tsunami;
1874
1875         tsunami_setup_blockops();
1876 }
1877
1878 static void __cpuinit poke_viking(void)
1879 {
1880         unsigned long mreg = srmmu_get_mmureg();
1881         static int smp_catch;
1882
1883         if(viking_mxcc_present) {
1884                 unsigned long mxcc_control = mxcc_get_creg();
1885
1886                 mxcc_control |= (MXCC_CTL_ECE | MXCC_CTL_PRE | MXCC_CTL_MCE);
1887                 mxcc_control &= ~(MXCC_CTL_RRC);
1888                 mxcc_set_creg(mxcc_control);
1889
1890                 /*
1891                  * We don't need memory parity checks.
1892                  * XXX This is a mess, have to dig out later. ecd.
1893                 viking_mxcc_turn_off_parity(&mreg, &mxcc_control);
1894                  */
1895
1896                 /* We do cache ptables on MXCC. */
1897                 mreg |= VIKING_TCENABLE;
1898         } else {
1899                 unsigned long bpreg;
1900
1901                 mreg &= ~(VIKING_TCENABLE);
1902                 if(smp_catch++) {
1903                         /* Must disable mixed-cmd mode here for other cpu's. */
1904                         bpreg = viking_get_bpreg();
1905                         bpreg &= ~(VIKING_ACTION_MIX);
1906                         viking_set_bpreg(bpreg);
1907
1908                         /* Just in case PROM does something funny. */
1909                         msi_set_sync();
1910                 }
1911         }
1912
1913         mreg |= VIKING_SPENABLE;
1914         mreg |= (VIKING_ICENABLE | VIKING_DCENABLE);
1915         mreg |= VIKING_SBENABLE;
1916         mreg &= ~(VIKING_ACENABLE);
1917         srmmu_set_mmureg(mreg);
1918 }
1919
1920 static void __init init_viking(void)
1921 {
1922         unsigned long mreg = srmmu_get_mmureg();
1923
1924         /* Ahhh, the viking.  SRMMU VLSI abortion number two... */
1925         if(mreg & VIKING_MMODE) {
1926                 srmmu_name = "TI Viking";
1927                 viking_mxcc_present = 0;
1928                 msi_set_sync();
1929
1930                 BTFIXUPSET_CALL(pte_clear, srmmu_pte_clear, BTFIXUPCALL_NORM);
1931                 BTFIXUPSET_CALL(pmd_clear, srmmu_pmd_clear, BTFIXUPCALL_NORM);
1932                 BTFIXUPSET_CALL(pgd_clear, srmmu_pgd_clear, BTFIXUPCALL_NORM);
1933
1934                 /*
1935                  * We need this to make sure old viking takes no hits
1936                  * on it's cache for dma snoops to workaround the
1937                  * "load from non-cacheable memory" interrupt bug.
1938                  * This is only necessary because of the new way in
1939                  * which we use the IOMMU.
1940                  */
1941                 BTFIXUPSET_CALL(flush_page_for_dma, viking_flush_page, BTFIXUPCALL_NORM);
1942
1943                 flush_page_for_dma_global = 0;
1944         } else {
1945                 srmmu_name = "TI Viking/MXCC";
1946                 viking_mxcc_present = 1;
1947
1948                 srmmu_cache_pagetables = 1;
1949
1950                 /* MXCC vikings lack the DMA snooping bug. */
1951                 BTFIXUPSET_CALL(flush_page_for_dma, viking_flush_page_for_dma, BTFIXUPCALL_NOP);
1952         }
1953
1954         BTFIXUPSET_CALL(flush_cache_all, viking_flush_cache_all, BTFIXUPCALL_NORM);
1955         BTFIXUPSET_CALL(flush_cache_mm, viking_flush_cache_mm, BTFIXUPCALL_NORM);
1956         BTFIXUPSET_CALL(flush_cache_page, viking_flush_cache_page, BTFIXUPCALL_NORM);
1957         BTFIXUPSET_CALL(flush_cache_range, viking_flush_cache_range, BTFIXUPCALL_NORM);
1958
1959 #ifdef CONFIG_SMP
1960         if (sparc_cpu_model == sun4d) {
1961                 BTFIXUPSET_CALL(flush_tlb_all, sun4dsmp_flush_tlb_all, BTFIXUPCALL_NORM);
1962                 BTFIXUPSET_CALL(flush_tlb_mm, sun4dsmp_flush_tlb_mm, BTFIXUPCALL_NORM);
1963                 BTFIXUPSET_CALL(flush_tlb_page, sun4dsmp_flush_tlb_page, BTFIXUPCALL_NORM);
1964                 BTFIXUPSET_CALL(flush_tlb_range, sun4dsmp_flush_tlb_range, BTFIXUPCALL_NORM);
1965         } else
1966 #endif
1967         {
1968                 BTFIXUPSET_CALL(flush_tlb_all, viking_flush_tlb_all, BTFIXUPCALL_NORM);
1969                 BTFIXUPSET_CALL(flush_tlb_mm, viking_flush_tlb_mm, BTFIXUPCALL_NORM);
1970                 BTFIXUPSET_CALL(flush_tlb_page, viking_flush_tlb_page, BTFIXUPCALL_NORM);
1971                 BTFIXUPSET_CALL(flush_tlb_range, viking_flush_tlb_range, BTFIXUPCALL_NORM);
1972         }
1973
1974         BTFIXUPSET_CALL(__flush_page_to_ram, viking_flush_page_to_ram, BTFIXUPCALL_NOP);
1975         BTFIXUPSET_CALL(flush_sig_insns, viking_flush_sig_insns, BTFIXUPCALL_NOP);
1976
1977         poke_srmmu = poke_viking;
1978 }
1979
1980 /* Probe for the srmmu chip version. */
1981 static void __init get_srmmu_type(void)
1982 {
1983         unsigned long mreg, psr;
1984         unsigned long mod_typ, mod_rev, psr_typ, psr_vers;
1985
1986         srmmu_modtype = SRMMU_INVAL_MOD;
1987         hwbug_bitmask = 0;
1988
1989         mreg = srmmu_get_mmureg(); psr = get_psr();
1990         mod_typ = (mreg & 0xf0000000) >> 28;
1991         mod_rev = (mreg & 0x0f000000) >> 24;
1992         psr_typ = (psr >> 28) & 0xf;
1993         psr_vers = (psr >> 24) & 0xf;
1994
1995         /* First, check for HyperSparc or Cypress. */
1996         if(mod_typ == 1) {
1997                 switch(mod_rev) {
1998                 case 7:
1999                         /* UP or MP Hypersparc */
2000                         init_hypersparc();
2001                         break;
2002                 case 0:
2003                 case 2:
2004                         /* Uniprocessor Cypress */
2005                         init_cypress_604();
2006                         break;
2007                 case 10:
2008                 case 11:
2009                 case 12:
2010                         /* _REALLY OLD_ Cypress MP chips... */
2011                 case 13:
2012                 case 14:
2013                 case 15:
2014                         /* MP Cypress mmu/cache-controller */
2015                         init_cypress_605(mod_rev);
2016                         break;
2017                 default:
2018                         /* Some other Cypress revision, assume a 605. */
2019                         init_cypress_605(mod_rev);
2020                         break;
2021                 };
2022                 return;
2023         }
2024
2025         /*
2026          * Now Fujitsu TurboSparc. It might happen that it is
2027          * in Swift emulation mode, so we will check later...
2028          */
2029         if (psr_typ == 0 && psr_vers == 5) {
2030                 init_turbosparc();
2031                 return;
2032         }
2033
2034         /* Next check for Fujitsu Swift. */
2035         if(psr_typ == 0 && psr_vers == 4) {
2036                 int cpunode;
2037                 char node_str[128];
2038
2039                 /* Look if it is not a TurboSparc emulating Swift... */
2040                 cpunode = prom_getchild(prom_root_node);
2041                 while((cpunode = prom_getsibling(cpunode)) != 0) {
2042                         prom_getstring(cpunode, "device_type", node_str, sizeof(node_str));
2043                         if(!strcmp(node_str, "cpu")) {
2044                                 if (!prom_getintdefault(cpunode, "psr-implementation", 1) &&
2045                                     prom_getintdefault(cpunode, "psr-version", 1) == 5) {
2046                                         init_turbosparc();
2047                                         return;
2048                                 }
2049                                 break;
2050                         }
2051                 }
2052
2053                 init_swift();
2054                 return;
2055         }
2056
2057         /* Now the Viking family of srmmu. */
2058         if(psr_typ == 4 &&
2059            ((psr_vers == 0) ||
2060             ((psr_vers == 1) && (mod_typ == 0) && (mod_rev == 0)))) {
2061                 init_viking();
2062                 return;
2063         }
2064
2065         /* Finally the Tsunami. */
2066         if(psr_typ == 4 && psr_vers == 1 && (mod_typ || mod_rev)) {
2067                 init_tsunami();
2068                 return;
2069         }
2070
2071         /* Oh well */
2072         srmmu_is_bad();
2073 }
2074
2075 /* don't laugh, static pagetables */
2076 static void srmmu_check_pgt_cache(int low, int high)
2077 {
2078 }
2079
2080 extern unsigned long spwin_mmu_patchme, fwin_mmu_patchme,
2081         tsetup_mmu_patchme, rtrap_mmu_patchme;
2082
2083 extern unsigned long spwin_srmmu_stackchk, srmmu_fwin_stackchk,
2084         tsetup_srmmu_stackchk, srmmu_rett_stackchk;
2085
2086 extern unsigned long srmmu_fault;
2087
2088 #define PATCH_BRANCH(insn, dest) do { \
2089                 iaddr = &(insn); \
2090                 daddr = &(dest); \
2091                 *iaddr = SPARC_BRANCH((unsigned long) daddr, (unsigned long) iaddr); \
2092         } while(0)
2093
2094 static void __init patch_window_trap_handlers(void)
2095 {
2096         unsigned long *iaddr, *daddr;
2097
2098         PATCH_BRANCH(spwin_mmu_patchme, spwin_srmmu_stackchk);
2099         PATCH_BRANCH(fwin_mmu_patchme, srmmu_fwin_stackchk);
2100         PATCH_BRANCH(tsetup_mmu_patchme, tsetup_srmmu_stackchk);
2101         PATCH_BRANCH(rtrap_mmu_patchme, srmmu_rett_stackchk);
2102         PATCH_BRANCH(sparc_ttable[SP_TRAP_TFLT].inst_three, srmmu_fault);
2103         PATCH_BRANCH(sparc_ttable[SP_TRAP_DFLT].inst_three, srmmu_fault);
2104         PATCH_BRANCH(sparc_ttable[SP_TRAP_DACC].inst_three, srmmu_fault);
2105 }
2106
2107 #ifdef CONFIG_SMP
2108 /* Local cross-calls. */
2109 static void smp_flush_page_for_dma(unsigned long page)
2110 {
2111         xc1((smpfunc_t) BTFIXUP_CALL(local_flush_page_for_dma), page);
2112         local_flush_page_for_dma(page);
2113 }
2114
2115 #endif
2116
2117 static pte_t srmmu_pgoff_to_pte(unsigned long pgoff)
2118 {
2119         return __pte((pgoff << SRMMU_PTE_FILE_SHIFT) | SRMMU_FILE);
2120 }
2121
2122 static unsigned long srmmu_pte_to_pgoff(pte_t pte)
2123 {
2124         return pte_val(pte) >> SRMMU_PTE_FILE_SHIFT;
2125 }
2126
2127 static pgprot_t srmmu_pgprot_noncached(pgprot_t prot)
2128 {
2129         prot &= ~__pgprot(SRMMU_CACHE);
2130
2131         return prot;
2132 }
2133
2134 /* Load up routines and constants for sun4m and sun4d mmu */
2135 void __init ld_mmu_srmmu(void)
2136 {
2137         extern void ld_mmu_iommu(void);
2138         extern void ld_mmu_iounit(void);
2139         extern void ___xchg32_sun4md(void);
2140
2141         BTFIXUPSET_SIMM13(pgdir_shift, SRMMU_PGDIR_SHIFT);
2142         BTFIXUPSET_SETHI(pgdir_size, SRMMU_PGDIR_SIZE);
2143         BTFIXUPSET_SETHI(pgdir_mask, SRMMU_PGDIR_MASK);
2144
2145         BTFIXUPSET_SIMM13(ptrs_per_pmd, SRMMU_PTRS_PER_PMD);
2146         BTFIXUPSET_SIMM13(ptrs_per_pgd, SRMMU_PTRS_PER_PGD);
2147
2148         BTFIXUPSET_INT(page_none, pgprot_val(SRMMU_PAGE_NONE));
2149         PAGE_SHARED = pgprot_val(SRMMU_PAGE_SHARED);
2150         BTFIXUPSET_INT(page_copy, pgprot_val(SRMMU_PAGE_COPY));
2151         BTFIXUPSET_INT(page_readonly, pgprot_val(SRMMU_PAGE_RDONLY));
2152         BTFIXUPSET_INT(page_kernel, pgprot_val(SRMMU_PAGE_KERNEL));
2153         page_kernel = pgprot_val(SRMMU_PAGE_KERNEL);
2154
2155         /* Functions */
2156         BTFIXUPSET_CALL(pgprot_noncached, srmmu_pgprot_noncached, BTFIXUPCALL_NORM);
2157 #ifndef CONFIG_SMP
2158         BTFIXUPSET_CALL(___xchg32, ___xchg32_sun4md, BTFIXUPCALL_SWAPG1G2);
2159 #endif
2160         BTFIXUPSET_CALL(do_check_pgt_cache, srmmu_check_pgt_cache, BTFIXUPCALL_NOP);
2161
2162         BTFIXUPSET_CALL(set_pte, srmmu_set_pte, BTFIXUPCALL_SWAPO0O1);
2163         BTFIXUPSET_CALL(switch_mm, srmmu_switch_mm, BTFIXUPCALL_NORM);
2164
2165         BTFIXUPSET_CALL(pte_pfn, srmmu_pte_pfn, BTFIXUPCALL_NORM);
2166         BTFIXUPSET_CALL(pmd_page, srmmu_pmd_page, BTFIXUPCALL_NORM);
2167         BTFIXUPSET_CALL(pgd_page_vaddr, srmmu_pgd_page, BTFIXUPCALL_NORM);
2168
2169         BTFIXUPSET_SETHI(none_mask, 0xF0000000);
2170
2171         BTFIXUPSET_CALL(pte_present, srmmu_pte_present, BTFIXUPCALL_NORM);
2172         BTFIXUPSET_CALL(pte_clear, srmmu_pte_clear, BTFIXUPCALL_SWAPO0G0);
2173
2174         BTFIXUPSET_CALL(pmd_bad, srmmu_pmd_bad, BTFIXUPCALL_NORM);
2175         BTFIXUPSET_CALL(pmd_present, srmmu_pmd_present, BTFIXUPCALL_NORM);
2176         BTFIXUPSET_CALL(pmd_clear, srmmu_pmd_clear, BTFIXUPCALL_SWAPO0G0);
2177
2178         BTFIXUPSET_CALL(pgd_none, srmmu_pgd_none, BTFIXUPCALL_NORM);
2179         BTFIXUPSET_CALL(pgd_bad, srmmu_pgd_bad, BTFIXUPCALL_NORM);
2180         BTFIXUPSET_CALL(pgd_present, srmmu_pgd_present, BTFIXUPCALL_NORM);
2181         BTFIXUPSET_CALL(pgd_clear, srmmu_pgd_clear, BTFIXUPCALL_SWAPO0G0);
2182
2183         BTFIXUPSET_CALL(mk_pte, srmmu_mk_pte, BTFIXUPCALL_NORM);
2184         BTFIXUPSET_CALL(mk_pte_phys, srmmu_mk_pte_phys, BTFIXUPCALL_NORM);
2185         BTFIXUPSET_CALL(mk_pte_io, srmmu_mk_pte_io, BTFIXUPCALL_NORM);
2186         BTFIXUPSET_CALL(pgd_set, srmmu_pgd_set, BTFIXUPCALL_NORM);
2187         BTFIXUPSET_CALL(pmd_set, srmmu_pmd_set, BTFIXUPCALL_NORM);
2188         BTFIXUPSET_CALL(pmd_populate, srmmu_pmd_populate, BTFIXUPCALL_NORM);
2189
2190         BTFIXUPSET_INT(pte_modify_mask, SRMMU_CHG_MASK);
2191         BTFIXUPSET_CALL(pmd_offset, srmmu_pmd_offset, BTFIXUPCALL_NORM);
2192         BTFIXUPSET_CALL(pte_offset_kernel, srmmu_pte_offset, BTFIXUPCALL_NORM);
2193
2194         BTFIXUPSET_CALL(free_pte_fast, srmmu_free_pte_fast, BTFIXUPCALL_NORM);
2195         BTFIXUPSET_CALL(pte_free, srmmu_pte_free, BTFIXUPCALL_NORM);
2196         BTFIXUPSET_CALL(pte_alloc_one_kernel, srmmu_pte_alloc_one_kernel, BTFIXUPCALL_NORM);
2197         BTFIXUPSET_CALL(pte_alloc_one, srmmu_pte_alloc_one, BTFIXUPCALL_NORM);
2198         BTFIXUPSET_CALL(free_pmd_fast, srmmu_pmd_free, BTFIXUPCALL_NORM);
2199         BTFIXUPSET_CALL(pmd_alloc_one, srmmu_pmd_alloc_one, BTFIXUPCALL_NORM);
2200         BTFIXUPSET_CALL(free_pgd_fast, srmmu_free_pgd_fast, BTFIXUPCALL_NORM);
2201         BTFIXUPSET_CALL(get_pgd_fast, srmmu_get_pgd_fast, BTFIXUPCALL_NORM);
2202
2203         BTFIXUPSET_HALF(pte_writei, SRMMU_WRITE);
2204         BTFIXUPSET_HALF(pte_dirtyi, SRMMU_DIRTY);
2205         BTFIXUPSET_HALF(pte_youngi, SRMMU_REF);
2206         BTFIXUPSET_HALF(pte_filei, SRMMU_FILE);
2207         BTFIXUPSET_HALF(pte_wrprotecti, SRMMU_WRITE);
2208         BTFIXUPSET_HALF(pte_mkcleani, SRMMU_DIRTY);
2209         BTFIXUPSET_HALF(pte_mkoldi, SRMMU_REF);
2210         BTFIXUPSET_CALL(pte_mkwrite, srmmu_pte_mkwrite, BTFIXUPCALL_ORINT(SRMMU_WRITE));
2211         BTFIXUPSET_CALL(pte_mkdirty, srmmu_pte_mkdirty, BTFIXUPCALL_ORINT(SRMMU_DIRTY));
2212         BTFIXUPSET_CALL(pte_mkyoung, srmmu_pte_mkyoung, BTFIXUPCALL_ORINT(SRMMU_REF));
2213         BTFIXUPSET_CALL(update_mmu_cache, srmmu_update_mmu_cache, BTFIXUPCALL_NOP);
2214         BTFIXUPSET_CALL(destroy_context, srmmu_destroy_context, BTFIXUPCALL_NORM);
2215
2216         BTFIXUPSET_CALL(sparc_mapiorange, srmmu_mapiorange, BTFIXUPCALL_NORM);
2217         BTFIXUPSET_CALL(sparc_unmapiorange, srmmu_unmapiorange, BTFIXUPCALL_NORM);
2218
2219         BTFIXUPSET_CALL(__swp_type, srmmu_swp_type, BTFIXUPCALL_NORM);
2220         BTFIXUPSET_CALL(__swp_offset, srmmu_swp_offset, BTFIXUPCALL_NORM);
2221         BTFIXUPSET_CALL(__swp_entry, srmmu_swp_entry, BTFIXUPCALL_NORM);
2222
2223         BTFIXUPSET_CALL(mmu_info, srmmu_mmu_info, BTFIXUPCALL_NORM);
2224
2225         BTFIXUPSET_CALL(alloc_thread_info, srmmu_alloc_thread_info, BTFIXUPCALL_NORM);
2226         BTFIXUPSET_CALL(free_thread_info, srmmu_free_thread_info, BTFIXUPCALL_NORM);
2227
2228         BTFIXUPSET_CALL(pte_to_pgoff, srmmu_pte_to_pgoff, BTFIXUPCALL_NORM);
2229         BTFIXUPSET_CALL(pgoff_to_pte, srmmu_pgoff_to_pte, BTFIXUPCALL_NORM);
2230
2231         get_srmmu_type();
2232         patch_window_trap_handlers();
2233
2234 #ifdef CONFIG_SMP
2235         /* El switcheroo... */
2236
2237         BTFIXUPCOPY_CALL(local_flush_cache_all, flush_cache_all);
2238         BTFIXUPCOPY_CALL(local_flush_cache_mm, flush_cache_mm);
2239         BTFIXUPCOPY_CALL(local_flush_cache_range, flush_cache_range);
2240         BTFIXUPCOPY_CALL(local_flush_cache_page, flush_cache_page);
2241         BTFIXUPCOPY_CALL(local_flush_tlb_all, flush_tlb_all);
2242         BTFIXUPCOPY_CALL(local_flush_tlb_mm, flush_tlb_mm);
2243         BTFIXUPCOPY_CALL(local_flush_tlb_range, flush_tlb_range);
2244         BTFIXUPCOPY_CALL(local_flush_tlb_page, flush_tlb_page);
2245         BTFIXUPCOPY_CALL(local_flush_page_to_ram, __flush_page_to_ram);
2246         BTFIXUPCOPY_CALL(local_flush_sig_insns, flush_sig_insns);
2247         BTFIXUPCOPY_CALL(local_flush_page_for_dma, flush_page_for_dma);
2248
2249         BTFIXUPSET_CALL(flush_cache_all, smp_flush_cache_all, BTFIXUPCALL_NORM);
2250         BTFIXUPSET_CALL(flush_cache_mm, smp_flush_cache_mm, BTFIXUPCALL_NORM);
2251         BTFIXUPSET_CALL(flush_cache_range, smp_flush_cache_range, BTFIXUPCALL_NORM);
2252         BTFIXUPSET_CALL(flush_cache_page, smp_flush_cache_page, BTFIXUPCALL_NORM);
2253         if (sparc_cpu_model != sun4d) {
2254                 BTFIXUPSET_CALL(flush_tlb_all, smp_flush_tlb_all, BTFIXUPCALL_NORM);
2255                 BTFIXUPSET_CALL(flush_tlb_mm, smp_flush_tlb_mm, BTFIXUPCALL_NORM);
2256                 BTFIXUPSET_CALL(flush_tlb_range, smp_flush_tlb_range, BTFIXUPCALL_NORM);
2257                 BTFIXUPSET_CALL(flush_tlb_page, smp_flush_tlb_page, BTFIXUPCALL_NORM);
2258         }
2259         BTFIXUPSET_CALL(__flush_page_to_ram, smp_flush_page_to_ram, BTFIXUPCALL_NORM);
2260         BTFIXUPSET_CALL(flush_sig_insns, smp_flush_sig_insns, BTFIXUPCALL_NORM);
2261         BTFIXUPSET_CALL(flush_page_for_dma, smp_flush_page_for_dma, BTFIXUPCALL_NORM);
2262
2263         if (poke_srmmu == poke_viking) {
2264                 /* Avoid unnecessary cross calls. */
2265                 BTFIXUPCOPY_CALL(flush_cache_all, local_flush_cache_all);
2266                 BTFIXUPCOPY_CALL(flush_cache_mm, local_flush_cache_mm);
2267                 BTFIXUPCOPY_CALL(flush_cache_range, local_flush_cache_range);
2268                 BTFIXUPCOPY_CALL(flush_cache_page, local_flush_cache_page);
2269                 BTFIXUPCOPY_CALL(__flush_page_to_ram, local_flush_page_to_ram);
2270                 BTFIXUPCOPY_CALL(flush_sig_insns, local_flush_sig_insns);
2271                 BTFIXUPCOPY_CALL(flush_page_for_dma, local_flush_page_for_dma);
2272         }
2273 #endif
2274
2275         if (sparc_cpu_model == sun4d)
2276                 ld_mmu_iounit();
2277         else
2278                 ld_mmu_iommu();
2279 #ifdef CONFIG_SMP
2280         if (sparc_cpu_model == sun4d)
2281                 sun4d_init_smp();
2282         else
2283                 sun4m_init_smp();
2284 #endif
2285 }