git.oblomov.eu Git - linux-2.6/blob - arch/sh/kernel/traps_32.c

   1 /*
   2  * 'traps.c' handles hardware traps and faults after we have saved some
   3  * state in 'entry.S'.
   4  *
   5  *  SuperH version: Copyright (C) 1999 Niibe Yutaka
   6  *                  Copyright (C) 2000 Philipp Rumpf
   7  *                  Copyright (C) 2000 David Howells
   8  *                  Copyright (C) 2002 - 2007 Paul Mundt
   9  *
  10  * This file is subject to the terms and conditions of the GNU General Public
  11  * License.  See the file "COPYING" in the main directory of this archive
  12  * for more details.
  13  */
  14 #include <linux/kernel.h>
  15 #include <linux/ptrace.h>
  16 #include <linux/init.h>
  17 #include <linux/spinlock.h>
  18 #include <linux/module.h>
  19 #include <linux/kallsyms.h>
  20 #include <linux/io.h>
  21 #include <linux/bug.h>
  22 #include <linux/debug_locks.h>
  23 #include <linux/kdebug.h>
  24 #include <linux/kexec.h>
  25 #include <linux/limits.h>
  26 #include <asm/system.h>
  27 #include <asm/uaccess.h>
  28
  29 #ifdef CONFIG_SH_KGDB
  30 #include <asm/kgdb.h>
  31 #define CHK_REMOTE_DEBUG(regs)                  \
  32 {                                               \
  33         if (kgdb_debug_hook && !user_mode(regs))\
  34                 (*kgdb_debug_hook)(regs);       \
  35 }
  36 #else
  37 #define CHK_REMOTE_DEBUG(regs)
  38 #endif
  39
  40 #ifdef CONFIG_CPU_SH2
  41 # define TRAP_RESERVED_INST     4
  42 # define TRAP_ILLEGAL_SLOT_INST 6
  43 # define TRAP_ADDRESS_ERROR     9
  44 # ifdef CONFIG_CPU_SH2A
  45 #  define TRAP_DIVZERO_ERROR    17
  46 #  define TRAP_DIVOVF_ERROR     18
  47 # endif
  48 #else
  49 #define TRAP_RESERVED_INST      12
  50 #define TRAP_ILLEGAL_SLOT_INST  13
  51 #endif
  52
  53 static void dump_mem(const char *str, unsigned long bottom, unsigned long top)
  54 {
  55         unsigned long p;
  56         int i;
  57
  58         printk("%s(0x%08lx to 0x%08lx)\n", str, bottom, top);
  59
  60         for (p = bottom & ~31; p < top; ) {
  61                 printk("%04lx: ", p & 0xffff);
  62
  63                 for (i = 0; i < 8; i++, p += 4) {
  64                         unsigned int val;
  65
  66                         if (p < bottom || p >= top)
  67                                 printk("         ");
  68                         else {
  69                                 if (__get_user(val, (unsigned int __user *)p)) {
  70                                         printk("\n");
  71                                         return;
  72                                 }
  73                                 printk("%08x ", val);
  74                         }
  75                 }
  76                 printk("\n");
  77         }
  78 }
  79
  80 static DEFINE_SPINLOCK(die_lock);
  81
  82 void die(const char * str, struct pt_regs * regs, long err)
  83 {
  84         static int die_counter;
  85
  86         oops_enter();
  87
  88         console_verbose();
  89         spin_lock_irq(&die_lock);
  90         bust_spinlocks(1);
  91
  92         printk("%s: %04lx [#%d]\n", str, err & 0xffff, ++die_counter);
  93
  94         CHK_REMOTE_DEBUG(regs);
  95         print_modules();
  96         show_regs(regs);
  97
  98         printk("Process: %s (pid: %d, stack limit = %p)\n", current->comm,
  99                         task_pid_nr(current), task_stack_page(current) + 1);
 100
 101         if (!user_mode(regs) || in_interrupt())
 102                 dump_mem("Stack: ", regs->regs[15], THREAD_SIZE +
 103                          (unsigned long)task_stack_page(current));
 104
 105         bust_spinlocks(0);
 106         add_taint(TAINT_DIE);
 107         spin_unlock_irq(&die_lock);
 108
 109         if (kexec_should_crash(current))
 110                 crash_kexec(regs);
 111
 112         if (in_interrupt())
 113                 panic("Fatal exception in interrupt");
 114
 115         if (panic_on_oops)
 116                 panic("Fatal exception");
 117
 118         oops_exit();
 119         do_exit(SIGSEGV);
 120 }
 121
 122 static inline void die_if_kernel(const char *str, struct pt_regs *regs,
 123                                  long err)
 124 {
 125         if (!user_mode(regs))
 126                 die(str, regs, err);
 127 }
 128
 129 /*
 130  * try and fix up kernelspace address errors
 131  * - userspace errors just cause EFAULT to be returned, resulting in SEGV
 132  * - kernel/userspace interfaces cause a jump to an appropriate handler
 133  * - other kernel errors are bad
 134  * - return 0 if fixed-up, -EFAULT if non-fatal (to the kernel) fault
 135  */
 136 static int die_if_no_fixup(const char * str, struct pt_regs * regs, long err)
 137 {
 138         if (!user_mode(regs)) {
 139                 const struct exception_table_entry *fixup;
 140                 fixup = search_exception_tables(regs->pc);
 141                 if (fixup) {
 142                         regs->pc = fixup->fixup;
 143                         return 0;
 144                 }
 145                 die(str, regs, err);
 146         }
 147         return -EFAULT;
 148 }
 149
 150 static inline void sign_extend(unsigned int count, unsigned char *dst)
 151 {
 152 #ifdef __LITTLE_ENDIAN__
 153         if ((count == 1) && dst[0] & 0x80) {
 154                 dst[1] = 0xff;
 155                 dst[2] = 0xff;
 156                 dst[3] = 0xff;
 157         }
 158         if ((count == 2) && dst[1] & 0x80) {
 159                 dst[2] = 0xff;
 160                 dst[3] = 0xff;
 161         }
 162 #else
 163         if ((count == 1) && dst[3] & 0x80) {
 164                 dst[2] = 0xff;
 165                 dst[1] = 0xff;
 166                 dst[0] = 0xff;
 167         }
 168         if ((count == 2) && dst[2] & 0x80) {
 169                 dst[1] = 0xff;
 170                 dst[0] = 0xff;
 171         }
 172 #endif
 173 }
 174
 175 static struct mem_access user_mem_access = {
 176         copy_from_user,
 177         copy_to_user,
 178 };
 179
 180 /*
 181  * handle an instruction that does an unaligned memory access by emulating the
 182  * desired behaviour
 183  * - note that PC _may not_ point to the faulting instruction
 184  *   (if that instruction is in a branch delay slot)
 185  * - return 0 if emulation okay, -EFAULT on existential error
 186  */
 187 static int handle_unaligned_ins(opcode_t instruction, struct pt_regs *regs,
 188                                 struct mem_access *ma)
 189 {
 190         int ret, index, count;
 191         unsigned long *rm, *rn;
 192         unsigned char *src, *dst;
 193
 194         index = (instruction>>8)&15;    /* 0x0F00 */
 195         rn = &regs->regs[index];
 196
 197         index = (instruction>>4)&15;    /* 0x00F0 */
 198         rm = &regs->regs[index];
 199
 200         count = 1<<(instruction&3);
 201
 202         ret = -EFAULT;
 203         switch (instruction>>12) {
 204         case 0: /* mov.[bwl] to/from memory via r0+rn */
 205                 if (instruction & 8) {
 206                         /* from memory */
 207                         src = (unsigned char*) *rm;
 208                         src += regs->regs[0];
 209                         dst = (unsigned char*) rn;
 210                         *(unsigned long*)dst = 0;
 211
 212 #if !defined(__LITTLE_ENDIAN__)
 213                         dst += 4-count;
 214 #endif
 215                         if (ma->from(dst, src, count))
 216                                 goto fetch_fault;
 217
 218                         sign_extend(count, dst);
 219                 } else {
 220                         /* to memory */
 221                         src = (unsigned char*) rm;
 222 #if !defined(__LITTLE_ENDIAN__)
 223                         src += 4-count;
 224 #endif
 225                         dst = (unsigned char*) *rn;
 226                         dst += regs->regs[0];
 227
 228                         if (ma->to(dst, src, count))
 229                                 goto fetch_fault;
 230                 }
 231                 ret = 0;
 232                 break;
 233
 234         case 1: /* mov.l Rm,@(disp,Rn) */
 235                 src = (unsigned char*) rm;
 236                 dst = (unsigned char*) *rn;
 237                 dst += (instruction&0x000F)<<2;
 238
 239                 if (ma->to(dst, src, 4))
 240                         goto fetch_fault;
 241                 ret = 0;
 242                 break;
 243
 244         case 2: /* mov.[bwl] to memory, possibly with pre-decrement */
 245                 if (instruction & 4)
 246                         *rn -= count;
 247                 src = (unsigned char*) rm;
 248                 dst = (unsigned char*) *rn;
 249 #if !defined(__LITTLE_ENDIAN__)
 250                 src += 4-count;
 251 #endif
 252                 if (ma->to(dst, src, count))
 253                         goto fetch_fault;
 254                 ret = 0;
 255                 break;
 256
 257         case 5: /* mov.l @(disp,Rm),Rn */
 258                 src = (unsigned char*) *rm;
 259                 src += (instruction&0x000F)<<2;
 260                 dst = (unsigned char*) rn;
 261                 *(unsigned long*)dst = 0;
 262
 263                 if (ma->from(dst, src, 4))
 264                         goto fetch_fault;
 265                 ret = 0;
 266                 break;
 267
 268         case 6: /* mov.[bwl] from memory, possibly with post-increment */
 269                 src = (unsigned char*) *rm;
 270                 if (instruction & 4)
 271                         *rm += count;
 272                 dst = (unsigned char*) rn;
 273                 *(unsigned long*)dst = 0;
 274
 275 #if !defined(__LITTLE_ENDIAN__)
 276                 dst += 4-count;
 277 #endif
 278                 if (ma->from(dst, src, count))
 279                         goto fetch_fault;
 280                 sign_extend(count, dst);
 281                 ret = 0;
 282                 break;
 283
 284         case 8:
 285                 switch ((instruction&0xFF00)>>8) {
 286                 case 0x81: /* mov.w R0,@(disp,Rn) */
 287                         src = (unsigned char*) &regs->regs[0];
 288 #if !defined(__LITTLE_ENDIAN__)
 289                         src += 2;
 290 #endif
 291                         dst = (unsigned char*) *rm; /* called Rn in the spec */
 292                         dst += (instruction&0x000F)<<1;
 293
 294                         if (ma->to(dst, src, 2))
 295                                 goto fetch_fault;
 296                         ret = 0;
 297                         break;
 298
 299                 case 0x85: /* mov.w @(disp,Rm),R0 */
 300                         src = (unsigned char*) *rm;
 301                         src += (instruction&0x000F)<<1;
 302                         dst = (unsigned char*) &regs->regs[0];
 303                         *(unsigned long*)dst = 0;
 304
 305 #if !defined(__LITTLE_ENDIAN__)
 306                         dst += 2;
 307 #endif
 308                         if (ma->from(dst, src, 2))
 309                                 goto fetch_fault;
 310                         sign_extend(2, dst);
 311                         ret = 0;
 312                         break;
 313                 }
 314                 break;
 315         }
 316         return ret;
 317
 318  fetch_fault:
 319         /* Argh. Address not only misaligned but also non-existent.
 320          * Raise an EFAULT and see if it's trapped
 321          */
 322         return die_if_no_fixup("Fault in unaligned fixup", regs, 0);
 323 }
 324
 325 /*
 326  * emulate the instruction in the delay slot
 327  * - fetches the instruction from PC+2
 328  */
 329 static inline int handle_delayslot(struct pt_regs *regs,
 330                                    opcode_t old_instruction,
 331                                    struct mem_access *ma)
 332 {
 333         opcode_t instruction;
 334         void *addr = (void *)(regs->pc + instruction_size(old_instruction));
 335
 336         if (copy_from_user(&instruction, addr, sizeof(instruction))) {
 337                 /* the instruction-fetch faulted */
 338                 if (user_mode(regs))
 339                         return -EFAULT;
 340
 341                 /* kernel */
 342                 die("delay-slot-insn faulting in handle_unaligned_delayslot",
 343                     regs, 0);
 344         }
 345
 346         return handle_unaligned_ins(instruction, regs, ma);
 347 }
 348
 349 /*
 350  * handle an instruction that does an unaligned memory access
 351  * - have to be careful of branch delay-slot instructions that fault
 352  *  SH3:
 353  *   - if the branch would be taken PC points to the branch
 354  *   - if the branch would not be taken, PC points to delay-slot
 355  *  SH4:
 356  *   - PC always points to delayed branch
 357  * - return 0 if handled, -EFAULT if failed (may not return if in kernel)
 358  */
 359
 360 /* Macros to determine offset from current PC for branch instructions */
 361 /* Explicit type coercion is used to force sign extension where needed */
 362 #define SH_PC_8BIT_OFFSET(instr) ((((signed char)(instr))*2) + 4)
 363 #define SH_PC_12BIT_OFFSET(instr) ((((signed short)(instr<<4))>>3) + 4)
 364
 365 /*
 366  * XXX: SH-2A needs this too, but it needs an overhaul thanks to mixed 32-bit
 367  * opcodes..
 368  */
 369
 370 static int handle_unaligned_notify_count = 10;
 371
 372 int handle_unaligned_access(opcode_t instruction, struct pt_regs *regs,
 373                             struct mem_access *ma)
 374 {
 375         u_int rm;
 376         int ret, index;
 377
 378         index = (instruction>>8)&15;    /* 0x0F00 */
 379         rm = regs->regs[index];
 380
 381         /* shout about the first ten userspace fixups */
 382         if (user_mode(regs) && handle_unaligned_notify_count>0) {
 383                 handle_unaligned_notify_count--;
 384
 385                 printk(KERN_NOTICE "Fixing up unaligned userspace access "
 386                        "in \"%s\" pid=%d pc=0x%p ins=0x%04hx\n",
 387                        current->comm, task_pid_nr(current),
 388                        (void *)regs->pc, instruction);
 389         }
 390
 391         ret = -EFAULT;
 392         switch (instruction&0xF000) {
 393         case 0x0000:
 394                 if (instruction==0x000B) {
 395                         /* rts */
 396                         ret = handle_delayslot(regs, instruction, ma);
 397                         if (ret==0)
 398                                 regs->pc = regs->pr;
 399                 }
 400                 else if ((instruction&0x00FF)==0x0023) {
 401                         /* braf @Rm */
 402                         ret = handle_delayslot(regs, instruction, ma);
 403                         if (ret==0)
 404                                 regs->pc += rm + 4;
 405                 }
 406                 else if ((instruction&0x00FF)==0x0003) {
 407                         /* bsrf @Rm */
 408                         ret = handle_delayslot(regs, instruction, ma);
 409                         if (ret==0) {
 410                                 regs->pr = regs->pc + 4;
 411                                 regs->pc += rm + 4;
 412                         }
 413                 }
 414                 else {
 415                         /* mov.[bwl] to/from memory via r0+rn */
 416                         goto simple;
 417                 }
 418                 break;
 419
 420         case 0x1000: /* mov.l Rm,@(disp,Rn) */
 421                 goto simple;
 422
 423         case 0x2000: /* mov.[bwl] to memory, possibly with pre-decrement */
 424                 goto simple;
 425
 426         case 0x4000:
 427                 if ((instruction&0x00FF)==0x002B) {
 428                         /* jmp @Rm */
 429                         ret = handle_delayslot(regs, instruction, ma);
 430                         if (ret==0)
 431                                 regs->pc = rm;
 432                 }
 433                 else if ((instruction&0x00FF)==0x000B) {
 434                         /* jsr @Rm */
 435                         ret = handle_delayslot(regs, instruction, ma);
 436                         if (ret==0) {
 437                                 regs->pr = regs->pc + 4;
 438                                 regs->pc = rm;
 439                         }
 440                 }
 441                 else {
 442                         /* mov.[bwl] to/from memory via r0+rn */
 443                         goto simple;
 444                 }
 445                 break;
 446
 447         case 0x5000: /* mov.l @(disp,Rm),Rn */
 448                 goto simple;
 449
 450         case 0x6000: /* mov.[bwl] from memory, possibly with post-increment */
 451                 goto simple;
 452
 453         case 0x8000: /* bf lab, bf/s lab, bt lab, bt/s lab */
 454                 switch (instruction&0x0F00) {
 455                 case 0x0100: /* mov.w R0,@(disp,Rm) */
 456                         goto simple;
 457                 case 0x0500: /* mov.w @(disp,Rm),R0 */
 458                         goto simple;
 459                 case 0x0B00: /* bf   lab - no delayslot*/
 460                         break;
 461                 case 0x0F00: /* bf/s lab */
 462                         ret = handle_delayslot(regs, instruction, ma);
 463                         if (ret==0) {
 464 #if defined(CONFIG_CPU_SH4) || defined(CONFIG_SH7705_CACHE_32KB)
 465                                 if ((regs->sr & 0x00000001) != 0)
 466                                         regs->pc += 4; /* next after slot */
 467                                 else
 468 #endif
 469                                         regs->pc += SH_PC_8BIT_OFFSET(instruction);
 470                         }
 471                         break;
 472                 case 0x0900: /* bt   lab - no delayslot */
 473                         break;
 474                 case 0x0D00: /* bt/s lab */
 475                         ret = handle_delayslot(regs, instruction, ma);
 476                         if (ret==0) {
 477 #if defined(CONFIG_CPU_SH4) || defined(CONFIG_SH7705_CACHE_32KB)
 478                                 if ((regs->sr & 0x00000001) == 0)
 479                                         regs->pc += 4; /* next after slot */
 480                                 else
 481 #endif
 482                                         regs->pc += SH_PC_8BIT_OFFSET(instruction);
 483                         }
 484                         break;
 485                 }
 486                 break;
 487
 488         case 0xA000: /* bra label */
 489                 ret = handle_delayslot(regs, instruction, ma);
 490                 if (ret==0)
 491                         regs->pc += SH_PC_12BIT_OFFSET(instruction);
 492                 break;
 493
 494         case 0xB000: /* bsr label */
 495                 ret = handle_delayslot(regs, instruction, ma);
 496                 if (ret==0) {
 497                         regs->pr = regs->pc + 4;
 498                         regs->pc += SH_PC_12BIT_OFFSET(instruction);
 499                 }
 500                 break;
 501         }
 502         return ret;
 503
 504         /* handle non-delay-slot instruction */
 505  simple:
 506         ret = handle_unaligned_ins(instruction, regs, ma);
 507         if (ret==0)
 508                 regs->pc += instruction_size(instruction);
 509         return ret;
 510 }
 511
 512 #ifdef CONFIG_CPU_HAS_SR_RB
 513 #define lookup_exception_vector(x)      \
 514         __asm__ __volatile__ ("stc r2_bank, %0\n\t" : "=r" ((x)))
 515 #else
 516 #define lookup_exception_vector(x)      \
 517         __asm__ __volatile__ ("mov r4, %0\n\t" : "=r" ((x)))
 518 #endif
 519
 520 /*
 521  * Handle various address error exceptions:
 522  *  - instruction address error:
 523  *       misaligned PC
 524  *       PC >= 0x80000000 in user mode
 525  *  - data address error (read and write)
 526  *       misaligned data access
 527  *       access to >= 0x80000000 is user mode
 528  * Unfortuntaly we can't distinguish between instruction address error
 529  * and data address errors caused by read accesses.
 530  */
 531 asmlinkage void do_address_error(struct pt_regs *regs,
 532                                  unsigned long writeaccess,
 533                                  unsigned long address)
 534 {
 535         unsigned long error_code = 0;
 536         mm_segment_t oldfs;
 537         siginfo_t info;
 538         opcode_t instruction;
 539         int tmp;
 540
 541         /* Intentional ifdef */
 542 #ifdef CONFIG_CPU_HAS_SR_RB
 543         lookup_exception_vector(error_code);
 544 #endif
 545
 546         oldfs = get_fs();
 547
 548         if (user_mode(regs)) {
 549                 int si_code = BUS_ADRERR;
 550
 551                 local_irq_enable();
 552
 553                 /* bad PC is not something we can fix */
 554                 if (regs->pc & 1) {
 555                         si_code = BUS_ADRALN;
 556                         goto uspace_segv;
 557                 }
 558
 559                 set_fs(USER_DS);
 560                 if (copy_from_user(&instruction, (void *)(regs->pc),
 561                                    sizeof(instruction))) {
 562                         /* Argh. Fault on the instruction itself.
 563                            This should never happen non-SMP
 564                         */
 565                         set_fs(oldfs);
 566                         goto uspace_segv;
 567                 }
 568
 569                 tmp = handle_unaligned_access(instruction, regs,
 570                                               &user_mem_access);
 571                 set_fs(oldfs);
 572
 573                 if (tmp==0)
 574                         return; /* sorted */
 575 uspace_segv:
 576                 printk(KERN_NOTICE "Sending SIGBUS to \"%s\" due to unaligned "
 577                        "access (PC %lx PR %lx)\n", current->comm, regs->pc,
 578                        regs->pr);
 579
 580                 info.si_signo = SIGBUS;
 581                 info.si_errno = 0;
 582                 info.si_code = si_code;
 583                 info.si_addr = (void __user *)address;
 584                 force_sig_info(SIGBUS, &info, current);
 585         } else {
 586                 if (regs->pc & 1)
 587                         die("unaligned program counter", regs, error_code);
 588
 589                 set_fs(KERNEL_DS);
 590                 if (copy_from_user(&instruction, (void *)(regs->pc),
 591                                    sizeof(instruction))) {
 592                         /* Argh. Fault on the instruction itself.
 593                            This should never happen non-SMP
 594                         */
 595                         set_fs(oldfs);
 596                         die("insn faulting in do_address_error", regs, 0);
 597                 }
 598
 599                 handle_unaligned_access(instruction, regs, &user_mem_access);
 600                 set_fs(oldfs);
 601         }
 602 }
 603
 604 #ifdef CONFIG_SH_DSP
 605 /*
 606  *      SH-DSP support gerg@snapgear.com.
 607  */
 608 int is_dsp_inst(struct pt_regs *regs)
 609 {
 610         unsigned short inst = 0;
 611
 612         /*
 613          * Safe guard if DSP mode is already enabled or we're lacking
 614          * the DSP altogether.
 615          */
 616         if (!(current_cpu_data.flags & CPU_HAS_DSP) || (regs->sr & SR_DSP))
 617                 return 0;
 618
 619         get_user(inst, ((unsigned short *) regs->pc));
 620
 621         inst &= 0xf000;
 622
 623         /* Check for any type of DSP or support instruction */
 624         if ((inst == 0xf000) || (inst == 0x4000))
 625                 return 1;
 626
 627         return 0;
 628 }
 629 #else
 630 #define is_dsp_inst(regs)       (0)
 631 #endif /* CONFIG_SH_DSP */
 632
 633 #ifdef CONFIG_CPU_SH2A
 634 asmlinkage void do_divide_error(unsigned long r4, unsigned long r5,
 635                                 unsigned long r6, unsigned long r7,
 636                                 struct pt_regs __regs)
 637 {
 638         siginfo_t info;
 639
 640         switch (r4) {
 641         case TRAP_DIVZERO_ERROR:
 642                 info.si_code = FPE_INTDIV;
 643                 break;
 644         case TRAP_DIVOVF_ERROR:
 645                 info.si_code = FPE_INTOVF;
 646                 break;
 647         }
 648
 649         force_sig_info(SIGFPE, &info, current);
 650 }
 651 #endif
 652
 653 asmlinkage void do_reserved_inst(unsigned long r4, unsigned long r5,
 654                                 unsigned long r6, unsigned long r7,
 655                                 struct pt_regs __regs)
 656 {
 657         struct pt_regs *regs = RELOC_HIDE(&__regs, 0);
 658         unsigned long error_code;
 659         struct task_struct *tsk = current;
 660
 661 #ifdef CONFIG_SH_FPU_EMU
 662         unsigned short inst = 0;
 663         int err;
 664
 665         get_user(inst, (unsigned short*)regs->pc);
 666
 667         err = do_fpu_inst(inst, regs);
 668         if (!err) {
 669                 regs->pc += instruction_size(inst);
 670                 return;
 671         }
 672         /* not a FPU inst. */
 673 #endif
 674
 675 #ifdef CONFIG_SH_DSP
 676         /* Check if it's a DSP instruction */
 677         if (is_dsp_inst(regs)) {
 678                 /* Enable DSP mode, and restart instruction. */
 679                 regs->sr |= SR_DSP;
 680                 return;
 681         }
 682 #endif
 683
 684         lookup_exception_vector(error_code);
 685
 686         local_irq_enable();
 687         CHK_REMOTE_DEBUG(regs);
 688         force_sig(SIGILL, tsk);
 689         die_if_no_fixup("reserved instruction", regs, error_code);
 690 }
 691
 692 #ifdef CONFIG_SH_FPU_EMU
 693 static int emulate_branch(unsigned short inst, struct pt_regs* regs)
 694 {
 695         /*
 696          * bfs: 8fxx: PC+=d*2+4;
 697          * bts: 8dxx: PC+=d*2+4;
 698          * bra: axxx: PC+=D*2+4;
 699          * bsr: bxxx: PC+=D*2+4  after PR=PC+4;
 700          * braf:0x23: PC+=Rn*2+4;
 701          * bsrf:0x03: PC+=Rn*2+4 after PR=PC+4;
 702          * jmp: 4x2b: PC=Rn;
 703          * jsr: 4x0b: PC=Rn      after PR=PC+4;
 704          * rts: 000b: PC=PR;
 705          */
 706         if ((inst & 0xfd00) == 0x8d00) {
 707                 regs->pc += SH_PC_8BIT_OFFSET(inst);
 708                 return 0;
 709         }
 710
 711         if ((inst & 0xe000) == 0xa000) {
 712                 regs->pc += SH_PC_12BIT_OFFSET(inst);
 713                 return 0;
 714         }
 715
 716         if ((inst & 0xf0df) == 0x0003) {
 717                 regs->pc += regs->regs[(inst & 0x0f00) >> 8] + 4;
 718                 return 0;
 719         }
 720
 721         if ((inst & 0xf0df) == 0x400b) {
 722                 regs->pc = regs->regs[(inst & 0x0f00) >> 8];
 723                 return 0;
 724         }
 725
 726         if ((inst & 0xffff) == 0x000b) {
 727                 regs->pc = regs->pr;
 728                 return 0;
 729         }
 730
 731         return 1;
 732 }
 733 #endif
 734
 735 asmlinkage void do_illegal_slot_inst(unsigned long r4, unsigned long r5,
 736                                 unsigned long r6, unsigned long r7,
 737                                 struct pt_regs __regs)
 738 {
 739         struct pt_regs *regs = RELOC_HIDE(&__regs, 0);
 740         unsigned long error_code;
 741         struct task_struct *tsk = current;
 742 #ifdef CONFIG_SH_FPU_EMU
 743         unsigned short inst = 0;
 744
 745         get_user(inst, (unsigned short *)regs->pc + 1);
 746         if (!do_fpu_inst(inst, regs)) {
 747                 get_user(inst, (unsigned short *)regs->pc);
 748                 if (!emulate_branch(inst, regs))
 749                         return;
 750                 /* fault in branch.*/
 751         }
 752         /* not a FPU inst. */
 753 #endif
 754
 755         lookup_exception_vector(error_code);
 756
 757         local_irq_enable();
 758         CHK_REMOTE_DEBUG(regs);
 759         force_sig(SIGILL, tsk);
 760         die_if_no_fixup("illegal slot instruction", regs, error_code);
 761 }
 762
 763 asmlinkage void do_exception_error(unsigned long r4, unsigned long r5,
 764                                    unsigned long r6, unsigned long r7,
 765                                    struct pt_regs __regs)
 766 {
 767         struct pt_regs *regs = RELOC_HIDE(&__regs, 0);
 768         long ex;
 769
 770         lookup_exception_vector(ex);
 771         die_if_kernel("exception", regs, ex);
 772 }
 773
 774 #if defined(CONFIG_SH_STANDARD_BIOS)
 775 void *gdb_vbr_vector;
 776
 777 static inline void __init gdb_vbr_init(void)
 778 {
 779         register unsigned long vbr;
 780
 781         /*
 782          * Read the old value of the VBR register to initialise
 783          * the vector through which debug and BIOS traps are
 784          * delegated by the Linux trap handler.
 785          */
 786         asm volatile("stc vbr, %0" : "=r" (vbr));
 787
 788         gdb_vbr_vector = (void *)(vbr + 0x100);
 789         printk("Setting GDB trap vector to 0x%08lx\n",
 790                (unsigned long)gdb_vbr_vector);
 791 }
 792 #endif
 793
 794 void __cpuinit per_cpu_trap_init(void)
 795 {
 796         extern void *vbr_base;
 797
 798 #ifdef CONFIG_SH_STANDARD_BIOS
 799         if (raw_smp_processor_id() == 0)
 800                 gdb_vbr_init();
 801 #endif
 802
 803         /* NOTE: The VBR value should be at P1
 804            (or P2, virtural "fixed" address space).
 805            It's definitely should not in physical address.  */
 806
 807         asm volatile("ldc       %0, vbr"
 808                      : /* no output */
 809                      : "r" (&vbr_base)
 810                      : "memory");
 811 }
 812
 813 void *set_exception_table_vec(unsigned int vec, void *handler)
 814 {
 815         extern void *exception_handling_table[];
 816         void *old_handler;
 817
 818         old_handler = exception_handling_table[vec];
 819         exception_handling_table[vec] = handler;
 820         return old_handler;
 821 }
 822
 823 void __init trap_init(void)
 824 {
 825         set_exception_table_vec(TRAP_RESERVED_INST, do_reserved_inst);
 826         set_exception_table_vec(TRAP_ILLEGAL_SLOT_INST, do_illegal_slot_inst);
 827
 828 #if defined(CONFIG_CPU_SH4) && !defined(CONFIG_SH_FPU) || \
 829     defined(CONFIG_SH_FPU_EMU)
 830         /*
 831          * For SH-4 lacking an FPU, treat floating point instructions as
 832          * reserved. They'll be handled in the math-emu case, or faulted on
 833          * otherwise.
 834          */
 835         set_exception_table_evt(0x800, do_reserved_inst);
 836         set_exception_table_evt(0x820, do_illegal_slot_inst);
 837 #elif defined(CONFIG_SH_FPU)
 838 #ifdef CONFIG_CPU_SUBTYPE_SHX3
 839         set_exception_table_evt(0xd80, fpu_state_restore_trap_handler);
 840         set_exception_table_evt(0xda0, fpu_state_restore_trap_handler);
 841 #else
 842         set_exception_table_evt(0x800, fpu_state_restore_trap_handler);
 843         set_exception_table_evt(0x820, fpu_state_restore_trap_handler);
 844 #endif
 845 #endif
 846
 847 #ifdef CONFIG_CPU_SH2
 848         set_exception_table_vec(TRAP_ADDRESS_ERROR, address_error_trap_handler);
 849 #endif
 850 #ifdef CONFIG_CPU_SH2A
 851         set_exception_table_vec(TRAP_DIVZERO_ERROR, do_divide_error);
 852         set_exception_table_vec(TRAP_DIVOVF_ERROR, do_divide_error);
 853 #endif
 854
 855         /* Setup VBR for boot cpu */
 856         per_cpu_trap_init();
 857 }
 858
 859 void show_trace(struct task_struct *tsk, unsigned long *sp,
 860                 struct pt_regs *regs)
 861 {
 862         unsigned long addr;
 863
 864         if (regs && user_mode(regs))
 865                 return;
 866
 867         printk("\nCall trace: ");
 868 #ifdef CONFIG_KALLSYMS
 869         printk("\n");
 870 #endif
 871
 872         while (!kstack_end(sp)) {
 873                 addr = *sp++;
 874                 if (kernel_text_address(addr))
 875                         print_ip_sym(addr);
 876         }
 877
 878         printk("\n");
 879
 880         if (!tsk)
 881                 tsk = current;
 882
 883         debug_show_held_locks(tsk);
 884 }
 885
 886 void show_stack(struct task_struct *tsk, unsigned long *sp)
 887 {
 888         unsigned long stack;
 889
 890         if (!tsk)
 891                 tsk = current;
 892         if (tsk == current)
 893                 sp = (unsigned long *)current_stack_pointer;
 894         else
 895                 sp = (unsigned long *)tsk->thread.sp;
 896
 897         stack = (unsigned long)sp;
 898         dump_mem("Stack: ", stack, THREAD_SIZE +
 899                  (unsigned long)task_stack_page(tsk));
 900         show_trace(tsk, sp, NULL);
 901 }
 902
 903 void dump_stack(void)
 904 {
 905         show_stack(NULL, NULL);
 906 }
 907 EXPORT_SYMBOL(dump_stack);