Merge master.kernel.org:/pub/scm/linux/kernel/git/davej/agpgart
[linux-2.6] / arch / powerpc / boot / dts / mpc8641_hpcn.dts
1 /*
2  * MPC8641 HPCN Device Tree Source
3  *
4  * Copyright 2006 Freescale Semiconductor Inc.
5  *
6  * This program is free software; you can redistribute  it and/or modify it
7  * under  the terms of  the GNU General  Public License as published by the
8  * Free Software Foundation;  either version 2 of the  License, or (at your
9  * option) any later version.
10  */
11
12
13 / {
14         model = "MPC8641HPCN";
15         compatible = "mpc86xx";
16         #address-cells = <1>;
17         #size-cells = <1>;
18
19         cpus {
20                 #address-cells = <1>;
21                 #size-cells = <0>;
22
23                 PowerPC,8641@0 {
24                         device_type = "cpu";
25                         reg = <0>;
26                         d-cache-line-size = <20>;       // 32 bytes
27                         i-cache-line-size = <20>;       // 32 bytes
28                         d-cache-size = <8000>;          // L1, 32K
29                         i-cache-size = <8000>;          // L1, 32K
30                         timebase-frequency = <0>;       // 33 MHz, from uboot
31                         bus-frequency = <0>;            // From uboot
32                         clock-frequency = <0>;          // From uboot
33                         32-bit;
34                 };
35                 PowerPC,8641@1 {
36                         device_type = "cpu";
37                         reg = <1>;
38                         d-cache-line-size = <20>;       // 32 bytes
39                         i-cache-line-size = <20>;       // 32 bytes
40                         d-cache-size = <8000>;          // L1, 32K
41                         i-cache-size = <8000>;          // L1, 32K
42                         timebase-frequency = <0>;       // 33 MHz, from uboot
43                         bus-frequency = <0>;            // From uboot
44                         clock-frequency = <0>;          // From uboot
45                         32-bit;
46                 };
47         };
48
49         memory {
50                 device_type = "memory";
51                 reg = <00000000 40000000>;      // 1G at 0x0
52         };
53
54         soc8641@f8000000 {
55                 #address-cells = <1>;
56                 #size-cells = <1>;
57                 #interrupt-cells = <2>;
58                 device_type = "soc";
59                 ranges = <0 f8000000 00100000>;
60                 reg = <f8000000 00100000>;      // CCSRBAR 1M
61                 bus-frequency = <0>;
62
63                 i2c@3000 {
64                         device_type = "i2c";
65                         compatible = "fsl-i2c";
66                         reg = <3000 100>;
67                         interrupts = <2b 2>;
68                         interrupt-parent = <&mpic>;
69                         dfsrr;
70                 };
71
72                 i2c@3100 {
73                         device_type = "i2c";
74                         compatible = "fsl-i2c";
75                         reg = <3100 100>;
76                         interrupts = <2b 2>;
77                         interrupt-parent = <&mpic>;
78                         dfsrr;
79                 };
80
81                 mdio@24520 {
82                         #address-cells = <1>;
83                         #size-cells = <0>;
84                         device_type = "mdio";
85                         compatible = "gianfar";
86                         reg = <24520 20>;
87                         phy0: ethernet-phy@0 {
88                                 interrupt-parent = <&mpic>;
89                                 interrupts = <4a 1>;
90                                 reg = <0>;
91                                 device_type = "ethernet-phy";
92                         };
93                         phy1: ethernet-phy@1 {
94                                 interrupt-parent = <&mpic>;
95                                 interrupts = <4a 1>;
96                                 reg = <1>;
97                                 device_type = "ethernet-phy";
98                         };
99                         phy2: ethernet-phy@2 {
100                                 interrupt-parent = <&mpic>;
101                                 interrupts = <4a 1>;
102                                 reg = <2>;
103                                 device_type = "ethernet-phy";
104                         };
105                         phy3: ethernet-phy@3 {
106                                 interrupt-parent = <&mpic>;
107                                 interrupts = <4a 1>;
108                                 reg = <3>;
109                                 device_type = "ethernet-phy";
110                         };
111                 };
112
113                 ethernet@24000 {
114                         #address-cells = <1>;
115                         #size-cells = <0>;
116                         device_type = "network";
117                         model = "TSEC";
118                         compatible = "gianfar";
119                         reg = <24000 1000>;
120                         mac-address = [ 00 E0 0C 00 73 00 ];
121                         interrupts = <1d 2 1e 2 22 2>;
122                         interrupt-parent = <&mpic>;
123                         phy-handle = <&phy0>;
124                 };
125
126                 ethernet@25000 {
127                         #address-cells = <1>;
128                         #size-cells = <0>;
129                         device_type = "network";
130                         model = "TSEC";
131                         compatible = "gianfar";
132                         reg = <25000 1000>;
133                         mac-address = [ 00 E0 0C 00 73 01 ];
134                         interrupts = <23 2 24 2 28 2>;
135                         interrupt-parent = <&mpic>;
136                         phy-handle = <&phy1>;
137                 };
138                 
139                 ethernet@26000 {
140                         #address-cells = <1>;
141                         #size-cells = <0>;
142                         device_type = "network";
143                         model = "TSEC";
144                         compatible = "gianfar";
145                         reg = <26000 1000>;
146                         mac-address = [ 00 E0 0C 00 02 FD ];
147                         interrupts = <1F 2 20 2 21 2>;
148                         interrupt-parent = <&mpic>;
149                         phy-handle = <&phy2>;
150                 };
151
152                 ethernet@27000 {
153                         #address-cells = <1>;
154                         #size-cells = <0>;
155                         device_type = "network";
156                         model = "TSEC";
157                         compatible = "gianfar";
158                         reg = <27000 1000>;
159                         mac-address = [ 00 E0 0C 00 03 FD ];
160                         interrupts = <25 2 26 2 27 2>;
161                         interrupt-parent = <&mpic>;
162                         phy-handle = <&phy3>;
163                 };
164                 serial@4500 {
165                         device_type = "serial";
166                         compatible = "ns16550";
167                         reg = <4500 100>;
168                         clock-frequency = <0>;
169                         interrupts = <2a 2>;
170                         interrupt-parent = <&mpic>;
171                 };
172
173                 serial@4600 {
174                         device_type = "serial";
175                         compatible = "ns16550";
176                         reg = <4600 100>;
177                         clock-frequency = <0>;
178                         interrupts = <1c 2>;
179                         interrupt-parent = <&mpic>;
180                 };
181
182                 pci@8000 {
183                         compatible = "86xx";
184                         device_type = "pci";
185                         #interrupt-cells = <1>;
186                         #size-cells = <2>;
187                         #address-cells = <3>;
188                         reg = <8000 1000>;
189                         bus-range = <0 fe>;
190                         ranges = <02000000 0 80000000 80000000 0 20000000
191                                   01000000 0 00000000 e2000000 0 00100000>;
192                         clock-frequency = <1fca055>;
193                         interrupt-parent = <&mpic>;
194                         interrupts = <18 2>;
195                         interrupt-map-mask = <f800 0 0 7>;
196                         interrupt-map = <
197                                 /* IDSEL 0x11 */
198                                 8800 0 0 1 &i8259 3 2
199                                 8800 0 0 2 &i8259 4 2
200                                 8800 0 0 3 &i8259 5 2
201                                 8800 0 0 4 &i8259 6 2
202
203                                 /* IDSEL 0x12 */
204                                 9000 0 0 1 &i8259 4 2
205                                 9000 0 0 2 &i8259 5 2
206                                 9000 0 0 3 &i8259 6 2
207                                 9000 0 0 4 &i8259 3 2
208
209                                 /* IDSEL 0x13 */
210                                 9800 0 0 1 &i8259 0 0
211                                 9800 0 0 2 &i8259 0 0
212                                 9800 0 0 3 &i8259 0 0
213                                 9800 0 0 4 &i8259 0 0
214
215                                 /* IDSEL 0x14 */
216                                 a000 0 0 1 &i8259 0 0
217                                 a000 0 0 2 &i8259 0 0
218                                 a000 0 0 3 &i8259 0 0
219                                 a000 0 0 4 &i8259 0 0
220
221                                 /* IDSEL 0x15 */
222                                 a800 0 0 1 &i8259 0 0
223                                 a800 0 0 2 &i8259 0 0
224                                 a800 0 0 3 &i8259 0 0
225                                 a800 0 0 4 &i8259 0 0
226
227                                 /* IDSEL 0x16 */
228                                 b000 0 0 1 &i8259 0 0
229                                 b000 0 0 2 &i8259 0 0
230                                 b000 0 0 3 &i8259 0 0
231                                 b000 0 0 4 &i8259 0 0
232
233                                 /* IDSEL 0x17 */
234                                 b800 0 0 1 &i8259 0 0
235                                 b800 0 0 2 &i8259 0 0
236                                 b800 0 0 3 &i8259 0 0
237                                 b800 0 0 4 &i8259 0 0
238
239                                 /* IDSEL 0x18 */
240                                 c000 0 0 1 &i8259 0 0
241                                 c000 0 0 2 &i8259 0 0
242                                 c000 0 0 3 &i8259 0 0
243                                 c000 0 0 4 &i8259 0 0
244
245                                 /* IDSEL 0x19 */
246                                 c800 0 0 1 &i8259 0 0
247                                 c800 0 0 2 &i8259 0 0
248                                 c800 0 0 3 &i8259 0 0
249                                 c800 0 0 4 &i8259 0 0
250
251                                 /* IDSEL 0x1a */
252                                 d000 0 0 1 &i8259 6 2
253                                 d000 0 0 2 &i8259 3 2
254                                 d000 0 0 3 &i8259 4 2
255                                 d000 0 0 4 &i8259 5 2
256
257
258                                 /* IDSEL 0x1b */
259                                 d800 0 0 1 &i8259 5 2
260                                 d800 0 0 2 &i8259 0 0
261                                 d800 0 0 3 &i8259 0 0
262                                 d800 0 0 4 &i8259 0 0
263
264                                 /* IDSEL 0x1c */
265                                 e000 0 0 1 &i8259 9 2
266                                 e000 0 0 2 &i8259 a 2
267                                 e000 0 0 3 &i8259 c 2
268                                 e000 0 0 4 &i8259 7 2
269
270                                 /* IDSEL 0x1d */
271                                 e800 0 0 1 &i8259 9 2
272                                 e800 0 0 2 &i8259 a 2
273                                 e800 0 0 3 &i8259 b 2
274                                 e800 0 0 4 &i8259 0 0
275
276                                 /* IDSEL 0x1e */
277                                 f000 0 0 1 &i8259 c 2
278                                 f000 0 0 2 &i8259 0 0
279                                 f000 0 0 3 &i8259 0 0
280                                 f000 0 0 4 &i8259 0 0
281
282                                 /* IDSEL 0x1f */
283                                 f800 0 0 1 &i8259 6 2
284                                 f800 0 0 2 &i8259 0 0
285                                 f800 0 0 3 &i8259 0 0
286                                 f800 0 0 4 &i8259 0 0
287                                 >;
288                         i8259: i8259@4d0 {
289                                 clock-frequency = <0>;
290                                 interrupt-controller;
291                                 device_type = "interrupt-controller";
292                                 #address-cells = <0>;
293                                 #interrupt-cells = <2>;
294                                 built-in;
295                                 compatible = "chrp,iic";
296                                 big-endian;
297                                 interrupts = <49 2>;
298                                 interrupt-parent = <&mpic>;
299                         };
300
301                 };
302
303                 pci@9000 {
304                         compatible = "86xx";
305                         device_type = "pci";
306                         #interrupt-cells = <1>;
307                         #size-cells = <2>;
308                         #address-cells = <3>;
309                         reg = <9000 1000>;
310                         bus-range = <0 ff>;
311                         ranges = <02000000 0 a0000000 a0000000 0 20000000
312                                   01000000 0 00000000 e3000000 0 00100000>;
313                         clock-frequency = <1fca055>;
314                         interrupt-parent = <&mpic>;
315                         interrupts = <19 2>;
316                         interrupt-map-mask = <f800 0 0 7>;
317                         interrupt-map = <
318                                 /* IDSEL 0x0 */
319                                 0000 0 0 1 &mpic 44 1
320                                 0000 0 0 2 &mpic 45 1
321                                 0000 0 0 3 &mpic 46 1
322                                 0000 0 0 4 &mpic 47 1
323                                 >;
324                 };
325
326                 mpic: pic@40000 {
327                         clock-frequency = <0>;
328                         interrupt-controller;
329                         #address-cells = <0>;
330                         #interrupt-cells = <2>;
331                         reg = <40000 40000>;
332                         built-in;
333                         compatible = "chrp,open-pic";
334                         device_type = "open-pic";
335                         big-endian;
336                 };
337         };
338 };