firewire: Schedule topology work before calling driver update functions.
[linux-2.6] / drivers / s390 / net / qeth_mpc.c
1 /*
2  * linux/drivers/s390/net/qeth_mpc.c
3  *
4  * Linux on zSeries OSA Express and HiperSockets support
5  *
6  * Copyright 2000,2003 IBM Corporation
7  * Author(s): Frank Pavlic <fpavlic@de.ibm.com>
8  *            Thomas Spatzier <tspat@de.ibm.com>
9  *
10  */
11 #include <asm/cio.h>
12 #include "qeth_mpc.h"
13
14 unsigned char IDX_ACTIVATE_READ[]={
15         0x00,0x00,0x80,0x00, 0x00,0x00,0x00,0x00,
16         0x19,0x01,0x01,0x80, 0x00,0x00,0x00,0x00,
17         0x00,0x00,0x00,0x00, 0x00,0x00,0xc8,0xc1,
18         0xd3,0xd3,0xd6,0xd3, 0xc5,0x40,0x00,0x00,
19         0x00,0x00
20 };
21
22 unsigned char IDX_ACTIVATE_WRITE[]={
23         0x00,0x00,0x80,0x00, 0x00,0x00,0x00,0x00,
24         0x15,0x01,0x01,0x80, 0x00,0x00,0x00,0x00,
25         0xff,0xff,0x00,0x00, 0x00,0x00,0xc8,0xc1,
26         0xd3,0xd3,0xd6,0xd3, 0xc5,0x40,0x00,0x00,
27         0x00,0x00
28 };
29
30 unsigned char CM_ENABLE[]={
31         0x00,0xe0,0x00,0x00, 0x00,0x00,0x00,0x01,
32         0x00,0x00,0x00,0x14, 0x00,0x00,0x00,0x63,
33         0x10,0x00,0x00,0x01,
34         0x00,0x00,0x00,0x00,
35         0x81,0x7e,0x00,0x01, 0x00,0x00,0x00,0x00,
36         0x00,0x00,0x00,0x00, 0x00,0x24,0x00,0x23,
37         0x00,0x00,0x23,0x05, 0x00,0x00,0x00,0x00,
38         0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,
39         0x01,0x00,0x00,0x23, 0x00,0x00,0x00,0x40,
40         0x00,0x0c,0x41,0x02, 0x00,0x17,0x00,0x00,
41         0x00,0x00,0x00,0x00,
42         0x00,0x0b,0x04,0x01,
43         0x7e,0x04,0x05,0x00, 0x01,0x01,0x0f,
44         0x00,
45         0x0c,0x04,0x02,0xff, 0xff,0xff,0xff,0xff,
46         0xff,0xff,0xff
47 };
48
49 unsigned char CM_SETUP[]={
50         0x00,0xe0,0x00,0x00, 0x00,0x00,0x00,0x02,
51         0x00,0x00,0x00,0x14, 0x00,0x00,0x00,0x64,
52         0x10,0x00,0x00,0x01,
53         0x00,0x00,0x00,0x00,
54         0x81,0x7e,0x00,0x01, 0x00,0x00,0x00,0x00,
55         0x00,0x00,0x00,0x00, 0x00,0x24,0x00,0x24,
56         0x00,0x00,0x24,0x05, 0x00,0x00,0x00,0x00,
57         0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,
58         0x01,0x00,0x00,0x24, 0x00,0x00,0x00,0x40,
59         0x00,0x0c,0x41,0x04, 0x00,0x18,0x00,0x00,
60         0x00,0x00,0x00,0x00,
61         0x00,0x09,0x04,0x04,
62         0x05,0x00,0x01,0x01, 0x11,
63         0x00,0x09,0x04,
64         0x05,0x05,0x00,0x00, 0x00,0x00,
65         0x00,0x06,
66         0x04,0x06,0xc8,0x00
67 };
68
69 unsigned char ULP_ENABLE[]={
70         0x00,0xe0,0x00,0x00, 0x00,0x00,0x00,0x03,
71         0x00,0x00,0x00,0x14, 0x00,0x00,0x00,0x6b,
72         0x10,0x00,0x00,0x01,
73         0x00,0x00,0x00,0x00,
74         0x41,0x7e,0x00,0x01, 0x00,0x00,0x00,0x01,
75         0x00,0x00,0x00,0x00, 0x00,0x24,0x00,0x2b,
76         0x00,0x00,0x2b,0x05, 0x20,0x01,0x00,0x00,
77         0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,
78         0x01,0x00,0x00,0x2b, 0x00,0x00,0x00,0x40,
79         0x00,0x0c,0x41,0x02, 0x00,0x1f,0x00,0x00,
80         0x00,0x00,0x00,0x00,
81         0x00,0x0b,0x04,0x01,
82         0x03,0x04,0x05,0x00, 0x01,0x01,0x12,
83         0x00,
84         0x14,0x04,0x0a,0x00, 0x20,0x00,0x00,0xff,
85         0xff,0x00,0x08,0xc8, 0xe8,0xc4,0xf1,0xc7,
86         0xf1,0x00,0x00
87 };
88
89 unsigned char ULP_SETUP[]={
90         0x00,0xe0,0x00,0x00, 0x00,0x00,0x00,0x04,
91         0x00,0x00,0x00,0x14, 0x00,0x00,0x00,0x6c,
92         0x10,0x00,0x00,0x01,
93         0x00,0x00,0x00,0x00,
94         0x41,0x7e,0x00,0x01, 0x00,0x00,0x00,0x02,
95         0x00,0x00,0x00,0x01, 0x00,0x24,0x00,0x2c,
96         0x00,0x00,0x2c,0x05, 0x20,0x01,0x00,0x00,
97         0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,
98         0x01,0x00,0x00,0x2c, 0x00,0x00,0x00,0x40,
99         0x00,0x0c,0x41,0x04, 0x00,0x20,0x00,0x00,
100         0x00,0x00,0x00,0x00,
101         0x00,0x09,0x04,0x04,
102         0x05,0x00,0x01,0x01, 0x14,
103         0x00,0x09,0x04,
104         0x05,0x05,0x30,0x01, 0x00,0x00,
105         0x00,0x06,
106         0x04,0x06,0x40,0x00,
107         0x00,0x08,0x04,0x0b,
108         0x00,0x00,0x00,0x00
109 };
110
111 unsigned char DM_ACT[]={
112         0x00,0xe0,0x00,0x00, 0x00,0x00,0x00,0x05,
113         0x00,0x00,0x00,0x14, 0x00,0x00,0x00,0x55,
114         0x10,0x00,0x00,0x01,
115         0x00,0x00,0x00,0x00,
116         0x41,0x7e,0x00,0x01, 0x00,0x00,0x00,0x03,
117         0x00,0x00,0x00,0x02, 0x00,0x24,0x00,0x15,
118         0x00,0x00,0x2c,0x05, 0x20,0x01,0x00,0x00,
119         0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,
120         0x01,0x00,0x00,0x15, 0x00,0x00,0x00,0x40,
121         0x00,0x0c,0x43,0x60, 0x00,0x09,0x00,0x00,
122         0x00,0x00,0x00,0x00,
123         0x00,0x09,0x04,0x04,
124         0x05,0x40,0x01,0x01, 0x00
125 };
126
127 unsigned char IPA_PDU_HEADER[]={
128         0x00,0xe0,0x00,0x00, 0x77,0x77,0x77,0x77,
129         0x00,0x00,0x00,0x14, 0x00,0x00,
130                 (IPA_PDU_HEADER_SIZE+sizeof(struct qeth_ipa_cmd))/256,
131                 (IPA_PDU_HEADER_SIZE+sizeof(struct qeth_ipa_cmd))%256,
132         0x10,0x00,0x00,0x01, 0x00,0x00,0x00,0x00,
133         0xc1,0x03,0x00,0x01, 0x00,0x00,0x00,0x00,
134         0x00,0x00,0x00,0x00, 0x00,0x24,
135                 sizeof(struct qeth_ipa_cmd)/256,
136                 sizeof(struct qeth_ipa_cmd)%256,
137         0x00,
138                 sizeof(struct qeth_ipa_cmd)/256,
139                 sizeof(struct qeth_ipa_cmd)%256,
140         0x05,
141         0x77,0x77,0x77,0x77,
142         0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,
143         0x01,0x00,
144                 sizeof(struct qeth_ipa_cmd)/256,
145                 sizeof(struct qeth_ipa_cmd)%256,
146         0x00,0x00,0x00,0x40,
147 };
148
149 unsigned char WRITE_CCW[]={
150         0x01,CCW_FLAG_SLI,0,0,
151         0,0,0,0
152 };
153
154 unsigned char READ_CCW[]={
155         0x02,CCW_FLAG_SLI,0,0,
156         0,0,0,0
157 };
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