2 Copyright (C) 2004 - 2007 rt2x00 SourceForge Project
3 <http://rt2x00.serialmonkey.com>
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the
17 Free Software Foundation, Inc.,
18 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
23 Abstract: rt61pci device specific routines.
24 Supported chipsets: RT2561, RT2561s, RT2661.
27 #include <linux/delay.h>
28 #include <linux/etherdevice.h>
29 #include <linux/init.h>
30 #include <linux/kernel.h>
31 #include <linux/module.h>
32 #include <linux/pci.h>
33 #include <linux/eeprom_93cx6.h>
36 #include "rt2x00pci.h"
41 * BBP and RF register require indirect register access,
42 * and use the CSR registers PHY_CSR3 and PHY_CSR4 to achieve this.
43 * These indirect registers work with busy bits,
44 * and we will try maximal REGISTER_BUSY_COUNT times to access
45 * the register while taking a REGISTER_BUSY_DELAY us delay
46 * between each attampt. When the busy bit is still set at that time,
47 * the access attempt is considered to have failed,
48 * and we will print an error.
50 static u32 rt61pci_bbp_check(struct rt2x00_dev *rt2x00dev)
55 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
56 rt2x00pci_register_read(rt2x00dev, PHY_CSR3, ®);
57 if (!rt2x00_get_field32(reg, PHY_CSR3_BUSY))
59 udelay(REGISTER_BUSY_DELAY);
65 static void rt61pci_bbp_write(struct rt2x00_dev *rt2x00dev,
66 const unsigned int word, const u8 value)
71 * Wait until the BBP becomes ready.
73 reg = rt61pci_bbp_check(rt2x00dev);
74 if (rt2x00_get_field32(reg, PHY_CSR3_BUSY)) {
75 ERROR(rt2x00dev, "PHY_CSR3 register busy. Write failed.\n");
80 * Write the data into the BBP.
83 rt2x00_set_field32(®, PHY_CSR3_VALUE, value);
84 rt2x00_set_field32(®, PHY_CSR3_REGNUM, word);
85 rt2x00_set_field32(®, PHY_CSR3_BUSY, 1);
86 rt2x00_set_field32(®, PHY_CSR3_READ_CONTROL, 0);
88 rt2x00pci_register_write(rt2x00dev, PHY_CSR3, reg);
91 static void rt61pci_bbp_read(struct rt2x00_dev *rt2x00dev,
92 const unsigned int word, u8 *value)
97 * Wait until the BBP becomes ready.
99 reg = rt61pci_bbp_check(rt2x00dev);
100 if (rt2x00_get_field32(reg, PHY_CSR3_BUSY)) {
101 ERROR(rt2x00dev, "PHY_CSR3 register busy. Read failed.\n");
106 * Write the request into the BBP.
109 rt2x00_set_field32(®, PHY_CSR3_REGNUM, word);
110 rt2x00_set_field32(®, PHY_CSR3_BUSY, 1);
111 rt2x00_set_field32(®, PHY_CSR3_READ_CONTROL, 1);
113 rt2x00pci_register_write(rt2x00dev, PHY_CSR3, reg);
116 * Wait until the BBP becomes ready.
118 reg = rt61pci_bbp_check(rt2x00dev);
119 if (rt2x00_get_field32(reg, PHY_CSR3_BUSY)) {
120 ERROR(rt2x00dev, "PHY_CSR3 register busy. Read failed.\n");
125 *value = rt2x00_get_field32(reg, PHY_CSR3_VALUE);
128 static void rt61pci_rf_write(struct rt2x00_dev *rt2x00dev,
129 const unsigned int word, const u32 value)
137 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
138 rt2x00pci_register_read(rt2x00dev, PHY_CSR4, ®);
139 if (!rt2x00_get_field32(reg, PHY_CSR4_BUSY))
141 udelay(REGISTER_BUSY_DELAY);
144 ERROR(rt2x00dev, "PHY_CSR4 register busy. Write failed.\n");
149 rt2x00_set_field32(®, PHY_CSR4_VALUE, value);
150 rt2x00_set_field32(®, PHY_CSR4_NUMBER_OF_BITS, 21);
151 rt2x00_set_field32(®, PHY_CSR4_IF_SELECT, 0);
152 rt2x00_set_field32(®, PHY_CSR4_BUSY, 1);
154 rt2x00pci_register_write(rt2x00dev, PHY_CSR4, reg);
155 rt2x00_rf_write(rt2x00dev, word, value);
158 static void rt61pci_mcu_request(struct rt2x00_dev *rt2x00dev,
159 const u8 command, const u8 token,
160 const u8 arg0, const u8 arg1)
164 rt2x00pci_register_read(rt2x00dev, H2M_MAILBOX_CSR, ®);
166 if (rt2x00_get_field32(reg, H2M_MAILBOX_CSR_OWNER)) {
167 ERROR(rt2x00dev, "mcu request error. "
168 "Request 0x%02x failed for token 0x%02x.\n",
173 rt2x00_set_field32(®, H2M_MAILBOX_CSR_OWNER, 1);
174 rt2x00_set_field32(®, H2M_MAILBOX_CSR_CMD_TOKEN, token);
175 rt2x00_set_field32(®, H2M_MAILBOX_CSR_ARG0, arg0);
176 rt2x00_set_field32(®, H2M_MAILBOX_CSR_ARG1, arg1);
177 rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CSR, reg);
179 rt2x00pci_register_read(rt2x00dev, HOST_CMD_CSR, ®);
180 rt2x00_set_field32(®, HOST_CMD_CSR_HOST_COMMAND, command);
181 rt2x00_set_field32(®, HOST_CMD_CSR_INTERRUPT_MCU, 1);
182 rt2x00pci_register_write(rt2x00dev, HOST_CMD_CSR, reg);
185 static void rt61pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
187 struct rt2x00_dev *rt2x00dev = eeprom->data;
190 rt2x00pci_register_read(rt2x00dev, E2PROM_CSR, ®);
192 eeprom->reg_data_in = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_IN);
193 eeprom->reg_data_out = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_OUT);
194 eeprom->reg_data_clock =
195 !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_CLOCK);
196 eeprom->reg_chip_select =
197 !!rt2x00_get_field32(reg, E2PROM_CSR_CHIP_SELECT);
200 static void rt61pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
202 struct rt2x00_dev *rt2x00dev = eeprom->data;
205 rt2x00_set_field32(®, E2PROM_CSR_DATA_IN, !!eeprom->reg_data_in);
206 rt2x00_set_field32(®, E2PROM_CSR_DATA_OUT, !!eeprom->reg_data_out);
207 rt2x00_set_field32(®, E2PROM_CSR_DATA_CLOCK,
208 !!eeprom->reg_data_clock);
209 rt2x00_set_field32(®, E2PROM_CSR_CHIP_SELECT,
210 !!eeprom->reg_chip_select);
212 rt2x00pci_register_write(rt2x00dev, E2PROM_CSR, reg);
215 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
216 #define CSR_OFFSET(__word) ( CSR_REG_BASE + ((__word) * sizeof(u32)) )
218 static void rt61pci_read_csr(struct rt2x00_dev *rt2x00dev,
219 const unsigned int word, u32 *data)
221 rt2x00pci_register_read(rt2x00dev, CSR_OFFSET(word), data);
224 static void rt61pci_write_csr(struct rt2x00_dev *rt2x00dev,
225 const unsigned int word, u32 data)
227 rt2x00pci_register_write(rt2x00dev, CSR_OFFSET(word), data);
230 static const struct rt2x00debug rt61pci_rt2x00debug = {
231 .owner = THIS_MODULE,
233 .read = rt61pci_read_csr,
234 .write = rt61pci_write_csr,
235 .word_size = sizeof(u32),
236 .word_count = CSR_REG_SIZE / sizeof(u32),
239 .read = rt2x00_eeprom_read,
240 .write = rt2x00_eeprom_write,
241 .word_size = sizeof(u16),
242 .word_count = EEPROM_SIZE / sizeof(u16),
245 .read = rt61pci_bbp_read,
246 .write = rt61pci_bbp_write,
247 .word_size = sizeof(u8),
248 .word_count = BBP_SIZE / sizeof(u8),
251 .read = rt2x00_rf_read,
252 .write = rt61pci_rf_write,
253 .word_size = sizeof(u32),
254 .word_count = RF_SIZE / sizeof(u32),
257 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
259 #ifdef CONFIG_RT61PCI_RFKILL
260 static int rt61pci_rfkill_poll(struct rt2x00_dev *rt2x00dev)
264 rt2x00pci_register_read(rt2x00dev, MAC_CSR13, ®);
265 return rt2x00_get_field32(reg, MAC_CSR13_BIT5);;
268 #define rt61pci_rfkill_poll NULL
269 #endif /* CONFIG_RT61PCI_RFKILL */
272 * Configuration handlers.
274 static void rt61pci_config_mac_addr(struct rt2x00_dev *rt2x00dev, __le32 *mac)
278 tmp = le32_to_cpu(mac[1]);
279 rt2x00_set_field32(&tmp, MAC_CSR3_UNICAST_TO_ME_MASK, 0xff);
280 mac[1] = cpu_to_le32(tmp);
282 rt2x00pci_register_multiwrite(rt2x00dev, MAC_CSR2, mac,
283 (2 * sizeof(__le32)));
286 static void rt61pci_config_bssid(struct rt2x00_dev *rt2x00dev, __le32 *bssid)
290 tmp = le32_to_cpu(bssid[1]);
291 rt2x00_set_field32(&tmp, MAC_CSR5_BSS_ID_MASK, 3);
292 bssid[1] = cpu_to_le32(tmp);
294 rt2x00pci_register_multiwrite(rt2x00dev, MAC_CSR4, bssid,
295 (2 * sizeof(__le32)));
298 static void rt61pci_config_type(struct rt2x00_dev *rt2x00dev, const int type,
304 * Clear current synchronisation setup.
305 * For the Beacon base registers we only need to clear
306 * the first byte since that byte contains the VALID and OWNER
307 * bits which (when set to 0) will invalidate the entire beacon.
309 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, 0);
310 rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE0, 0);
311 rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE1, 0);
312 rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE2, 0);
313 rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE3, 0);
316 * Enable synchronisation.
318 rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, ®);
319 rt2x00_set_field32(®, TXRX_CSR9_TSF_TICKING, 1);
320 rt2x00_set_field32(®, TXRX_CSR9_TBTT_ENABLE,
321 (tsf_sync == TSF_SYNC_BEACON));
322 rt2x00_set_field32(®, TXRX_CSR9_BEACON_GEN, 0);
323 rt2x00_set_field32(®, TXRX_CSR9_TSF_SYNC, tsf_sync);
324 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
327 static void rt61pci_config_preamble(struct rt2x00_dev *rt2x00dev,
328 const int short_preamble,
329 const int ack_timeout,
330 const int ack_consume_time)
334 rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, ®);
335 rt2x00_set_field32(®, TXRX_CSR0_RX_ACK_TIMEOUT, ack_timeout);
336 rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
338 rt2x00pci_register_read(rt2x00dev, TXRX_CSR4, ®);
339 rt2x00_set_field32(®, TXRX_CSR4_AUTORESPOND_PREAMBLE,
341 rt2x00pci_register_write(rt2x00dev, TXRX_CSR4, reg);
344 static void rt61pci_config_phymode(struct rt2x00_dev *rt2x00dev,
345 const int basic_rate_mask)
347 rt2x00pci_register_write(rt2x00dev, TXRX_CSR5, basic_rate_mask);
350 static void rt61pci_config_channel(struct rt2x00_dev *rt2x00dev,
351 struct rf_channel *rf, const int txpower)
357 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
358 rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
360 smart = !(rt2x00_rf(&rt2x00dev->chip, RF5225) ||
361 rt2x00_rf(&rt2x00dev->chip, RF2527));
363 rt61pci_bbp_read(rt2x00dev, 3, &r3);
364 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, smart);
365 rt61pci_bbp_write(rt2x00dev, 3, r3);
368 if (txpower > MAX_TXPOWER && txpower <= (MAX_TXPOWER + r94))
369 r94 += txpower - MAX_TXPOWER;
370 else if (txpower < MIN_TXPOWER && txpower >= (MIN_TXPOWER - r94))
372 rt61pci_bbp_write(rt2x00dev, 94, r94);
374 rt61pci_rf_write(rt2x00dev, 1, rf->rf1);
375 rt61pci_rf_write(rt2x00dev, 2, rf->rf2);
376 rt61pci_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
377 rt61pci_rf_write(rt2x00dev, 4, rf->rf4);
381 rt61pci_rf_write(rt2x00dev, 1, rf->rf1);
382 rt61pci_rf_write(rt2x00dev, 2, rf->rf2);
383 rt61pci_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
384 rt61pci_rf_write(rt2x00dev, 4, rf->rf4);
388 rt61pci_rf_write(rt2x00dev, 1, rf->rf1);
389 rt61pci_rf_write(rt2x00dev, 2, rf->rf2);
390 rt61pci_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
391 rt61pci_rf_write(rt2x00dev, 4, rf->rf4);
396 static void rt61pci_config_txpower(struct rt2x00_dev *rt2x00dev,
399 struct rf_channel rf;
401 rt2x00_rf_read(rt2x00dev, 1, &rf.rf1);
402 rt2x00_rf_read(rt2x00dev, 2, &rf.rf2);
403 rt2x00_rf_read(rt2x00dev, 3, &rf.rf3);
404 rt2x00_rf_read(rt2x00dev, 4, &rf.rf4);
406 rt61pci_config_channel(rt2x00dev, &rf, txpower);
409 static void rt61pci_config_antenna_5x(struct rt2x00_dev *rt2x00dev,
410 struct antenna_setup *ant)
416 rt61pci_bbp_read(rt2x00dev, 3, &r3);
417 rt61pci_bbp_read(rt2x00dev, 4, &r4);
418 rt61pci_bbp_read(rt2x00dev, 77, &r77);
420 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE,
421 rt2x00_rf(&rt2x00dev->chip, RF5325));
424 * Configure the RX antenna.
427 case ANTENNA_HW_DIVERSITY:
428 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 2);
429 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END,
430 (rt2x00dev->curr_hwmode != HWMODE_A));
433 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
434 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
435 if (rt2x00dev->curr_hwmode == HWMODE_A)
436 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
438 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
440 case ANTENNA_SW_DIVERSITY:
442 * NOTE: We should never come here because rt2x00lib is
443 * supposed to catch this and send us the correct antenna
444 * explicitely. However we are nog going to bug about this.
445 * Instead, just default to antenna B.
448 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
449 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
450 if (rt2x00dev->curr_hwmode == HWMODE_A)
451 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
453 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
457 rt61pci_bbp_write(rt2x00dev, 77, r77);
458 rt61pci_bbp_write(rt2x00dev, 3, r3);
459 rt61pci_bbp_write(rt2x00dev, 4, r4);
462 static void rt61pci_config_antenna_2x(struct rt2x00_dev *rt2x00dev,
463 struct antenna_setup *ant)
469 rt61pci_bbp_read(rt2x00dev, 3, &r3);
470 rt61pci_bbp_read(rt2x00dev, 4, &r4);
471 rt61pci_bbp_read(rt2x00dev, 77, &r77);
473 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE,
474 rt2x00_rf(&rt2x00dev->chip, RF2529));
475 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END,
476 !test_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags));
479 * Configure the RX antenna.
482 case ANTENNA_HW_DIVERSITY:
483 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 2);
486 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
487 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
489 case ANTENNA_SW_DIVERSITY:
491 * NOTE: We should never come here because rt2x00lib is
492 * supposed to catch this and send us the correct antenna
493 * explicitely. However we are nog going to bug about this.
494 * Instead, just default to antenna B.
497 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
498 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
502 rt61pci_bbp_write(rt2x00dev, 77, r77);
503 rt61pci_bbp_write(rt2x00dev, 3, r3);
504 rt61pci_bbp_write(rt2x00dev, 4, r4);
507 static void rt61pci_config_antenna_2529_rx(struct rt2x00_dev *rt2x00dev,
508 const int p1, const int p2)
512 rt2x00pci_register_read(rt2x00dev, MAC_CSR13, ®);
514 rt2x00_set_field32(®, MAC_CSR13_BIT4, p1);
515 rt2x00_set_field32(®, MAC_CSR13_BIT12, 0);
517 rt2x00_set_field32(®, MAC_CSR13_BIT3, !p2);
518 rt2x00_set_field32(®, MAC_CSR13_BIT11, 0);
520 rt2x00pci_register_write(rt2x00dev, MAC_CSR13, reg);
523 static void rt61pci_config_antenna_2529(struct rt2x00_dev *rt2x00dev,
524 struct antenna_setup *ant)
530 rt61pci_bbp_read(rt2x00dev, 3, &r3);
531 rt61pci_bbp_read(rt2x00dev, 4, &r4);
532 rt61pci_bbp_read(rt2x00dev, 77, &r77);
534 /* FIXME: Antenna selection for the rf 2529 is very confusing in the
535 * legacy driver. The code below should be ok for non-diversity setups.
539 * Configure the RX antenna.
543 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
544 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
545 rt61pci_config_antenna_2529_rx(rt2x00dev, 0, 0);
547 case ANTENNA_SW_DIVERSITY:
548 case ANTENNA_HW_DIVERSITY:
550 * NOTE: We should never come here because rt2x00lib is
551 * supposed to catch this and send us the correct antenna
552 * explicitely. However we are nog going to bug about this.
553 * Instead, just default to antenna B.
556 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
557 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
558 rt61pci_config_antenna_2529_rx(rt2x00dev, 1, 1);
562 rt61pci_bbp_write(rt2x00dev, 77, r77);
563 rt61pci_bbp_write(rt2x00dev, 3, r3);
564 rt61pci_bbp_write(rt2x00dev, 4, r4);
570 * value[0] -> non-LNA
576 static const struct antenna_sel antenna_sel_a[] = {
577 { 96, { 0x58, 0x78 } },
578 { 104, { 0x38, 0x48 } },
579 { 75, { 0xfe, 0x80 } },
580 { 86, { 0xfe, 0x80 } },
581 { 88, { 0xfe, 0x80 } },
582 { 35, { 0x60, 0x60 } },
583 { 97, { 0x58, 0x58 } },
584 { 98, { 0x58, 0x58 } },
587 static const struct antenna_sel antenna_sel_bg[] = {
588 { 96, { 0x48, 0x68 } },
589 { 104, { 0x2c, 0x3c } },
590 { 75, { 0xfe, 0x80 } },
591 { 86, { 0xfe, 0x80 } },
592 { 88, { 0xfe, 0x80 } },
593 { 35, { 0x50, 0x50 } },
594 { 97, { 0x48, 0x48 } },
595 { 98, { 0x48, 0x48 } },
598 static void rt61pci_config_antenna(struct rt2x00_dev *rt2x00dev,
599 struct antenna_setup *ant)
601 const struct antenna_sel *sel;
606 if (rt2x00dev->curr_hwmode == HWMODE_A) {
608 lna = test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
610 sel = antenna_sel_bg;
611 lna = test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
614 for (i = 0; i < ARRAY_SIZE(antenna_sel_a); i++)
615 rt61pci_bbp_write(rt2x00dev, sel[i].word, sel[i].value[lna]);
617 rt2x00pci_register_read(rt2x00dev, PHY_CSR0, ®);
619 rt2x00_set_field32(®, PHY_CSR0_PA_PE_BG,
620 (rt2x00dev->curr_hwmode == HWMODE_B ||
621 rt2x00dev->curr_hwmode == HWMODE_G));
622 rt2x00_set_field32(®, PHY_CSR0_PA_PE_A,
623 (rt2x00dev->curr_hwmode == HWMODE_A));
625 rt2x00pci_register_write(rt2x00dev, PHY_CSR0, reg);
627 if (rt2x00_rf(&rt2x00dev->chip, RF5225) ||
628 rt2x00_rf(&rt2x00dev->chip, RF5325))
629 rt61pci_config_antenna_5x(rt2x00dev, ant);
630 else if (rt2x00_rf(&rt2x00dev->chip, RF2527))
631 rt61pci_config_antenna_2x(rt2x00dev, ant);
632 else if (rt2x00_rf(&rt2x00dev->chip, RF2529)) {
633 if (test_bit(CONFIG_DOUBLE_ANTENNA, &rt2x00dev->flags))
634 rt61pci_config_antenna_2x(rt2x00dev, ant);
636 rt61pci_config_antenna_2529(rt2x00dev, ant);
640 static void rt61pci_config_duration(struct rt2x00_dev *rt2x00dev,
641 struct rt2x00lib_conf *libconf)
645 rt2x00pci_register_read(rt2x00dev, MAC_CSR9, ®);
646 rt2x00_set_field32(®, MAC_CSR9_SLOT_TIME, libconf->slot_time);
647 rt2x00pci_register_write(rt2x00dev, MAC_CSR9, reg);
649 rt2x00pci_register_read(rt2x00dev, MAC_CSR8, ®);
650 rt2x00_set_field32(®, MAC_CSR8_SIFS, libconf->sifs);
651 rt2x00_set_field32(®, MAC_CSR8_SIFS_AFTER_RX_OFDM, 3);
652 rt2x00_set_field32(®, MAC_CSR8_EIFS, libconf->eifs);
653 rt2x00pci_register_write(rt2x00dev, MAC_CSR8, reg);
655 rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, ®);
656 rt2x00_set_field32(®, TXRX_CSR0_TSF_OFFSET, IEEE80211_HEADER);
657 rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
659 rt2x00pci_register_read(rt2x00dev, TXRX_CSR4, ®);
660 rt2x00_set_field32(®, TXRX_CSR4_AUTORESPOND_ENABLE, 1);
661 rt2x00pci_register_write(rt2x00dev, TXRX_CSR4, reg);
663 rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, ®);
664 rt2x00_set_field32(®, TXRX_CSR9_BEACON_INTERVAL,
665 libconf->conf->beacon_int * 16);
666 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
669 static void rt61pci_config(struct rt2x00_dev *rt2x00dev,
670 const unsigned int flags,
671 struct rt2x00lib_conf *libconf)
673 if (flags & CONFIG_UPDATE_PHYMODE)
674 rt61pci_config_phymode(rt2x00dev, libconf->basic_rates);
675 if (flags & CONFIG_UPDATE_CHANNEL)
676 rt61pci_config_channel(rt2x00dev, &libconf->rf,
677 libconf->conf->power_level);
678 if ((flags & CONFIG_UPDATE_TXPOWER) && !(flags & CONFIG_UPDATE_CHANNEL))
679 rt61pci_config_txpower(rt2x00dev, libconf->conf->power_level);
680 if (flags & CONFIG_UPDATE_ANTENNA)
681 rt61pci_config_antenna(rt2x00dev, &libconf->ant);
682 if (flags & (CONFIG_UPDATE_SLOT_TIME | CONFIG_UPDATE_BEACON_INT))
683 rt61pci_config_duration(rt2x00dev, libconf);
689 static void rt61pci_enable_led(struct rt2x00_dev *rt2x00dev)
695 rt2x00pci_register_read(rt2x00dev, MAC_CSR14, ®);
696 rt2x00_set_field32(®, MAC_CSR14_ON_PERIOD, 70);
697 rt2x00_set_field32(®, MAC_CSR14_OFF_PERIOD, 30);
698 rt2x00pci_register_write(rt2x00dev, MAC_CSR14, reg);
700 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_RADIO_STATUS, 1);
701 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_LINK_A_STATUS,
702 (rt2x00dev->rx_status.phymode == MODE_IEEE80211A));
703 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_LINK_BG_STATUS,
704 (rt2x00dev->rx_status.phymode != MODE_IEEE80211A));
706 arg0 = rt2x00dev->led_reg & 0xff;
707 arg1 = (rt2x00dev->led_reg >> 8) & 0xff;
709 rt61pci_mcu_request(rt2x00dev, MCU_LED, 0xff, arg0, arg1);
712 static void rt61pci_disable_led(struct rt2x00_dev *rt2x00dev)
718 led_reg = rt2x00dev->led_reg;
719 rt2x00_set_field16(&led_reg, MCU_LEDCS_RADIO_STATUS, 0);
720 rt2x00_set_field16(&led_reg, MCU_LEDCS_LINK_BG_STATUS, 0);
721 rt2x00_set_field16(&led_reg, MCU_LEDCS_LINK_A_STATUS, 0);
723 arg0 = led_reg & 0xff;
724 arg1 = (led_reg >> 8) & 0xff;
726 rt61pci_mcu_request(rt2x00dev, MCU_LED, 0xff, arg0, arg1);
729 static void rt61pci_activity_led(struct rt2x00_dev *rt2x00dev, int rssi)
733 if (rt2x00dev->led_mode != LED_MODE_SIGNAL_STRENGTH)
737 * Led handling requires a positive value for the rssi,
738 * to do that correctly we need to add the correction.
740 rssi += rt2x00dev->rssi_offset;
755 rt61pci_mcu_request(rt2x00dev, MCU_LED_STRENGTH, 0xff, led, 0);
761 static void rt61pci_link_stats(struct rt2x00_dev *rt2x00dev,
762 struct link_qual *qual)
767 * Update FCS error count from register.
769 rt2x00pci_register_read(rt2x00dev, STA_CSR0, ®);
770 qual->rx_failed = rt2x00_get_field32(reg, STA_CSR0_FCS_ERROR);
773 * Update False CCA count from register.
775 rt2x00pci_register_read(rt2x00dev, STA_CSR1, ®);
776 qual->false_cca = rt2x00_get_field32(reg, STA_CSR1_FALSE_CCA_ERROR);
779 static void rt61pci_reset_tuner(struct rt2x00_dev *rt2x00dev)
781 rt61pci_bbp_write(rt2x00dev, 17, 0x20);
782 rt2x00dev->link.vgc_level = 0x20;
785 static void rt61pci_link_tuner(struct rt2x00_dev *rt2x00dev)
787 int rssi = rt2x00_get_link_rssi(&rt2x00dev->link);
793 * Update Led strength
795 rt61pci_activity_led(rt2x00dev, rssi);
797 rt61pci_bbp_read(rt2x00dev, 17, &r17);
800 * Determine r17 bounds.
802 if (rt2x00dev->rx_status.phymode == MODE_IEEE80211A) {
805 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags)) {
812 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags)) {
819 * Special big-R17 for very short distance
823 rt61pci_bbp_write(rt2x00dev, 17, 0x60);
828 * Special big-R17 for short distance
832 rt61pci_bbp_write(rt2x00dev, 17, up_bound);
837 * Special big-R17 for middle-short distance
841 if (r17 != low_bound)
842 rt61pci_bbp_write(rt2x00dev, 17, low_bound);
847 * Special mid-R17 for middle distance
851 if (r17 != low_bound)
852 rt61pci_bbp_write(rt2x00dev, 17, low_bound);
857 * Special case: Change up_bound based on the rssi.
858 * Lower up_bound when rssi is weaker then -74 dBm.
860 up_bound -= 2 * (-74 - rssi);
861 if (low_bound > up_bound)
862 up_bound = low_bound;
864 if (r17 > up_bound) {
865 rt61pci_bbp_write(rt2x00dev, 17, up_bound);
870 * r17 does not yet exceed upper limit, continue and base
871 * the r17 tuning on the false CCA count.
873 if (rt2x00dev->link.qual.false_cca > 512 && r17 < up_bound) {
874 if (++r17 > up_bound)
876 rt61pci_bbp_write(rt2x00dev, 17, r17);
877 } else if (rt2x00dev->link.qual.false_cca < 100 && r17 > low_bound) {
878 if (--r17 < low_bound)
880 rt61pci_bbp_write(rt2x00dev, 17, r17);
885 * Firmware name function.
887 static char *rt61pci_get_firmware_name(struct rt2x00_dev *rt2x00dev)
891 switch (rt2x00dev->chip.rt) {
893 fw_name = FIRMWARE_RT2561;
896 fw_name = FIRMWARE_RT2561s;
899 fw_name = FIRMWARE_RT2661;
910 * Initialization functions.
912 static int rt61pci_load_firmware(struct rt2x00_dev *rt2x00dev, void *data,
919 * Wait for stable hardware.
921 for (i = 0; i < 100; i++) {
922 rt2x00pci_register_read(rt2x00dev, MAC_CSR0, ®);
929 ERROR(rt2x00dev, "Unstable hardware.\n");
934 * Prepare MCU and mailbox for firmware loading.
937 rt2x00_set_field32(®, MCU_CNTL_CSR_RESET, 1);
938 rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
939 rt2x00pci_register_write(rt2x00dev, M2H_CMD_DONE_CSR, 0xffffffff);
940 rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
941 rt2x00pci_register_write(rt2x00dev, HOST_CMD_CSR, 0);
944 * Write firmware to device.
947 rt2x00_set_field32(®, MCU_CNTL_CSR_RESET, 1);
948 rt2x00_set_field32(®, MCU_CNTL_CSR_SELECT_BANK, 1);
949 rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
951 rt2x00pci_register_multiwrite(rt2x00dev, FIRMWARE_IMAGE_BASE,
954 rt2x00_set_field32(®, MCU_CNTL_CSR_SELECT_BANK, 0);
955 rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
957 rt2x00_set_field32(®, MCU_CNTL_CSR_RESET, 0);
958 rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
960 for (i = 0; i < 100; i++) {
961 rt2x00pci_register_read(rt2x00dev, MCU_CNTL_CSR, ®);
962 if (rt2x00_get_field32(reg, MCU_CNTL_CSR_READY))
968 ERROR(rt2x00dev, "MCU Control register not ready.\n");
973 * Reset MAC and BBP registers.
976 rt2x00_set_field32(®, MAC_CSR1_SOFT_RESET, 1);
977 rt2x00_set_field32(®, MAC_CSR1_BBP_RESET, 1);
978 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
980 rt2x00pci_register_read(rt2x00dev, MAC_CSR1, ®);
981 rt2x00_set_field32(®, MAC_CSR1_SOFT_RESET, 0);
982 rt2x00_set_field32(®, MAC_CSR1_BBP_RESET, 0);
983 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
985 rt2x00pci_register_read(rt2x00dev, MAC_CSR1, ®);
986 rt2x00_set_field32(®, MAC_CSR1_HOST_READY, 1);
987 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
992 static void rt61pci_init_rxentry(struct rt2x00_dev *rt2x00dev,
993 struct data_entry *entry)
995 __le32 *rxd = entry->priv;
998 rt2x00_desc_read(rxd, 5, &word);
999 rt2x00_set_field32(&word, RXD_W5_BUFFER_PHYSICAL_ADDRESS,
1001 rt2x00_desc_write(rxd, 5, word);
1003 rt2x00_desc_read(rxd, 0, &word);
1004 rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1);
1005 rt2x00_desc_write(rxd, 0, word);
1008 static void rt61pci_init_txentry(struct rt2x00_dev *rt2x00dev,
1009 struct data_entry *entry)
1011 __le32 *txd = entry->priv;
1014 rt2x00_desc_read(txd, 1, &word);
1015 rt2x00_set_field32(&word, TXD_W1_BUFFER_COUNT, 1);
1016 rt2x00_desc_write(txd, 1, word);
1018 rt2x00_desc_read(txd, 5, &word);
1019 rt2x00_set_field32(&word, TXD_W5_PID_TYPE, entry->ring->queue_idx);
1020 rt2x00_set_field32(&word, TXD_W5_PID_SUBTYPE, entry->entry_idx);
1021 rt2x00_desc_write(txd, 5, word);
1023 rt2x00_desc_read(txd, 6, &word);
1024 rt2x00_set_field32(&word, TXD_W6_BUFFER_PHYSICAL_ADDRESS,
1026 rt2x00_desc_write(txd, 6, word);
1028 rt2x00_desc_read(txd, 0, &word);
1029 rt2x00_set_field32(&word, TXD_W0_VALID, 0);
1030 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0);
1031 rt2x00_desc_write(txd, 0, word);
1034 static int rt61pci_init_rings(struct rt2x00_dev *rt2x00dev)
1039 * Initialize registers.
1041 rt2x00pci_register_read(rt2x00dev, TX_RING_CSR0, ®);
1042 rt2x00_set_field32(®, TX_RING_CSR0_AC0_RING_SIZE,
1043 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA0].stats.limit);
1044 rt2x00_set_field32(®, TX_RING_CSR0_AC1_RING_SIZE,
1045 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA1].stats.limit);
1046 rt2x00_set_field32(®, TX_RING_CSR0_AC2_RING_SIZE,
1047 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA2].stats.limit);
1048 rt2x00_set_field32(®, TX_RING_CSR0_AC3_RING_SIZE,
1049 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA3].stats.limit);
1050 rt2x00pci_register_write(rt2x00dev, TX_RING_CSR0, reg);
1052 rt2x00pci_register_read(rt2x00dev, TX_RING_CSR1, ®);
1053 rt2x00_set_field32(®, TX_RING_CSR1_MGMT_RING_SIZE,
1054 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA4].stats.limit);
1055 rt2x00_set_field32(®, TX_RING_CSR1_TXD_SIZE,
1056 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA0].desc_size /
1058 rt2x00pci_register_write(rt2x00dev, TX_RING_CSR1, reg);
1060 rt2x00pci_register_read(rt2x00dev, AC0_BASE_CSR, ®);
1061 rt2x00_set_field32(®, AC0_BASE_CSR_RING_REGISTER,
1062 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA0].data_dma);
1063 rt2x00pci_register_write(rt2x00dev, AC0_BASE_CSR, reg);
1065 rt2x00pci_register_read(rt2x00dev, AC1_BASE_CSR, ®);
1066 rt2x00_set_field32(®, AC1_BASE_CSR_RING_REGISTER,
1067 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA1].data_dma);
1068 rt2x00pci_register_write(rt2x00dev, AC1_BASE_CSR, reg);
1070 rt2x00pci_register_read(rt2x00dev, AC2_BASE_CSR, ®);
1071 rt2x00_set_field32(®, AC2_BASE_CSR_RING_REGISTER,
1072 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA2].data_dma);
1073 rt2x00pci_register_write(rt2x00dev, AC2_BASE_CSR, reg);
1075 rt2x00pci_register_read(rt2x00dev, AC3_BASE_CSR, ®);
1076 rt2x00_set_field32(®, AC3_BASE_CSR_RING_REGISTER,
1077 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA3].data_dma);
1078 rt2x00pci_register_write(rt2x00dev, AC3_BASE_CSR, reg);
1080 rt2x00pci_register_read(rt2x00dev, MGMT_BASE_CSR, ®);
1081 rt2x00_set_field32(®, MGMT_BASE_CSR_RING_REGISTER,
1082 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA4].data_dma);
1083 rt2x00pci_register_write(rt2x00dev, MGMT_BASE_CSR, reg);
1085 rt2x00pci_register_read(rt2x00dev, RX_RING_CSR, ®);
1086 rt2x00_set_field32(®, RX_RING_CSR_RING_SIZE,
1087 rt2x00dev->rx->stats.limit);
1088 rt2x00_set_field32(®, RX_RING_CSR_RXD_SIZE,
1089 rt2x00dev->rx->desc_size / 4);
1090 rt2x00_set_field32(®, RX_RING_CSR_RXD_WRITEBACK_SIZE, 4);
1091 rt2x00pci_register_write(rt2x00dev, RX_RING_CSR, reg);
1093 rt2x00pci_register_read(rt2x00dev, RX_BASE_CSR, ®);
1094 rt2x00_set_field32(®, RX_BASE_CSR_RING_REGISTER,
1095 rt2x00dev->rx->data_dma);
1096 rt2x00pci_register_write(rt2x00dev, RX_BASE_CSR, reg);
1098 rt2x00pci_register_read(rt2x00dev, TX_DMA_DST_CSR, ®);
1099 rt2x00_set_field32(®, TX_DMA_DST_CSR_DEST_AC0, 2);
1100 rt2x00_set_field32(®, TX_DMA_DST_CSR_DEST_AC1, 2);
1101 rt2x00_set_field32(®, TX_DMA_DST_CSR_DEST_AC2, 2);
1102 rt2x00_set_field32(®, TX_DMA_DST_CSR_DEST_AC3, 2);
1103 rt2x00_set_field32(®, TX_DMA_DST_CSR_DEST_MGMT, 0);
1104 rt2x00pci_register_write(rt2x00dev, TX_DMA_DST_CSR, reg);
1106 rt2x00pci_register_read(rt2x00dev, LOAD_TX_RING_CSR, ®);
1107 rt2x00_set_field32(®, LOAD_TX_RING_CSR_LOAD_TXD_AC0, 1);
1108 rt2x00_set_field32(®, LOAD_TX_RING_CSR_LOAD_TXD_AC1, 1);
1109 rt2x00_set_field32(®, LOAD_TX_RING_CSR_LOAD_TXD_AC2, 1);
1110 rt2x00_set_field32(®, LOAD_TX_RING_CSR_LOAD_TXD_AC3, 1);
1111 rt2x00_set_field32(®, LOAD_TX_RING_CSR_LOAD_TXD_MGMT, 1);
1112 rt2x00pci_register_write(rt2x00dev, LOAD_TX_RING_CSR, reg);
1114 rt2x00pci_register_read(rt2x00dev, RX_CNTL_CSR, ®);
1115 rt2x00_set_field32(®, RX_CNTL_CSR_LOAD_RXD, 1);
1116 rt2x00pci_register_write(rt2x00dev, RX_CNTL_CSR, reg);
1121 static int rt61pci_init_registers(struct rt2x00_dev *rt2x00dev)
1125 rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, ®);
1126 rt2x00_set_field32(®, TXRX_CSR0_AUTO_TX_SEQ, 1);
1127 rt2x00_set_field32(®, TXRX_CSR0_DISABLE_RX, 0);
1128 rt2x00_set_field32(®, TXRX_CSR0_TX_WITHOUT_WAITING, 0);
1129 rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
1131 rt2x00pci_register_read(rt2x00dev, TXRX_CSR1, ®);
1132 rt2x00_set_field32(®, TXRX_CSR1_BBP_ID0, 47); /* CCK Signal */
1133 rt2x00_set_field32(®, TXRX_CSR1_BBP_ID0_VALID, 1);
1134 rt2x00_set_field32(®, TXRX_CSR1_BBP_ID1, 30); /* Rssi */
1135 rt2x00_set_field32(®, TXRX_CSR1_BBP_ID1_VALID, 1);
1136 rt2x00_set_field32(®, TXRX_CSR1_BBP_ID2, 42); /* OFDM Rate */
1137 rt2x00_set_field32(®, TXRX_CSR1_BBP_ID2_VALID, 1);
1138 rt2x00_set_field32(®, TXRX_CSR1_BBP_ID3, 30); /* Rssi */
1139 rt2x00_set_field32(®, TXRX_CSR1_BBP_ID3_VALID, 1);
1140 rt2x00pci_register_write(rt2x00dev, TXRX_CSR1, reg);
1143 * CCK TXD BBP registers
1145 rt2x00pci_register_read(rt2x00dev, TXRX_CSR2, ®);
1146 rt2x00_set_field32(®, TXRX_CSR2_BBP_ID0, 13);
1147 rt2x00_set_field32(®, TXRX_CSR2_BBP_ID0_VALID, 1);
1148 rt2x00_set_field32(®, TXRX_CSR2_BBP_ID1, 12);
1149 rt2x00_set_field32(®, TXRX_CSR2_BBP_ID1_VALID, 1);
1150 rt2x00_set_field32(®, TXRX_CSR2_BBP_ID2, 11);
1151 rt2x00_set_field32(®, TXRX_CSR2_BBP_ID2_VALID, 1);
1152 rt2x00_set_field32(®, TXRX_CSR2_BBP_ID3, 10);
1153 rt2x00_set_field32(®, TXRX_CSR2_BBP_ID3_VALID, 1);
1154 rt2x00pci_register_write(rt2x00dev, TXRX_CSR2, reg);
1157 * OFDM TXD BBP registers
1159 rt2x00pci_register_read(rt2x00dev, TXRX_CSR3, ®);
1160 rt2x00_set_field32(®, TXRX_CSR3_BBP_ID0, 7);
1161 rt2x00_set_field32(®, TXRX_CSR3_BBP_ID0_VALID, 1);
1162 rt2x00_set_field32(®, TXRX_CSR3_BBP_ID1, 6);
1163 rt2x00_set_field32(®, TXRX_CSR3_BBP_ID1_VALID, 1);
1164 rt2x00_set_field32(®, TXRX_CSR3_BBP_ID2, 5);
1165 rt2x00_set_field32(®, TXRX_CSR3_BBP_ID2_VALID, 1);
1166 rt2x00pci_register_write(rt2x00dev, TXRX_CSR3, reg);
1168 rt2x00pci_register_read(rt2x00dev, TXRX_CSR7, ®);
1169 rt2x00_set_field32(®, TXRX_CSR7_ACK_CTS_6MBS, 59);
1170 rt2x00_set_field32(®, TXRX_CSR7_ACK_CTS_9MBS, 53);
1171 rt2x00_set_field32(®, TXRX_CSR7_ACK_CTS_12MBS, 49);
1172 rt2x00_set_field32(®, TXRX_CSR7_ACK_CTS_18MBS, 46);
1173 rt2x00pci_register_write(rt2x00dev, TXRX_CSR7, reg);
1175 rt2x00pci_register_read(rt2x00dev, TXRX_CSR8, ®);
1176 rt2x00_set_field32(®, TXRX_CSR8_ACK_CTS_24MBS, 44);
1177 rt2x00_set_field32(®, TXRX_CSR8_ACK_CTS_36MBS, 42);
1178 rt2x00_set_field32(®, TXRX_CSR8_ACK_CTS_48MBS, 42);
1179 rt2x00_set_field32(®, TXRX_CSR8_ACK_CTS_54MBS, 42);
1180 rt2x00pci_register_write(rt2x00dev, TXRX_CSR8, reg);
1182 rt2x00pci_register_write(rt2x00dev, TXRX_CSR15, 0x0000000f);
1184 rt2x00pci_register_write(rt2x00dev, MAC_CSR6, 0x00000fff);
1186 rt2x00pci_register_read(rt2x00dev, MAC_CSR9, ®);
1187 rt2x00_set_field32(®, MAC_CSR9_CW_SELECT, 0);
1188 rt2x00pci_register_write(rt2x00dev, MAC_CSR9, reg);
1190 rt2x00pci_register_write(rt2x00dev, MAC_CSR10, 0x0000071c);
1192 if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
1195 rt2x00pci_register_write(rt2x00dev, MAC_CSR13, 0x0000e000);
1198 * Invalidate all Shared Keys (SEC_CSR0),
1199 * and clear the Shared key Cipher algorithms (SEC_CSR1 & SEC_CSR5)
1201 rt2x00pci_register_write(rt2x00dev, SEC_CSR0, 0x00000000);
1202 rt2x00pci_register_write(rt2x00dev, SEC_CSR1, 0x00000000);
1203 rt2x00pci_register_write(rt2x00dev, SEC_CSR5, 0x00000000);
1205 rt2x00pci_register_write(rt2x00dev, PHY_CSR1, 0x000023b0);
1206 rt2x00pci_register_write(rt2x00dev, PHY_CSR5, 0x060a100c);
1207 rt2x00pci_register_write(rt2x00dev, PHY_CSR6, 0x00080606);
1208 rt2x00pci_register_write(rt2x00dev, PHY_CSR7, 0x00000a08);
1210 rt2x00pci_register_write(rt2x00dev, PCI_CFG_CSR, 0x28ca4404);
1212 rt2x00pci_register_write(rt2x00dev, TEST_MODE_CSR, 0x00000200);
1214 rt2x00pci_register_write(rt2x00dev, M2H_CMD_DONE_CSR, 0xffffffff);
1216 rt2x00pci_register_read(rt2x00dev, AC_TXOP_CSR0, ®);
1217 rt2x00_set_field32(®, AC_TXOP_CSR0_AC0_TX_OP, 0);
1218 rt2x00_set_field32(®, AC_TXOP_CSR0_AC1_TX_OP, 0);
1219 rt2x00pci_register_write(rt2x00dev, AC_TXOP_CSR0, reg);
1221 rt2x00pci_register_read(rt2x00dev, AC_TXOP_CSR1, ®);
1222 rt2x00_set_field32(®, AC_TXOP_CSR1_AC2_TX_OP, 192);
1223 rt2x00_set_field32(®, AC_TXOP_CSR1_AC3_TX_OP, 48);
1224 rt2x00pci_register_write(rt2x00dev, AC_TXOP_CSR1, reg);
1227 * We must clear the error counters.
1228 * These registers are cleared on read,
1229 * so we may pass a useless variable to store the value.
1231 rt2x00pci_register_read(rt2x00dev, STA_CSR0, ®);
1232 rt2x00pci_register_read(rt2x00dev, STA_CSR1, ®);
1233 rt2x00pci_register_read(rt2x00dev, STA_CSR2, ®);
1236 * Reset MAC and BBP registers.
1238 rt2x00pci_register_read(rt2x00dev, MAC_CSR1, ®);
1239 rt2x00_set_field32(®, MAC_CSR1_SOFT_RESET, 1);
1240 rt2x00_set_field32(®, MAC_CSR1_BBP_RESET, 1);
1241 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1243 rt2x00pci_register_read(rt2x00dev, MAC_CSR1, ®);
1244 rt2x00_set_field32(®, MAC_CSR1_SOFT_RESET, 0);
1245 rt2x00_set_field32(®, MAC_CSR1_BBP_RESET, 0);
1246 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1248 rt2x00pci_register_read(rt2x00dev, MAC_CSR1, ®);
1249 rt2x00_set_field32(®, MAC_CSR1_HOST_READY, 1);
1250 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1255 static int rt61pci_init_bbp(struct rt2x00_dev *rt2x00dev)
1262 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1263 rt61pci_bbp_read(rt2x00dev, 0, &value);
1264 if ((value != 0xff) && (value != 0x00))
1265 goto continue_csr_init;
1266 NOTICE(rt2x00dev, "Waiting for BBP register.\n");
1267 udelay(REGISTER_BUSY_DELAY);
1270 ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
1274 rt61pci_bbp_write(rt2x00dev, 3, 0x00);
1275 rt61pci_bbp_write(rt2x00dev, 15, 0x30);
1276 rt61pci_bbp_write(rt2x00dev, 21, 0xc8);
1277 rt61pci_bbp_write(rt2x00dev, 22, 0x38);
1278 rt61pci_bbp_write(rt2x00dev, 23, 0x06);
1279 rt61pci_bbp_write(rt2x00dev, 24, 0xfe);
1280 rt61pci_bbp_write(rt2x00dev, 25, 0x0a);
1281 rt61pci_bbp_write(rt2x00dev, 26, 0x0d);
1282 rt61pci_bbp_write(rt2x00dev, 34, 0x12);
1283 rt61pci_bbp_write(rt2x00dev, 37, 0x07);
1284 rt61pci_bbp_write(rt2x00dev, 39, 0xf8);
1285 rt61pci_bbp_write(rt2x00dev, 41, 0x60);
1286 rt61pci_bbp_write(rt2x00dev, 53, 0x10);
1287 rt61pci_bbp_write(rt2x00dev, 54, 0x18);
1288 rt61pci_bbp_write(rt2x00dev, 60, 0x10);
1289 rt61pci_bbp_write(rt2x00dev, 61, 0x04);
1290 rt61pci_bbp_write(rt2x00dev, 62, 0x04);
1291 rt61pci_bbp_write(rt2x00dev, 75, 0xfe);
1292 rt61pci_bbp_write(rt2x00dev, 86, 0xfe);
1293 rt61pci_bbp_write(rt2x00dev, 88, 0xfe);
1294 rt61pci_bbp_write(rt2x00dev, 90, 0x0f);
1295 rt61pci_bbp_write(rt2x00dev, 99, 0x00);
1296 rt61pci_bbp_write(rt2x00dev, 102, 0x16);
1297 rt61pci_bbp_write(rt2x00dev, 107, 0x04);
1299 DEBUG(rt2x00dev, "Start initialization from EEPROM...\n");
1300 for (i = 0; i < EEPROM_BBP_SIZE; i++) {
1301 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
1303 if (eeprom != 0xffff && eeprom != 0x0000) {
1304 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
1305 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
1306 DEBUG(rt2x00dev, "BBP: 0x%02x, value: 0x%02x.\n",
1308 rt61pci_bbp_write(rt2x00dev, reg_id, value);
1311 DEBUG(rt2x00dev, "...End initialization from EEPROM.\n");
1317 * Device state switch handlers.
1319 static void rt61pci_toggle_rx(struct rt2x00_dev *rt2x00dev,
1320 enum dev_state state)
1324 rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, ®);
1325 rt2x00_set_field32(®, TXRX_CSR0_DISABLE_RX,
1326 state == STATE_RADIO_RX_OFF);
1327 rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
1330 static void rt61pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
1331 enum dev_state state)
1333 int mask = (state == STATE_RADIO_IRQ_OFF);
1337 * When interrupts are being enabled, the interrupt registers
1338 * should clear the register to assure a clean state.
1340 if (state == STATE_RADIO_IRQ_ON) {
1341 rt2x00pci_register_read(rt2x00dev, INT_SOURCE_CSR, ®);
1342 rt2x00pci_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
1344 rt2x00pci_register_read(rt2x00dev, MCU_INT_SOURCE_CSR, ®);
1345 rt2x00pci_register_write(rt2x00dev, MCU_INT_SOURCE_CSR, reg);
1349 * Only toggle the interrupts bits we are going to use.
1350 * Non-checked interrupt bits are disabled by default.
1352 rt2x00pci_register_read(rt2x00dev, INT_MASK_CSR, ®);
1353 rt2x00_set_field32(®, INT_MASK_CSR_TXDONE, mask);
1354 rt2x00_set_field32(®, INT_MASK_CSR_RXDONE, mask);
1355 rt2x00_set_field32(®, INT_MASK_CSR_ENABLE_MITIGATION, mask);
1356 rt2x00_set_field32(®, INT_MASK_CSR_MITIGATION_PERIOD, 0xff);
1357 rt2x00pci_register_write(rt2x00dev, INT_MASK_CSR, reg);
1359 rt2x00pci_register_read(rt2x00dev, MCU_INT_MASK_CSR, ®);
1360 rt2x00_set_field32(®, MCU_INT_MASK_CSR_0, mask);
1361 rt2x00_set_field32(®, MCU_INT_MASK_CSR_1, mask);
1362 rt2x00_set_field32(®, MCU_INT_MASK_CSR_2, mask);
1363 rt2x00_set_field32(®, MCU_INT_MASK_CSR_3, mask);
1364 rt2x00_set_field32(®, MCU_INT_MASK_CSR_4, mask);
1365 rt2x00_set_field32(®, MCU_INT_MASK_CSR_5, mask);
1366 rt2x00_set_field32(®, MCU_INT_MASK_CSR_6, mask);
1367 rt2x00_set_field32(®, MCU_INT_MASK_CSR_7, mask);
1368 rt2x00pci_register_write(rt2x00dev, MCU_INT_MASK_CSR, reg);
1371 static int rt61pci_enable_radio(struct rt2x00_dev *rt2x00dev)
1376 * Initialize all registers.
1378 if (rt61pci_init_rings(rt2x00dev) ||
1379 rt61pci_init_registers(rt2x00dev) ||
1380 rt61pci_init_bbp(rt2x00dev)) {
1381 ERROR(rt2x00dev, "Register initialization failed.\n");
1386 * Enable interrupts.
1388 rt61pci_toggle_irq(rt2x00dev, STATE_RADIO_IRQ_ON);
1393 rt2x00pci_register_read(rt2x00dev, RX_CNTL_CSR, ®);
1394 rt2x00_set_field32(®, RX_CNTL_CSR_ENABLE_RX_DMA, 1);
1395 rt2x00pci_register_write(rt2x00dev, RX_CNTL_CSR, reg);
1400 rt61pci_enable_led(rt2x00dev);
1405 static void rt61pci_disable_radio(struct rt2x00_dev *rt2x00dev)
1412 rt61pci_disable_led(rt2x00dev);
1414 rt2x00pci_register_write(rt2x00dev, MAC_CSR10, 0x00001818);
1417 * Disable synchronisation.
1419 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, 0);
1424 rt2x00pci_register_read(rt2x00dev, TX_CNTL_CSR, ®);
1425 rt2x00_set_field32(®, TX_CNTL_CSR_ABORT_TX_AC0, 1);
1426 rt2x00_set_field32(®, TX_CNTL_CSR_ABORT_TX_AC1, 1);
1427 rt2x00_set_field32(®, TX_CNTL_CSR_ABORT_TX_AC2, 1);
1428 rt2x00_set_field32(®, TX_CNTL_CSR_ABORT_TX_AC3, 1);
1429 rt2x00_set_field32(®, TX_CNTL_CSR_ABORT_TX_MGMT, 1);
1430 rt2x00pci_register_write(rt2x00dev, TX_CNTL_CSR, reg);
1433 * Disable interrupts.
1435 rt61pci_toggle_irq(rt2x00dev, STATE_RADIO_IRQ_OFF);
1438 static int rt61pci_set_state(struct rt2x00_dev *rt2x00dev, enum dev_state state)
1445 put_to_sleep = (state != STATE_AWAKE);
1447 rt2x00pci_register_read(rt2x00dev, MAC_CSR12, ®);
1448 rt2x00_set_field32(®, MAC_CSR12_FORCE_WAKEUP, !put_to_sleep);
1449 rt2x00_set_field32(®, MAC_CSR12_PUT_TO_SLEEP, put_to_sleep);
1450 rt2x00pci_register_write(rt2x00dev, MAC_CSR12, reg);
1453 * Device is not guaranteed to be in the requested state yet.
1454 * We must wait until the register indicates that the
1455 * device has entered the correct state.
1457 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1458 rt2x00pci_register_read(rt2x00dev, MAC_CSR12, ®);
1460 rt2x00_get_field32(reg, MAC_CSR12_BBP_CURRENT_STATE);
1461 if (current_state == !put_to_sleep)
1466 NOTICE(rt2x00dev, "Device failed to enter state %d, "
1467 "current device state %d.\n", !put_to_sleep, current_state);
1472 static int rt61pci_set_device_state(struct rt2x00_dev *rt2x00dev,
1473 enum dev_state state)
1478 case STATE_RADIO_ON:
1479 retval = rt61pci_enable_radio(rt2x00dev);
1481 case STATE_RADIO_OFF:
1482 rt61pci_disable_radio(rt2x00dev);
1484 case STATE_RADIO_RX_ON:
1485 case STATE_RADIO_RX_ON_LINK:
1486 rt61pci_toggle_rx(rt2x00dev, STATE_RADIO_RX_ON);
1488 case STATE_RADIO_RX_OFF:
1489 case STATE_RADIO_RX_OFF_LINK:
1490 rt61pci_toggle_rx(rt2x00dev, STATE_RADIO_RX_OFF);
1492 case STATE_DEEP_SLEEP:
1496 retval = rt61pci_set_state(rt2x00dev, state);
1507 * TX descriptor initialization
1509 static void rt61pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
1510 struct sk_buff *skb,
1511 struct txdata_entry_desc *desc,
1512 struct ieee80211_tx_control *control)
1514 struct skb_desc *skbdesc = get_skb_desc(skb);
1515 __le32 *txd = skbdesc->desc;
1519 * Start writing the descriptor words.
1521 rt2x00_desc_read(txd, 1, &word);
1522 rt2x00_set_field32(&word, TXD_W1_HOST_Q_ID, desc->queue);
1523 rt2x00_set_field32(&word, TXD_W1_AIFSN, desc->aifs);
1524 rt2x00_set_field32(&word, TXD_W1_CWMIN, desc->cw_min);
1525 rt2x00_set_field32(&word, TXD_W1_CWMAX, desc->cw_max);
1526 rt2x00_set_field32(&word, TXD_W1_IV_OFFSET, IEEE80211_HEADER);
1527 rt2x00_set_field32(&word, TXD_W1_HW_SEQUENCE, 1);
1528 rt2x00_desc_write(txd, 1, word);
1530 rt2x00_desc_read(txd, 2, &word);
1531 rt2x00_set_field32(&word, TXD_W2_PLCP_SIGNAL, desc->signal);
1532 rt2x00_set_field32(&word, TXD_W2_PLCP_SERVICE, desc->service);
1533 rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_LOW, desc->length_low);
1534 rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_HIGH, desc->length_high);
1535 rt2x00_desc_write(txd, 2, word);
1537 rt2x00_desc_read(txd, 5, &word);
1538 rt2x00_set_field32(&word, TXD_W5_TX_POWER,
1539 TXPOWER_TO_DEV(control->power_level));
1540 rt2x00_set_field32(&word, TXD_W5_WAITING_DMA_DONE_INT, 1);
1541 rt2x00_desc_write(txd, 5, word);
1543 rt2x00_desc_read(txd, 11, &word);
1544 rt2x00_set_field32(&word, TXD_W11_BUFFER_LENGTH0, skbdesc->data_len);
1545 rt2x00_desc_write(txd, 11, word);
1547 rt2x00_desc_read(txd, 0, &word);
1548 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1);
1549 rt2x00_set_field32(&word, TXD_W0_VALID, 1);
1550 rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
1551 test_bit(ENTRY_TXD_MORE_FRAG, &desc->flags));
1552 rt2x00_set_field32(&word, TXD_W0_ACK,
1553 test_bit(ENTRY_TXD_ACK, &desc->flags));
1554 rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
1555 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &desc->flags));
1556 rt2x00_set_field32(&word, TXD_W0_OFDM,
1557 test_bit(ENTRY_TXD_OFDM_RATE, &desc->flags));
1558 rt2x00_set_field32(&word, TXD_W0_IFS, desc->ifs);
1559 rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
1561 IEEE80211_TXCTL_LONG_RETRY_LIMIT));
1562 rt2x00_set_field32(&word, TXD_W0_TKIP_MIC, 0);
1563 rt2x00_set_field32(&word, TXD_W0_DATABYTE_COUNT, skbdesc->data_len);
1564 rt2x00_set_field32(&word, TXD_W0_BURST,
1565 test_bit(ENTRY_TXD_BURST, &desc->flags));
1566 rt2x00_set_field32(&word, TXD_W0_CIPHER_ALG, CIPHER_NONE);
1567 rt2x00_desc_write(txd, 0, word);
1571 * TX data initialization
1573 static void rt61pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
1578 if (queue == IEEE80211_TX_QUEUE_BEACON) {
1580 * For Wi-Fi faily generated beacons between participating
1581 * stations. Set TBTT phase adaptive adjustment step to 8us.
1583 rt2x00pci_register_write(rt2x00dev, TXRX_CSR10, 0x00001008);
1585 rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, ®);
1586 if (!rt2x00_get_field32(reg, TXRX_CSR9_BEACON_GEN)) {
1587 rt2x00_set_field32(®, TXRX_CSR9_BEACON_GEN, 1);
1588 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
1593 rt2x00pci_register_read(rt2x00dev, TX_CNTL_CSR, ®);
1594 rt2x00_set_field32(®, TX_CNTL_CSR_KICK_TX_AC0,
1595 (queue == IEEE80211_TX_QUEUE_DATA0));
1596 rt2x00_set_field32(®, TX_CNTL_CSR_KICK_TX_AC1,
1597 (queue == IEEE80211_TX_QUEUE_DATA1));
1598 rt2x00_set_field32(®, TX_CNTL_CSR_KICK_TX_AC2,
1599 (queue == IEEE80211_TX_QUEUE_DATA2));
1600 rt2x00_set_field32(®, TX_CNTL_CSR_KICK_TX_AC3,
1601 (queue == IEEE80211_TX_QUEUE_DATA3));
1602 rt2x00_set_field32(®, TX_CNTL_CSR_KICK_TX_MGMT,
1603 (queue == IEEE80211_TX_QUEUE_DATA4));
1604 rt2x00pci_register_write(rt2x00dev, TX_CNTL_CSR, reg);
1608 * RX control handlers
1610 static int rt61pci_agc_to_rssi(struct rt2x00_dev *rt2x00dev, int rxd_w1)
1616 lna = rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_LNA);
1631 if (rt2x00dev->rx_status.phymode == MODE_IEEE80211A) {
1632 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags))
1635 if (lna == 3 || lna == 2)
1638 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &eeprom);
1639 offset -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_A_1);
1641 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags))
1644 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &eeprom);
1645 offset -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_BG_1);
1648 return rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_AGC) * 2 - offset;
1651 static void rt61pci_fill_rxdone(struct data_entry *entry,
1652 struct rxdata_entry_desc *desc)
1654 __le32 *rxd = entry->priv;
1658 rt2x00_desc_read(rxd, 0, &word0);
1659 rt2x00_desc_read(rxd, 1, &word1);
1662 if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
1663 desc->flags |= RX_FLAG_FAILED_FCS_CRC;
1666 * Obtain the status about this packet.
1668 desc->signal = rt2x00_get_field32(word1, RXD_W1_SIGNAL);
1669 desc->rssi = rt61pci_agc_to_rssi(entry->ring->rt2x00dev, word1);
1670 desc->ofdm = rt2x00_get_field32(word0, RXD_W0_OFDM);
1671 desc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
1672 desc->my_bss = !!rt2x00_get_field32(word0, RXD_W0_MY_BSS);
1676 * Interrupt functions.
1678 static void rt61pci_txdone(struct rt2x00_dev *rt2x00dev)
1680 struct data_ring *ring;
1681 struct data_entry *entry;
1682 struct data_entry *entry_done;
1693 * During each loop we will compare the freshly read
1694 * STA_CSR4 register value with the value read from
1695 * the previous loop. If the 2 values are equal then
1696 * we should stop processing because the chance it
1697 * quite big that the device has been unplugged and
1698 * we risk going into an endless loop.
1703 rt2x00pci_register_read(rt2x00dev, STA_CSR4, ®);
1704 if (!rt2x00_get_field32(reg, STA_CSR4_VALID))
1712 * Skip this entry when it contains an invalid
1713 * ring identication number.
1715 type = rt2x00_get_field32(reg, STA_CSR4_PID_TYPE);
1716 ring = rt2x00lib_get_ring(rt2x00dev, type);
1717 if (unlikely(!ring))
1721 * Skip this entry when it contains an invalid
1724 index = rt2x00_get_field32(reg, STA_CSR4_PID_SUBTYPE);
1725 if (unlikely(index >= ring->stats.limit))
1728 entry = &ring->entry[index];
1730 rt2x00_desc_read(txd, 0, &word);
1732 if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
1733 !rt2x00_get_field32(word, TXD_W0_VALID))
1736 entry_done = rt2x00_get_data_entry_done(ring);
1737 while (entry != entry_done) {
1738 /* Catch up. Just report any entries we missed as
1741 "TX status report missed for entry %p\n",
1743 rt2x00pci_txdone(rt2x00dev, entry_done, TX_FAIL_OTHER,
1745 entry_done = rt2x00_get_data_entry_done(ring);
1749 * Obtain the status about this packet.
1751 tx_status = rt2x00_get_field32(reg, STA_CSR4_TX_RESULT);
1752 retry = rt2x00_get_field32(reg, STA_CSR4_RETRY_COUNT);
1754 rt2x00pci_txdone(rt2x00dev, entry, tx_status, retry);
1758 static irqreturn_t rt61pci_interrupt(int irq, void *dev_instance)
1760 struct rt2x00_dev *rt2x00dev = dev_instance;
1765 * Get the interrupt sources & saved to local variable.
1766 * Write register value back to clear pending interrupts.
1768 rt2x00pci_register_read(rt2x00dev, MCU_INT_SOURCE_CSR, ®_mcu);
1769 rt2x00pci_register_write(rt2x00dev, MCU_INT_SOURCE_CSR, reg_mcu);
1771 rt2x00pci_register_read(rt2x00dev, INT_SOURCE_CSR, ®);
1772 rt2x00pci_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
1774 if (!reg && !reg_mcu)
1777 if (!test_bit(DEVICE_ENABLED_RADIO, &rt2x00dev->flags))
1781 * Handle interrupts, walk through all bits
1782 * and run the tasks, the bits are checked in order of
1787 * 1 - Rx ring done interrupt.
1789 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_RXDONE))
1790 rt2x00pci_rxdone(rt2x00dev);
1793 * 2 - Tx ring done interrupt.
1795 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_TXDONE))
1796 rt61pci_txdone(rt2x00dev);
1799 * 3 - Handle MCU command done.
1802 rt2x00pci_register_write(rt2x00dev,
1803 M2H_CMD_DONE_CSR, 0xffffffff);
1809 * Device probe functions.
1811 static int rt61pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
1813 struct eeprom_93cx6 eeprom;
1819 rt2x00pci_register_read(rt2x00dev, E2PROM_CSR, ®);
1821 eeprom.data = rt2x00dev;
1822 eeprom.register_read = rt61pci_eepromregister_read;
1823 eeprom.register_write = rt61pci_eepromregister_write;
1824 eeprom.width = rt2x00_get_field32(reg, E2PROM_CSR_TYPE_93C46) ?
1825 PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66;
1826 eeprom.reg_data_in = 0;
1827 eeprom.reg_data_out = 0;
1828 eeprom.reg_data_clock = 0;
1829 eeprom.reg_chip_select = 0;
1831 eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
1832 EEPROM_SIZE / sizeof(u16));
1835 * Start validation of the data that has been read.
1837 mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
1838 if (!is_valid_ether_addr(mac)) {
1839 DECLARE_MAC_BUF(macbuf);
1841 random_ether_addr(mac);
1842 EEPROM(rt2x00dev, "MAC: %s\n", print_mac(macbuf, mac));
1845 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
1846 if (word == 0xffff) {
1847 rt2x00_set_field16(&word, EEPROM_ANTENNA_NUM, 2);
1848 rt2x00_set_field16(&word, EEPROM_ANTENNA_TX_DEFAULT,
1850 rt2x00_set_field16(&word, EEPROM_ANTENNA_RX_DEFAULT,
1852 rt2x00_set_field16(&word, EEPROM_ANTENNA_FRAME_TYPE, 0);
1853 rt2x00_set_field16(&word, EEPROM_ANTENNA_DYN_TXAGC, 0);
1854 rt2x00_set_field16(&word, EEPROM_ANTENNA_HARDWARE_RADIO, 0);
1855 rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF5225);
1856 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
1857 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
1860 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
1861 if (word == 0xffff) {
1862 rt2x00_set_field16(&word, EEPROM_NIC_ENABLE_DIVERSITY, 0);
1863 rt2x00_set_field16(&word, EEPROM_NIC_TX_DIVERSITY, 0);
1864 rt2x00_set_field16(&word, EEPROM_NIC_TX_RX_FIXED, 0);
1865 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_BG, 0);
1866 rt2x00_set_field16(&word, EEPROM_NIC_CARDBUS_ACCEL, 0);
1867 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_A, 0);
1868 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
1869 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
1872 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &word);
1873 if (word == 0xffff) {
1874 rt2x00_set_field16(&word, EEPROM_LED_LED_MODE,
1876 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED, word);
1877 EEPROM(rt2x00dev, "Led: 0x%04x\n", word);
1880 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
1881 if (word == 0xffff) {
1882 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
1883 rt2x00_set_field16(&word, EEPROM_FREQ_SEQ, 0);
1884 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
1885 EEPROM(rt2x00dev, "Freq: 0x%04x\n", word);
1888 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &word);
1889 if (word == 0xffff) {
1890 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0);
1891 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0);
1892 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word);
1893 EEPROM(rt2x00dev, "RSSI OFFSET BG: 0x%04x\n", word);
1895 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_1);
1896 if (value < -10 || value > 10)
1897 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0);
1898 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_2);
1899 if (value < -10 || value > 10)
1900 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0);
1901 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word);
1904 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &word);
1905 if (word == 0xffff) {
1906 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0);
1907 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0);
1908 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word);
1909 EEPROM(rt2x00dev, "RSSI OFFSET BG: 0x%04x\n", word);
1911 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_1);
1912 if (value < -10 || value > 10)
1913 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0);
1914 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_2);
1915 if (value < -10 || value > 10)
1916 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0);
1917 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word);
1923 static int rt61pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
1931 * Read EEPROM word for configuration.
1933 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
1936 * Identify RF chipset.
1937 * To determine the RT chip we have to read the
1938 * PCI header of the device.
1940 pci_read_config_word(rt2x00dev_pci(rt2x00dev),
1941 PCI_CONFIG_HEADER_DEVICE, &device);
1942 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
1943 rt2x00pci_register_read(rt2x00dev, MAC_CSR0, ®);
1944 rt2x00_set_chip(rt2x00dev, device, value, reg);
1946 if (!rt2x00_rf(&rt2x00dev->chip, RF5225) &&
1947 !rt2x00_rf(&rt2x00dev->chip, RF5325) &&
1948 !rt2x00_rf(&rt2x00dev->chip, RF2527) &&
1949 !rt2x00_rf(&rt2x00dev->chip, RF2529)) {
1950 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
1955 * Determine number of antenna's.
1957 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_NUM) == 2)
1958 __set_bit(CONFIG_DOUBLE_ANTENNA, &rt2x00dev->flags);
1961 * Identify default antenna configuration.
1963 rt2x00dev->default_ant.tx =
1964 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
1965 rt2x00dev->default_ant.rx =
1966 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
1969 * Read the Frame type.
1971 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_FRAME_TYPE))
1972 __set_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags);
1975 * Detect if this device has an hardware controlled radio.
1977 #ifdef CONFIG_RT61PCI_RFKILL
1978 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO))
1979 __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
1980 #endif /* CONFIG_RT61PCI_RFKILL */
1983 * Read frequency offset and RF programming sequence.
1985 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
1986 if (rt2x00_get_field16(eeprom, EEPROM_FREQ_SEQ))
1987 __set_bit(CONFIG_RF_SEQUENCE, &rt2x00dev->flags);
1989 rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
1992 * Read external LNA informations.
1994 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
1996 if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_A))
1997 __set_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
1998 if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_BG))
1999 __set_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
2002 * When working with a RF2529 chip without double antenna
2003 * the antenna settings should be gathered from the NIC
2006 if (rt2x00_rf(&rt2x00dev->chip, RF2529) &&
2007 !test_bit(CONFIG_DOUBLE_ANTENNA, &rt2x00dev->flags)) {
2008 switch (rt2x00_get_field16(eeprom, EEPROM_NIC_TX_RX_FIXED)) {
2010 rt2x00dev->default_ant.tx = ANTENNA_B;
2011 rt2x00dev->default_ant.rx = ANTENNA_A;
2014 rt2x00dev->default_ant.tx = ANTENNA_B;
2015 rt2x00dev->default_ant.rx = ANTENNA_B;
2018 rt2x00dev->default_ant.tx = ANTENNA_A;
2019 rt2x00dev->default_ant.rx = ANTENNA_A;
2022 rt2x00dev->default_ant.tx = ANTENNA_A;
2023 rt2x00dev->default_ant.rx = ANTENNA_B;
2027 if (rt2x00_get_field16(eeprom, EEPROM_NIC_TX_DIVERSITY))
2028 rt2x00dev->default_ant.tx = ANTENNA_SW_DIVERSITY;
2029 if (rt2x00_get_field16(eeprom, EEPROM_NIC_ENABLE_DIVERSITY))
2030 rt2x00dev->default_ant.rx = ANTENNA_SW_DIVERSITY;
2034 * Store led settings, for correct led behaviour.
2035 * If the eeprom value is invalid,
2036 * switch to default led mode.
2038 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &eeprom);
2040 rt2x00dev->led_mode = rt2x00_get_field16(eeprom, EEPROM_LED_LED_MODE);
2042 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_LED_MODE,
2043 rt2x00dev->led_mode);
2044 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_GPIO_0,
2045 rt2x00_get_field16(eeprom,
2046 EEPROM_LED_POLARITY_GPIO_0));
2047 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_GPIO_1,
2048 rt2x00_get_field16(eeprom,
2049 EEPROM_LED_POLARITY_GPIO_1));
2050 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_GPIO_2,
2051 rt2x00_get_field16(eeprom,
2052 EEPROM_LED_POLARITY_GPIO_2));
2053 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_GPIO_3,
2054 rt2x00_get_field16(eeprom,
2055 EEPROM_LED_POLARITY_GPIO_3));
2056 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_GPIO_4,
2057 rt2x00_get_field16(eeprom,
2058 EEPROM_LED_POLARITY_GPIO_4));
2059 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_ACT,
2060 rt2x00_get_field16(eeprom, EEPROM_LED_POLARITY_ACT));
2061 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_READY_BG,
2062 rt2x00_get_field16(eeprom,
2063 EEPROM_LED_POLARITY_RDY_G));
2064 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_READY_A,
2065 rt2x00_get_field16(eeprom,
2066 EEPROM_LED_POLARITY_RDY_A));
2072 * RF value list for RF5225 & RF5325
2073 * Supports: 2.4 GHz & 5.2 GHz, rf_sequence disabled
2075 static const struct rf_channel rf_vals_noseq[] = {
2076 { 1, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa0b },
2077 { 2, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa1f },
2078 { 3, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa0b },
2079 { 4, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa1f },
2080 { 5, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa0b },
2081 { 6, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa1f },
2082 { 7, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa0b },
2083 { 8, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa1f },
2084 { 9, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa0b },
2085 { 10, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa1f },
2086 { 11, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa0b },
2087 { 12, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa1f },
2088 { 13, 0x00002ccc, 0x0000479e, 0x00068455, 0x000ffa0b },
2089 { 14, 0x00002ccc, 0x000047a2, 0x00068455, 0x000ffa13 },
2091 /* 802.11 UNI / HyperLan 2 */
2092 { 36, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa23 },
2093 { 40, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa03 },
2094 { 44, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa0b },
2095 { 48, 0x00002ccc, 0x000049aa, 0x0009be55, 0x000ffa13 },
2096 { 52, 0x00002ccc, 0x000049ae, 0x0009ae55, 0x000ffa1b },
2097 { 56, 0x00002ccc, 0x000049b2, 0x0009ae55, 0x000ffa23 },
2098 { 60, 0x00002ccc, 0x000049ba, 0x0009ae55, 0x000ffa03 },
2099 { 64, 0x00002ccc, 0x000049be, 0x0009ae55, 0x000ffa0b },
2101 /* 802.11 HyperLan 2 */
2102 { 100, 0x00002ccc, 0x00004a2a, 0x000bae55, 0x000ffa03 },
2103 { 104, 0x00002ccc, 0x00004a2e, 0x000bae55, 0x000ffa0b },
2104 { 108, 0x00002ccc, 0x00004a32, 0x000bae55, 0x000ffa13 },
2105 { 112, 0x00002ccc, 0x00004a36, 0x000bae55, 0x000ffa1b },
2106 { 116, 0x00002ccc, 0x00004a3a, 0x000bbe55, 0x000ffa23 },
2107 { 120, 0x00002ccc, 0x00004a82, 0x000bbe55, 0x000ffa03 },
2108 { 124, 0x00002ccc, 0x00004a86, 0x000bbe55, 0x000ffa0b },
2109 { 128, 0x00002ccc, 0x00004a8a, 0x000bbe55, 0x000ffa13 },
2110 { 132, 0x00002ccc, 0x00004a8e, 0x000bbe55, 0x000ffa1b },
2111 { 136, 0x00002ccc, 0x00004a92, 0x000bbe55, 0x000ffa23 },
2114 { 140, 0x00002ccc, 0x00004a9a, 0x000bbe55, 0x000ffa03 },
2115 { 149, 0x00002ccc, 0x00004aa2, 0x000bbe55, 0x000ffa1f },
2116 { 153, 0x00002ccc, 0x00004aa6, 0x000bbe55, 0x000ffa27 },
2117 { 157, 0x00002ccc, 0x00004aae, 0x000bbe55, 0x000ffa07 },
2118 { 161, 0x00002ccc, 0x00004ab2, 0x000bbe55, 0x000ffa0f },
2119 { 165, 0x00002ccc, 0x00004ab6, 0x000bbe55, 0x000ffa17 },
2121 /* MMAC(Japan)J52 ch 34,38,42,46 */
2122 { 34, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa0b },
2123 { 38, 0x00002ccc, 0x0000499e, 0x0009be55, 0x000ffa13 },
2124 { 42, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa1b },
2125 { 46, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa23 },
2129 * RF value list for RF5225 & RF5325
2130 * Supports: 2.4 GHz & 5.2 GHz, rf_sequence enabled
2132 static const struct rf_channel rf_vals_seq[] = {
2133 { 1, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa0b },
2134 { 2, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa1f },
2135 { 3, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa0b },
2136 { 4, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa1f },
2137 { 5, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa0b },
2138 { 6, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa1f },
2139 { 7, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa0b },
2140 { 8, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa1f },
2141 { 9, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa0b },
2142 { 10, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa1f },
2143 { 11, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa0b },
2144 { 12, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa1f },
2145 { 13, 0x00002ccc, 0x0000479e, 0x00068455, 0x000ffa0b },
2146 { 14, 0x00002ccc, 0x000047a2, 0x00068455, 0x000ffa13 },
2148 /* 802.11 UNI / HyperLan 2 */
2149 { 36, 0x00002cd4, 0x0004481a, 0x00098455, 0x000c0a03 },
2150 { 40, 0x00002cd0, 0x00044682, 0x00098455, 0x000c0a03 },
2151 { 44, 0x00002cd0, 0x00044686, 0x00098455, 0x000c0a1b },
2152 { 48, 0x00002cd0, 0x0004468e, 0x00098655, 0x000c0a0b },
2153 { 52, 0x00002cd0, 0x00044692, 0x00098855, 0x000c0a23 },
2154 { 56, 0x00002cd0, 0x0004469a, 0x00098c55, 0x000c0a13 },
2155 { 60, 0x00002cd0, 0x000446a2, 0x00098e55, 0x000c0a03 },
2156 { 64, 0x00002cd0, 0x000446a6, 0x00099255, 0x000c0a1b },
2158 /* 802.11 HyperLan 2 */
2159 { 100, 0x00002cd4, 0x0004489a, 0x000b9855, 0x000c0a03 },
2160 { 104, 0x00002cd4, 0x000448a2, 0x000b9855, 0x000c0a03 },
2161 { 108, 0x00002cd4, 0x000448aa, 0x000b9855, 0x000c0a03 },
2162 { 112, 0x00002cd4, 0x000448b2, 0x000b9a55, 0x000c0a03 },
2163 { 116, 0x00002cd4, 0x000448ba, 0x000b9a55, 0x000c0a03 },
2164 { 120, 0x00002cd0, 0x00044702, 0x000b9a55, 0x000c0a03 },
2165 { 124, 0x00002cd0, 0x00044706, 0x000b9a55, 0x000c0a1b },
2166 { 128, 0x00002cd0, 0x0004470e, 0x000b9c55, 0x000c0a0b },
2167 { 132, 0x00002cd0, 0x00044712, 0x000b9c55, 0x000c0a23 },
2168 { 136, 0x00002cd0, 0x0004471a, 0x000b9e55, 0x000c0a13 },
2171 { 140, 0x00002cd0, 0x00044722, 0x000b9e55, 0x000c0a03 },
2172 { 149, 0x00002cd0, 0x0004472e, 0x000ba255, 0x000c0a1b },
2173 { 153, 0x00002cd0, 0x00044736, 0x000ba255, 0x000c0a0b },
2174 { 157, 0x00002cd4, 0x0004490a, 0x000ba255, 0x000c0a17 },
2175 { 161, 0x00002cd4, 0x00044912, 0x000ba255, 0x000c0a17 },
2176 { 165, 0x00002cd4, 0x0004491a, 0x000ba255, 0x000c0a17 },
2178 /* MMAC(Japan)J52 ch 34,38,42,46 */
2179 { 34, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000c0a0b },
2180 { 38, 0x00002ccc, 0x0000499e, 0x0009be55, 0x000c0a13 },
2181 { 42, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000c0a1b },
2182 { 46, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000c0a23 },
2185 static void rt61pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
2187 struct hw_mode_spec *spec = &rt2x00dev->spec;
2192 * Initialize all hw fields.
2194 rt2x00dev->hw->flags =
2195 IEEE80211_HW_HOST_GEN_BEACON_TEMPLATE |
2196 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING;
2197 rt2x00dev->hw->extra_tx_headroom = 0;
2198 rt2x00dev->hw->max_signal = MAX_SIGNAL;
2199 rt2x00dev->hw->max_rssi = MAX_RX_SSI;
2200 rt2x00dev->hw->queues = 5;
2202 SET_IEEE80211_DEV(rt2x00dev->hw, &rt2x00dev_pci(rt2x00dev)->dev);
2203 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
2204 rt2x00_eeprom_addr(rt2x00dev,
2205 EEPROM_MAC_ADDR_0));
2208 * Convert tx_power array in eeprom.
2210 txpower = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_G_START);
2211 for (i = 0; i < 14; i++)
2212 txpower[i] = TXPOWER_FROM_DEV(txpower[i]);
2215 * Initialize hw_mode information.
2217 spec->num_modes = 2;
2218 spec->num_rates = 12;
2219 spec->tx_power_a = NULL;
2220 spec->tx_power_bg = txpower;
2221 spec->tx_power_default = DEFAULT_TXPOWER;
2223 if (!test_bit(CONFIG_RF_SEQUENCE, &rt2x00dev->flags)) {
2224 spec->num_channels = 14;
2225 spec->channels = rf_vals_noseq;
2227 spec->num_channels = 14;
2228 spec->channels = rf_vals_seq;
2231 if (rt2x00_rf(&rt2x00dev->chip, RF5225) ||
2232 rt2x00_rf(&rt2x00dev->chip, RF5325)) {
2233 spec->num_modes = 3;
2234 spec->num_channels = ARRAY_SIZE(rf_vals_seq);
2236 txpower = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A_START);
2237 for (i = 0; i < 14; i++)
2238 txpower[i] = TXPOWER_FROM_DEV(txpower[i]);
2240 spec->tx_power_a = txpower;
2244 static int rt61pci_probe_hw(struct rt2x00_dev *rt2x00dev)
2249 * Allocate eeprom data.
2251 retval = rt61pci_validate_eeprom(rt2x00dev);
2255 retval = rt61pci_init_eeprom(rt2x00dev);
2260 * Initialize hw specifications.
2262 rt61pci_probe_hw_mode(rt2x00dev);
2265 * This device requires firmware
2267 __set_bit(DRIVER_REQUIRE_FIRMWARE, &rt2x00dev->flags);
2270 * Set the rssi offset.
2272 rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
2278 * IEEE80211 stack callback functions.
2280 static void rt61pci_configure_filter(struct ieee80211_hw *hw,
2281 unsigned int changed_flags,
2282 unsigned int *total_flags,
2284 struct dev_addr_list *mc_list)
2286 struct rt2x00_dev *rt2x00dev = hw->priv;
2290 * Mask off any flags we are going to ignore from
2291 * the total_flags field.
2302 * Apply some rules to the filters:
2303 * - Some filters imply different filters to be set.
2304 * - Some things we can't filter out at all.
2307 *total_flags |= FIF_ALLMULTI;
2308 if (*total_flags & FIF_OTHER_BSS ||
2309 *total_flags & FIF_PROMISC_IN_BSS)
2310 *total_flags |= FIF_PROMISC_IN_BSS | FIF_OTHER_BSS;
2313 * Check if there is any work left for us.
2315 if (rt2x00dev->packet_filter == *total_flags)
2317 rt2x00dev->packet_filter = *total_flags;
2320 * Start configuration steps.
2321 * Note that the version error will always be dropped
2322 * and broadcast frames will always be accepted since
2323 * there is no filter for it at this time.
2325 rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, ®);
2326 rt2x00_set_field32(®, TXRX_CSR0_DROP_CRC,
2327 !(*total_flags & FIF_FCSFAIL));
2328 rt2x00_set_field32(®, TXRX_CSR0_DROP_PHYSICAL,
2329 !(*total_flags & FIF_PLCPFAIL));
2330 rt2x00_set_field32(®, TXRX_CSR0_DROP_CONTROL,
2331 !(*total_flags & FIF_CONTROL));
2332 rt2x00_set_field32(®, TXRX_CSR0_DROP_NOT_TO_ME,
2333 !(*total_flags & FIF_PROMISC_IN_BSS));
2334 rt2x00_set_field32(®, TXRX_CSR0_DROP_TO_DS,
2335 !(*total_flags & FIF_PROMISC_IN_BSS));
2336 rt2x00_set_field32(®, TXRX_CSR0_DROP_VERSION_ERROR, 1);
2337 rt2x00_set_field32(®, TXRX_CSR0_DROP_MULTICAST,
2338 !(*total_flags & FIF_ALLMULTI));
2339 rt2x00_set_field32(®, TXRX_CSR0_DROP_BORADCAST, 0);
2340 rt2x00_set_field32(®, TXRX_CSR0_DROP_ACK_CTS, 1);
2341 rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
2344 static int rt61pci_set_retry_limit(struct ieee80211_hw *hw,
2345 u32 short_retry, u32 long_retry)
2347 struct rt2x00_dev *rt2x00dev = hw->priv;
2350 rt2x00pci_register_read(rt2x00dev, TXRX_CSR4, ®);
2351 rt2x00_set_field32(®, TXRX_CSR4_LONG_RETRY_LIMIT, long_retry);
2352 rt2x00_set_field32(®, TXRX_CSR4_SHORT_RETRY_LIMIT, short_retry);
2353 rt2x00pci_register_write(rt2x00dev, TXRX_CSR4, reg);
2358 static u64 rt61pci_get_tsf(struct ieee80211_hw *hw)
2360 struct rt2x00_dev *rt2x00dev = hw->priv;
2364 rt2x00pci_register_read(rt2x00dev, TXRX_CSR13, ®);
2365 tsf = (u64) rt2x00_get_field32(reg, TXRX_CSR13_HIGH_TSFTIMER) << 32;
2366 rt2x00pci_register_read(rt2x00dev, TXRX_CSR12, ®);
2367 tsf |= rt2x00_get_field32(reg, TXRX_CSR12_LOW_TSFTIMER);
2372 static void rt61pci_reset_tsf(struct ieee80211_hw *hw)
2374 struct rt2x00_dev *rt2x00dev = hw->priv;
2376 rt2x00pci_register_write(rt2x00dev, TXRX_CSR12, 0);
2377 rt2x00pci_register_write(rt2x00dev, TXRX_CSR13, 0);
2380 static int rt61pci_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb,
2381 struct ieee80211_tx_control *control)
2383 struct rt2x00_dev *rt2x00dev = hw->priv;
2384 struct skb_desc *desc;
2385 struct data_ring *ring;
2386 struct data_entry *entry;
2389 * Just in case the ieee80211 doesn't set this,
2390 * but we need this queue set for the descriptor
2393 control->queue = IEEE80211_TX_QUEUE_BEACON;
2394 ring = rt2x00lib_get_ring(rt2x00dev, control->queue);
2395 entry = rt2x00_get_data_entry(ring);
2398 * We need to append the descriptor in front of the
2401 if (skb_headroom(skb) < TXD_DESC_SIZE) {
2402 if (pskb_expand_head(skb, TXD_DESC_SIZE, 0, GFP_ATOMIC)) {
2409 * Add the descriptor in front of the skb.
2411 skb_push(skb, ring->desc_size);
2412 memset(skb->data, 0, ring->desc_size);
2415 * Fill in skb descriptor
2417 desc = get_skb_desc(skb);
2418 desc->desc_len = ring->desc_size;
2419 desc->data_len = skb->len - ring->desc_size;
2420 desc->desc = skb->data;
2421 desc->data = skb->data + ring->desc_size;
2423 desc->entry = entry;
2425 rt2x00lib_write_tx_desc(rt2x00dev, skb, control);
2428 * Write entire beacon with descriptor to register,
2429 * and kick the beacon generator.
2431 rt2x00pci_register_multiwrite(rt2x00dev, HW_BEACON_BASE0,
2432 skb->data, skb->len);
2433 rt61pci_kick_tx_queue(rt2x00dev, IEEE80211_TX_QUEUE_BEACON);
2438 static const struct ieee80211_ops rt61pci_mac80211_ops = {
2440 .start = rt2x00mac_start,
2441 .stop = rt2x00mac_stop,
2442 .add_interface = rt2x00mac_add_interface,
2443 .remove_interface = rt2x00mac_remove_interface,
2444 .config = rt2x00mac_config,
2445 .config_interface = rt2x00mac_config_interface,
2446 .configure_filter = rt61pci_configure_filter,
2447 .get_stats = rt2x00mac_get_stats,
2448 .set_retry_limit = rt61pci_set_retry_limit,
2449 .bss_info_changed = rt2x00mac_bss_info_changed,
2450 .conf_tx = rt2x00mac_conf_tx,
2451 .get_tx_stats = rt2x00mac_get_tx_stats,
2452 .get_tsf = rt61pci_get_tsf,
2453 .reset_tsf = rt61pci_reset_tsf,
2454 .beacon_update = rt61pci_beacon_update,
2457 static const struct rt2x00lib_ops rt61pci_rt2x00_ops = {
2458 .irq_handler = rt61pci_interrupt,
2459 .probe_hw = rt61pci_probe_hw,
2460 .get_firmware_name = rt61pci_get_firmware_name,
2461 .load_firmware = rt61pci_load_firmware,
2462 .initialize = rt2x00pci_initialize,
2463 .uninitialize = rt2x00pci_uninitialize,
2464 .init_rxentry = rt61pci_init_rxentry,
2465 .init_txentry = rt61pci_init_txentry,
2466 .set_device_state = rt61pci_set_device_state,
2467 .rfkill_poll = rt61pci_rfkill_poll,
2468 .link_stats = rt61pci_link_stats,
2469 .reset_tuner = rt61pci_reset_tuner,
2470 .link_tuner = rt61pci_link_tuner,
2471 .write_tx_desc = rt61pci_write_tx_desc,
2472 .write_tx_data = rt2x00pci_write_tx_data,
2473 .kick_tx_queue = rt61pci_kick_tx_queue,
2474 .fill_rxdone = rt61pci_fill_rxdone,
2475 .config_mac_addr = rt61pci_config_mac_addr,
2476 .config_bssid = rt61pci_config_bssid,
2477 .config_type = rt61pci_config_type,
2478 .config_preamble = rt61pci_config_preamble,
2479 .config = rt61pci_config,
2482 static const struct rt2x00_ops rt61pci_ops = {
2483 .name = KBUILD_MODNAME,
2484 .rxd_size = RXD_DESC_SIZE,
2485 .txd_size = TXD_DESC_SIZE,
2486 .eeprom_size = EEPROM_SIZE,
2488 .lib = &rt61pci_rt2x00_ops,
2489 .hw = &rt61pci_mac80211_ops,
2490 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
2491 .debugfs = &rt61pci_rt2x00debug,
2492 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
2496 * RT61pci module information.
2498 static struct pci_device_id rt61pci_device_table[] = {
2500 { PCI_DEVICE(0x1814, 0x0301), PCI_DEVICE_DATA(&rt61pci_ops) },
2502 { PCI_DEVICE(0x1814, 0x0302), PCI_DEVICE_DATA(&rt61pci_ops) },
2504 { PCI_DEVICE(0x1814, 0x0401), PCI_DEVICE_DATA(&rt61pci_ops) },
2508 MODULE_AUTHOR(DRV_PROJECT);
2509 MODULE_VERSION(DRV_VERSION);
2510 MODULE_DESCRIPTION("Ralink RT61 PCI & PCMCIA Wireless LAN driver.");
2511 MODULE_SUPPORTED_DEVICE("Ralink RT2561, RT2561s & RT2661 "
2512 "PCI & PCMCIA chipset based cards");
2513 MODULE_DEVICE_TABLE(pci, rt61pci_device_table);
2514 MODULE_FIRMWARE(FIRMWARE_RT2561);
2515 MODULE_FIRMWARE(FIRMWARE_RT2561s);
2516 MODULE_FIRMWARE(FIRMWARE_RT2661);
2517 MODULE_LICENSE("GPL");
2519 static struct pci_driver rt61pci_driver = {
2520 .name = KBUILD_MODNAME,
2521 .id_table = rt61pci_device_table,
2522 .probe = rt2x00pci_probe,
2523 .remove = __devexit_p(rt2x00pci_remove),
2524 .suspend = rt2x00pci_suspend,
2525 .resume = rt2x00pci_resume,
2528 static int __init rt61pci_init(void)
2530 return pci_register_driver(&rt61pci_driver);
2533 static void __exit rt61pci_exit(void)
2535 pci_unregister_driver(&rt61pci_driver);
2538 module_init(rt61pci_init);
2539 module_exit(rt61pci_exit);