git.oblomov.eu Git - linux-2.6/blob - drivers/scsi/stex.c

   1 /*
   2  * SuperTrak EX Series Storage Controller driver for Linux
   3  *
   4  *      Copyright (C) 2005-2009 Promise Technology Inc.
   5  *
   6  *      This program is free software; you can redistribute it and/or
   7  *      modify it under the terms of the GNU General Public License
   8  *      as published by the Free Software Foundation; either version
   9  *      2 of the License, or (at your option) any later version.
  10  *
  11  *      Written By:
  12  *              Ed Lin <promise_linux@promise.com>
  13  *
  14  */
  15
  16 #include <linux/init.h>
  17 #include <linux/errno.h>
  18 #include <linux/kernel.h>
  19 #include <linux/delay.h>
  20 #include <linux/time.h>
  21 #include <linux/pci.h>
  22 #include <linux/blkdev.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/types.h>
  25 #include <linux/module.h>
  26 #include <linux/spinlock.h>
  27 #include <asm/io.h>
  28 #include <asm/irq.h>
  29 #include <asm/byteorder.h>
  30 #include <scsi/scsi.h>
  31 #include <scsi/scsi_device.h>
  32 #include <scsi/scsi_cmnd.h>
  33 #include <scsi/scsi_host.h>
  34 #include <scsi/scsi_tcq.h>
  35 #include <scsi/scsi_dbg.h>
  36 #include <scsi/scsi_eh.h>
  37
  38 #define DRV_NAME "stex"
  39 #define ST_DRIVER_VERSION "4.6.0000.1"
  40 #define ST_VER_MAJOR            4
  41 #define ST_VER_MINOR            6
  42 #define ST_OEM                  0
  43 #define ST_BUILD_VER            1
  44
  45 enum {
  46         /* MU register offset */
  47         IMR0    = 0x10, /* MU_INBOUND_MESSAGE_REG0 */
  48         IMR1    = 0x14, /* MU_INBOUND_MESSAGE_REG1 */
  49         OMR0    = 0x18, /* MU_OUTBOUND_MESSAGE_REG0 */
  50         OMR1    = 0x1c, /* MU_OUTBOUND_MESSAGE_REG1 */
  51         IDBL    = 0x20, /* MU_INBOUND_DOORBELL */
  52         IIS     = 0x24, /* MU_INBOUND_INTERRUPT_STATUS */
  53         IIM     = 0x28, /* MU_INBOUND_INTERRUPT_MASK */
  54         ODBL    = 0x2c, /* MU_OUTBOUND_DOORBELL */
  55         OIS     = 0x30, /* MU_OUTBOUND_INTERRUPT_STATUS */
  56         OIM     = 0x3c, /* MU_OUTBOUND_INTERRUPT_MASK */
  57
  58         /* MU register value */
  59         MU_INBOUND_DOORBELL_HANDSHAKE           = 1,
  60         MU_INBOUND_DOORBELL_REQHEADCHANGED      = 2,
  61         MU_INBOUND_DOORBELL_STATUSTAILCHANGED   = 4,
  62         MU_INBOUND_DOORBELL_HMUSTOPPED          = 8,
  63         MU_INBOUND_DOORBELL_RESET               = 16,
  64
  65         MU_OUTBOUND_DOORBELL_HANDSHAKE          = 1,
  66         MU_OUTBOUND_DOORBELL_REQUESTTAILCHANGED = 2,
  67         MU_OUTBOUND_DOORBELL_STATUSHEADCHANGED  = 4,
  68         MU_OUTBOUND_DOORBELL_BUSCHANGE          = 8,
  69         MU_OUTBOUND_DOORBELL_HASEVENT           = 16,
  70
  71         /* MU status code */
  72         MU_STATE_STARTING                       = 1,
  73         MU_STATE_FMU_READY_FOR_HANDSHAKE        = 2,
  74         MU_STATE_SEND_HANDSHAKE_FRAME           = 3,
  75         MU_STATE_STARTED                        = 4,
  76         MU_STATE_RESETTING                      = 5,
  77
  78         MU_MAX_DELAY                            = 120,
  79         MU_HANDSHAKE_SIGNATURE                  = 0x55aaaa55,
  80         MU_HANDSHAKE_SIGNATURE_HALF             = 0x5a5a0000,
  81         MU_HARD_RESET_WAIT                      = 30000,
  82         HMU_PARTNER_TYPE                        = 2,
  83
  84         /* firmware returned values */
  85         SRB_STATUS_SUCCESS                      = 0x01,
  86         SRB_STATUS_ERROR                        = 0x04,
  87         SRB_STATUS_BUSY                         = 0x05,
  88         SRB_STATUS_INVALID_REQUEST              = 0x06,
  89         SRB_STATUS_SELECTION_TIMEOUT            = 0x0A,
  90         SRB_SEE_SENSE                           = 0x80,
  91
  92         /* task attribute */
  93         TASK_ATTRIBUTE_SIMPLE                   = 0x0,
  94         TASK_ATTRIBUTE_HEADOFQUEUE              = 0x1,
  95         TASK_ATTRIBUTE_ORDERED                  = 0x2,
  96         TASK_ATTRIBUTE_ACA                      = 0x4,
  97
  98         /* request count, etc. */
  99         MU_MAX_REQUEST                          = 32,
 100
 101         /* one message wasted, use MU_MAX_REQUEST+1
 102                 to handle MU_MAX_REQUEST messages */
 103         MU_REQ_COUNT                            = (MU_MAX_REQUEST + 1),
 104         MU_STATUS_COUNT                         = (MU_MAX_REQUEST + 1),
 105
 106         STEX_CDB_LENGTH                         = 16,
 107         REQ_VARIABLE_LEN                        = 1024,
 108         STATUS_VAR_LEN                          = 128,
 109         ST_CAN_QUEUE                            = MU_MAX_REQUEST,
 110         ST_CMD_PER_LUN                          = MU_MAX_REQUEST,
 111         ST_MAX_SG                               = 32,
 112
 113         /* sg flags */
 114         SG_CF_EOT                               = 0x80, /* end of table */
 115         SG_CF_64B                               = 0x40, /* 64 bit item */
 116         SG_CF_HOST                              = 0x20, /* sg in host memory */
 117         MSG_DATA_DIR_ND                         = 0,
 118         MSG_DATA_DIR_IN                         = 1,
 119         MSG_DATA_DIR_OUT                        = 2,
 120
 121         st_shasta                               = 0,
 122         st_vsc                                  = 1,
 123         st_vsc1                                 = 2,
 124         st_yosemite                             = 3,
 125         st_seq                                  = 4,
 126
 127         PASSTHRU_REQ_TYPE                       = 0x00000001,
 128         PASSTHRU_REQ_NO_WAKEUP                  = 0x00000100,
 129         ST_INTERNAL_TIMEOUT                     = 180,
 130
 131         ST_TO_CMD                               = 0,
 132         ST_FROM_CMD                             = 1,
 133
 134         /* vendor specific commands of Promise */
 135         MGT_CMD                                 = 0xd8,
 136         SINBAND_MGT_CMD                         = 0xd9,
 137         ARRAY_CMD                               = 0xe0,
 138         CONTROLLER_CMD                          = 0xe1,
 139         DEBUGGING_CMD                           = 0xe2,
 140         PASSTHRU_CMD                            = 0xe3,
 141
 142         PASSTHRU_GET_ADAPTER                    = 0x05,
 143         PASSTHRU_GET_DRVVER                     = 0x10,
 144
 145         CTLR_CONFIG_CMD                         = 0x03,
 146         CTLR_SHUTDOWN                           = 0x0d,
 147
 148         CTLR_POWER_STATE_CHANGE                 = 0x0e,
 149         CTLR_POWER_SAVING                       = 0x01,
 150
 151         PASSTHRU_SIGNATURE                      = 0x4e415041,
 152         MGT_CMD_SIGNATURE                       = 0xba,
 153
 154         INQUIRY_EVPD                            = 0x01,
 155
 156         ST_ADDITIONAL_MEM                       = 0x200000,
 157 };
 158
 159 struct st_sgitem {
 160         u8 ctrl;        /* SG_CF_xxx */
 161         u8 reserved[3];
 162         __le32 count;
 163         __le64 addr;
 164 };
 165
 166 struct st_sgtable {
 167         __le16 sg_count;
 168         __le16 max_sg_count;
 169         __le32 sz_in_byte;
 170 };
 171
 172 struct handshake_frame {
 173         __le64 rb_phy;          /* request payload queue physical address */
 174         __le16 req_sz;          /* size of each request payload */
 175         __le16 req_cnt;         /* count of reqs the buffer can hold */
 176         __le16 status_sz;       /* size of each status payload */
 177         __le16 status_cnt;      /* count of status the buffer can hold */
 178         __le64 hosttime;        /* seconds from Jan 1, 1970 (GMT) */
 179         u8 partner_type;        /* who sends this frame */
 180         u8 reserved0[7];
 181         __le32 partner_ver_major;
 182         __le32 partner_ver_minor;
 183         __le32 partner_ver_oem;
 184         __le32 partner_ver_build;
 185         __le32 extra_offset;    /* NEW */
 186         __le32 extra_size;      /* NEW */
 187         u32 reserved1[2];
 188 };
 189
 190 struct req_msg {
 191         __le16 tag;
 192         u8 lun;
 193         u8 target;
 194         u8 task_attr;
 195         u8 task_manage;
 196         u8 data_dir;
 197         u8 payload_sz;          /* payload size in 4-byte, not used */
 198         u8 cdb[STEX_CDB_LENGTH];
 199         u8 variable[REQ_VARIABLE_LEN];
 200 };
 201
 202 struct status_msg {
 203         __le16 tag;
 204         u8 lun;
 205         u8 target;
 206         u8 srb_status;
 207         u8 scsi_status;
 208         u8 reserved;
 209         u8 payload_sz;          /* payload size in 4-byte */
 210         u8 variable[STATUS_VAR_LEN];
 211 };
 212
 213 struct ver_info {
 214         u32 major;
 215         u32 minor;
 216         u32 oem;
 217         u32 build;
 218         u32 reserved[2];
 219 };
 220
 221 struct st_frame {
 222         u32 base[6];
 223         u32 rom_addr;
 224
 225         struct ver_info drv_ver;
 226         struct ver_info bios_ver;
 227
 228         u32 bus;
 229         u32 slot;
 230         u32 irq_level;
 231         u32 irq_vec;
 232         u32 id;
 233         u32 subid;
 234
 235         u32 dimm_size;
 236         u8 dimm_type;
 237         u8 reserved[3];
 238
 239         u32 channel;
 240         u32 reserved1;
 241 };
 242
 243 struct st_drvver {
 244         u32 major;
 245         u32 minor;
 246         u32 oem;
 247         u32 build;
 248         u32 signature[2];
 249         u8 console_id;
 250         u8 host_no;
 251         u8 reserved0[2];
 252         u32 reserved[3];
 253 };
 254
 255 #define MU_REQ_BUFFER_SIZE      (MU_REQ_COUNT * sizeof(struct req_msg))
 256 #define MU_STATUS_BUFFER_SIZE   (MU_STATUS_COUNT * sizeof(struct status_msg))
 257 #define MU_BUFFER_SIZE          (MU_REQ_BUFFER_SIZE + MU_STATUS_BUFFER_SIZE)
 258 #define STEX_EXTRA_SIZE         sizeof(struct st_frame)
 259 #define STEX_BUFFER_SIZE        (MU_BUFFER_SIZE + STEX_EXTRA_SIZE)
 260
 261 struct st_ccb {
 262         struct req_msg *req;
 263         struct scsi_cmnd *cmd;
 264
 265         void *sense_buffer;
 266         unsigned int sense_bufflen;
 267         int sg_count;
 268
 269         u32 req_type;
 270         u8 srb_status;
 271         u8 scsi_status;
 272         u8 reserved[2];
 273 };
 274
 275 struct st_hba {
 276         void __iomem *mmio_base;        /* iomapped PCI memory space */
 277         void *dma_mem;
 278         dma_addr_t dma_handle;
 279         size_t dma_size;
 280
 281         struct Scsi_Host *host;
 282         struct pci_dev *pdev;
 283
 284         u32 req_head;
 285         u32 req_tail;
 286         u32 status_head;
 287         u32 status_tail;
 288
 289         struct status_msg *status_buffer;
 290         void *copy_buffer; /* temp buffer for driver-handled commands */
 291         struct st_ccb ccb[MU_MAX_REQUEST];
 292         struct st_ccb *wait_ccb;
 293
 294         unsigned int mu_status;
 295         unsigned int cardtype;
 296         int msi_enabled;
 297         int out_req_cnt;
 298 };
 299
 300 static int msi;
 301 module_param(msi, int, 0);
 302 MODULE_PARM_DESC(msi, "Enable Message Signaled Interrupts(0=off, 1=on)");
 303
 304 static const char console_inq_page[] =
 305 {
 306         0x03,0x00,0x03,0x03,0xFA,0x00,0x00,0x30,
 307         0x50,0x72,0x6F,0x6D,0x69,0x73,0x65,0x20,        /* "Promise " */
 308         0x52,0x41,0x49,0x44,0x20,0x43,0x6F,0x6E,        /* "RAID Con" */
 309         0x73,0x6F,0x6C,0x65,0x20,0x20,0x20,0x20,        /* "sole    " */
 310         0x31,0x2E,0x30,0x30,0x20,0x20,0x20,0x20,        /* "1.00    " */
 311         0x53,0x58,0x2F,0x52,0x53,0x41,0x46,0x2D,        /* "SX/RSAF-" */
 312         0x54,0x45,0x31,0x2E,0x30,0x30,0x20,0x20,        /* "TE1.00  " */
 313         0x0C,0x20,0x20,0x20,0x20,0x20,0x20,0x20
 314 };
 315
 316 MODULE_AUTHOR("Ed Lin");
 317 MODULE_DESCRIPTION("Promise Technology SuperTrak EX Controllers");
 318 MODULE_LICENSE("GPL");
 319 MODULE_VERSION(ST_DRIVER_VERSION);
 320
 321 static void stex_gettime(__le64 *time)
 322 {
 323         struct timeval tv;
 324
 325         do_gettimeofday(&tv);
 326         *time = cpu_to_le64(tv.tv_sec);
 327 }
 328
 329 static struct status_msg *stex_get_status(struct st_hba *hba)
 330 {
 331         struct status_msg *status = hba->status_buffer + hba->status_tail;
 332
 333         ++hba->status_tail;
 334         hba->status_tail %= MU_STATUS_COUNT;
 335
 336         return status;
 337 }
 338
 339 static void stex_invalid_field(struct scsi_cmnd *cmd,
 340                                void (*done)(struct scsi_cmnd *))
 341 {
 342         cmd->result = (DRIVER_SENSE << 24) | SAM_STAT_CHECK_CONDITION;
 343
 344         /* "Invalid field in cdb" */
 345         scsi_build_sense_buffer(0, cmd->sense_buffer, ILLEGAL_REQUEST, 0x24,
 346                                 0x0);
 347         done(cmd);
 348 }
 349
 350 static struct req_msg *stex_alloc_req(struct st_hba *hba)
 351 {
 352         struct req_msg *req = ((struct req_msg *)hba->dma_mem) +
 353                 hba->req_head;
 354
 355         ++hba->req_head;
 356         hba->req_head %= MU_REQ_COUNT;
 357
 358         return req;
 359 }
 360
 361 static int stex_map_sg(struct st_hba *hba,
 362         struct req_msg *req, struct st_ccb *ccb)
 363 {
 364         struct scsi_cmnd *cmd;
 365         struct scatterlist *sg;
 366         struct st_sgtable *dst;
 367         struct st_sgitem *table;
 368         int i, nseg;
 369
 370         cmd = ccb->cmd;
 371         nseg = scsi_dma_map(cmd);
 372         BUG_ON(nseg < 0);
 373         if (nseg) {
 374                 dst = (struct st_sgtable *)req->variable;
 375
 376                 ccb->sg_count = nseg;
 377                 dst->sg_count = cpu_to_le16((u16)nseg);
 378                 dst->max_sg_count = cpu_to_le16(hba->host->sg_tablesize);
 379                 dst->sz_in_byte = cpu_to_le32(scsi_bufflen(cmd));
 380
 381                 table = (struct st_sgitem *)(dst + 1);
 382                 scsi_for_each_sg(cmd, sg, nseg, i) {
 383                         table[i].count = cpu_to_le32((u32)sg_dma_len(sg));
 384                         table[i].addr = cpu_to_le64(sg_dma_address(sg));
 385                         table[i].ctrl = SG_CF_64B | SG_CF_HOST;
 386                 }
 387                 table[--i].ctrl |= SG_CF_EOT;
 388         }
 389
 390         return nseg;
 391 }
 392
 393 static void stex_controller_info(struct st_hba *hba, struct st_ccb *ccb)
 394 {
 395         struct st_frame *p;
 396         size_t count = sizeof(struct st_frame);
 397
 398         p = hba->copy_buffer;
 399         scsi_sg_copy_to_buffer(ccb->cmd, p, count);
 400         memset(p->base, 0, sizeof(u32)*6);
 401         *(unsigned long *)(p->base) = pci_resource_start(hba->pdev, 0);
 402         p->rom_addr = 0;
 403
 404         p->drv_ver.major = ST_VER_MAJOR;
 405         p->drv_ver.minor = ST_VER_MINOR;
 406         p->drv_ver.oem = ST_OEM;
 407         p->drv_ver.build = ST_BUILD_VER;
 408
 409         p->bus = hba->pdev->bus->number;
 410         p->slot = hba->pdev->devfn;
 411         p->irq_level = 0;
 412         p->irq_vec = hba->pdev->irq;
 413         p->id = hba->pdev->vendor << 16 | hba->pdev->device;
 414         p->subid =
 415                 hba->pdev->subsystem_vendor << 16 | hba->pdev->subsystem_device;
 416
 417         scsi_sg_copy_from_buffer(ccb->cmd, p, count);
 418 }
 419
 420 static void
 421 stex_send_cmd(struct st_hba *hba, struct req_msg *req, u16 tag)
 422 {
 423         req->tag = cpu_to_le16(tag);
 424
 425         hba->ccb[tag].req = req;
 426         hba->out_req_cnt++;
 427
 428         writel(hba->req_head, hba->mmio_base + IMR0);
 429         writel(MU_INBOUND_DOORBELL_REQHEADCHANGED, hba->mmio_base + IDBL);
 430         readl(hba->mmio_base + IDBL); /* flush */
 431 }
 432
 433 static int
 434 stex_slave_alloc(struct scsi_device *sdev)
 435 {
 436         /* Cheat: usually extracted from Inquiry data */
 437         sdev->tagged_supported = 1;
 438
 439         scsi_activate_tcq(sdev, sdev->host->can_queue);
 440
 441         return 0;
 442 }
 443
 444 static int
 445 stex_slave_config(struct scsi_device *sdev)
 446 {
 447         sdev->use_10_for_rw = 1;
 448         sdev->use_10_for_ms = 1;
 449         blk_queue_rq_timeout(sdev->request_queue, 60 * HZ);
 450         sdev->tagged_supported = 1;
 451
 452         return 0;
 453 }
 454
 455 static void
 456 stex_slave_destroy(struct scsi_device *sdev)
 457 {
 458         scsi_deactivate_tcq(sdev, 1);
 459 }
 460
 461 static int
 462 stex_queuecommand(struct scsi_cmnd *cmd, void (* done)(struct scsi_cmnd *))
 463 {
 464         struct st_hba *hba;
 465         struct Scsi_Host *host;
 466         unsigned int id, lun;
 467         struct req_msg *req;
 468         u16 tag;
 469
 470         host = cmd->device->host;
 471         id = cmd->device->id;
 472         lun = cmd->device->lun;
 473         hba = (struct st_hba *) &host->hostdata[0];
 474
 475         switch (cmd->cmnd[0]) {
 476         case MODE_SENSE_10:
 477         {
 478                 static char ms10_caching_page[12] =
 479                         { 0, 0x12, 0, 0, 0, 0, 0, 0, 0x8, 0xa, 0x4, 0 };
 480                 unsigned char page;
 481
 482                 page = cmd->cmnd[2] & 0x3f;
 483                 if (page == 0x8 || page == 0x3f) {
 484                         scsi_sg_copy_from_buffer(cmd, ms10_caching_page,
 485                                                  sizeof(ms10_caching_page));
 486                         cmd->result = DID_OK << 16 | COMMAND_COMPLETE << 8;
 487                         done(cmd);
 488                 } else
 489                         stex_invalid_field(cmd, done);
 490                 return 0;
 491         }
 492         case REPORT_LUNS:
 493                 /*
 494                  * The shasta firmware does not report actual luns in the
 495                  * target, so fail the command to force sequential lun scan.
 496                  * Also, the console device does not support this command.
 497                  */
 498                 if (hba->cardtype == st_shasta || id == host->max_id - 1) {
 499                         stex_invalid_field(cmd, done);
 500                         return 0;
 501                 }
 502                 break;
 503         case TEST_UNIT_READY:
 504                 if (id == host->max_id - 1) {
 505                         cmd->result = DID_OK << 16 | COMMAND_COMPLETE << 8;
 506                         done(cmd);
 507                         return 0;
 508                 }
 509                 break;
 510         case INQUIRY:
 511                 if (id != host->max_id - 1)
 512                         break;
 513                 if (lun == 0 && (cmd->cmnd[1] & INQUIRY_EVPD) == 0) {
 514                         scsi_sg_copy_from_buffer(cmd, (void *)console_inq_page,
 515                                                  sizeof(console_inq_page));
 516                         cmd->result = DID_OK << 16 | COMMAND_COMPLETE << 8;
 517                         done(cmd);
 518                 } else
 519                         stex_invalid_field(cmd, done);
 520                 return 0;
 521         case PASSTHRU_CMD:
 522                 if (cmd->cmnd[1] == PASSTHRU_GET_DRVVER) {
 523                         struct st_drvver ver;
 524                         size_t cp_len = sizeof(ver);
 525
 526                         ver.major = ST_VER_MAJOR;
 527                         ver.minor = ST_VER_MINOR;
 528                         ver.oem = ST_OEM;
 529                         ver.build = ST_BUILD_VER;
 530                         ver.signature[0] = PASSTHRU_SIGNATURE;
 531                         ver.console_id = host->max_id - 1;
 532                         ver.host_no = hba->host->host_no;
 533                         cp_len = scsi_sg_copy_from_buffer(cmd, &ver, cp_len);
 534                         cmd->result = sizeof(ver) == cp_len ?
 535                                 DID_OK << 16 | COMMAND_COMPLETE << 8 :
 536                                 DID_ERROR << 16 | COMMAND_COMPLETE << 8;
 537                         done(cmd);
 538                         return 0;
 539                 }
 540         default:
 541                 break;
 542         }
 543
 544         cmd->scsi_done = done;
 545
 546         tag = cmd->request->tag;
 547
 548         if (unlikely(tag >= host->can_queue))
 549                 return SCSI_MLQUEUE_HOST_BUSY;
 550
 551         req = stex_alloc_req(hba);
 552
 553         req->lun = lun;
 554         req->target = id;
 555
 556         /* cdb */
 557         memcpy(req->cdb, cmd->cmnd, STEX_CDB_LENGTH);
 558
 559         if (cmd->sc_data_direction == DMA_FROM_DEVICE)
 560                 req->data_dir = MSG_DATA_DIR_IN;
 561         else if (cmd->sc_data_direction == DMA_TO_DEVICE)
 562                 req->data_dir = MSG_DATA_DIR_OUT;
 563         else
 564                 req->data_dir = MSG_DATA_DIR_ND;
 565
 566         hba->ccb[tag].cmd = cmd;
 567         hba->ccb[tag].sense_bufflen = SCSI_SENSE_BUFFERSIZE;
 568         hba->ccb[tag].sense_buffer = cmd->sense_buffer;
 569
 570         if (cmd->sc_data_direction != DMA_NONE)
 571                 stex_map_sg(hba, req, &hba->ccb[tag]);
 572
 573         stex_send_cmd(hba, req, tag);
 574         return 0;
 575 }
 576
 577 static void stex_scsi_done(struct st_ccb *ccb)
 578 {
 579         struct scsi_cmnd *cmd = ccb->cmd;
 580         int result;
 581
 582         if (ccb->srb_status == SRB_STATUS_SUCCESS || ccb->srb_status == 0) {
 583                 result = ccb->scsi_status;
 584                 switch (ccb->scsi_status) {
 585                 case SAM_STAT_GOOD:
 586                         result |= DID_OK << 16 | COMMAND_COMPLETE << 8;
 587                         break;
 588                 case SAM_STAT_CHECK_CONDITION:
 589                         result |= DRIVER_SENSE << 24;
 590                         break;
 591                 case SAM_STAT_BUSY:
 592                         result |= DID_BUS_BUSY << 16 | COMMAND_COMPLETE << 8;
 593                         break;
 594                 default:
 595                         result |= DID_ERROR << 16 | COMMAND_COMPLETE << 8;
 596                         break;
 597                 }
 598         }
 599         else if (ccb->srb_status & SRB_SEE_SENSE)
 600                 result = DRIVER_SENSE << 24 | SAM_STAT_CHECK_CONDITION;
 601         else switch (ccb->srb_status) {
 602                 case SRB_STATUS_SELECTION_TIMEOUT:
 603                         result = DID_NO_CONNECT << 16 | COMMAND_COMPLETE << 8;
 604                         break;
 605                 case SRB_STATUS_BUSY:
 606                         result = DID_BUS_BUSY << 16 | COMMAND_COMPLETE << 8;
 607                         break;
 608                 case SRB_STATUS_INVALID_REQUEST:
 609                 case SRB_STATUS_ERROR:
 610                 default:
 611                         result = DID_ERROR << 16 | COMMAND_COMPLETE << 8;
 612                         break;
 613         }
 614
 615         cmd->result = result;
 616         cmd->scsi_done(cmd);
 617 }
 618
 619 static void stex_copy_data(struct st_ccb *ccb,
 620         struct status_msg *resp, unsigned int variable)
 621 {
 622         if (resp->scsi_status != SAM_STAT_GOOD) {
 623                 if (ccb->sense_buffer != NULL)
 624                         memcpy(ccb->sense_buffer, resp->variable,
 625                                 min(variable, ccb->sense_bufflen));
 626                 return;
 627         }
 628
 629         if (ccb->cmd == NULL)
 630                 return;
 631         scsi_sg_copy_from_buffer(ccb->cmd, resp->variable, variable);
 632 }
 633
 634 static void stex_check_cmd(struct st_hba *hba,
 635         struct st_ccb *ccb, struct status_msg *resp)
 636 {
 637         if (ccb->cmd->cmnd[0] == MGT_CMD &&
 638                 resp->scsi_status != SAM_STAT_CHECK_CONDITION)
 639                 scsi_set_resid(ccb->cmd, scsi_bufflen(ccb->cmd) -
 640                         le32_to_cpu(*(__le32 *)&resp->variable[0]));
 641 }
 642
 643 static void stex_mu_intr(struct st_hba *hba, u32 doorbell)
 644 {
 645         void __iomem *base = hba->mmio_base;
 646         struct status_msg *resp;
 647         struct st_ccb *ccb;
 648         unsigned int size;
 649         u16 tag;
 650
 651         if (unlikely(!(doorbell & MU_OUTBOUND_DOORBELL_STATUSHEADCHANGED)))
 652                 return;
 653
 654         /* status payloads */
 655         hba->status_head = readl(base + OMR1);
 656         if (unlikely(hba->status_head >= MU_STATUS_COUNT)) {
 657                 printk(KERN_WARNING DRV_NAME "(%s): invalid status head\n",
 658                         pci_name(hba->pdev));
 659                 return;
 660         }
 661
 662         /*
 663          * it's not a valid status payload if:
 664          * 1. there are no pending requests(e.g. during init stage)
 665          * 2. there are some pending requests, but the controller is in
 666          *     reset status, and its type is not st_yosemite
 667          * firmware of st_yosemite in reset status will return pending requests
 668          * to driver, so we allow it to pass
 669          */
 670         if (unlikely(hba->out_req_cnt <= 0 ||
 671                         (hba->mu_status == MU_STATE_RESETTING &&
 672                          hba->cardtype != st_yosemite))) {
 673                 hba->status_tail = hba->status_head;
 674                 goto update_status;
 675         }
 676
 677         while (hba->status_tail != hba->status_head) {
 678                 resp = stex_get_status(hba);
 679                 tag = le16_to_cpu(resp->tag);
 680                 if (unlikely(tag >= hba->host->can_queue)) {
 681                         printk(KERN_WARNING DRV_NAME
 682                                 "(%s): invalid tag\n", pci_name(hba->pdev));
 683                         continue;
 684                 }
 685
 686                 hba->out_req_cnt--;
 687                 ccb = &hba->ccb[tag];
 688                 if (unlikely(hba->wait_ccb == ccb))
 689                         hba->wait_ccb = NULL;
 690                 if (unlikely(ccb->req == NULL)) {
 691                         printk(KERN_WARNING DRV_NAME
 692                                 "(%s): lagging req\n", pci_name(hba->pdev));
 693                         continue;
 694                 }
 695
 696                 size = resp->payload_sz * sizeof(u32); /* payload size */
 697                 if (unlikely(size < sizeof(*resp) - STATUS_VAR_LEN ||
 698                         size > sizeof(*resp))) {
 699                         printk(KERN_WARNING DRV_NAME "(%s): bad status size\n",
 700                                 pci_name(hba->pdev));
 701                 } else {
 702                         size -= sizeof(*resp) - STATUS_VAR_LEN; /* copy size */
 703                         if (size)
 704                                 stex_copy_data(ccb, resp, size);
 705                 }
 706
 707                 ccb->req = NULL;
 708                 ccb->srb_status = resp->srb_status;
 709                 ccb->scsi_status = resp->scsi_status;
 710
 711                 if (likely(ccb->cmd != NULL)) {
 712                         if (hba->cardtype == st_yosemite)
 713                                 stex_check_cmd(hba, ccb, resp);
 714
 715                         if (unlikely(ccb->cmd->cmnd[0] == PASSTHRU_CMD &&
 716                                 ccb->cmd->cmnd[1] == PASSTHRU_GET_ADAPTER))
 717                                 stex_controller_info(hba, ccb);
 718
 719                         scsi_dma_unmap(ccb->cmd);
 720                         stex_scsi_done(ccb);
 721                 } else
 722                         ccb->req_type = 0;
 723         }
 724
 725 update_status:
 726         writel(hba->status_head, base + IMR1);
 727         readl(base + IMR1); /* flush */
 728 }
 729
 730 static irqreturn_t stex_intr(int irq, void *__hba)
 731 {
 732         struct st_hba *hba = __hba;
 733         void __iomem *base = hba->mmio_base;
 734         u32 data;
 735         unsigned long flags;
 736         int handled = 0;
 737
 738         spin_lock_irqsave(hba->host->host_lock, flags);
 739
 740         data = readl(base + ODBL);
 741
 742         if (data && data != 0xffffffff) {
 743                 /* clear the interrupt */
 744                 writel(data, base + ODBL);
 745                 readl(base + ODBL); /* flush */
 746                 stex_mu_intr(hba, data);
 747                 handled = 1;
 748         }
 749
 750         spin_unlock_irqrestore(hba->host->host_lock, flags);
 751
 752         return IRQ_RETVAL(handled);
 753 }
 754
 755 static int stex_handshake(struct st_hba *hba)
 756 {
 757         void __iomem *base = hba->mmio_base;
 758         struct handshake_frame *h;
 759         dma_addr_t status_phys;
 760         u32 data;
 761         unsigned long before;
 762
 763         if (readl(base + OMR0) != MU_HANDSHAKE_SIGNATURE) {
 764                 writel(MU_INBOUND_DOORBELL_HANDSHAKE, base + IDBL);
 765                 readl(base + IDBL);
 766                 before = jiffies;
 767                 while (readl(base + OMR0) != MU_HANDSHAKE_SIGNATURE) {
 768                         if (time_after(jiffies, before + MU_MAX_DELAY * HZ)) {
 769                                 printk(KERN_ERR DRV_NAME
 770                                         "(%s): no handshake signature\n",
 771                                         pci_name(hba->pdev));
 772                                 return -1;
 773                         }
 774                         rmb();
 775                         msleep(1);
 776                 }
 777         }
 778
 779         udelay(10);
 780
 781         data = readl(base + OMR1);
 782         if ((data & 0xffff0000) == MU_HANDSHAKE_SIGNATURE_HALF) {
 783                 data &= 0x0000ffff;
 784                 if (hba->host->can_queue > data) {
 785                         hba->host->can_queue = data;
 786                         hba->host->cmd_per_lun = data;
 787                 }
 788         }
 789
 790         h = (struct handshake_frame *)hba->status_buffer;
 791         h->rb_phy = cpu_to_le64(hba->dma_handle);
 792         h->req_sz = cpu_to_le16(sizeof(struct req_msg));
 793         h->req_cnt = cpu_to_le16(MU_REQ_COUNT);
 794         h->status_sz = cpu_to_le16(sizeof(struct status_msg));
 795         h->status_cnt = cpu_to_le16(MU_STATUS_COUNT);
 796         stex_gettime(&h->hosttime);
 797         h->partner_type = HMU_PARTNER_TYPE;
 798         if (hba->dma_size > STEX_BUFFER_SIZE) {
 799                 h->extra_offset = cpu_to_le32(STEX_BUFFER_SIZE);
 800                 h->extra_size = cpu_to_le32(ST_ADDITIONAL_MEM);
 801         } else
 802                 h->extra_offset = h->extra_size = 0;
 803
 804         status_phys = hba->dma_handle + MU_REQ_BUFFER_SIZE;
 805         writel(status_phys, base + IMR0);
 806         readl(base + IMR0);
 807         writel((status_phys >> 16) >> 16, base + IMR1);
 808         readl(base + IMR1);
 809
 810         writel((status_phys >> 16) >> 16, base + OMR0); /* old fw compatible */
 811         readl(base + OMR0);
 812         writel(MU_INBOUND_DOORBELL_HANDSHAKE, base + IDBL);
 813         readl(base + IDBL); /* flush */
 814
 815         udelay(10);
 816         before = jiffies;
 817         while (readl(base + OMR0) != MU_HANDSHAKE_SIGNATURE) {
 818                 if (time_after(jiffies, before + MU_MAX_DELAY * HZ)) {
 819                         printk(KERN_ERR DRV_NAME
 820                                 "(%s): no signature after handshake frame\n",
 821                                 pci_name(hba->pdev));
 822                         return -1;
 823                 }
 824                 rmb();
 825                 msleep(1);
 826         }
 827
 828         writel(0, base + IMR0);
 829         readl(base + IMR0);
 830         writel(0, base + OMR0);
 831         readl(base + OMR0);
 832         writel(0, base + IMR1);
 833         readl(base + IMR1);
 834         writel(0, base + OMR1);
 835         readl(base + OMR1); /* flush */
 836         hba->mu_status = MU_STATE_STARTED;
 837         return 0;
 838 }
 839
 840 static int stex_abort(struct scsi_cmnd *cmd)
 841 {
 842         struct Scsi_Host *host = cmd->device->host;
 843         struct st_hba *hba = (struct st_hba *)host->hostdata;
 844         u16 tag = cmd->request->tag;
 845         void __iomem *base;
 846         u32 data;
 847         int result = SUCCESS;
 848         unsigned long flags;
 849
 850         printk(KERN_INFO DRV_NAME
 851                 "(%s): aborting command\n", pci_name(hba->pdev));
 852         scsi_print_command(cmd);
 853
 854         base = hba->mmio_base;
 855         spin_lock_irqsave(host->host_lock, flags);
 856         if (tag < host->can_queue && hba->ccb[tag].cmd == cmd)
 857                 hba->wait_ccb = &hba->ccb[tag];
 858         else {
 859                 for (tag = 0; tag < host->can_queue; tag++)
 860                         if (hba->ccb[tag].cmd == cmd) {
 861                                 hba->wait_ccb = &hba->ccb[tag];
 862                                 break;
 863                         }
 864                 if (tag >= host->can_queue)
 865                         goto out;
 866         }
 867
 868         data = readl(base + ODBL);
 869         if (data == 0 || data == 0xffffffff)
 870                 goto fail_out;
 871
 872         writel(data, base + ODBL);
 873         readl(base + ODBL); /* flush */
 874
 875         stex_mu_intr(hba, data);
 876
 877         if (hba->wait_ccb == NULL) {
 878                 printk(KERN_WARNING DRV_NAME
 879                         "(%s): lost interrupt\n", pci_name(hba->pdev));
 880                 goto out;
 881         }
 882
 883 fail_out:
 884         scsi_dma_unmap(cmd);
 885         hba->wait_ccb->req = NULL; /* nullify the req's future return */
 886         hba->wait_ccb = NULL;
 887         result = FAILED;
 888 out:
 889         spin_unlock_irqrestore(host->host_lock, flags);
 890         return result;
 891 }
 892
 893 static void stex_hard_reset(struct st_hba *hba)
 894 {
 895         struct pci_bus *bus;
 896         int i;
 897         u16 pci_cmd;
 898         u8 pci_bctl;
 899
 900         for (i = 0; i < 16; i++)
 901                 pci_read_config_dword(hba->pdev, i * 4,
 902                         &hba->pdev->saved_config_space[i]);
 903
 904         /* Reset secondary bus. Our controller(MU/ATU) is the only device on
 905            secondary bus. Consult Intel 80331/3 developer's manual for detail */
 906         bus = hba->pdev->bus;
 907         pci_read_config_byte(bus->self, PCI_BRIDGE_CONTROL, &pci_bctl);
 908         pci_bctl |= PCI_BRIDGE_CTL_BUS_RESET;
 909         pci_write_config_byte(bus->self, PCI_BRIDGE_CONTROL, pci_bctl);
 910
 911         /*
 912          * 1 ms may be enough for 8-port controllers. But 16-port controllers
 913          * require more time to finish bus reset. Use 100 ms here for safety
 914          */
 915         msleep(100);
 916         pci_bctl &= ~PCI_BRIDGE_CTL_BUS_RESET;
 917         pci_write_config_byte(bus->self, PCI_BRIDGE_CONTROL, pci_bctl);
 918
 919         for (i = 0; i < MU_HARD_RESET_WAIT; i++) {
 920                 pci_read_config_word(hba->pdev, PCI_COMMAND, &pci_cmd);
 921                 if (pci_cmd != 0xffff && (pci_cmd & PCI_COMMAND_MASTER))
 922                         break;
 923                 msleep(1);
 924         }
 925
 926         ssleep(5);
 927         for (i = 0; i < 16; i++)
 928                 pci_write_config_dword(hba->pdev, i * 4,
 929                         hba->pdev->saved_config_space[i]);
 930 }
 931
 932 static int stex_reset(struct scsi_cmnd *cmd)
 933 {
 934         struct st_hba *hba;
 935         void __iomem *base;
 936         unsigned long flags, before;
 937
 938         hba = (struct st_hba *) &cmd->device->host->hostdata[0];
 939
 940         printk(KERN_INFO DRV_NAME
 941                 "(%s): resetting host\n", pci_name(hba->pdev));
 942         scsi_print_command(cmd);
 943
 944         hba->mu_status = MU_STATE_RESETTING;
 945
 946         if (hba->cardtype == st_shasta)
 947                 stex_hard_reset(hba);
 948
 949         if (hba->cardtype != st_yosemite) {
 950                 if (stex_handshake(hba)) {
 951                         printk(KERN_WARNING DRV_NAME
 952                                 "(%s): resetting: handshake failed\n",
 953                                 pci_name(hba->pdev));
 954                         return FAILED;
 955                 }
 956                 spin_lock_irqsave(hba->host->host_lock, flags);
 957                 hba->req_head = 0;
 958                 hba->req_tail = 0;
 959                 hba->status_head = 0;
 960                 hba->status_tail = 0;
 961                 hba->out_req_cnt = 0;
 962                 spin_unlock_irqrestore(hba->host->host_lock, flags);
 963                 return SUCCESS;
 964         }
 965
 966         /* st_yosemite */
 967         writel(MU_INBOUND_DOORBELL_RESET, hba->mmio_base + IDBL);
 968         readl(hba->mmio_base + IDBL); /* flush */
 969         before = jiffies;
 970         while (hba->out_req_cnt > 0) {
 971                 if (time_after(jiffies, before + ST_INTERNAL_TIMEOUT * HZ)) {
 972                         printk(KERN_WARNING DRV_NAME
 973                                 "(%s): reset timeout\n", pci_name(hba->pdev));
 974                         return FAILED;
 975                 }
 976                 msleep(1);
 977         }
 978
 979         base = hba->mmio_base;
 980         writel(0, base + IMR0);
 981         readl(base + IMR0);
 982         writel(0, base + OMR0);
 983         readl(base + OMR0);
 984         writel(0, base + IMR1);
 985         readl(base + IMR1);
 986         writel(0, base + OMR1);
 987         readl(base + OMR1); /* flush */
 988         spin_lock_irqsave(hba->host->host_lock, flags);
 989         hba->req_head = 0;
 990         hba->req_tail = 0;
 991         hba->status_head = 0;
 992         hba->status_tail = 0;
 993         hba->out_req_cnt = 0;
 994         hba->mu_status = MU_STATE_STARTED;
 995         spin_unlock_irqrestore(hba->host->host_lock, flags);
 996         return SUCCESS;
 997 }
 998
 999 static int stex_biosparam(struct scsi_device *sdev,
1000         struct block_device *bdev, sector_t capacity, int geom[])
1001 {
1002         int heads = 255, sectors = 63;
1003
1004         if (capacity < 0x200000) {
1005                 heads = 64;
1006                 sectors = 32;
1007         }
1008
1009         sector_div(capacity, heads * sectors);
1010
1011         geom[0] = heads;
1012         geom[1] = sectors;
1013         geom[2] = capacity;
1014
1015         return 0;
1016 }
1017
1018 static struct scsi_host_template driver_template = {
1019         .module                         = THIS_MODULE,
1020         .name                           = DRV_NAME,
1021         .proc_name                      = DRV_NAME,
1022         .bios_param                     = stex_biosparam,
1023         .queuecommand                   = stex_queuecommand,
1024         .slave_alloc                    = stex_slave_alloc,
1025         .slave_configure                = stex_slave_config,
1026         .slave_destroy                  = stex_slave_destroy,
1027         .eh_abort_handler               = stex_abort,
1028         .eh_host_reset_handler          = stex_reset,
1029         .can_queue                      = ST_CAN_QUEUE,
1030         .this_id                        = -1,
1031         .sg_tablesize                   = ST_MAX_SG,
1032         .cmd_per_lun                    = ST_CMD_PER_LUN,
1033 };
1034
1035 static int stex_set_dma_mask(struct pci_dev * pdev)
1036 {
1037         int ret;
1038
1039         if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)
1040                 && !pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK))
1041                 return 0;
1042         ret = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1043         if (!ret)
1044                 ret = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1045         return ret;
1046 }
1047
1048 static int stex_request_irq(struct st_hba *hba)
1049 {
1050         struct pci_dev *pdev = hba->pdev;
1051         int status;
1052
1053         if (msi) {
1054                 status = pci_enable_msi(pdev);
1055                 if (status != 0)
1056                         printk(KERN_ERR DRV_NAME
1057                                 "(%s): error %d setting up MSI\n",
1058                                 pci_name(pdev), status);
1059                 else
1060                         hba->msi_enabled = 1;
1061         } else
1062                 hba->msi_enabled = 0;
1063
1064         status = request_irq(pdev->irq, stex_intr, IRQF_SHARED, DRV_NAME, hba);
1065
1066         if (status != 0) {
1067                 if (hba->msi_enabled)
1068                         pci_disable_msi(pdev);
1069         }
1070         return status;
1071 }
1072
1073 static void stex_free_irq(struct st_hba *hba)
1074 {
1075         struct pci_dev *pdev = hba->pdev;
1076
1077         free_irq(pdev->irq, hba);
1078         if (hba->msi_enabled)
1079                 pci_disable_msi(pdev);
1080 }
1081
1082 static int __devinit
1083 stex_probe(struct pci_dev *pdev, const struct pci_device_id *id)
1084 {
1085         struct st_hba *hba;
1086         struct Scsi_Host *host;
1087         int err;
1088
1089         err = pci_enable_device(pdev);
1090         if (err)
1091                 return err;
1092
1093         pci_set_master(pdev);
1094
1095         host = scsi_host_alloc(&driver_template, sizeof(struct st_hba));
1096
1097         if (!host) {
1098                 printk(KERN_ERR DRV_NAME "(%s): scsi_host_alloc failed\n",
1099                         pci_name(pdev));
1100                 err = -ENOMEM;
1101                 goto out_disable;
1102         }
1103
1104         hba = (struct st_hba *)host->hostdata;
1105         memset(hba, 0, sizeof(struct st_hba));
1106
1107         err = pci_request_regions(pdev, DRV_NAME);
1108         if (err < 0) {
1109                 printk(KERN_ERR DRV_NAME "(%s): request regions failed\n",
1110                         pci_name(pdev));
1111                 goto out_scsi_host_put;
1112         }
1113
1114         hba->mmio_base = pci_ioremap_bar(pdev, 0);
1115         if ( !hba->mmio_base) {
1116                 printk(KERN_ERR DRV_NAME "(%s): memory map failed\n",
1117                         pci_name(pdev));
1118                 err = -ENOMEM;
1119                 goto out_release_regions;
1120         }
1121
1122         err = stex_set_dma_mask(pdev);
1123         if (err) {
1124                 printk(KERN_ERR DRV_NAME "(%s): set dma mask failed\n",
1125                         pci_name(pdev));
1126                 goto out_iounmap;
1127         }
1128
1129         hba->cardtype = (unsigned int) id->driver_data;
1130         if (hba->cardtype == st_vsc && (pdev->subsystem_device & 1))
1131                 hba->cardtype = st_vsc1;
1132         hba->dma_size = (hba->cardtype == st_vsc1 || hba->cardtype == st_seq) ?
1133                 (STEX_BUFFER_SIZE + ST_ADDITIONAL_MEM) : (STEX_BUFFER_SIZE);
1134         hba->dma_mem = dma_alloc_coherent(&pdev->dev,
1135                 hba->dma_size, &hba->dma_handle, GFP_KERNEL);
1136         if (!hba->dma_mem) {
1137                 err = -ENOMEM;
1138                 printk(KERN_ERR DRV_NAME "(%s): dma mem alloc failed\n",
1139                         pci_name(pdev));
1140                 goto out_iounmap;
1141         }
1142
1143         hba->status_buffer =
1144                 (struct status_msg *)(hba->dma_mem + MU_REQ_BUFFER_SIZE);
1145         hba->copy_buffer = hba->dma_mem + MU_BUFFER_SIZE;
1146         hba->mu_status = MU_STATE_STARTING;
1147
1148         if (hba->cardtype == st_shasta) {
1149                 host->max_lun = 8;
1150                 host->max_id = 16 + 1;
1151         } else if (hba->cardtype == st_yosemite) {
1152                 host->max_lun = 256;
1153                 host->max_id = 1 + 1;
1154         } else {
1155                 /* st_vsc , st_vsc1 and st_seq */
1156                 host->max_lun = 1;
1157                 host->max_id = 128 + 1;
1158         }
1159         host->max_channel = 0;
1160         host->unique_id = host->host_no;
1161         host->max_cmd_len = STEX_CDB_LENGTH;
1162
1163         hba->host = host;
1164         hba->pdev = pdev;
1165
1166         err = stex_request_irq(hba);
1167         if (err) {
1168                 printk(KERN_ERR DRV_NAME "(%s): request irq failed\n",
1169                         pci_name(pdev));
1170                 goto out_pci_free;
1171         }
1172
1173         err = stex_handshake(hba);
1174         if (err)
1175                 goto out_free_irq;
1176
1177         err = scsi_init_shared_tag_map(host, host->can_queue);
1178         if (err) {
1179                 printk(KERN_ERR DRV_NAME "(%s): init shared queue failed\n",
1180                         pci_name(pdev));
1181                 goto out_free_irq;
1182         }
1183
1184         pci_set_drvdata(pdev, hba);
1185
1186         err = scsi_add_host(host, &pdev->dev);
1187         if (err) {
1188                 printk(KERN_ERR DRV_NAME "(%s): scsi_add_host failed\n",
1189                         pci_name(pdev));
1190                 goto out_free_irq;
1191         }
1192
1193         scsi_scan_host(host);
1194
1195         return 0;
1196
1197 out_free_irq:
1198         stex_free_irq(hba);
1199 out_pci_free:
1200         dma_free_coherent(&pdev->dev, hba->dma_size,
1201                           hba->dma_mem, hba->dma_handle);
1202 out_iounmap:
1203         iounmap(hba->mmio_base);
1204 out_release_regions:
1205         pci_release_regions(pdev);
1206 out_scsi_host_put:
1207         scsi_host_put(host);
1208 out_disable:
1209         pci_disable_device(pdev);
1210
1211         return err;
1212 }
1213
1214 static void stex_hba_stop(struct st_hba *hba)
1215 {
1216         struct req_msg *req;
1217         unsigned long flags;
1218         unsigned long before;
1219         u16 tag = 0;
1220
1221         spin_lock_irqsave(hba->host->host_lock, flags);
1222         req = stex_alloc_req(hba);
1223         memset(req->cdb, 0, STEX_CDB_LENGTH);
1224
1225         if (hba->cardtype == st_yosemite) {
1226                 req->cdb[0] = MGT_CMD;
1227                 req->cdb[1] = MGT_CMD_SIGNATURE;
1228                 req->cdb[2] = CTLR_CONFIG_CMD;
1229                 req->cdb[3] = CTLR_SHUTDOWN;
1230         } else {
1231                 req->cdb[0] = CONTROLLER_CMD;
1232                 req->cdb[1] = CTLR_POWER_STATE_CHANGE;
1233                 req->cdb[2] = CTLR_POWER_SAVING;
1234         }
1235
1236         hba->ccb[tag].cmd = NULL;
1237         hba->ccb[tag].sg_count = 0;
1238         hba->ccb[tag].sense_bufflen = 0;
1239         hba->ccb[tag].sense_buffer = NULL;
1240         hba->ccb[tag].req_type = PASSTHRU_REQ_TYPE;
1241
1242         stex_send_cmd(hba, req, tag);
1243         spin_unlock_irqrestore(hba->host->host_lock, flags);
1244
1245         before = jiffies;
1246         while (hba->ccb[tag].req_type & PASSTHRU_REQ_TYPE) {
1247                 if (time_after(jiffies, before + ST_INTERNAL_TIMEOUT * HZ)) {
1248                         hba->ccb[tag].req_type = 0;
1249                         return;
1250                 }
1251                 msleep(1);
1252         }
1253 }
1254
1255 static void stex_hba_free(struct st_hba *hba)
1256 {
1257         stex_free_irq(hba);
1258
1259         iounmap(hba->mmio_base);
1260
1261         pci_release_regions(hba->pdev);
1262
1263         dma_free_coherent(&hba->pdev->dev, hba->dma_size,
1264                           hba->dma_mem, hba->dma_handle);
1265 }
1266
1267 static void stex_remove(struct pci_dev *pdev)
1268 {
1269         struct st_hba *hba = pci_get_drvdata(pdev);
1270
1271         scsi_remove_host(hba->host);
1272
1273         pci_set_drvdata(pdev, NULL);
1274
1275         stex_hba_stop(hba);
1276
1277         stex_hba_free(hba);
1278
1279         scsi_host_put(hba->host);
1280
1281         pci_disable_device(pdev);
1282 }
1283
1284 static void stex_shutdown(struct pci_dev *pdev)
1285 {
1286         struct st_hba *hba = pci_get_drvdata(pdev);
1287
1288         stex_hba_stop(hba);
1289 }
1290
1291 static struct pci_device_id stex_pci_tbl[] = {
1292         /* st_shasta */
1293         { 0x105a, 0x8350, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1294                 st_shasta }, /* SuperTrak EX8350/8300/16350/16300 */
1295         { 0x105a, 0xc350, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1296                 st_shasta }, /* SuperTrak EX12350 */
1297         { 0x105a, 0x4302, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1298                 st_shasta }, /* SuperTrak EX4350 */
1299         { 0x105a, 0xe350, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1300                 st_shasta }, /* SuperTrak EX24350 */
1301
1302         /* st_vsc */
1303         { 0x105a, 0x7250, PCI_ANY_ID, PCI_ANY_ID, 0, 0, st_vsc },
1304
1305         /* st_yosemite */
1306         { 0x105a, 0x8650, PCI_ANY_ID, PCI_ANY_ID, 0, 0, st_yosemite },
1307
1308         /* st_seq */
1309         { 0x105a, 0x3360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, st_seq },
1310         { }     /* terminate list */
1311 };
1312 MODULE_DEVICE_TABLE(pci, stex_pci_tbl);
1313
1314 static struct pci_driver stex_pci_driver = {
1315         .name           = DRV_NAME,
1316         .id_table       = stex_pci_tbl,
1317         .probe          = stex_probe,
1318         .remove         = __devexit_p(stex_remove),
1319         .shutdown       = stex_shutdown,
1320 };
1321
1322 static int __init stex_init(void)
1323 {
1324         printk(KERN_INFO DRV_NAME
1325                 ": Promise SuperTrak EX Driver version: %s\n",
1326                  ST_DRIVER_VERSION);
1327
1328         return pci_register_driver(&stex_pci_driver);
1329 }
1330
1331 static void __exit stex_exit(void)
1332 {
1333         pci_unregister_driver(&stex_pci_driver);
1334 }
1335
1336 module_init(stex_init);
1337 module_exit(stex_exit);