1 /* Device Tree Source for Motorola PrPMC2800
3 * Author: Mark A. Greer <mgreer@mvista.com>
5 * 2007 (c) MontaVista, Software, Inc. This file is licensed under
6 * the terms of the GNU General Public License version 2. This program
7 * is licensed "as is" without any warranty of any kind, whether express
10 * Property values that are labeled as "Default" will be updated by bootwrapper
11 * if it can determine the exact PrPMC type.
14 * dtc -I dts -O asm -o prpmc2800.S -b 0 prpmc2800.dts
15 * dtc -I dts -O dtb -o prpmc2800.dtb -b 0 prpmc2800.dts
21 model = "PrPMC280/PrPMC2800"; /* Default */
22 compatible = "motorola,PrPMC2800";
32 clock-frequency = <2bb0b140>; /* Default (733 MHz) */
33 bus-frequency = <7f28155>; /* 133.333333 MHz */
34 timebase-frequency = <1fca055>; /* 33.333333 MHz */
35 i-cache-line-size = <20>;
36 d-cache-line-size = <20>;
37 i-cache-size = <8000>;
38 d-cache-size = <8000>;
43 device_type = "memory";
44 reg = <00000000 20000000>; /* Default (512MB) */
47 mv64x60@f1000000 { /* Marvell Discovery */
50 #interrupt-cells = <1>;
51 model = "mv64360"; /* Default */
52 compatible = "marvell,mv64x60";
53 clock-frequency = <7f28155>; /* 133.333333 MHz */
54 reg = <f1000000 00010000>;
55 virtual-reg = <f1000000>;
56 ranges = <88000000 88000000 01000000 /* PCI 0 I/O Space */
57 80000000 80000000 08000000 /* PCI 0 MEM Space */
58 a0000000 a0000000 04000000 /* User FLASH */
59 00000000 f1000000 00010000 /* Bridge's regs */
60 f2000000 f2000000 00040000>; /* Integrated SRAM */
64 compatible = "direct-mapped";
65 reg = <a0000000 4000000>; /* Default (64MB) */
68 partitions = <00000000 00100000 /* RO */
69 00100000 00040001 /* RW */
70 00140000 00400000 /* RO */
71 00540000 039c0000 /* RO */
72 03f00000 00100000>; /* RO */
73 partition-names = "FW Image A", "FW Config Data", "Kernel Image", "Filesystem", "FW Image B";
80 compatible = "marvell,mv64x60-mdio";
82 device_type = "ethernet-phy";
83 compatible = "broadcom,bcm5421";
84 interrupts = <4c>; /* GPP 12 */
85 interrupt-parent = <&/mv64x60/pic>;
89 device_type = "ethernet-phy";
90 compatible = "broadcom,bcm5421";
91 interrupts = <4c>; /* GPP 12 */
92 interrupt-parent = <&/mv64x60/pic>;
100 device_type = "network";
101 compatible = "marvell,mv64x60-eth";
104 interrupt-parent = <&/mv64x60/pic>;
105 phy = <&/mv64x60/mdio/ethernet-phy@1>;
106 local-mac-address = [ 00 00 00 00 00 00 ];
109 device_type = "network";
110 compatible = "marvell,mv64x60-eth";
113 interrupt-parent = <&/mv64x60/pic>;
114 phy = <&/mv64x60/mdio/ethernet-phy@3>;
115 local-mac-address = [ 00 00 00 00 00 00 ];
121 compatible = "marvell,mv64x60-sdma";
123 virtual-reg = <f1004000>;
124 interrupt-base = <0>;
126 interrupt-parent = <&/mv64x60/pic>;
131 compatible = "marvell,mv64x60-sdma";
133 virtual-reg = <f1006000>;
134 interrupt-base = <0>;
136 interrupt-parent = <&/mv64x60/pic>;
140 compatible = "marvell,mv64x60-brg";
143 clock-frequency = <7ed6b40>;
144 current-speed = <2580>;
149 compatible = "marvell,mv64x60-brg";
152 clock-frequency = <7ed6b40>;
153 current-speed = <2580>;
167 virtual-reg = <f100b800>;
171 device_type = "serial";
172 compatible = "marvell,mpsc";
174 virtual-reg = <f1008000>;
175 sdma = <&/mv64x60/sdma@4000>;
176 brg = <&/mv64x60/brg@b200>;
177 cunit = <&/mv64x60/cunit@f200>;
178 mpscrouting = <&/mv64x60/mpscrouting@b400>;
179 mpscintr = <&/mv64x60/mpscintr@b800>;
187 interrupt-parent = <&/mv64x60/pic>;
191 device_type = "serial";
192 compatible = "marvell,mpsc";
194 virtual-reg = <f1009000>;
195 sdma = <&/mv64x60/sdma@6000>;
196 brg = <&/mv64x60/brg@b208>;
197 cunit = <&/mv64x60/cunit@f200>;
198 mpscrouting = <&/mv64x60/mpscrouting@b400>;
199 mpscintr = <&/mv64x60/mpscintr@b800>;
207 interrupt-parent = <&/mv64x60/pic>;
212 compatible = "marvell,mv64x60-i2c";
214 virtual-reg = <f100c000>;
217 timeout = <3e8>; /* 1000 = 1 second */
220 interrupt-parent = <&/mv64x60/pic>;
224 #interrupt-cells = <1>;
225 #address-cells = <0>;
226 compatible = "marvell,mv64x60-pic";
228 interrupt-controller;
232 compatible = "marvell,mv64x60-mpp";
237 compatible = "marvell,mv64x60-gpp";
242 #address-cells = <3>;
244 #interrupt-cells = <1>;
246 compatible = "marvell,mv64x60-pci";
248 ranges = <01000000 0 0 88000000 0 01000000
249 02000000 0 80000000 80000000 0 08000000>;
251 clock-frequency = <3EF1480>;
252 interrupt-pci-iack = <0c34>;
253 interrupt-parent = <&/mv64x60/pic>;
254 interrupt-map-mask = <f800 0 0 7>;
257 5000 0 0 1 &/mv64x60/pic 50
258 5000 0 0 2 &/mv64x60/pic 51
259 5000 0 0 3 &/mv64x60/pic 5b
260 5000 0 0 4 &/mv64x60/pic 5d
263 5800 0 0 1 &/mv64x60/pic 5b
264 5800 0 0 2 &/mv64x60/pic 5d
265 5800 0 0 3 &/mv64x60/pic 50
266 5800 0 0 4 &/mv64x60/pic 51
269 6000 0 0 1 &/mv64x60/pic 5b
270 6000 0 0 2 &/mv64x60/pic 5d
271 6000 0 0 3 &/mv64x60/pic 50
272 6000 0 0 4 &/mv64x60/pic 51
275 6800 0 0 1 &/mv64x60/pic 5d
276 6800 0 0 2 &/mv64x60/pic 50
277 6800 0 0 3 &/mv64x60/pic 51
278 6800 0 0 4 &/mv64x60/pic 5b
283 compatible = "marvell,mv64x60-cpu-error";
284 reg = <0070 10 0128 28>;
286 interrupt-parent = <&/mv64x60/pic>;
290 compatible = "marvell,mv64x60-sram-ctrl";
293 interrupt-parent = <&/mv64x60/pic>;
297 compatible = "marvell,mv64x60-pci-error";
298 reg = <1d40 40 0c28 4>;
300 interrupt-parent = <&/mv64x60/pic>;
304 compatible = "marvell,mv64x60-mem-ctrl";
307 interrupt-parent = <&/mv64x60/pic>;
313 linux,stdout-path = "/mv64x60@f1000000/mpsc@8000";