1 #ifndef __ASM_CPU_SH4_DMA_H
2 #define __ASM_CPU_SH4_DMA_H
4 #define DMAOR_INIT ( 0x8000 | DMAOR_DME )
6 /* SH7751/7760/7780 DMA IRQ sources */
17 #ifdef CONFIG_CPU_SH4A
18 #define SH_DMAC_BASE 0xfc808020
20 #define CHCR_TS_MASK 0x18
21 #define CHCR_TS_SHIFT 3
23 #include <asm/cpu/dma-sh7780.h>
25 #define SH_DMAC_BASE 0xffa00000
27 /* Definitions for the SuperH DMAC */
28 #define TM_BURST 0x0000080
29 #define TS_8 0x00000010
30 #define TS_16 0x00000020
31 #define TS_32 0x00000030
32 #define TS_64 0x00000000
34 #define CHCR_TS_MASK 0x30
35 #define CHCR_TS_SHIFT 4
37 #define DMAOR_COD 0x00000008
40 * The SuperH DMAC supports a number of transmit sizes, we list them here,
41 * with their respective values as they appear in the CHCR registers.
43 * Defaults to a 64-bit transfer size.
54 * The DMA count is defined as the number of bytes to transfer.
56 static unsigned int ts_shift[] __maybe_unused = {
65 #endif /* __ASM_CPU_SH4_DMA_H */