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   1 /*
   2  *  linux/drivers/media/mmc/omap.c
   3  *
   4  *  Copyright (C) 2004 Nokia Corporation
   5  *  Written by Tuukka Tikkanen and Juha Yrjölä<juha.yrjola@nokia.com>
   6  *  Misc hacks here and there by Tony Lindgren <tony@atomide.com>
   7  *  Other hacks (DMA, SD, etc) by David Brownell
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  */
  13
  14 #include <linux/module.h>
  15 #include <linux/moduleparam.h>
  16 #include <linux/init.h>
  17 #include <linux/ioport.h>
  18 #include <linux/platform_device.h>
  19 #include <linux/interrupt.h>
  20 #include <linux/dma-mapping.h>
  21 #include <linux/delay.h>
  22 #include <linux/spinlock.h>
  23 #include <linux/timer.h>
  24 #include <linux/mmc/host.h>
  25 #include <linux/mmc/card.h>
  26 #include <linux/clk.h>
  27
  28 #include <asm/io.h>
  29 #include <asm/irq.h>
  30 #include <asm/scatterlist.h>
  31 #include <asm/mach-types.h>
  32
  33 #include <asm/arch/board.h>
  34 #include <asm/arch/gpio.h>
  35 #include <asm/arch/dma.h>
  36 #include <asm/arch/mux.h>
  37 #include <asm/arch/fpga.h>
  38 #include <asm/arch/tps65010.h>
  39
  40 #define OMAP_MMC_REG_CMD        0x00
  41 #define OMAP_MMC_REG_ARGL       0x04
  42 #define OMAP_MMC_REG_ARGH       0x08
  43 #define OMAP_MMC_REG_CON        0x0c
  44 #define OMAP_MMC_REG_STAT       0x10
  45 #define OMAP_MMC_REG_IE         0x14
  46 #define OMAP_MMC_REG_CTO        0x18
  47 #define OMAP_MMC_REG_DTO        0x1c
  48 #define OMAP_MMC_REG_DATA       0x20
  49 #define OMAP_MMC_REG_BLEN       0x24
  50 #define OMAP_MMC_REG_NBLK       0x28
  51 #define OMAP_MMC_REG_BUF        0x2c
  52 #define OMAP_MMC_REG_SDIO       0x34
  53 #define OMAP_MMC_REG_REV        0x3c
  54 #define OMAP_MMC_REG_RSP0       0x40
  55 #define OMAP_MMC_REG_RSP1       0x44
  56 #define OMAP_MMC_REG_RSP2       0x48
  57 #define OMAP_MMC_REG_RSP3       0x4c
  58 #define OMAP_MMC_REG_RSP4       0x50
  59 #define OMAP_MMC_REG_RSP5       0x54
  60 #define OMAP_MMC_REG_RSP6       0x58
  61 #define OMAP_MMC_REG_RSP7       0x5c
  62 #define OMAP_MMC_REG_IOSR       0x60
  63 #define OMAP_MMC_REG_SYSC       0x64
  64 #define OMAP_MMC_REG_SYSS       0x68
  65
  66 #define OMAP_MMC_STAT_CARD_ERR          (1 << 14)
  67 #define OMAP_MMC_STAT_CARD_IRQ          (1 << 13)
  68 #define OMAP_MMC_STAT_OCR_BUSY          (1 << 12)
  69 #define OMAP_MMC_STAT_A_EMPTY           (1 << 11)
  70 #define OMAP_MMC_STAT_A_FULL            (1 << 10)
  71 #define OMAP_MMC_STAT_CMD_CRC           (1 <<  8)
  72 #define OMAP_MMC_STAT_CMD_TOUT          (1 <<  7)
  73 #define OMAP_MMC_STAT_DATA_CRC          (1 <<  6)
  74 #define OMAP_MMC_STAT_DATA_TOUT         (1 <<  5)
  75 #define OMAP_MMC_STAT_END_BUSY          (1 <<  4)
  76 #define OMAP_MMC_STAT_END_OF_DATA       (1 <<  3)
  77 #define OMAP_MMC_STAT_CARD_BUSY         (1 <<  2)
  78 #define OMAP_MMC_STAT_END_OF_CMD        (1 <<  0)
  79
  80 #define OMAP_MMC_READ(host, reg)        __raw_readw((host)->virt_base + OMAP_MMC_REG_##reg)
  81 #define OMAP_MMC_WRITE(host, reg, val)  __raw_writew((val), (host)->virt_base + OMAP_MMC_REG_##reg)
  82
  83 /*
  84  * Command types
  85  */
  86 #define OMAP_MMC_CMDTYPE_BC     0
  87 #define OMAP_MMC_CMDTYPE_BCR    1
  88 #define OMAP_MMC_CMDTYPE_AC     2
  89 #define OMAP_MMC_CMDTYPE_ADTC   3
  90
  91
  92 #define DRIVER_NAME "mmci-omap"
  93
  94 /* Specifies how often in millisecs to poll for card status changes
  95  * when the cover switch is open */
  96 #define OMAP_MMC_SWITCH_POLL_DELAY      500
  97
  98 static int mmc_omap_enable_poll = 1;
  99
 100 struct mmc_omap_host {
 101         int                     initialized;
 102         int                     suspended;
 103         struct mmc_request *    mrq;
 104         struct mmc_command *    cmd;
 105         struct mmc_data *       data;
 106         struct mmc_host *       mmc;
 107         struct device *         dev;
 108         unsigned char           id; /* 16xx chips have 2 MMC blocks */
 109         struct clk *            iclk;
 110         struct clk *            fclk;
 111         struct resource         *mem_res;
 112         void __iomem            *virt_base;
 113         unsigned int            phys_base;
 114         int                     irq;
 115         unsigned char           bus_mode;
 116         unsigned char           hw_bus_mode;
 117
 118         unsigned int            sg_len;
 119         int                     sg_idx;
 120         u16 *                   buffer;
 121         u32                     buffer_bytes_left;
 122         u32                     total_bytes_left;
 123
 124         unsigned                use_dma:1;
 125         unsigned                brs_received:1, dma_done:1;
 126         unsigned                dma_is_read:1;
 127         unsigned                dma_in_use:1;
 128         int                     dma_ch;
 129         spinlock_t              dma_lock;
 130         struct timer_list       dma_timer;
 131         unsigned                dma_len;
 132
 133         short                   power_pin;
 134         short                   wp_pin;
 135
 136         int                     switch_pin;
 137         struct work_struct      switch_work;
 138         struct timer_list       switch_timer;
 139         int                     switch_last_state;
 140 };
 141
 142 static inline int
 143 mmc_omap_cover_is_open(struct mmc_omap_host *host)
 144 {
 145         if (host->switch_pin < 0)
 146                 return 0;
 147         return omap_get_gpio_datain(host->switch_pin);
 148 }
 149
 150 static ssize_t
 151 mmc_omap_show_cover_switch(struct device *dev,
 152         struct device_attribute *attr, char *buf)
 153 {
 154         struct mmc_omap_host *host = dev_get_drvdata(dev);
 155
 156         return sprintf(buf, "%s\n", mmc_omap_cover_is_open(host) ? "open" :
 157                         "closed");
 158 }
 159
 160 static DEVICE_ATTR(cover_switch, S_IRUGO, mmc_omap_show_cover_switch, NULL);
 161
 162 static ssize_t
 163 mmc_omap_show_enable_poll(struct device *dev,
 164         struct device_attribute *attr, char *buf)
 165 {
 166         return snprintf(buf, PAGE_SIZE, "%d\n", mmc_omap_enable_poll);
 167 }
 168
 169 static ssize_t
 170 mmc_omap_store_enable_poll(struct device *dev,
 171         struct device_attribute *attr, const char *buf,
 172         size_t size)
 173 {
 174         int enable_poll;
 175
 176         if (sscanf(buf, "%10d", &enable_poll) != 1)
 177                 return -EINVAL;
 178
 179         if (enable_poll != mmc_omap_enable_poll) {
 180                 struct mmc_omap_host *host = dev_get_drvdata(dev);
 181
 182                 mmc_omap_enable_poll = enable_poll;
 183                 if (enable_poll && host->switch_pin >= 0)
 184                         schedule_work(&host->switch_work);
 185         }
 186         return size;
 187 }
 188
 189 static DEVICE_ATTR(enable_poll, 0664,
 190                    mmc_omap_show_enable_poll, mmc_omap_store_enable_poll);
 191
 192 static void
 193 mmc_omap_start_command(struct mmc_omap_host *host, struct mmc_command *cmd)
 194 {
 195         u32 cmdreg;
 196         u32 resptype;
 197         u32 cmdtype;
 198
 199         host->cmd = cmd;
 200
 201         resptype = 0;
 202         cmdtype = 0;
 203
 204         /* Our hardware needs to know exact type */
 205         switch (mmc_resp_type(cmd)) {
 206         case MMC_RSP_NONE:
 207                 break;
 208         case MMC_RSP_R1:
 209         case MMC_RSP_R1B:
 210                 /* resp 1, 1b, 6, 7 */
 211                 resptype = 1;
 212                 break;
 213         case MMC_RSP_R2:
 214                 resptype = 2;
 215                 break;
 216         case MMC_RSP_R3:
 217                 resptype = 3;
 218                 break;
 219         default:
 220                 dev_err(mmc_dev(host->mmc), "Invalid response type: %04x\n", mmc_resp_type(cmd));
 221                 break;
 222         }
 223
 224         if (mmc_cmd_type(cmd) == MMC_CMD_ADTC) {
 225                 cmdtype = OMAP_MMC_CMDTYPE_ADTC;
 226         } else if (mmc_cmd_type(cmd) == MMC_CMD_BC) {
 227                 cmdtype = OMAP_MMC_CMDTYPE_BC;
 228         } else if (mmc_cmd_type(cmd) == MMC_CMD_BCR) {
 229                 cmdtype = OMAP_MMC_CMDTYPE_BCR;
 230         } else {
 231                 cmdtype = OMAP_MMC_CMDTYPE_AC;
 232         }
 233
 234         cmdreg = cmd->opcode | (resptype << 8) | (cmdtype << 12);
 235
 236         if (host->bus_mode == MMC_BUSMODE_OPENDRAIN)
 237                 cmdreg |= 1 << 6;
 238
 239         if (cmd->flags & MMC_RSP_BUSY)
 240                 cmdreg |= 1 << 11;
 241
 242         if (host->data && !(host->data->flags & MMC_DATA_WRITE))
 243                 cmdreg |= 1 << 15;
 244
 245         clk_enable(host->fclk);
 246
 247         OMAP_MMC_WRITE(host, CTO, 200);
 248         OMAP_MMC_WRITE(host, ARGL, cmd->arg & 0xffff);
 249         OMAP_MMC_WRITE(host, ARGH, cmd->arg >> 16);
 250         OMAP_MMC_WRITE(host, IE,
 251                        OMAP_MMC_STAT_A_EMPTY    | OMAP_MMC_STAT_A_FULL    |
 252                        OMAP_MMC_STAT_CMD_CRC    | OMAP_MMC_STAT_CMD_TOUT  |
 253                        OMAP_MMC_STAT_DATA_CRC   | OMAP_MMC_STAT_DATA_TOUT |
 254                        OMAP_MMC_STAT_END_OF_CMD | OMAP_MMC_STAT_CARD_ERR  |
 255                        OMAP_MMC_STAT_END_OF_DATA);
 256         OMAP_MMC_WRITE(host, CMD, cmdreg);
 257 }
 258
 259 static void
 260 mmc_omap_xfer_done(struct mmc_omap_host *host, struct mmc_data *data)
 261 {
 262         if (host->dma_in_use) {
 263                 enum dma_data_direction dma_data_dir;
 264
 265                 BUG_ON(host->dma_ch < 0);
 266                 if (data->error != MMC_ERR_NONE)
 267                         omap_stop_dma(host->dma_ch);
 268                 /* Release DMA channel lazily */
 269                 mod_timer(&host->dma_timer, jiffies + HZ);
 270                 if (data->flags & MMC_DATA_WRITE)
 271                         dma_data_dir = DMA_TO_DEVICE;
 272                 else
 273                         dma_data_dir = DMA_FROM_DEVICE;
 274                 dma_unmap_sg(mmc_dev(host->mmc), data->sg, host->sg_len,
 275                              dma_data_dir);
 276         }
 277         host->data = NULL;
 278         host->sg_len = 0;
 279         clk_disable(host->fclk);
 280
 281         /* NOTE:  MMC layer will sometimes poll-wait CMD13 next, issuing
 282          * dozens of requests until the card finishes writing data.
 283          * It'd be cheaper to just wait till an EOFB interrupt arrives...
 284          */
 285
 286         if (!data->stop) {
 287                 host->mrq = NULL;
 288                 mmc_request_done(host->mmc, data->mrq);
 289                 return;
 290         }
 291
 292         mmc_omap_start_command(host, data->stop);
 293 }
 294
 295 static void
 296 mmc_omap_end_of_data(struct mmc_omap_host *host, struct mmc_data *data)
 297 {
 298         unsigned long flags;
 299         int done;
 300
 301         if (!host->dma_in_use) {
 302                 mmc_omap_xfer_done(host, data);
 303                 return;
 304         }
 305         done = 0;
 306         spin_lock_irqsave(&host->dma_lock, flags);
 307         if (host->dma_done)
 308                 done = 1;
 309         else
 310                 host->brs_received = 1;
 311         spin_unlock_irqrestore(&host->dma_lock, flags);
 312         if (done)
 313                 mmc_omap_xfer_done(host, data);
 314 }
 315
 316 static void
 317 mmc_omap_dma_timer(unsigned long data)
 318 {
 319         struct mmc_omap_host *host = (struct mmc_omap_host *) data;
 320
 321         BUG_ON(host->dma_ch < 0);
 322         omap_free_dma(host->dma_ch);
 323         host->dma_ch = -1;
 324 }
 325
 326 static void
 327 mmc_omap_dma_done(struct mmc_omap_host *host, struct mmc_data *data)
 328 {
 329         unsigned long flags;
 330         int done;
 331
 332         done = 0;
 333         spin_lock_irqsave(&host->dma_lock, flags);
 334         if (host->brs_received)
 335                 done = 1;
 336         else
 337                 host->dma_done = 1;
 338         spin_unlock_irqrestore(&host->dma_lock, flags);
 339         if (done)
 340                 mmc_omap_xfer_done(host, data);
 341 }
 342
 343 static void
 344 mmc_omap_cmd_done(struct mmc_omap_host *host, struct mmc_command *cmd)
 345 {
 346         host->cmd = NULL;
 347
 348         if (cmd->flags & MMC_RSP_PRESENT) {
 349                 if (cmd->flags & MMC_RSP_136) {
 350                         /* response type 2 */
 351                         cmd->resp[3] =
 352                                 OMAP_MMC_READ(host, RSP0) |
 353                                 (OMAP_MMC_READ(host, RSP1) << 16);
 354                         cmd->resp[2] =
 355                                 OMAP_MMC_READ(host, RSP2) |
 356                                 (OMAP_MMC_READ(host, RSP3) << 16);
 357                         cmd->resp[1] =
 358                                 OMAP_MMC_READ(host, RSP4) |
 359                                 (OMAP_MMC_READ(host, RSP5) << 16);
 360                         cmd->resp[0] =
 361                                 OMAP_MMC_READ(host, RSP6) |
 362                                 (OMAP_MMC_READ(host, RSP7) << 16);
 363                 } else {
 364                         /* response types 1, 1b, 3, 4, 5, 6 */
 365                         cmd->resp[0] =
 366                                 OMAP_MMC_READ(host, RSP6) |
 367                                 (OMAP_MMC_READ(host, RSP7) << 16);
 368                 }
 369         }
 370
 371         if (host->data == NULL || cmd->error != MMC_ERR_NONE) {
 372                 host->mrq = NULL;
 373                 clk_disable(host->fclk);
 374                 mmc_request_done(host->mmc, cmd->mrq);
 375         }
 376 }
 377
 378 /* PIO only */
 379 static void
 380 mmc_omap_sg_to_buf(struct mmc_omap_host *host)
 381 {
 382         struct scatterlist *sg;
 383
 384         sg = host->data->sg + host->sg_idx;
 385         host->buffer_bytes_left = sg->length;
 386         host->buffer = page_address(sg->page) + sg->offset;
 387         if (host->buffer_bytes_left > host->total_bytes_left)
 388                 host->buffer_bytes_left = host->total_bytes_left;
 389 }
 390
 391 /* PIO only */
 392 static void
 393 mmc_omap_xfer_data(struct mmc_omap_host *host, int write)
 394 {
 395         int n;
 396
 397         if (host->buffer_bytes_left == 0) {
 398                 host->sg_idx++;
 399                 BUG_ON(host->sg_idx == host->sg_len);
 400                 mmc_omap_sg_to_buf(host);
 401         }
 402         n = 64;
 403         if (n > host->buffer_bytes_left)
 404                 n = host->buffer_bytes_left;
 405         host->buffer_bytes_left -= n;
 406         host->total_bytes_left -= n;
 407         host->data->bytes_xfered += n;
 408
 409         if (write) {
 410                 __raw_writesw(host->virt_base + OMAP_MMC_REG_DATA, host->buffer, n);
 411         } else {
 412                 __raw_readsw(host->virt_base + OMAP_MMC_REG_DATA, host->buffer, n);
 413         }
 414 }
 415
 416 static inline void mmc_omap_report_irq(u16 status)
 417 {
 418         static const char *mmc_omap_status_bits[] = {
 419                 "EOC", "CD", "CB", "BRS", "EOFB", "DTO", "DCRC", "CTO",
 420                 "CCRC", "CRW", "AF", "AE", "OCRB", "CIRQ", "CERR"
 421         };
 422         int i, c = 0;
 423
 424         for (i = 0; i < ARRAY_SIZE(mmc_omap_status_bits); i++)
 425                 if (status & (1 << i)) {
 426                         if (c)
 427                                 printk(" ");
 428                         printk("%s", mmc_omap_status_bits[i]);
 429                         c++;
 430                 }
 431 }
 432
 433 static irqreturn_t mmc_omap_irq(int irq, void *dev_id)
 434 {
 435         struct mmc_omap_host * host = (struct mmc_omap_host *)dev_id;
 436         u16 status;
 437         int end_command;
 438         int end_transfer;
 439         int transfer_error;
 440
 441         if (host->cmd == NULL && host->data == NULL) {
 442                 status = OMAP_MMC_READ(host, STAT);
 443                 dev_info(mmc_dev(host->mmc),"spurious irq 0x%04x\n", status);
 444                 if (status != 0) {
 445                         OMAP_MMC_WRITE(host, STAT, status);
 446                         OMAP_MMC_WRITE(host, IE, 0);
 447                 }
 448                 return IRQ_HANDLED;
 449         }
 450
 451         end_command = 0;
 452         end_transfer = 0;
 453         transfer_error = 0;
 454
 455         while ((status = OMAP_MMC_READ(host, STAT)) != 0) {
 456                 OMAP_MMC_WRITE(host, STAT, status);
 457 #ifdef CONFIG_MMC_DEBUG
 458                 dev_dbg(mmc_dev(host->mmc), "MMC IRQ %04x (CMD %d): ",
 459                         status, host->cmd != NULL ? host->cmd->opcode : -1);
 460                 mmc_omap_report_irq(status);
 461                 printk("\n");
 462 #endif
 463                 if (host->total_bytes_left) {
 464                         if ((status & OMAP_MMC_STAT_A_FULL) ||
 465                             (status & OMAP_MMC_STAT_END_OF_DATA))
 466                                 mmc_omap_xfer_data(host, 0);
 467                         if (status & OMAP_MMC_STAT_A_EMPTY)
 468                                 mmc_omap_xfer_data(host, 1);
 469                 }
 470
 471                 if (status & OMAP_MMC_STAT_END_OF_DATA) {
 472                         end_transfer = 1;
 473                 }
 474
 475                 if (status & OMAP_MMC_STAT_DATA_TOUT) {
 476                         dev_dbg(mmc_dev(host->mmc), "data timeout\n");
 477                         if (host->data) {
 478                                 host->data->error |= MMC_ERR_TIMEOUT;
 479                                 transfer_error = 1;
 480                         }
 481                 }
 482
 483                 if (status & OMAP_MMC_STAT_DATA_CRC) {
 484                         if (host->data) {
 485                                 host->data->error |= MMC_ERR_BADCRC;
 486                                 dev_dbg(mmc_dev(host->mmc),
 487                                          "data CRC error, bytes left %d\n",
 488                                         host->total_bytes_left);
 489                                 transfer_error = 1;
 490                         } else {
 491                                 dev_dbg(mmc_dev(host->mmc), "data CRC error\n");
 492                         }
 493                 }
 494
 495                 if (status & OMAP_MMC_STAT_CMD_TOUT) {
 496                         /* Timeouts are routine with some commands */
 497                         if (host->cmd) {
 498                                 if (host->cmd->opcode != MMC_ALL_SEND_CID &&
 499                                                 host->cmd->opcode !=
 500                                                 MMC_SEND_OP_COND &&
 501                                                 host->cmd->opcode !=
 502                                                 MMC_APP_CMD &&
 503                                                 !mmc_omap_cover_is_open(host))
 504                                         dev_err(mmc_dev(host->mmc),
 505                                                 "command timeout, CMD %d\n",
 506                                                 host->cmd->opcode);
 507                                 host->cmd->error = MMC_ERR_TIMEOUT;
 508                                 end_command = 1;
 509                         }
 510                 }
 511
 512                 if (status & OMAP_MMC_STAT_CMD_CRC) {
 513                         if (host->cmd) {
 514                                 dev_err(mmc_dev(host->mmc),
 515                                         "command CRC error (CMD%d, arg 0x%08x)\n",
 516                                         host->cmd->opcode, host->cmd->arg);
 517                                 host->cmd->error = MMC_ERR_BADCRC;
 518                                 end_command = 1;
 519                         } else
 520                                 dev_err(mmc_dev(host->mmc),
 521                                         "command CRC error without cmd?\n");
 522                 }
 523
 524                 if (status & OMAP_MMC_STAT_CARD_ERR) {
 525                         if (host->cmd && host->cmd->opcode == MMC_STOP_TRANSMISSION) {
 526                                 u32 response = OMAP_MMC_READ(host, RSP6)
 527                                         | (OMAP_MMC_READ(host, RSP7) << 16);
 528                                 /* STOP sometimes sets must-ignore bits */
 529                                 if (!(response & (R1_CC_ERROR
 530                                                                 | R1_ILLEGAL_COMMAND
 531                                                                 | R1_COM_CRC_ERROR))) {
 532                                         end_command = 1;
 533                                         continue;
 534                                 }
 535                         }
 536
 537                         dev_dbg(mmc_dev(host->mmc), "card status error (CMD%d)\n",
 538                                 host->cmd->opcode);
 539                         if (host->cmd) {
 540                                 host->cmd->error = MMC_ERR_FAILED;
 541                                 end_command = 1;
 542                         }
 543                         if (host->data) {
 544                                 host->data->error = MMC_ERR_FAILED;
 545                                 transfer_error = 1;
 546                         }
 547                 }
 548
 549                 /*
 550                  * NOTE: On 1610 the END_OF_CMD may come too early when
 551                  * starting a write
 552                  */
 553                 if ((status & OMAP_MMC_STAT_END_OF_CMD) &&
 554                     (!(status & OMAP_MMC_STAT_A_EMPTY))) {
 555                         end_command = 1;
 556                 }
 557         }
 558
 559         if (end_command) {
 560                 mmc_omap_cmd_done(host, host->cmd);
 561         }
 562         if (transfer_error)
 563                 mmc_omap_xfer_done(host, host->data);
 564         else if (end_transfer)
 565                 mmc_omap_end_of_data(host, host->data);
 566
 567         return IRQ_HANDLED;
 568 }
 569
 570 static irqreturn_t mmc_omap_switch_irq(int irq, void *dev_id)
 571 {
 572         struct mmc_omap_host *host = (struct mmc_omap_host *) dev_id;
 573
 574         schedule_work(&host->switch_work);
 575
 576         return IRQ_HANDLED;
 577 }
 578
 579 static void mmc_omap_switch_timer(unsigned long arg)
 580 {
 581         struct mmc_omap_host *host = (struct mmc_omap_host *) arg;
 582
 583         schedule_work(&host->switch_work);
 584 }
 585
 586 static void mmc_omap_switch_handler(struct work_struct *work)
 587 {
 588         struct mmc_omap_host *host = container_of(work, struct mmc_omap_host, switch_work);
 589         struct mmc_card *card;
 590         static int complained = 0;
 591         int cards = 0, cover_open;
 592
 593         if (host->switch_pin == -1)
 594                 return;
 595         cover_open = mmc_omap_cover_is_open(host);
 596         if (cover_open != host->switch_last_state) {
 597                 kobject_uevent(&host->dev->kobj, KOBJ_CHANGE);
 598                 host->switch_last_state = cover_open;
 599         }
 600         mmc_detect_change(host->mmc, 0);
 601         list_for_each_entry(card, &host->mmc->cards, node) {
 602                 if (mmc_card_present(card))
 603                         cards++;
 604         }
 605         if (mmc_omap_cover_is_open(host)) {
 606                 if (!complained) {
 607                         dev_info(mmc_dev(host->mmc), "cover is open\n");
 608                         complained = 1;
 609                 }
 610                 if (mmc_omap_enable_poll)
 611                         mod_timer(&host->switch_timer, jiffies +
 612                                 msecs_to_jiffies(OMAP_MMC_SWITCH_POLL_DELAY));
 613         } else {
 614                 complained = 0;
 615         }
 616 }
 617
 618 /* Prepare to transfer the next segment of a scatterlist */
 619 static void
 620 mmc_omap_prepare_dma(struct mmc_omap_host *host, struct mmc_data *data)
 621 {
 622         int dma_ch = host->dma_ch;
 623         unsigned long data_addr;
 624         u16 buf, frame;
 625         u32 count;
 626         struct scatterlist *sg = &data->sg[host->sg_idx];
 627         int src_port = 0;
 628         int dst_port = 0;
 629         int sync_dev = 0;
 630
 631         data_addr = host->phys_base + OMAP_MMC_REG_DATA;
 632         frame = data->blksz;
 633         count = sg_dma_len(sg);
 634
 635         if ((data->blocks == 1) && (count > data->blksz))
 636                 count = frame;
 637
 638         host->dma_len = count;
 639
 640         /* FIFO is 16x2 bytes on 15xx, and 32x2 bytes on 16xx and 24xx.
 641          * Use 16 or 32 word frames when the blocksize is at least that large.
 642          * Blocksize is usually 512 bytes; but not for some SD reads.
 643          */
 644         if (cpu_is_omap15xx() && frame > 32)
 645                 frame = 32;
 646         else if (frame > 64)
 647                 frame = 64;
 648         count /= frame;
 649         frame >>= 1;
 650
 651         if (!(data->flags & MMC_DATA_WRITE)) {
 652                 buf = 0x800f | ((frame - 1) << 8);
 653
 654                 if (cpu_class_is_omap1()) {
 655                         src_port = OMAP_DMA_PORT_TIPB;
 656                         dst_port = OMAP_DMA_PORT_EMIFF;
 657                 }
 658                 if (cpu_is_omap24xx())
 659                         sync_dev = OMAP24XX_DMA_MMC1_RX;
 660
 661                 omap_set_dma_src_params(dma_ch, src_port,
 662                                         OMAP_DMA_AMODE_CONSTANT,
 663                                         data_addr, 0, 0);
 664                 omap_set_dma_dest_params(dma_ch, dst_port,
 665                                          OMAP_DMA_AMODE_POST_INC,
 666                                          sg_dma_address(sg), 0, 0);
 667                 omap_set_dma_dest_data_pack(dma_ch, 1);
 668                 omap_set_dma_dest_burst_mode(dma_ch, OMAP_DMA_DATA_BURST_4);
 669         } else {
 670                 buf = 0x0f80 | ((frame - 1) << 0);
 671
 672                 if (cpu_class_is_omap1()) {
 673                         src_port = OMAP_DMA_PORT_EMIFF;
 674                         dst_port = OMAP_DMA_PORT_TIPB;
 675                 }
 676                 if (cpu_is_omap24xx())
 677                         sync_dev = OMAP24XX_DMA_MMC1_TX;
 678
 679                 omap_set_dma_dest_params(dma_ch, dst_port,
 680                                          OMAP_DMA_AMODE_CONSTANT,
 681                                          data_addr, 0, 0);
 682                 omap_set_dma_src_params(dma_ch, src_port,
 683                                         OMAP_DMA_AMODE_POST_INC,
 684                                         sg_dma_address(sg), 0, 0);
 685                 omap_set_dma_src_data_pack(dma_ch, 1);
 686                 omap_set_dma_src_burst_mode(dma_ch, OMAP_DMA_DATA_BURST_4);
 687         }
 688
 689         /* Max limit for DMA frame count is 0xffff */
 690         BUG_ON(count > 0xffff);
 691
 692         OMAP_MMC_WRITE(host, BUF, buf);
 693         omap_set_dma_transfer_params(dma_ch, OMAP_DMA_DATA_TYPE_S16,
 694                                      frame, count, OMAP_DMA_SYNC_FRAME,
 695                                      sync_dev, 0);
 696 }
 697
 698 /* A scatterlist segment completed */
 699 static void mmc_omap_dma_cb(int lch, u16 ch_status, void *data)
 700 {
 701         struct mmc_omap_host *host = (struct mmc_omap_host *) data;
 702         struct mmc_data *mmcdat = host->data;
 703
 704         if (unlikely(host->dma_ch < 0)) {
 705                 dev_err(mmc_dev(host->mmc),
 706                         "DMA callback while DMA not enabled\n");
 707                 return;
 708         }
 709         /* FIXME: We really should do something to _handle_ the errors */
 710         if (ch_status & OMAP1_DMA_TOUT_IRQ) {
 711                 dev_err(mmc_dev(host->mmc),"DMA timeout\n");
 712                 return;
 713         }
 714         if (ch_status & OMAP_DMA_DROP_IRQ) {
 715                 dev_err(mmc_dev(host->mmc), "DMA sync error\n");
 716                 return;
 717         }
 718         if (!(ch_status & OMAP_DMA_BLOCK_IRQ)) {
 719                 return;
 720         }
 721         mmcdat->bytes_xfered += host->dma_len;
 722         host->sg_idx++;
 723         if (host->sg_idx < host->sg_len) {
 724                 mmc_omap_prepare_dma(host, host->data);
 725                 omap_start_dma(host->dma_ch);
 726         } else
 727                 mmc_omap_dma_done(host, host->data);
 728 }
 729
 730 static int mmc_omap_get_dma_channel(struct mmc_omap_host *host, struct mmc_data *data)
 731 {
 732         const char *dev_name;
 733         int sync_dev, dma_ch, is_read, r;
 734
 735         is_read = !(data->flags & MMC_DATA_WRITE);
 736         del_timer_sync(&host->dma_timer);
 737         if (host->dma_ch >= 0) {
 738                 if (is_read == host->dma_is_read)
 739                         return 0;
 740                 omap_free_dma(host->dma_ch);
 741                 host->dma_ch = -1;
 742         }
 743
 744         if (is_read) {
 745                 if (host->id == 1) {
 746                         sync_dev = OMAP_DMA_MMC_RX;
 747                         dev_name = "MMC1 read";
 748                 } else {
 749                         sync_dev = OMAP_DMA_MMC2_RX;
 750                         dev_name = "MMC2 read";
 751                 }
 752         } else {
 753                 if (host->id == 1) {
 754                         sync_dev = OMAP_DMA_MMC_TX;
 755                         dev_name = "MMC1 write";
 756                 } else {
 757                         sync_dev = OMAP_DMA_MMC2_TX;
 758                         dev_name = "MMC2 write";
 759                 }
 760         }
 761         r = omap_request_dma(sync_dev, dev_name, mmc_omap_dma_cb,
 762                              host, &dma_ch);
 763         if (r != 0) {
 764                 dev_dbg(mmc_dev(host->mmc), "omap_request_dma() failed with %d\n", r);
 765                 return r;
 766         }
 767         host->dma_ch = dma_ch;
 768         host->dma_is_read = is_read;
 769
 770         return 0;
 771 }
 772
 773 static inline void set_cmd_timeout(struct mmc_omap_host *host, struct mmc_request *req)
 774 {
 775         u16 reg;
 776
 777         reg = OMAP_MMC_READ(host, SDIO);
 778         reg &= ~(1 << 5);
 779         OMAP_MMC_WRITE(host, SDIO, reg);
 780         /* Set maximum timeout */
 781         OMAP_MMC_WRITE(host, CTO, 0xff);
 782 }
 783
 784 static inline void set_data_timeout(struct mmc_omap_host *host, struct mmc_request *req)
 785 {
 786         int timeout;
 787         u16 reg;
 788
 789         /* Convert ns to clock cycles by assuming 20MHz frequency
 790          * 1 cycle at 20MHz = 500 ns
 791          */
 792         timeout = req->data->timeout_clks + req->data->timeout_ns / 500;
 793
 794         /* Check if we need to use timeout multiplier register */
 795         reg = OMAP_MMC_READ(host, SDIO);
 796         if (timeout > 0xffff) {
 797                 reg |= (1 << 5);
 798                 timeout /= 1024;
 799         } else
 800                 reg &= ~(1 << 5);
 801         OMAP_MMC_WRITE(host, SDIO, reg);
 802         OMAP_MMC_WRITE(host, DTO, timeout);
 803 }
 804
 805 static void
 806 mmc_omap_prepare_data(struct mmc_omap_host *host, struct mmc_request *req)
 807 {
 808         struct mmc_data *data = req->data;
 809         int i, use_dma, block_size;
 810         unsigned sg_len;
 811
 812         host->data = data;
 813         if (data == NULL) {
 814                 OMAP_MMC_WRITE(host, BLEN, 0);
 815                 OMAP_MMC_WRITE(host, NBLK, 0);
 816                 OMAP_MMC_WRITE(host, BUF, 0);
 817                 host->dma_in_use = 0;
 818                 set_cmd_timeout(host, req);
 819                 return;
 820         }
 821
 822         block_size = data->blksz;
 823
 824         OMAP_MMC_WRITE(host, NBLK, data->blocks - 1);
 825         OMAP_MMC_WRITE(host, BLEN, block_size - 1);
 826         set_data_timeout(host, req);
 827
 828         /* cope with calling layer confusion; it issues "single
 829          * block" writes using multi-block scatterlists.
 830          */
 831         sg_len = (data->blocks == 1) ? 1 : data->sg_len;
 832
 833         /* Only do DMA for entire blocks */
 834         use_dma = host->use_dma;
 835         if (use_dma) {
 836                 for (i = 0; i < sg_len; i++) {
 837                         if ((data->sg[i].length % block_size) != 0) {
 838                                 use_dma = 0;
 839                                 break;
 840                         }
 841                 }
 842         }
 843
 844         host->sg_idx = 0;
 845         if (use_dma) {
 846                 if (mmc_omap_get_dma_channel(host, data) == 0) {
 847                         enum dma_data_direction dma_data_dir;
 848
 849                         if (data->flags & MMC_DATA_WRITE)
 850                                 dma_data_dir = DMA_TO_DEVICE;
 851                         else
 852                                 dma_data_dir = DMA_FROM_DEVICE;
 853
 854                         host->sg_len = dma_map_sg(mmc_dev(host->mmc), data->sg,
 855                                                 sg_len, dma_data_dir);
 856                         host->total_bytes_left = 0;
 857                         mmc_omap_prepare_dma(host, req->data);
 858                         host->brs_received = 0;
 859                         host->dma_done = 0;
 860                         host->dma_in_use = 1;
 861                 } else
 862                         use_dma = 0;
 863         }
 864
 865         /* Revert to PIO? */
 866         if (!use_dma) {
 867                 OMAP_MMC_WRITE(host, BUF, 0x1f1f);
 868                 host->total_bytes_left = data->blocks * block_size;
 869                 host->sg_len = sg_len;
 870                 mmc_omap_sg_to_buf(host);
 871                 host->dma_in_use = 0;
 872         }
 873 }
 874
 875 static void mmc_omap_request(struct mmc_host *mmc, struct mmc_request *req)
 876 {
 877         struct mmc_omap_host *host = mmc_priv(mmc);
 878
 879         WARN_ON(host->mrq != NULL);
 880
 881         host->mrq = req;
 882
 883         /* only touch fifo AFTER the controller readies it */
 884         mmc_omap_prepare_data(host, req);
 885         mmc_omap_start_command(host, req->cmd);
 886         if (host->dma_in_use)
 887                 omap_start_dma(host->dma_ch);
 888 }
 889
 890 static void innovator_fpga_socket_power(int on)
 891 {
 892 #if defined(CONFIG_MACH_OMAP_INNOVATOR) && defined(CONFIG_ARCH_OMAP15XX)
 893         if (on) {
 894                 fpga_write(fpga_read(OMAP1510_FPGA_POWER) | (1 << 3),
 895                      OMAP1510_FPGA_POWER);
 896         } else {
 897                 fpga_write(fpga_read(OMAP1510_FPGA_POWER) & ~(1 << 3),
 898                      OMAP1510_FPGA_POWER);
 899         }
 900 #endif
 901 }
 902
 903 /*
 904  * Turn the socket power on/off. Innovator uses FPGA, most boards
 905  * probably use GPIO.
 906  */
 907 static void mmc_omap_power(struct mmc_omap_host *host, int on)
 908 {
 909         if (on) {
 910                 if (machine_is_omap_innovator())
 911                         innovator_fpga_socket_power(1);
 912                 else if (machine_is_omap_h2())
 913                         tps65010_set_gpio_out_value(GPIO3, HIGH);
 914                 else if (machine_is_omap_h3())
 915                         /* GPIO 4 of TPS65010 sends SD_EN signal */
 916                         tps65010_set_gpio_out_value(GPIO4, HIGH);
 917                 else if (cpu_is_omap24xx()) {
 918                         u16 reg = OMAP_MMC_READ(host, CON);
 919                         OMAP_MMC_WRITE(host, CON, reg | (1 << 11));
 920                 } else
 921                         if (host->power_pin >= 0)
 922                                 omap_set_gpio_dataout(host->power_pin, 1);
 923         } else {
 924                 if (machine_is_omap_innovator())
 925                         innovator_fpga_socket_power(0);
 926                 else if (machine_is_omap_h2())
 927                         tps65010_set_gpio_out_value(GPIO3, LOW);
 928                 else if (machine_is_omap_h3())
 929                         tps65010_set_gpio_out_value(GPIO4, LOW);
 930                 else if (cpu_is_omap24xx()) {
 931                         u16 reg = OMAP_MMC_READ(host, CON);
 932                         OMAP_MMC_WRITE(host, CON, reg & ~(1 << 11));
 933                 } else
 934                         if (host->power_pin >= 0)
 935                                 omap_set_gpio_dataout(host->power_pin, 0);
 936         }
 937 }
 938
 939 static int mmc_omap_calc_divisor(struct mmc_host *mmc, struct mmc_ios *ios)
 940 {
 941         struct mmc_omap_host *host = mmc_priv(mmc);
 942         int func_clk_rate = clk_get_rate(host->fclk);
 943         int dsor;
 944
 945         if (ios->clock == 0)
 946                 return 0;
 947
 948         dsor = func_clk_rate / ios->clock;
 949         if (dsor < 1)
 950                 dsor = 1;
 951
 952         if (func_clk_rate / dsor > ios->clock)
 953                 dsor++;
 954
 955         if (dsor > 250)
 956                 dsor = 250;
 957         dsor++;
 958
 959         if (ios->bus_width == MMC_BUS_WIDTH_4)
 960                 dsor |= 1 << 15;
 961
 962         return dsor;
 963 }
 964
 965 static void mmc_omap_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
 966 {
 967         struct mmc_omap_host *host = mmc_priv(mmc);
 968         int dsor;
 969         int i;
 970
 971         dsor = mmc_omap_calc_divisor(mmc, ios);
 972         host->bus_mode = ios->bus_mode;
 973         host->hw_bus_mode = host->bus_mode;
 974
 975         switch (ios->power_mode) {
 976         case MMC_POWER_OFF:
 977                 mmc_omap_power(host, 0);
 978                 break;
 979         case MMC_POWER_UP:
 980                 /* Cannot touch dsor yet, just power up MMC */
 981                 mmc_omap_power(host, 1);
 982                 return;
 983         case MMC_POWER_ON:
 984                 dsor |= 1 << 11;
 985                 break;
 986         }
 987
 988         clk_enable(host->fclk);
 989
 990         /* On insanely high arm_per frequencies something sometimes
 991          * goes somehow out of sync, and the POW bit is not being set,
 992          * which results in the while loop below getting stuck.
 993          * Writing to the CON register twice seems to do the trick. */
 994         for (i = 0; i < 2; i++)
 995                 OMAP_MMC_WRITE(host, CON, dsor);
 996         if (ios->power_mode == MMC_POWER_ON) {
 997                 /* Send clock cycles, poll completion */
 998                 OMAP_MMC_WRITE(host, IE, 0);
 999                 OMAP_MMC_WRITE(host, STAT, 0xffff);
1000                 OMAP_MMC_WRITE(host, CMD, 1 << 7);
1001                 while ((OMAP_MMC_READ(host, STAT) & 1) == 0);
1002                 OMAP_MMC_WRITE(host, STAT, 1);
1003         }
1004         clk_disable(host->fclk);
1005 }
1006
1007 static int mmc_omap_get_ro(struct mmc_host *mmc)
1008 {
1009         struct mmc_omap_host *host = mmc_priv(mmc);
1010
1011         return host->wp_pin && omap_get_gpio_datain(host->wp_pin);
1012 }
1013
1014 static const struct mmc_host_ops mmc_omap_ops = {
1015         .request        = mmc_omap_request,
1016         .set_ios        = mmc_omap_set_ios,
1017         .get_ro         = mmc_omap_get_ro,
1018 };
1019
1020 static int __init mmc_omap_probe(struct platform_device *pdev)
1021 {
1022         struct omap_mmc_conf *minfo = pdev->dev.platform_data;
1023         struct mmc_host *mmc;
1024         struct mmc_omap_host *host = NULL;
1025         struct resource *res;
1026         int ret = 0;
1027         int irq;
1028
1029         if (minfo == NULL) {
1030                 dev_err(&pdev->dev, "platform data missing\n");
1031                 return -ENXIO;
1032         }
1033
1034         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1035         irq = platform_get_irq(pdev, 0);
1036         if (res == NULL || irq < 0)
1037                 return -ENXIO;
1038
1039         res = request_mem_region(res->start, res->end - res->start + 1,
1040                                  pdev->name);
1041         if (res == NULL)
1042                 return -EBUSY;
1043
1044         mmc = mmc_alloc_host(sizeof(struct mmc_omap_host), &pdev->dev);
1045         if (mmc == NULL) {
1046                 ret = -ENOMEM;
1047                 goto err_free_mem_region;
1048         }
1049
1050         host = mmc_priv(mmc);
1051         host->mmc = mmc;
1052
1053         spin_lock_init(&host->dma_lock);
1054         init_timer(&host->dma_timer);
1055         host->dma_timer.function = mmc_omap_dma_timer;
1056         host->dma_timer.data = (unsigned long) host;
1057
1058         host->id = pdev->id;
1059         host->mem_res = res;
1060         host->irq = irq;
1061
1062         if (cpu_is_omap24xx()) {
1063                 host->iclk = clk_get(&pdev->dev, "mmc_ick");
1064                 if (IS_ERR(host->iclk))
1065                         goto err_free_mmc_host;
1066                 clk_enable(host->iclk);
1067         }
1068
1069         if (!cpu_is_omap24xx())
1070                 host->fclk = clk_get(&pdev->dev, "mmc_ck");
1071         else
1072                 host->fclk = clk_get(&pdev->dev, "mmc_fck");
1073
1074         if (IS_ERR(host->fclk)) {
1075                 ret = PTR_ERR(host->fclk);
1076                 goto err_free_iclk;
1077         }
1078
1079         /* REVISIT:
1080          * Also, use minfo->cover to decide how to manage
1081          * the card detect sensing.
1082          */
1083         host->power_pin = minfo->power_pin;
1084         host->switch_pin = minfo->switch_pin;
1085         host->wp_pin = minfo->wp_pin;
1086         host->use_dma = 1;
1087         host->dma_ch = -1;
1088
1089         host->irq = irq;
1090         host->phys_base = host->mem_res->start;
1091         host->virt_base = (void __iomem *) IO_ADDRESS(host->phys_base);
1092
1093         mmc->ops = &mmc_omap_ops;
1094         mmc->f_min = 400000;
1095         mmc->f_max = 24000000;
1096         mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
1097         mmc->caps = MMC_CAP_MULTIWRITE | MMC_CAP_BYTEBLOCK;
1098
1099         if (minfo->wire4)
1100                  mmc->caps |= MMC_CAP_4_BIT_DATA;
1101
1102         /* Use scatterlist DMA to reduce per-transfer costs.
1103          * NOTE max_seg_size assumption that small blocks aren't
1104          * normally used (except e.g. for reading SD registers).
1105          */
1106         mmc->max_phys_segs = 32;
1107         mmc->max_hw_segs = 32;
1108         mmc->max_blk_size = 2048;       /* BLEN is 11 bits (+1) */
1109         mmc->max_blk_count = 2048;      /* NBLK is 11 bits (+1) */
1110         mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
1111         mmc->max_seg_size = mmc->max_req_size;
1112
1113         if (host->power_pin >= 0) {
1114                 if ((ret = omap_request_gpio(host->power_pin)) != 0) {
1115                         dev_err(mmc_dev(host->mmc),
1116                                 "Unable to get GPIO pin for MMC power\n");
1117                         goto err_free_fclk;
1118                 }
1119                 omap_set_gpio_direction(host->power_pin, 0);
1120         }
1121
1122         ret = request_irq(host->irq, mmc_omap_irq, 0, DRIVER_NAME, host);
1123         if (ret)
1124                 goto err_free_power_gpio;
1125
1126         host->dev = &pdev->dev;
1127         platform_set_drvdata(pdev, host);
1128
1129         if (host->switch_pin >= 0) {
1130                 INIT_WORK(&host->switch_work, mmc_omap_switch_handler);
1131                 init_timer(&host->switch_timer);
1132                 host->switch_timer.function = mmc_omap_switch_timer;
1133                 host->switch_timer.data = (unsigned long) host;
1134                 if (omap_request_gpio(host->switch_pin) != 0) {
1135                         dev_warn(mmc_dev(host->mmc), "Unable to get GPIO pin for MMC cover switch\n");
1136                         host->switch_pin = -1;
1137                         goto no_switch;
1138                 }
1139
1140                 omap_set_gpio_direction(host->switch_pin, 1);
1141                 ret = request_irq(OMAP_GPIO_IRQ(host->switch_pin),
1142                                   mmc_omap_switch_irq, IRQF_TRIGGER_RISING, DRIVER_NAME, host);
1143                 if (ret) {
1144                         dev_warn(mmc_dev(host->mmc), "Unable to get IRQ for MMC cover switch\n");
1145                         omap_free_gpio(host->switch_pin);
1146                         host->switch_pin = -1;
1147                         goto no_switch;
1148                 }
1149                 ret = device_create_file(&pdev->dev, &dev_attr_cover_switch);
1150                 if (ret == 0) {
1151                         ret = device_create_file(&pdev->dev, &dev_attr_enable_poll);
1152                         if (ret != 0)
1153                                 device_remove_file(&pdev->dev, &dev_attr_cover_switch);
1154                 }
1155                 if (ret) {
1156                         dev_warn(mmc_dev(host->mmc), "Unable to create sysfs attributes\n");
1157                         free_irq(OMAP_GPIO_IRQ(host->switch_pin), host);
1158                         omap_free_gpio(host->switch_pin);
1159                         host->switch_pin = -1;
1160                         goto no_switch;
1161                 }
1162                 if (mmc_omap_enable_poll && mmc_omap_cover_is_open(host))
1163                         schedule_work(&host->switch_work);
1164         }
1165
1166         mmc_add_host(mmc);
1167
1168         return 0;
1169
1170 no_switch:
1171         /* FIXME: Free other resources too. */
1172         if (host) {
1173                 if (host->iclk && !IS_ERR(host->iclk))
1174                         clk_put(host->iclk);
1175                 if (host->fclk && !IS_ERR(host->fclk))
1176                         clk_put(host->fclk);
1177                 mmc_free_host(host->mmc);
1178         }
1179 err_free_power_gpio:
1180         if (host->power_pin >= 0)
1181                 omap_free_gpio(host->power_pin);
1182 err_free_fclk:
1183         clk_put(host->fclk);
1184 err_free_iclk:
1185         if (host->iclk != NULL) {
1186                 clk_disable(host->iclk);
1187                 clk_put(host->iclk);
1188         }
1189 err_free_mmc_host:
1190         mmc_free_host(host->mmc);
1191 err_free_mem_region:
1192         release_mem_region(res->start, res->end - res->start + 1);
1193         return ret;
1194 }
1195
1196 static int mmc_omap_remove(struct platform_device *pdev)
1197 {
1198         struct mmc_omap_host *host = platform_get_drvdata(pdev);
1199
1200         platform_set_drvdata(pdev, NULL);
1201
1202         BUG_ON(host == NULL);
1203
1204         mmc_remove_host(host->mmc);
1205         free_irq(host->irq, host);
1206
1207         if (host->power_pin >= 0)
1208                 omap_free_gpio(host->power_pin);
1209         if (host->switch_pin >= 0) {
1210                 device_remove_file(&pdev->dev, &dev_attr_enable_poll);
1211                 device_remove_file(&pdev->dev, &dev_attr_cover_switch);
1212                 free_irq(OMAP_GPIO_IRQ(host->switch_pin), host);
1213                 omap_free_gpio(host->switch_pin);
1214                 host->switch_pin = -1;
1215                 del_timer_sync(&host->switch_timer);
1216                 flush_scheduled_work();
1217         }
1218         if (host->iclk && !IS_ERR(host->iclk))
1219                 clk_put(host->iclk);
1220         if (host->fclk && !IS_ERR(host->fclk))
1221                 clk_put(host->fclk);
1222
1223         release_mem_region(pdev->resource[0].start,
1224                            pdev->resource[0].end - pdev->resource[0].start + 1);
1225
1226         mmc_free_host(host->mmc);
1227
1228         return 0;
1229 }
1230
1231 #ifdef CONFIG_PM
1232 static int mmc_omap_suspend(struct platform_device *pdev, pm_message_t mesg)
1233 {
1234         int ret = 0;
1235         struct mmc_omap_host *host = platform_get_drvdata(pdev);
1236
1237         if (host && host->suspended)
1238                 return 0;
1239
1240         if (host) {
1241                 ret = mmc_suspend_host(host->mmc, mesg);
1242                 if (ret == 0)
1243                         host->suspended = 1;
1244         }
1245         return ret;
1246 }
1247
1248 static int mmc_omap_resume(struct platform_device *pdev)
1249 {
1250         int ret = 0;
1251         struct mmc_omap_host *host = platform_get_drvdata(pdev);
1252
1253         if (host && !host->suspended)
1254                 return 0;
1255
1256         if (host) {
1257                 ret = mmc_resume_host(host->mmc);
1258                 if (ret == 0)
1259                         host->suspended = 0;
1260         }
1261
1262         return ret;
1263 }
1264 #else
1265 #define mmc_omap_suspend        NULL
1266 #define mmc_omap_resume         NULL
1267 #endif
1268
1269 static struct platform_driver mmc_omap_driver = {
1270         .probe          = mmc_omap_probe,
1271         .remove         = mmc_omap_remove,
1272         .suspend        = mmc_omap_suspend,
1273         .resume         = mmc_omap_resume,
1274         .driver         = {
1275                 .name   = DRIVER_NAME,
1276         },
1277 };
1278
1279 static int __init mmc_omap_init(void)
1280 {
1281         return platform_driver_register(&mmc_omap_driver);
1282 }
1283
1284 static void __exit mmc_omap_exit(void)
1285 {
1286         platform_driver_unregister(&mmc_omap_driver);
1287 }
1288
1289 module_init(mmc_omap_init);
1290 module_exit(mmc_omap_exit);
1291
1292 MODULE_DESCRIPTION("OMAP Multimedia Card driver");
1293 MODULE_LICENSE("GPL");
1294 MODULE_ALIAS(DRIVER_NAME);
1295 MODULE_AUTHOR("Juha Yrjölä");